1
®HI5731
12-Bit, 100MSPS, High Speed D/A
Converter
The HI5731 is a 12-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the conv erter provides
-20.48mA of full scale output current and includes an inpu t
data register and bandgap voltage reference. Low glitch
energy and excell ent frequency domain performan ce are
achie ved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and tra nslated internally to ECL.
All inter nal logic is implemented in ECL to achieve high
swi tching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.
Features
•Pb-free Available as an Option
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . .3.0pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
Applications
• Cellular Base Stations
• GSM Base Stations
• Wireless Communications
• Direct Digital Frequency Synthesi s
• Signal Reconstruction
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout HI5731
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP.
RANGE (°C) PACKAGE PKG. DWG.
#
HI5731BIP -40 to 85 28 Ld PDIP E28.6
HI5731BIPZ
(See Note) -40 to 85 28 Ld PDIP
(Pb-free) E28.6
HI5731BIB -40 to 85 28 Ld SOIC M28.3
HI5731BIB-T 28 Ld SOIC Tape and Reel M28.3
HI5731BIBZ
(See Note) -40 to 85 28 Ld SOIC
(Pb-free) M28.3
HI5731-EVS 25 Evaluation Board (SOIC)
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DGND
REF OUT
CTRL OUT
CTRL IN
RSET
IOUT
ARTN
DVEE
DGND
DVCC
CLOCK
AGND
AVEE
IOUT
Data Sheet September 15, 2004 FN4070.9
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
2
Typical Application Circuit
Functional Block Diagram
D9 (3)
D8 (4)
D7 (5)
D6 (6)
D5 (7)
D4 (8)
D3 (9)
D2 (10)
D9
D8
D7
D6
D5
D4
D3
D2
+5V
DVCC (16)
0.01µF
DGND (17, 28)
CLK (15)
-5.2V (AVEE)
0.1µF
(19) ARTN
(22) AVEE
D/A OUT
(21) IOUT
(20) IOUT
(23) RSET 976Ω
64Ω
(24) CTRL IN
HI5731
D10
D11 D11 (MSB) (1)
D10 (2)
DVEE (18)
- 5.2V (AVEE)
0.01µF
(25) CTRL OUT
(26) REF OUT
64Ω
0.1µF
- 5.2V (DVEE)
0.01µF
0.1µF
(27) AGND
50Ω
D1 (11)
D0 (LSB) (12)
D1
D0
UPPER
SLAVE
IOUT
(LSB) D0
D1
D2
D3
D4
D5
D6
D9
D7
D8
4-BIT
DECODER
IOUT
+
-CTRL
REF OUT RSET
CTRL
25Ω
12-BIT
MASTER
REGISTER
AVEE AGND DVEE DGND DVCC
15
SWITCHED
CURRENT
CELLS
D10
(MSB) D11
REGISTER
DATA
BUFFER/
LEVEL
SHIFTER
OVERDRIVEABLE
VOLTAGE
REFERENCE
CLK
REF CELL
IN
OUT
8 LSBs
CURRENT
CELLS
R2R
NETWORK
227Ω227Ω
15 15
ARTN
HI5731
3
Absolute Maximum Ratings Thermal Info rmation
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN. . . . . -5.5V
Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA
Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 oC to 85oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Maximum Junction Temperature
HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other co nditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for detail s.
Electrical Specifications AVEE, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal
TA = 25oC for All Typical Values
PARAMETER TEST CONDITIONS
HI5731BI
TA = -40oC TO 85oC
UNITSMIN TYP MAX
SYSTEM PERFORMANCE
Resolution 12 - - Bits
Integral Linearity Error, INL (Note 4) (“Best Fit” Straight Line) - 0.75 1.5 LSB
Differential Linearity Error, DNL (Note 4) - 0.5 1.0 LSB
Offset Error, IOS (Note 4) - 20 75 µA
Full Scale Gain Error, FSE (Notes 2, 4) - 1 10 %
Full Scale Gain Drift With Internal Reference - ±150 - ppm
FSR/oC
Offset Drift Coefficient (Note 3) - - 0.05 µA/oC
Full Scale Output Current, IFS -20.48- mA
Output Voltage Compliance Range (Note 3) -1.25 - 0 V
DYNAMIC CHARACTERISTICS
Throughput Rate (Note 3) 100 - - MSPS
Output Voltage Full Scale Step
Settling Time, tSETT, Full Scale To ±0.5 LSB Error Band RL = 50Ω
(Note 3) -20- ns
Singlet Glitch Area, GE (Peak) RL = 50Ω (Note 3) - 5 - pV-s
Doublet Glitch Area, (Net) -3-pV-s
Output Slew Rate RL = 50Ω, DAC Operating in Latched Mode (Note 3) - 1,000 - V/µs
Output Rise Time RL = 50Ω, DAC Operating in Latched Mode (Note 3) - 675 - ps
Output Fall Time RL = 50Ω, DAC Operating in Latched Mode (Note 3) - 470 - ps
Spurious Free Dynamic Range within a Window
(Note 3) fCLK = 10MSPS, fOUT = 1.23MHz, 2MHz Span - 85 - dBc
fCLK = 20MSPS, fOUT = 5.055MHz, 2MHz Span - 77 - dBc
fCLK = 40MSPS, fOUT = 16MHz, 10MHz Span - 75 - dBc
fCLK = 50MSPS, fOUT = 10.1MHz, 2MHz Span - 80 - dBc
fCLK = 80MSPS, fOUT = 5.1MHz, 2MHz Span - 78 - dBc
fCLK = 100MSPS, fOUT = 10.1MHz, 2MHz Span - 79 - dBc
HI5731
4
Spurious Free Dynamic Range to Nyquist
(Note 3) fCLK = 40MSPS, fOUT = 2.02MHz, 20MHz Span - 70 - dBc
fCLK = 80MSPS, fOUT = 2.02MHz, 40MHz Span - 70 - dBc
fCLK = 100MSPS, fOUT = 2.02MHz, 50MHz Span - 69 - dBc
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, VREF (Note 4) -1.27 -1.23 -1.17 V
Internal Reference Voltage Drift (Note 3) - 175 - µV/oC
Internal Reference Output Current Sink/Source
Capability (Note 3) -125 - +50 µA
Internal Reference Load Regulation IREF = 0 to IREF = -125µA-50-µV
Input Impedance at REF OUT pin (Note 3) - 1.4 - kΩ
Amplifier Large Signal Bandwidth (0.6VP-P) Sine Wave Input, to Slew Rate Limited (Note 3) - 3 - MHz
Amplifier Small Signal Bandwidth (0.1VP-P) Sine Wave Input, to -3dB Loss (Note 3) - 10 - MHz
Reference Input Impedance (Note 3) - 12 - kΩ
Reference Input Multiplying Bandwidth (CTL IN) RL = 50Ω, 100mV Sine Wave, to -3dB Loss at IOUT
(Note 3) - 200 - MHz
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, VIH (Note 4) 2.0 - - V
Input Logic Low Voltage, VIL (Note 4) - - 0.8 V
Input Logic Current, IIH (Note 4) - - 400 µA
Input Logic Current, IIL (Note 4) - - 700 µA
Digital Input Capacitance, CIN (Note 3) - 3.0 - pF
TIMING CHARACTERISTICS
Data Setup Time, tSU See Figure 1 (Note 3) 3.0 2.0 - ns
Data Hold Time, tHLD See Figure 1 (Note 3) 0.5 0.25 - ns
Propagation Delay Time, t PD See Figure 1 (Note 3) - 4.5 - ns
CLK Pulse Width, tPW1, tPW2 See Figure 1 (Note 3) 3.0 - - ns
POWER SUPPLY CHARACTERISTICS
IEEA (Note 4) - 42 50 mA
IEED (Note 4) - 70 85 mA
ICCD (Note 4) - 13 20 mA
Power Dissipation (Note 4) - 650 - mW
Power Supply Rejection Ratio VCC ±5%, VEE ±5% - 5 - µA/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 1.28mA). Ideally the
ratio should be 16.
3. Parameter guaranteed by design or characterization and not production tested.
4. All devices are 100% tested at 25oC.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
Electrical Specifications AVEE, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal
TA = 25oC for All Typical Values (Continued)
PARAMETER TEST CONDITIONS
HI5731BI
TA = -40oC TO 85oC
UNITSMIN TYP MAX
HI5731
5
Timing Diagrams
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
D11-D0
IOUT
50%
tSETT
±1/2 LSB ERROR BAND
tPD
V
t(ps)
HEIGHT (H)
WIDTH (W)
GLITCH AREA = 1/2 (H x W)
CLK
D11-D0
IOUT
50%
tPW1 tPW2
tSU
tHLD
tSU tSU
tPD
tPD tPD
tHLD tHLD
HI5731
6
Typical P erformance Curves
FIGURE 4. TYPICAL PO WER DISSIPATION O VER
TEMPERATURE FIGURE 5. TYPICAL REFERENCE VO L TAGE O VER
TEMPERATURE
FIGURE 6. TYPICAL INL FIGURE 7. TYPICAL DNL
FIGURE 8. OFFSET CURRENT OVER TEMPERATURE FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc
-50 -30 -10 10 30 50 70 90
560
600
640
680
TEMPERATURE
(mW)
CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
-50 -30 -10 10 30 50 70 90
-1.29
-1.27
-1.25
-1.23
-1.21
TEMPERATURE
(V)
0 600 1200 1800 2400 3000 3600 4200
1.5
-0.5
0.5
1.5
CODE
(LSB)
400 1000 1600 2200 2800 3400 4000
-0.8
-0.4
0.0
0.4
0.8
CODE
(LSB)
-40 -20 -0 20 40 60 80 100
TEMPERATURE
(µA)
12
16
20
24
28 ∆MKR -87.33dB
-73kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 1.237MHz
S
C
fC = 10MSPS
HI5731
7
FIGURE 10. SPURIOUS FREE DYNAMIC RANGE = 76.16dBc FIGURE 11. SPURIOUS FREE DYNAMIC RANGE = 75.17dBc
FIGURE 12. SPURIOUS FREE DYNAMIC RANGE = -81.67dBc FIGURE 13. SPURIOUS FREE DYNAMIC RANGE = 77dBc
FIGURE 14. SPURIOUS FREE DYNAMIC RANGE = -85.60dBc FIGURE 15. SPURIOUS FREE DYNAMIC RANGE = 85.5dBc
Typical P erformance Curves (Continued)
∆MKR -76.16dB
-53kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 5.055MHz
C
fC = 20MSPS
∆MKR -75.17dB
-70kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 10.00MHzCENTER 16.00MHz
C
S
fC = 40MSPS
∆MKR -81.67dB
-953kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 10.100MHz
C
S
fC = 50MSPS
∆MKR -77.00dB
-93kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 5.097MHz
C
fC = 80MSPS
∆MKR -85.60dB
-33kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 2.027MHz
S
C
fC = 100MSPS
∆MKR -85.50dB
73kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 5.000MHz
S
C
fC = 100MSPS
HI5731
8
FIGURE 16. SPURIOUS FREE DYNAMIC RANGE = 80.5dBc FIGURE 17. SPURIOUS FREE DYNAMIC RANGE = 72.17dBc
FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc FIGURE 19. SPURIOUS FREE DYNAMIC RANGE = 70.5dBc
FIGURE 20. SPURIOUS FREE DYN AMIC RANGE = 70dBc
Typical P erformance Curves (Continued)
∆MKR -80.50dB
-807kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 10.133MHz
fC = 100MSPS
∆MKR -72.17dB
-467kHz
10dB/
ATTEN 20dB
RL -10.0dBm
SPAN 2.000MHzCENTER 26.637MHz
C
S
fC = 100MSPS
∆MKR -71.16dB
2.99MHz
10dB/
ATTEN 20dB
RL -10.0dBm
C
S
STOP FREQUENCY 20MHzSTART FREQUENCY 500kHz
fC = 40MSPS
fO = 2.02MHz
∆MKR -70.50dB
1.98MHz
10dB/
ATTEN 20dB
RL -10.0dBm
STOP FREQUENCY 40MHzSTART FREQUENCY 500kHz
C
S
fC = 80MSPS
fO = 2.02MHz
∆MKR -70.00dB
4.13MHz
10dB/
ATTEN 20dB
RL -10.0dBm
C
S
STOP FREQUENCY 50MHzSTART FREQUENCY 500kHz
fC = 100MSPS
fO = 2.02MHz
HI5731
9
Detailed Description
The HI5731 is a 12 -bit, current out D/A con verter . The D AC can
conv ert at 100MSPS and runs on +5V and -5.2V supplies. The
architecture is an R/2R and segmented switching current cell
arrangement to reduce glitch. Laser trimming is employ ed to
tune linearity to true 12-bit lev els. The HI5731 achie v es its low
power and high speed perf ormance from an advanced
BiCMOS process. The HI5731 consumes 650mW (typical) and
has an improved hold time of only 0.25ns (typical). The HI5731
is an excellent conv erter for use in communications applications
and high performance instrumentation systems.
Digital Inputs
The HI5731 is a TTL/CMOS compatible D/A. Data is latched
by a Master register. Once latched, data inputs D0 (LSB)
thru D11 (MSB) are internally translated fro m TTL to ECL.
The internal latch and switching current source controls are
implemented in ECL technology to maintain high switchi ng
speeds and low noise characteristics.
Decoder/Driver
The architecture employs a split R/2R ladder and
Segmented Current source arrangement. Bits D0 (LSB) thru
D7 directly drive a typical R/2R network to create the binary
weighted current sources. Bits D8 thru D11 (MSB) pass thru
a “therm ometer” decoder that converts the incoming data
into 15 individual segmented current source enables. This
split architecture helps to improve glitch, thus resulti ng in a
more constant glitch characteristic across the entire output
transf er function.
Clocks and Termination
The internal 12-bit register is updated on the rising edge of
the clock. Since the HI5731 clock rate can run to 100MSPS,
to minimize reflections and clock noise into the part proper
termination should be used. In PCB lay out cloc k runs should
be kept short and have a minimum of loads. To guarantee
consistent results from board to board controlled impedance
PCBs should be used with a characteristic line impeda nce
ZO of 50Ω.
To terminate the clock line, a shunt terminator to ground is
the most effective type at a 100MSPS clock rate. A typical
value for termination can be determined by the equation:
RT = ZO,
for the te rmination resistor. For a controlled impedance
board with a ZO of 50Ω, the RT = 50Ω. Shunt termination is
best used at the receiving end of the transmission line or as
close to the HI5731 CLK pin as possible.
Rise and Fall times and propagati on delay of the line will be
affected by the Shunt Terminator. The terminator should be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1µF and 0.01µF
ceramic capacitors placed as close to the body of the
Pin Descriptions
PIN NUMBER PIN NAME PIN DESCRIPTION
1-12 D11 (MSB) thru
D0 (LSB) Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit.
15 CLK Data Clock Pin DC to 100MSPS.
13, 14 NC No Connect.
16 DVCC Digital Logic Supply +5V.
17, 28 DGND Digital Ground.
18 DVEE -5.2V Logic supply.
23 RSET External resistor to set the full scale output current. IFS = 16 x (VREF OUT / RSET). Typically 976Ω.
27 AGND Analog Ground supply current return pin.
19 ARTN Analog Signal Return for the R/2R ladder.
21 IOUT Current Output Pin.
20 IOUT Complementary Current Output Pin.
22 AVEE -5.2V Analog Supply.
24 CTRL IN Input to the current source base rail. Typically connected to CTRL OUT and a 0.1µF capacitor to AVEE. Allows
external control of the current sources.
25 CTRL OUT Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that
IFS = 16 x (VREF OUT / RSET).
26 REF OUT -1.23V (Typ) bandgap reference voltage output. Can sink up to 125µA or be overdriven by an external
reference capable of delivering up to 2mA.
FIGURE 21. CLOCK LINE TERMINATION
RT = 50Ω
HI5731
DAC
CLK
ZO = 50Ω
HI5731
10
HI5731 as possible on the analog (AVEE) and digital (DVEE)
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
operation on power u p. The VCC power pin should also be
decoupled with a 0.1µF capacitor.
Reference
The internal reference of the HI5731 is a -1.23V (typical)
bandgap voltage reference with 175µV/oC of temperature
drift (typical). The internal reference is connected to the
Control Amplifier which in turn drives the segmented current
cells. Reference Out (REF OUT) is internally connected to
the Control Amplifier. The Contro l Amplifier Output (CTRL
OUT) should be used to drive the Control Amplifier Input
(CTRL IN) and a 0.1µF capacitor to analog VEE. This
improves settling time by providing an AC ground at the
current source base node. The Full Scale Output Current is
controlled by the REF OUT pin and the set resistor (RSET).
The ratio is:
IOUT (Full Scale) = (VREF OUT/RSET) x 16,
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provi de better
perf ormance ov er temperature. Figure 22 illustrates a typical
external reference configuration.
Multipl ying Capability
The HI5731 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
of up to 0.6VP-P can be applied directly to the REF OUT pin
as shown in Figure 23.
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in seri es with REF OU T if DC multiplying is not
required. The lower input bandwidth can be calculated using
the following formula:
For multiplying frequenci es above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 24.
The nominal input/outp ut relationship is defined as:
In order to prev ent the full scale output current from
exceeding 20.48mA, the RSET resistor must be adjusted
according to the following equation:
The circuit in Figure 24 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Tab le 1 below
illustrates the relationship.
Also, the input sign al must be limited to 1VP-P to av oid
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
Outputs
The outputs IOUT and IOUT are complementary current
outputs. Current is steered to either IOUT or IOUT in
proportion to the digi tal input code. The sum of the two
currents is alwa ys equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a load resistor. Both current outputs should have the
same load resistor (64Ω typically). By usi n g a 64Ω load on
the output, a 50Ω effective output resistance (ROUT) is
achieved due to the 227Ω (±15%) parallel resistance seen
looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50Ω output is needed for
matching the output with a 50Ω line. The load resistor should
FIGURE 22. EXTERNAL REFERENCE CONFIGURATION
(26) REF OUT
HI5731
R
-5.2V
-1.25V
FIGURE 23. LOW FREQUENCY MULTIPLYING BAND WIDTH
CIRCUIT
REF OUT
HI5731
CIN (OPTIONAL)
0.01µF
RSET
VIN
CTRL OUT
CTRL IN
AVEE
TABLE 1. CAPACITOR SELECTION
fIN C1 C2
100kHz 0.01µF1µF
>1MHz 0.001µF0.1µF
CIN 1
2π()1400()fIN
()
------------------------------------------- .=
FIGURE 24. HIGH FREQUENCY MULTIPLYING BAND WIDTH
CIRCUIT
HI5731
CTRL IN
VIN
CTRL OUT
AVEE
200ΩC2
C1
50Ω
∆IOUT
∆VIN
80Ω
--------------.=
RSET 16VREF
IOUT(FULL SCALE) VIN PEAK()
80Ω
-----------------------------
–
----------------------------------------------------------------------------------------------- .=
HI5731
11
be chosen so that the effective output resistance (ROUT)
matches the line resistance. The output voltage is:
VOUT = IOUT x ROUT.
IOUT is defined in the reference section. IOUT is not trimmed
to 12 bits, so it is not recommended that it be used in
conjunction with IOUT in a differential-to-single-ended
application. The compliance range of the output is from -
1.25V to 0V, with a 1VP-P voltage swing allowed within this
range.
Settling Time
The settling ti me of the HI5731 is measured as the time it
takes for the output of the DAC to settle to within a ±1/2 LSB
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performan ce of the
HI5731 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
Glitch
The output glitch of the HI5731 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymme trical mean i ng that the turn off time is
faster th an the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. In order to minimize this, the
Intersil HI5731 employes an internal register , just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converte rs usually
occurs at the major transition (i.e., code 2047 to 2048).
However, due to the split architecture of the HI5731, the
glitch is moved to the 255 to 256 transition (and every
subsequent 256 code transitions thereafter). This split R/2R
segmented current source architecture, which decreases the
amount of current switching at any one time, makes the
glitch practically constant over the entire output range. By
making the glitch a constant size ov er the entire output range
this effectively integrates this error out of the end application.
In measuring the output glitch of the HI5731 the output is
ter m inated into a 64Ω load. The glitch is measured at any
one of the current cell carry (code 255 to 256 transition or
any multiple thereof) throughout the DACs output range.
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 26 shows the area considered
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
Applications
Bipolar Applications
To convert the output of the HI5731 to a bipolar 4V swing,
the fol lowing applications circuit is recommended. The
reference can only provide 125µA of drive, so it must be
buffered to create the bipolar offset current needed to
generate the -2V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the vo l tag e swing and error.
TABLE 2. INPUT CODING vs CURRENT OUTPUT
INPUT CODE (D11-D0) IOUT (mA) IOUT (mA)
1111 1111 1111 -20.48 0
1000 0000 0000 -10.24 -10.24
0000 0000 0000 0 -20.48
(21) IOUT 100MHz
LOW PASS
FILTER
SCOPE
HI5731
64Ω50Ω
FIGURE 25. GLITCH TEST CIRCUIT
FIGURE 26. MEASURING GLITCH ENERGY
a (mV)
t (ns)
GLITCH ENERGY = (a x t)/2
HI5731
REF OUT
IOUT
1/2 CA2904
+
-+
-
+
-
50Ω
5kΩ1/2 CA2904
5kΩ
60Ω
240Ω
240Ω
HFA1100
VOUT
0.1µF
FIGURE 27. BIPOLAR OUTPUT CONFIGURATION
(21)
(26)
HI5731
12
Interfacing to the HSP45106 NCO-16
The HSP45106 is a 16-bit, Numerically Controlled Oscillator
(NCO). The HSP45106 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 28 shows how to interface an HI5731 to
the HSP45106.
Interfacing to the HSP45102 NCO-12
The HSP45102 is a 12-bit, Numerically Controlled Oscillator
(NCO). The HSP45102 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 29 shows how to interface an HI5731 to
the HSP45102.
This high level block diagram is that of a basic PSK
modulator. In this example the encoder generates the PSK
wa vef orm by driving the Phase Modulation Inputs (P1, P0) of
the HSP45102. The P1-0 inputs impart a phase shift to the
carrier wa ve as defined in Table 2.
The data port of the HSP45102 drives the 12-bit HI5731
DAC which converts the NCO output into an analog
waveform. The output filter connected to the DAC can be
tailored to remove unwanted spurs for the desired carrier
frequency. The controller is used to load the desired center
frequency and control the HSP45102. The HI5731 coupled
with the HSP45102 make an inexpensive PSK modulato r
with Spurious Free performance down to -76dBc.
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates fro m a best fit straight line of data
values along the transfer curve.
Differential Li neari ty Error, DNL, is the measure of the
error in step size between adjacent codes along the
conv erter’ s transf er curve. Ideally, the step size is 1 LSB from
one code to the next, and the deviation from 1 LSB is known
as DNL. A DNL specification of greater than -1 LSB
guara nt ee s mo notonicity.
Feedthru, is the measure of the undesirable s witching noise
coupled to the output.
Output Voltage Full Scale Settling Time, is the time
required from the 50% point on the clock input for a full scale
step to settle within an ±1/2 LSB error band.
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input fo r a 100mV
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area, GE, is the switching transient appearing on the
output dur ing a code transition. It is measured as the area
under the curve and exp r essed as a picoVolt-time
specification (typically pV-s).
Differential Gain, ∆AV, is the gain error from an ideal sine
wa ve with a normalized amplitude.
Differential Phase, ∆Φ, is the phase error from an ideal sine
wave.
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics
are ignored, and an output filter of 1/2 the clock frequency is
used to eliminate alias products.
Total Harmonic Di stortion, THD, is the ra tio of the DAC
output fundamental to the RMS sum of the harmonics. The
first 5 har monics are included, and an ou tput filter of 1/2 the
clock frequency is used to eliminate alias products.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur . A sine wa ve is loaded into the
D/A and the output filtered at 1/2 the cl ock frequency to
eliminate noise from clocking alias terms.
Intermodulation Distortion, IMD , is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
TABLE 3. PHASE MODULATION INPUT CODING
P1 P0 PHASE SHIFT (DEGREES)
00 0
01 90
1 0 270
1 1 180
IMD 20Log (RMS of Sum and Difference Distortion Products)
RMS Amplitude of the Fundamental()
-------------------------------------------------------------------------------------------------------------------------------------------------------.=
HI5731
13
ENCODER
CONTROLLER
BASEBAND
BIT
STREAM
K9
C11
B11
33MSPS
CLK CLK
MOD2
MOD1
HSP45106
SIN15
R4
50
1
2
3
4
5
6
7
8
9
10
15
28
17
18
U2
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
DVCC
VCC 16 U1
CLK
DGND
HI5731
DVEE
DGND
-5.2V_D AVEE
AVSS
IOUT
IOUT
CNTRL OUT
CNTRL IN
RSET
ARET
REF OUT
21
20
24
25
26
23
19
27
22
R1
64
R2
64
R3
976
C2 0.1µF
C1 0.01µF
-5.2V_A
-5.2V_A
FILTER TO RF
UP-CONVERT
STAGE
L2
10µH
L1
10µH-5.2V_A-5.2V_D
C10 MOD0
A11
F10
F9
F11
H11
G11
G9
J11
G10
D10
J10
K11
B8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
B10
B9
A10
E11
E9
H10
K2
J2
A8
VCC
VCC
VCC
PMSEL
ENPOREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
INITPAC
INITTAC
TEST
PARSER
BINFMT
C15_MSB
C4
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
A2
A1
A0
CS
WR
PACI
OES
OEC
DACSTRB
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
L1
K3
L2
L3
L4
J5
K5
L5
K6
J6
J7
L7
L6
L8
K8
L9
L10
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
TICO
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
K1
B2
11
12 D1
D0 (LSB)
-5.2V_A
FIGURE 28. MODULATOR USING THE HI5731 AND THE HSP45106 16-BIT NCO
HI5731
14
ENCODER
CONTROLLER
BASEBAND
BIT
STREAM
CONTROL
BUS
16
19
20
18
17
12
9
14
13
10
11
I
Q
40MSPS
CLK CLK
P1
P0
LOAD#
TXFR#
ENPHAC#
SEL_L/M#
SCLK
SD
SFTEN#
MSB/LSB#
HSP45102
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
6
5
4
3
2
1
28
27
26
25
24
23
R4
50
U1
L2
10µH
L1
10
µ
H
-5.2V_A-5.2V_D
1
2
3
4
5
6
7
8
9
10
15
28
17
18
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
DVCC
VCC 16 U2
CLK
DGND
HI5731
DVEE
DGND
-5.2V_D AVEE
AVSS
IOUT
IOUT
CNTRL OUT
CNTRL IN
RSET
ARET
REF OUT
21
20
24
25
26
23
19
27
22
R1
64
R2
64
R3
976
C2 0.1µF
C1 0.01µF
-5.2V_A
-5.2V_A
FILTER TO RF
UP-CONVERT
STAGE
11
12 D1
D0 (LSB)
-5.2V_A
FIGURE 29. PSK MODULATOR USING THE HI5731 AND THE HSP45102 12-BIT NCO
HI5731
15
Die Characteristics
DIE DIMENSIONS
161.5 mils x 160.7 mils x 19 mils
METALLIZATION
Type: AlSiCu
Thickness: M1 - 8kÅ, M2 - 17kÅ
PASSIVATION
Type: Sand w i c h Passiva ti o n
Undoped Silicon Glass (USG) + Nitride
Thickness: USG - 8kÅ, Nitride - 4.2kÅ
Total 12.2kÅ + 2kÅ
SUBSTRAT E POTENTIAL (POWERED UP)
VEED
Metallization Mask Layout HI5731
D8 D9 D10 D11 DGND
AGND
REF OUT
CTRL OUT
IOUT
IOUT
ARTN
DVEE
DGNDDVCC
CLKD0
D1
D2
D3
D4
D5
D6
D7
RSET
AVEE
CTRL IN
HI5731
16
HI5731
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C 0.008 0.015 0.204 0.381 -
D 1.380 1.565 35.1 39.7 5
D1 0.005 - 0.13 - 5
E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB- 0.700 - 17.78 7
L 0.115 0.200 2.93 5.08 4
N28 289
Rev. 1 12/00
17
All Intersil products are manuf actured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s q uality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to v erify that dat a sheets are curre nt bef ore placing orders . Information furnished by Intersil is belie v ed to be accur ate and relia bl e. Ho w-
ev er, no responsibility is assumed b y Intersil or its subsi diaries f or its use; nor f or an y infringements of patents or ot her rights of third parties which may result from its use . No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
HI5731
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
α0o8o0o8o-
Rev. 0 12/93
