M29KW016E 16 Mbit (1Mb x16, Uniform Block) 3V Supply LightFlashTM Memory PRELIMINARY DATA FEATURES SUMMARY SUPPLY VOLTAGE Figure 1. Packages - VCC = 2.7V to 3.6V for Read - VPP = 11.4V to 12.6V for Program and Erase ACCESS TIME: 90, 110ns PROGRAMMING TIME - 9s per Word typical - Multiple Word Programming Option (2s typical Chip Program) SO44 (M) ERASE TIME - 11s typical factory Chip Erase UNIFORM BLOCKS - 8 blocks of 2 Mbits PROGRAM/ERASE CONTROLLER - Embedded Word Program algorithms 10,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE TSOP48 (N) 12 x 20mm FBGA - Manufacturer Code: 0020h - Device Code : 88ABh TFBGA48 (ZA) 6 x 9mm July 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/31 M29KW016E TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 5. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Multiple Word Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/31 M29KW016E STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VPP Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7. Multiple Word Program Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 14. Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16. Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline . . . . . . . . 24 Table 17. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . 24 Figure 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 25 Table 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 25 Figure 17. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline . . . . 26 Table 19. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . . 26 Figure 18. TFBGA48 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 27 Figure 19. TFBGA48 Daisy Chain - PCB Connections (Top view through package) . . . . . . . . . . . 28 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 21. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 22. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3/31 M29KW016E SUMMARY DESCRIPTION The M29KW016E LightFlashTM is a 16 Mbit (1Mb x16) non-volatile memory that can be read, erased and reprogrammed. Read operations can be performed using a single low voltage (2.7 to 3.6V) supply. Program and Erase operations require an additional VPP (11.4 to 12.6) power supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into 8 uniform blocks that can be erased independently so it is possible to preserve valid data while old data is erased (see Figures 2, Block Addresses). Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller (P/E.C.) simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The M29KW016E LightFlashTM features a new command, Multiple Word Program, used to program large streams of data. It greatly reduces the total programming time when a large number of Words are written to the memory at any one time. Using this command the entire memory can be programmed in 2s, compared to 9s using the standard Word Program. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in SO44, TSOP48 (12 x 20mm) and TFBGA48 (6 x 9mm, 0.8mm pitch) packages. The memory is supplied with all the bits erased (set to '1'). 4/31 Figure 2. Logic Diagram VCC VPP 20 16 A0-A19 DQ0-DQ15 W E M29KW016E G RP RB VSS AI04371 Note: RB not available on SO44 package. Table 1. Signal Names A0-A19 Address Inputs DQ0-DQ15 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable RP Reset RB Ready/Busy Output (not available on SO44 package) VCC Supply Voltage read VPP Supply Voltage program erase VSS Ground NC Not Connected Internally M29KW016E Figure 3. SO Connections Figure 4. TSOP Connections A15 RP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 44 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 11 M29KW016E 34 33 12 32 13 31 14 30 15 29 16 17 28 18 27 19 26 20 25 21 24 22 23 W A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 VPP VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC 1 48 A14 A13 A12 A11 A10 A9 A8 A19 NC W RP NC VPP 12 37 M29KW016E 13 36 AI04377 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 24 25 DQ0 G VSS E A0 AI04376b 5/31 M29KW016E Figure 5. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A A3 A7 RB W A9 A13 B A4 A17 VPP RP A8 A12 C A2 A6 A18 NC A10 A14 D A1 A5 NC A19 A11 A15 E A0 DQ0 DQ2 DQ5 DQ7 A16 F E DQ8 DQ10 DQ12 DQ14 NC G G DQ9 DQ11 VCC DQ13 DQ15 H VSS DQ1 DQ3 DQ4 DQ6 VSS AI04373 Table 2. Block Addresses Block Number Address Range 8 E0000h-FFFFFh 7 C0000h-DFFFFh 6 A0000h-BFFFFh 5 80000h-9FFFFh 4 60000h-7FFFFh 3 40000h-5FFFFh 2 20000h-3FFFFh 1 00000h-1FFFFh 6/31 M29KW016E SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Reset (RP). The Reset pin can be used to apply a Hardware Reset to the memory. A Hardware Reset is achieved by holding Reset Low, V IL, for at least tPLPX. After Reset goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or t RHEL, whichever occurs last. See the Ready/Busy Output section, Table 16 and Figure 14, Reset AC Characteristics for more details. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read. Ready/Busy is high-impedance during Read mode and Auto Select mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 16 and Figure 14, Reset AC Characteristics. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low during Read/Reset commands or Hardware Resets until the memory is ready to enter Read mode. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. VCC Supply Voltage. The VCC Supply Voltage supplies the power for Read operations. The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. V PP Program Supply Voltage. VPP is both a power supply and Write Protect pin. The two functions are selected by the voltage range applied to the pin. The Supply Voltage VCC must be applied before the Program Supply Voltage VPP. If VPP is in the range 11.4V to 12.6V it acts as a power supply pin for program and erase operations. VPP must be stable until the Program/Erase algorithm is completed. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a Write Protect pin. In this case a voltage lower than VHH gives an absolute protection against program or erase, while V PP in the range of V HH enables these functions (see Table 12, DC Characteristics for the relevant values). Note that VPP must not be left floating or unconnected as the device may become unreliable. Vss Ground. The VSS Ground is the reference for all voltage measurements. 7/31 M29KW016E BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby, Automatic Standby and Electronic Signature. See Tables 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11, Read Mode AC Waveforms, and Table 13, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 12 and 13, Write AC Waveforms, and Tables 14 and 15, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 12, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 3, Bus Operations. Table 3. Bus Operations Address Inputs A0-A19 Data Inputs/Outputs DQ15-DQ0 E G W VPP Bus Read VIL VIL VIH XX(4) Cell Address Bus Write VIL VIH VIL VHH(3) Command Address X VIH VIH X X Hi-Z Standby VIH X X X X Hi-Z Read Manufacturer Code VIL VIL VIH XX A0 = VIL, A1 = VIL, Others VIL or VIH 0020h Read Device Code VIL VIL VIH XX A0 = VIH, A1 = VIL, Others VIL or VIH 88ABh Operation Output Disable Note: 1. 2. 3. 4. 8/31 X = VIL or VIH. XX = VIL , VIH or VHH Not necessary for Auto Select or Read/Reset commands. When reading the Status Register during Program or Erase operations, V PP must be kept at VHH. Data Output Data Input M29KW016E COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. Refer to Tables 4 and 5, for a summary of the commands. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command is executed regardless of the value of VPP (VIL, VIH or VHH). Auto Select Command. The Auto Select command is used to read the Manufacturer Code and the Device Code. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued, all other commands are ignored. The Auto Select command is executed regardless of the value of VPP (VIL, VIH or VHH). From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. Word Program Command. The Word Program command can be used to program a Word to the memory array. V PP must be set to V HH during Word Program. If VPP is set to either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Multiple Word Program Command The Multiple Word Program command can be used to program large streams of data. It greatly reduces the total programming time when a large number of Words are written to the memory at any one time. V PP must be set to VHH during Multiple Word Program. If VPP is set to either VIL or VIH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. It has four phases: the Setup Phase to initiate the command, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Setup Phase. The Multiple Word Program command requires three Bus Write operations to initiate the command (refer to Table 5, Multiple Word Program Command and Figure 6, Multiple Word Program Flowchart). The Status Register Toggle bit (DQ6) should be checked to verify that the operation has started and the Multiple Word Program bit (DQ0) checked to verify that the P/E.C. is ready for the first Word. Program Phase. The Program Phase requires n+1 cycles, where n is the number of Words, to execute the programming phase (refer to Table 5, Multiple Word Program Command and Figure 6, Multiple Word Program Flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. The fourth Bus Write operation of the command latches the Start Address and the first Word to be programmed. The Status Register Multiple Word Program bit (DQ0) should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can remain the Start Address, be incremented or be any address in the same block, as the device automatically increments the address with each sucssesive Bus Write 9/31 M29KW016E cycle. If the command is used to program in more than one block then the address must remain in the starting block as any address that is not in the same block as the Start Address terminates the Program operation. The Status Register Multiple Word Program bit (DQ0) must be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate the programming phase. The memory is now set to enter the Verify Phase. Verify Phase. The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. If the check fails the P/E.C will try to reprogram the correct data. The P/E.C will remain busy until the correct data has been successfully programmed. The Verify Phase is mandatory. If the Verify Phase is not executed the programmed data cannot be guaranteed. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register Multiple Word Program bit (DQ0) should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be verified is latched with a new Bus Write operation. If any address that is not in the same block as the Start Address is given, the Verify operation terminates. The Status Register Multiple Word Program (DQ0) must be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation to any address outside the block containing the Start Address, to terminate the Verify Phase. Exit Phase . Read the Status Register to verify that DQ6 has stopped toggling. If the Verify Phase is successfully completed the memory returns to the Read mode. If the P/E.C. fails to reprogram a given location, the Verify Phase will terminate and Error bit DQ5 will be set in the Status Register. If the error is due to a V PP failure DQ4 will also be set. If the operation fails a Read/Reset command must be issued to return the device to Read mode. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. 10/31 Note that the Multiple Word Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Block Erase Command. The Block Erase command can be used to erase a block. It sets all of the bits in the block to '1'. All previous data in the block is lost. VPP must be set to V HH during Block Erase. If VPP is set to either V IL or V IH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. Six Bus Write operations are required to select the block . The Block Erase operation starts the Program/Erase Controller after the last Bus Write operation. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. During the Block Erase operation the memory will ignore all commands. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Chip Erase Command. The Chip Erase command can be used to erase the entire memory. It sets all of the bits in the memory to '1'. All previous data in the memory is lost. VPP must be set to V HH during Chip Erase. If VPP is set to either V IL or V IH the command will be ignored, the data will remain unchanged and the device will revert to Read/Reset mode. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. M29KW016E Table 4. Standard Commands Length Command Bus Write Operations 1st 2nd Add Data 1 X F0 3 555 Auto Select 3 Word Program 3rd 4th Add Data Add Data AA 2AA 55 X F0 555 AA 2AA 55 555 90 4 555 AA 2AA 55 555 Block Erase 6+ 555 AA 2AA 55 Chip Erase 6 555 AA 2AA 55 5th Add Data A0 PA PD 555 80 555 555 80 555 6th Add Data Add Data AA 2AA 55 BA 30 AA 2AA 55 555 10 Read/Reset Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ15 are Don't Care. Length Table 5. Multiple Word Program Command Phase Bus Write Operations 1st 2nd 3rd 4th 5th Final -1 Final Add Data Add Data Add Data Add Data Add Data Add Data Add Data Program 3+n +1 555 AA 2AA 55 555 20 PA1 PD1 PA1 PD2 PA1 PAn NOT PA1 X Verify n+1 PA1 PD1 PA1 PD2 PA1 PD3 PA1 PD4 PA1 PD5 PA1 PAn NOT PA1 X Note: A Bus Read must be done between each Write cycle where the data is programmed or verified, to Read the Status Register and check that the memory is ready to accept the next data. NOT PA1 is any address that is not in the same block as PA1. X Don't Care, n = number of Words to be programmed. Table 6. Program, Erase Times and Program, Erase Endurance Cycles Typ (1) Typical after 10k W/E Cycles (1) Max Unit Chip Erase 11 25 120 s Block Erase (128 KWords) 1.5 6 s Program (Word) 9 250 s Chip Program (Multiple Word) 2 35 s Chip Program (Word by Word) 9 35 s Parameter Min Program/Erase Cycles (per Block) 10,000 cycles Note: 1. TA = 25C, VPP = 12V. Table 7. Multiple Word Program Timings Symbol Parameter tMWP-SETUP MWP Setup time tMWP-PROG MWP Program Time tMWP-TRAN MWP Program to Verify transition tMWP-END MWP Verify to End transition Min 2 Typ Max Unit 500 ns 9 250 s 10 20 s 2 3 s Note: 1. MWP = Multiple Word Program. 11/31 M29KW016E Figure 6. Multiple Word Program Flowchart Start Setup Phase Verify Phase Read Status Register Write AAh Address 555h (tMWP-TRAN(1)) Write 55h Address 2AAh NO DQ0 = 0? YES Write 20h Address 555h Write Data1 (PD1) Start Address (PA1) Read Status Register Read Status Register NO NO Setup time exceeded? YES NO DQ6 toggling? (tMWP-SETUP(1)) EXIT (setup failed) NO NO DQ0 = 0? YES Word program time exceeded? YES (tMWP-PROG(1)) YES Write Data 2 (PD2) Address in Start Block DQ0 = 0? YES Program Phase Write Data1(PD1) Start Address (PA1) Read Status Register NO Read Status Register NO DQ0 = 0? (tMWP-PROG(1)) YES DQ0 = 0? Word program time exceeded? YES NO Write Data n (PDn) Address in Start Block YES Write Data 2 (PD2) Address in Start Block Read Status Register NO Read Status Register NO DQ0 = 0? (tMWP-PROG(1)) YES DQ0 = 0? Word program time exceeded? YES NO Write XX Any Address NOT in Start Block YES Write Data n (PDn) Address in Start Block Read Status Register YES Read Status Register DQ5 = 1 DQ4 = 0? Fail error Read Status Register DQ6 toggling? DQ0 = 0? Exit Phase NO YES Write XX Any Address NOT in Start Block NO NO Fail, VPP error YES (tMWP-END(1)) Write F0h Address XX Exit (read mode) AI05554c Note: 1. Refer to Table 7, Multiple Word Program Timings, for the values. 12/31 M29KW016E STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. The bits in the Status Register are summarized in Table 8, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Data Polling Bit is output on DQ7 when the Status Register is read. During a Word Program operation the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Word Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. The Data Polling Bit is not available during a Multiple Word Program operation. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. Figure 7, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. Figure 8, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. VPP Status Bit (DQ4). The VPP Status Bit can be used to identify if any Program or Erase operation has failed due to a VPP error. If VPP falls below V HH during any Program or Erase operation, the operation aborts and DQ4 is set to `1'. If VPP remains at VHH throughout the Program or Erase operation, the operation completes and DQ4 is set to `0'. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Block and Chip Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations to any address. Once the operation completes the memory returns to Read mode. If an Erase operation fails and the Error Bit is set, the Alternative Toggle Bit will continue to toggle with successive Bus Read operations to any address. The Alternative Toggle Bit does not change if the addressed block has erased correctly. Multiple Word Program Bit (DQ0). The Multiple Word Program Bit can be used to indicate whether the Program/Erase Controller is active or inactive during Multiple Word Program. When the Program/Erase Controller has written one Word and is ready to accept the next Word, the bit is set to `0'. Status Register Bit DQ1 is reserved. 13/31 M29KW016E Table 8. Status Register Bits Operation Condition DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ0 RB Any Address DQ7 Toggle 0 - - - - 0 VPP = VHH DQ7 Toggle 1 0 - - - 0 VPP < VHH DQ7 Toggle 1 1 - - - 0 Any Address 0 Toggle 0 - 1 Toggle(2) - 0 VPP = VHH 0 Toggle 1 0 1 Toggle(2) - 0 VPP < VHH 0 Toggle 1 1 1 Toggle(2) - 0 P/E.C. active - Toggle 0 - - - 1 0 Multiple Word Program P/E.C. inactive, waiting for next Word - Toggle 0 - - - 0 1 Multiple Word Program Error VPP = VHH - Toggle 1 0 - - 1 0 VPP < VHH - Toggle 1 1 - - 1 0 Word Program Word Program Error Block/ Chip Erase Erase Error Note: 1. Unspecified data bits should be ignored. 2. DQ2 toggles on any address during Block or Chip Erase and after an Erase error. Figure 7. Data Polling Flowchart Figure 8. Data Toggle Flowchart START START READ DQ6 READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA READ DQ5 & DQ6 YES DQ6 = TOGGLE NO NO YES NO DQ5 =1 NO YES DQ5 =1 YES READ DQ7 at VALID ADDRESS READ DQ6 TWICE DQ7 = DATA YES DQ6 = TOGGLE NO FAIL PASS NO YES FAIL PASS AI03598 AI01370B 14/31 M29KW016E MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 9. Absolute Maximum Ratings Symbol Parameter Min Max Unit TBIAS Temperature Under Bias -50 125 C TSTG Storage Temperature -65 150 C VIO Input or Output Voltage (1,2) -0.6 VCC +0.6 V VCC Read Supply Voltage -0.6 4 V VPP Program/Erase Supply Voltage -0.6 13.5 V Note: 1. Minimum voltage may undershoot to -2V for less than 20ns during transitions. 2. Maximum voltage may overshoot to V CC +2V for less than 20ns during transitions. 3. Maximum voltage may overshoot to 14.0V for less than 20ns during transitions. VPP must not remain at VHH for more than a total of 80hrs. 15/31 M29KW016E DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 10, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 10. Operating and AC Measurement Conditions M29KW016E Parameter 90 110 Unit Min Max Min Max VCC Read Supply Voltage 2.7 3.6 2.7 3.6 V VPP Program/Erase Supply Voltage 11.4 12.6 11.4 12.6 V 0 70 0 70 C Ambient Operating Temperature Load Capacitance (CL) 30 30 Input Rise and Fall Times pF 10 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 9. AC Measurement I/O Waveform 10 ns 0 to VCC 0 to VCC V VCC/2 VCC/2 V Figure 10. AC Measurement Load Circuit VCC VCC VCC VCC/2 25k 0V DEVICE UNDER TEST AI05546 0.1F CL 25k CL includes JIG capacitance AI05547 Table 11. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 16/31 Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF M29KW016E Table 12. DC Characteristics Symbol Parameter Test Condition Min Max Unit 0V VIN VCC 1 A ILI Input Leakage Current ILO Output Leakage Current 0V VOUT VCC 1 A ICC1 Supply Current (Read) E = VIL, G = VIH, f = 6MHz 10 mA ICC2 Supply Current (Standby) E = VCC 0.2V, RP = VCC 0.2V 100 A ICC3 Supply Current (Program/Erase) P/E.C. active 20 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 0.7VCC VCC +0.3 V VOL Output Low Voltage IOL = 1.8mA 0.45 V VOH Output High Voltage IOH = -100 A VHH VPP Program/Erase Voltage IHH1 VPP Current (Read/Standby) IHH2 VPP Current (Program/Erase) VLKO Program/Erase Lockout Supply Voltage VCC -0.4 11.4 V 12.6 V VPP = VHH 100 A P/E.C. Active 10 mA 2.3 V 1.8 17/31 M29KW016E Figure 11. Read AC Waveforms tAVAV A0-A19 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGLQV tGHQZ DQ0-DQ15 VALID AI05548 Table 13. Read AC Characteristics M29KW016E Symbol Alt Parameter Test Condition Unit 90 110 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 90 110 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 90 110 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 90 110 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 35 35 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 30 30 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 30 30 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 ns Note: 1. Sampled only, not 100% tested. 18/31 M29KW016E Figure 12. Write AC Waveforms, Write Enable Controlled tAVAV A0-A19 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ15 tWHDX VALID VCC tVCHEL VPP tVPHEL RB tWHRL AI05549 19/31 M29KW016E Table 14. Write AC Characteristics, Write Enable Controlled M29KW016E Symbol Alt Parameter Unit 90 110 tAVAV tWC Address Valid to Next Address Valid Min 90 110 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 35 35 ns tDVWH tDS Input Valid to Write Enable High Min 35 35 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 30 30 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns Read mode Min 0 0 ns Read SR Toggle bits Min 10 10 ns Read mode Min 0 0 ns Read SR Toggle bits in Multiple Word Program Min 20 20 ns Read SR Toggle bits other operations Min 30 30 ns tBUSY Program/Erase Valid to RB Low Max 35 35 ns tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 s tVPHEL(2) tVCS VPP High to Chip Enable Low Min 500 500 ns Output Enable High to Write Enable Low tGHWL tWHGL tWHRL (1) tOEH Write Enable High to Output Enable Low Note: 1. Sampled only, not 100% tested. 2. Not required in Auto Select or Read/Reset command sequences. 20/31 M29KW016E Figure 13. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A19 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ15 tEHDX VALID VCC tVCHWL VPP tVPHWL RB tEHRL AI05550 21/31 M29KW016E Table 15. Write AC Characteristics, Chip Enable Controlled M29KW016E Symbol Alt Parameter Unit 90 110 tAVAV tWC Address Valid to Next Address Valid Min 90 110 ns tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 35 35 ns tDVEH tDS Input Valid to Chip Enable High Min 35 35 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 30 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns Read mode Min 0 0 ns Read SR Toggle bits Min 10 10 ns Read mode Min 0 0 ns Read SR Toggle bits in Multiple Word Program Min 20 20 ns Read SR Toggle bits other operations Min 30 30 ns Output Enable High to Chip Enable Low tGHEL tEHGL tOEH Chip Enable High to Output Enable Low tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 35 35 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 50 s tVPHWL(2) tVCS VPP High to Write Enable Low Min 500 500 ns Note: 1. Sampled only, not 100% tested. 2. Not required in Auto Select or Read/Reset command sequences. 22/31 M29KW016E Figure 14. Reset AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL tPLPX RP tPLYH AI05551 Table 16. Reset AC Characteristics M29KW016E Symbol tPHWL (1) tPHEL Alt Parameter Unit 90 110 tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 50 50 ns tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 ns tPLPX tRP RP Pulse Width Min 500 500 ns tPLYH (1) tREADY RP Low to Read Mode Max 10 10 s tPHGL (1) tRHWL (1) tRHEL (1) tRHGL (1) Note: 1. Sampled only, not 100% tested. 23/31 M29KW016E PACKAGE MECHANICAL Figure 15. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline A A2 C B CP e D N E H 1 A1 L SO-b Note: Drawing is not to scale. Table 17. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data mm inches Symb Typ Min Max A 2.42 A1 A2 Min Max 2.62 0.095 0.103 0.22 0.23 0.009 0.010 2.25 2.35 0.089 0.093 B 0.50 0.020 C 0.10 0.25 0.004 0.010 D 28.10 28.30 1.106 1.114 E 13.20 13.40 0.520 0.528 - - - - 15.90 16.10 0.626 0.634 e 1.27 H 0.050 L 0.80 - - 0.031 - - 3 - - 3 - - N CP 24/31 Typ 44 44 0.10 0.004 M29KW016E Figure 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline A2 N 1 e E B N/2 D1 A CP D DIE C A1 TSOP-a L Note: Drawing is not to scale. Table 18. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.20 Max 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 E 11.90 12.10 0.4685 0.4764 - - - - L 0.50 0.70 0.0197 0.0276 0 5 0 5 N 48 e CP 0.50 0.0197 48 0.10 0.0039 25/31 M29KW016E Figure 17. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Bottom View Package Outline D D1 FD FE SD SE BALL "A1" E E1 ddd e e b A A2 A1 BGA-Z00 Note: Drawing is not to scale. Table 19. TFBGA48 6x9mm - 8x6 ball array, 0.80 mm pitch, Package Mechanical Data millimeters Symbol Typ Min A Max Typ Min 1.200 A1 Max 0.0472 0.200 A2 0.0079 1.000 0.0394 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 D 6.000 5.900 6.100 0.2362 0.2323 0.2402 D1 4.000 - - 0.1575 - - ddd 26/31 inches 0.100 0.0039 E 9.000 8.900 9.100 0.3543 0.3504 0.3583 e 0.800 - - 0.0315 - - E1 5.600 - - 0.2205 - - FD 1.000 - - 0.0394 - - FE 1.700 - - 0.0669 - - SD 0.400 - - 0.0157 - - SE 0.400 - - 0.0157 - - M29KW016E Figure 18. TFBGA48 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 A B C D E F G H AI05552b 27/31 M29KW016E Figure 19. TFBGA48 Daisy Chain - PCB Connections (Top view through package) END POINT START POINT 1 2 3 4 5 6 A B C D E F G H AI05553b 28/31 M29KW016E PART NUMBERING Table 20. Ordering Information Scheme Example: M29KW016E 90 N 1 T Device Type M29K = LightFlashTM Operating Voltage W = VCC = 2.7 to 3.6V Device Function 016E = 16 Mbit (x16) Speed 90 = 90 ns 110 = 110 ns Package M = SO44: N = TSOP48: 12 x 20 mm ZA = TFBGA48: 6 x 9mm - 0.80mm pitch Temperature Range 1 = 0 to 70 C Option T = Tape & Reel Packing Table 21. Daisy Chain Ordering Scheme Example: M29K DCL3-16 T Device Type M29K Daisy Chain DCL3-16 = Daisy Chain Level 3 for 16 Mbit parts Option T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 29/31 M29KW016E REVISION HISTORY Table 22. Document Revision History Date Version 09-Oct-2001 -01 First Issue 26-Mar-2002 -02 LFBGA changed to TFBGA package. Write AC Characteristics tWLWH, tDVWH, tWLAX, tGHWL, tWHGL, tELEH, tDVEH, tELAX, tGHEL and tEHGL modified. Multiple Word Program description and flowchart clarified. Document classed as Product Preview. 07-May-2002 -03 TFBGA Pin F6 changed to NC. Multiple Word Program flowchart clarified, Alternative Toggle Bit DQ2 description clarified, Status Register Bits Table modified. Document classed as Preliminary Data. 12-Jul-2002 -04 Figure 8 modified. 4.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 04 becomes 4.0). Figure 6, Multiple Word Program Flowchart, modified; Table 7, Multiple Word Program Timings, added. 23-Jul-2002 30/31 Revision Details M29KW016E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subjec to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are no authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics LightFlash is a trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 31/31