SPRS073B – AUGUST 1998 – REVISED APRIL 2000
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Best Price/Performance Digital Signal
Processors (DSPs)
Fixed-Point: TMS320C6211
Floating-Point: TMS320C6711
– 10-, 6.7-ns Instruction Cycle Time
– 100-, 150-MHz Clock Rates
– Eight 32-Bit Instructions/Cycle
– 1200 MIPS (’C6211)
– 900 MFLOPS (’C6711)
– ’C6211 and ’C6711 are Pin-Compatible
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C6200 CPU Core (’C6211)
– Eight Highly Independent Functional
Units:
– Six ALUs (32-/40-Bit)
– Two 16-Bit Multipliers (32-Bit Results)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C6700 CPU Core (’C6711)
– Eight Highly Independent Functional
Units:
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions (’C6711
Only)
– Hardware Support for IEEE
Double-Precision Instructions (’C6711
Only)
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
L1/L2 Memory Architecture
– 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
– 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
– 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
– 1024M-Byte Addressable External
Memory Space
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Enhanced Direct-Memory-Access (EDMA)
Controller
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package
(GFN Suffix)
0.18-µm/5-Level Metal Process
– CMOS Technology
3.3-V I/Os, 1.8-V Internal
ADVANCE INFORMATION
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
VelociTI is a trademark of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Table of Contents
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 26.
parameter measurement information 27. . . . . . . . . . . . . . .
input and output clocks 28. . . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 31. . . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 34. . . . . . . . . . . . . . . . .
synchronous DRAM timing 36. . . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 42. . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 45. . . . . . . . . . . . . . . . . . . . . . . . . .
host-port interface timing 46. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 49. . . . . . . . . . . . .
timer timing 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG test-port timing 61. . . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GFN BGA package (bottom view) 2. . . . . . . . . . . . . . . . . . . . . .
description 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device compatibility 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU diagram 5. . . . . . . . . . . . . . . . . . . . .
CPU description 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal groups description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
signal descriptions 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
documentation support 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
clock PLL 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 26. . . . . . . . . . . . . . . . . . .
GFN BGA package (bottom view)
1915 1713119
Y
V
T
U
P
N
R
W
75
L
J
K
H
F
G
31
D
B
C
A
E
M
2468 201816141210
GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
description
The TMS320C62x DSPs (including the TMS320C6211 device) are the fixed-point DSP family in the
TMS320C6000 platform. The TMS320C67x DSPs (including the TMS320C6711 device) are the
floating-point DSP family in the TMS320C6000 platform. The TMS320C6211 (’C6211) and TMS320C6711
(’C6711) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and
multifunction applications.
With performance of up to 1200 million instructions per second (MIPS) at a clock rate of 150 MHz, the ’C6211
device offers cost-effective solutions to high-performance DSP programming challenges. The ’C6211 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional
units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and
two 16-bit multipliers for a 32-bit result. The ’C6211 can produce two multiply-accumulates (MACs) per cycle
for a total of 300 million MACs per second (MMACS).
With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of
150 MHz, the ’C6711 device also offers cost-effective solutions to high-performance DSP programming
challenges. The 100-MHz device is the lowest-cost DSP in the ’C6000 family. The ’C6711 DSP possesses the
operational flexibility of high-speed controllers and the numerical capability of array processors. This processor
has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight
functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point
multipliers. The ’C6711 can produce two MACs per cycle for a total of 300 MMACS.
Both the ’C6211 and ’C6711 DSPs have the same application-specific hardware logic, on-chip memory, and
additional on-chip peripherals.
The ’C6211/’C6711 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two.The peripheral set includes two multichannel buf fered serial ports (McBSPs),
two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)
capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.
The ’C6211/’C6711 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source
code execution.
ADVANCE INFORMATION
TMS320C62x, TMS320C6000, and TMS320C67x are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device characteristics
Table 1 provides an overview of the ’C6211/’C6711 DSP. The table shows significant features of each device,
including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the ’C6211/’C6711 Processors
HARDWARE FEATURES ’C6211 (FIXED-POINT DSP) ’C6711 (FLOATING-POINT DSP)
EMIF 1 1
EDMA 1 1
Peripherals HPI 1 1
Peri herals
McBSPs 2 2
32-Bit Timers 2 2
Size (Bytes) 72K 72K
On-Chip Memory Organization 4K-Byte (4KB) L1 Program (L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified Mapped RAM/Cache (L2)
4K-Byte (4KB) L1 Program (L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified Mapped RAM/Cache (L2)
Frequency MHz 150 150, 100
Cycle Time ns 6.7 ns (’6211-150) 6.7 ns (’6711-150)
10 ns (’6711-100 [Lowest-Cost Device])
Voltage
Core (V) 1.8 1.8
Voltage I/O (V) 3.3 3.3
PLL Options CLKIN frequency multiplier Bypass (x1), x4 Bypass (x1), x4
BGA Package 27 x 27 mm 256-Pin BGA (GFN) 256-Pin BGA (GFN)
Process Technology µm0.18 µm0.18 µm
Product Status Product Preview (PP)
Advance Information (AI)
Production Data (PD) AI AI
device compatibility
The TMS320C6211 and ’C6711 devices are pin-compatible and have the same peripheral set; thus, making ne w
system designs easier and providing faster time to market. The following list summarizes the device
characteristic differences between the ’C6211 and ’C6711 devices:
The ’C6211 device has a fixed-point ’C62x CPU, while the ’C6711 device has a floating-point ’C67x CPU.
A 100-MHz version of the ’C6711 is available, providing the lowest-cost entry in the TMS320C6000
platform.
For a more detailed discussion on the similarities/differences between the ’C6211 and ’C6711 devices, see the
How to Begin Development Today with the TMS320C6211 DSP
and
How to Begin Development Today with the
TMS320C6711 DSP
application reports (literature number SPRA474 and SPRA522, respectively).
ADVANCE INFORMATION
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5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block and CPU diagram
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Test
’C6000 CPU†
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1‡.S1‡.M1‡.D1 .D2 .M2‡.S2‡.L2‡
32
SDRAM
ROM/FLASH
SBSRAM
I/O Devices
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way Set
Associative
4K Bytes Total
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
’C6211/’C6711 Digital Signal Processors
†The ’C6211 device has a fixed-point ’C62x CPU, while the ’C6711 device has a floating-point ’C67x CPU.
‡For the ’C6711 device only, in addition to fixed-point instructions, these functional units execute floating-point instructions.
Enhanced
DMA
Controller
(16 channel)
16
L2
Memory
4 Banks
64K Bytes
Total
PLL
(x1, x4)
Timer 0
External
Memory
Interface
(EMIF)
Multichannel
Buffered
Serial Port 1
(McBSP1)
Multichannel
Buffered
Serial Port 0
(McBSP0)
Host Port
Interface
(HPI)
SRAM
Timer 1
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit ins t r u c t i ons to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by w h i c h a l l e i ght units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C62x and ’C67x CPUs from other VLIW
architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and
Figure 1 for the ’C6211 device; and see the functional block and CPU diagram and Figure 2 for the ’C6711
device). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which
the two sets of functional units can access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight
functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two
functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the ’C62x/’C67x CPU is the load/store architecture, where all instructions operate on
registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for
all data transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C62x/’C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing
modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers.
Some registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
ADVANCE INFORMATION
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7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description (continued)
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2X
1X
.L2
.S2
.M2
.D2
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.M1
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.L1
long src
dst
src
2
src
1
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src
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src
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src
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src
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src
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src
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src
1
8
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8
88
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src
2
src
2
src
2
src
2
src
2
src
2
src
2
long src
ÁÁ
DA1
DA2
ST1
LD1
LD2
ST2
32
32
Register
File A
(A0–A15)
long src
long dst
long dst
long src
Data Path B
Data Path A
Register
File B
(B0–B15)
Control
Register
File
Figure 1. TMS320C62x CPU Data Paths
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
CPU description (continued)
8
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8
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
long src
long dst
long dst
long src
8
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2X
1X
.L2†
.S2†
.M2†
.D2
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Á
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
.D1
.M1†
Á
Á
Á
Á
Á
Á
Á
ÁÁ
ÁÁ
Á
Á
Á
.S1†
Á
ÁÁ
ÁÁ
Á
Á
.L1†
Á
Á
Á
Á
Á
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
Á
Á
Control
Register File
Á
DA1
DA2
ST1
LD1 32 LSB
LD2 32 LSB
LD2 32 MSB
32
32
Data Path A
Data Path B
Register
File A
(A0–A15)
Register
File B
(B0–B15)
LD1 32 MSB
32
ST2 32
8
8
8
Á
Á
†For the ’C6711 device only, in addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 2. TMS320C67x CPU Data Paths
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal groups description
HHWIL
HCNTL0
HCNTL1
TRST
EXT_INT7
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Data
Register Select
Half-Word
Select
Reset and
Interrupts
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
HD[15:0]
NMI
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
EXT_INT6
EXT_INT5
EXT_INT4
RESET
RSV4
RSV3
RSV2
RSV1
RSV0
Clock/PLL
CLKIN
CLKOUT1
CLKMODE0
PLLV
PLLG
PLLF
CLKOUT2
EMU2
EMU3
EMU4
EMU5
RSV5
Figure 3. CPU and Peripheral Signals
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
signal groups description (continued)
CE3
ECLKOUT
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Address
Byte Enables
32
20
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
ECLKIN
HOLD
HOLDA
BUSREQ
Bus
Arbitration
ARE/SDCAS/SSADS
Figure 4. Peripheral Signals
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions
SIGNAL
TYPE†
IPD/
‡
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡
DESCRIPTION
CLOCK/PLL
CLKIN A3 I IPU Clock Input
CLKOUT1 D7 O IPD Clock output at device speed
CLKOUT2 Y12 O IPD Clock output at half of device speed
CLKMODE0 C4 I IPU Clock mode select
•Selects whether the CPU clock frequency = input clock frequency x4 or x1
PLLV§A4 A¶PLL analog VCC connection for the low-pass filter
PLLG§C6 A¶PLL analog GND connection for the low-pass filter
PLLF B5 A¶PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS B7 I IPU JTAG test-port mode select
TDO A8 O/Z IPU JTAG test-port data out
TDI A7 I IPU JTAG test-port data in
TCK A6 I IPU JTAG test-port clock
TRST B6 I IPD JTAG test-port reset
EMU5 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 D10 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
EMU1 B9 I/O/Z IPU Emulation pin 1#
EMU0 D9 I/O/Z IPU Emulation pin 0#
RESETS AND INTERRUPTS
RESET A13 I IPU Device reset
NMI C13 I IPD Nonmaskable interrupt
•Edge-driven (rising edge)
EXT_INT7 E3
EXT_INT6 D2
I
IPU
External interrupts
EXT_INT5 C1 I IPU
External
interru ts
•Edge-driven (rising edge)
EXT_INT4 C2
g(gg)
HOST-PORT INTERFACE (HPI)
HINT J20 O IPU Host interrupt (from DSP to host)
HCNTL1 G19 I IPU Host control – selects between control, address, or data registers
HCNTL0 G18 I IPU Host control – selects between control, address, or data registers
HHWIL H20 I IPU Host half-word select – first or second half-word (not necessarily high or low order)
HR/W G20 I IPU Host read or write select
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
§PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these
pins.
¶A = Analog Signal (PLL Filter)
#The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with an external dedicated
resistor in the range of 4.7 kΩ to 5.1 kΩ.
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD15 B14 IPU
HD14 C14 IPU
HD13 A15 IPU
HD12 C15 IPU
HD11 A16 IPU Host-port data
Udft f fdt dd d tl
HD10 B16 IPU •Used for transfer of data, address, and control
•Also controls initialization of DSP modes at reset via
p
ullu
p
/
p
ulldown resistors
HD9 C16 IPU •
Al
so con
t
ro
l
s
i
n
iti
a
li
za
ti
on o
f
DSP
mo
d
es a
t
rese
t
v
i
a pu
ll
up
/
pu
lld
own res
i
s
t
ors
– Device Endian Mode
HD8 B17
I/O/Z
IPU
Device
Endian
Mode
HD8: 0 – Big Endian
1 Little Endian
HD7 A18 I/O/Z IPU 1 – Little Endian
–
Boot mode
HD6 C17 IPU –
Boot
mode
HD[4:3]: 00 – HPI boot
HD5 B18 IPU
HD[4:3]: 00 HPI
boot
01 – 8-bit ROM boot with default timings
10 16 bit ROM boot with default timings
HD4 C19 IPD 10 – 16-bit ROM boot with default timings
11
–
32
-
bit ROM boot with default timings
HD3 C20 IPU
11
–
32
-
bit
ROM
boot
with
default
timings
HD2 D18 IPU
HD1 D20 IPU
HD0 E20 IPU
HAS E18 I IPU Host address strobe
HCS F20 I IPU Host chip select
HDS1 E19 I IPU Host data strobe 1
HDS2 F18 I IPU Host data strobe 2
HRDY H19 O IPU Host ready (from DSP to host)
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 V6 O/Z IPU
CE2 W6 O/Z IPU Memory space enables
•Enabled by bits 28 through 31 of the word address
CE1 W18 O/Z IPU •Enabled by bits 28 through 31 of the word address
•
O
nl
y
o
n
e
asse
rt
ed
du
rin
g
a
n
y
e
xt
e
rn
a
l
da
t
a
access
CE0 V17 O/Z IPU
•Only
one
asserted
during
any
external
data
access
BE3 V5 O/Z IPU
Byte-enable control
BE2 Y4 O/Z IPU
B
yte-ena
bl
e contro
l
•Decoded from the two lowest bits of the internal address
BE1 U19 O/Z IPU
•Decoded
from
the
two
lowest
bits
of
the
internal
address
•Byte-write enables for most types of memory
C b di tl t d t SDRAM d d it k i l (SDQM)
BE0 V20 O/Z IPU
yyy
•Can be directly connected to SDRAM read and write mask signal (SDQM)
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡DESCRIPTION
EMIF – BUS ARBITRATION
HOLDA J18 O/Z IPU Hold-request-acknowledge to the host
HOLD J17 I IPU Hold request from the host
BUSREQ J19 O/Z IPU Bus request output
EMIF – ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL
ECLKIN Y11 I IPD EMIF input clock
ECLKOUT Y10 O IPD EMIF output clock (based on ECLKIN)
ARE/SDCAS/
SSADS V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe
AOE/SDRAS/
SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable
AWE/SDWE/
SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable
ARDY Y5 I IPU Asynchronous memory ready input
EMIF – ADDRESS
EA21 U18
EA20 Y18
EA19 W17
EA18 Y16
EA17 V16
EA16 Y15
EA15 W15
EA14 Y14
EA13 W14
EA12 V14
O/Z
IPU
External address (word address)
EA11 W13 O/Z IPU External address (word address)
EA10 V10
EA9 Y9
EA8 V9
EA7 Y8
EA6 W8
EA5 V8
EA4 W7
EA3 V7
EA2 Y6
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡ DESCRIPTION
EMIF – DATA
ED31 N3
ED30 P3
ED29 P2
ED28 P1
ED27 R2
ED26 R3
ED25 T2
ED24 T1
ED23 U3
ED22 U1
ED21 U2
ED20 V1
ED19 V2
ED18 Y3
ED17 W4
ED16 V4
I/O/Z
IPU
External data
ED15 T19 I/O/Z IPU External data
ED14 T20
ED13 T18
ED12 R20
ED11 R19
ED10 P20
ED9 P18
ED8 N20
ED7 N19
ED6 N18
ED5 M20
ED4 M19
ED3 L19
ED2 L18
ED1 K19
ED0 K18
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
‡IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a resistor in the range of 4.7 kΩ to 5.1 kΩ should be used.]
ADVANCE INFORMATION
SPRS073B – AUGUST 1998 – REVISED APRIL 2000
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
Signal Descriptions (Continued)
SIGNAL
TYPE†
IPD/
DESCRIPTION
NAME NO. TYPE
†
IPD/
IPU‡ DESCRIPTION
TIMERS
TOUT1 F1 O IPD Timer 1 or general-purpose output
TINP1 F2 I IPD Timer 1 or general-purpose input
TOUT0 G1 O IPD Timer 0 or general-purpose output
TINP0 G2 I IPD Timer 0 or general-purpose input
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 E1 I IPD External clock source (as opposed to internal)
CLKR1 M1 I/O/Z IPD Receive clock
CLKX1 L3 I/O/Z IPD Transmit clock
DR1 M2 I IPU Receive data
DX1 L2 O/Z IPU Transmit data
FSR1 M3 I/O/Z IPD Receive frame sync
FSX1 L1 I/O/Z IPD Transmit frame sync
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 K3 I IPD External clock source (as opposed to internal)
CLKR0 H3 I/O/Z IPD Receive clock
CLKX0 G3 I/O/Z IPD Transmit clock
DR0 J1 I IPU Receive data
DX0 H2 O/Z IPU Transmit data
FSR0 J3 I/O/Z IPD Receive frame sync
FSX0 H1 I/O/Z IPD Transmit frame sync
RESERVED FOR TEST
RSV0 C12 O IPU Reserved (leave unconnected,
do not
connect to power or ground)
RSV1
