/ / SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Processors (DSPs) Fixed-Point: TMS320C6211 Floating-Point: TMS320C6711 - 10-, 6.7-ns Instruction Cycle Time - 100-, 150-MHz Clock Rates - Eight 32-Bit Instructions/Cycle - 1200 MIPS ('C6211) - 900 MFLOPS ('C6711) - 'C6211 and 'C6711 are Pin-Compatible VelociTI Advanced Very Long Instruction Word (VLIW) 'C6200 CPU Core ('C6211) - Eight Highly Independent Functional Units: - Six ALUs (32-/40-Bit) - Two 16-Bit Multipliers (32-Bit Results) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional VelociTI Advanced Very Long Instruction Word (VLIW) 'C6700 CPU Core ('C6711) - Eight Highly Independent Functional Units: - Four ALUs (Floating- and Fixed-Point) - Two ALUs (Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Hardware Support for IEEE Single-Precision Instructions ('C6711 Only) - Hardware Support for IEEE Double-Precision Instructions ('C6711 Only) - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation - Bit-Field Extract, Set, Clear - Bit-Counting - Normalization L1/L2 Memory Architecture - 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) - 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) - 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) - 1024M-Byte Addressable External Memory Space 32-Bit External Memory Interface (EMIF) - Glueless Interface to Synchronous Memories: SDRAM and SBSRAM - Glueless Interface to Asynchronous Memories: SRAM and EPROM Enhanced Direct-Memory-Access (EDMA) Controller 16-Bit Host-Port Interface (HPI) - Access to Entire Memory Map Two Multichannel Buffered Serial Ports (McBSPs) - Direct Interface to T1/E1, MVIP, SCSA Framers - ST-Bus-Switching Compatible - Up to 256 Channels Each - AC97-Compatible - Serial-Peripheral-Interface (SPI) Compatible (Motorola) Two 32-Bit General-Purpose Timers Flexible Phase-Locked-Loop (PLL) Clock Generator IEEE-1149.1 (JTAG) Boundary-Scan-Compatible 256-Pin Ball Grid Array (BGA) Package (GFN Suffix) 0.18-m/5-Level Metal Process - CMOS Technology 3.3-V I/Os, 1.8-V Internal ADVANCE INFORMATION Best Price/Performance Digital Signal Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. VelociTI is a trademark of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. Copyright 2000, Texas Instruments Incorporated '&)&* &. ()',+* "& +! *%($"& ') ()()',+"'& (!* ' -$'(%&+ !)+)"*+" + & '+!) *(""+"'&* ) *,#+ +' !& ."+!',+ &'+" POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Table of Contents ADVANCE INFORMATION GFN BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 functional block and CPU diagram . . . . . . . . . . . . . . . . . . . . . 5 CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 recommended operating conditions . . . . . . . . . . . . . . . . . . . 26 electrical characteristics over recommended ranges of supply voltage and operating case temperature . 26 parameter measurement information . . . . . . . . . . . . . . . input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . synchronous-burst memory timing . . . . . . . . . . . . . . . . . synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . multichannel buffered serial port timing . . . . . . . . . . . . . timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GFN BGA package (bottom view) GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) Y W V U T R P N M L K J H G F E D C B A 1 3 2 2 5 4 7 6 POST OFFICE BOX 1443 9 8 11 10 13 12 15 14 17 16 19 18 * HOUSTON, TEXAS 77251-1443 20 27 28 31 34 36 42 43 45 46 49 60 61 62 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 description The TMS320C62x DSPs (including the TMS320C6211 device) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C67x DSPs (including the TMS320C6711 device) are the floating-point DSP family in the TMS320C6000 platform. The TMS320C6211 ('C6211) and TMS320C6711 ('C6711) devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the 'C6711 device also offers cost-effective solutions to high-performance DSP programming challenges. The 100-MHz device is the lowest-cost DSP in the 'C6000 family. The 'C6711 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The 'C6711 can produce two MACs per cycle for a total of 300 MMACS. Both the 'C6211 and 'C6711 DSPs have the same application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The 'C6211/'C6711 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals. The 'C6211/'C6711 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution. TMS320C62x, TMS320C6000, and TMS320C67x are trademarks of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 ADVANCE INFORMATION With performance of up to 1200 million instructions per second (MIPS) at a clock rate of 150 MHz, the 'C6211 device offers cost-effective solutions to high-performance DSP programming challenges. The 'C6211 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The 'C6211 can produce two multiply-accumulates (MACs) per cycle for a total of 300 million MACs per second (MMACS). SPRS073B - AUGUST 1998 - REVISED APRIL 2000 device characteristics Table 1 provides an overview of the 'C6211/'C6711 DSP. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. Table 1. Characteristics of the 'C6211/'C6711 Processors HARDWARE FEATURES Peripherals Peri herals ADVANCE INFORMATION On-Chip Memory Frequency Cycle Time Voltage 'C6211 (FIXED-POINT DSP) 'C6711 (FLOATING-POINT DSP) EMIF 1 1 EDMA 1 1 HPI 1 1 McBSPs 2 2 32-Bit Timers 2 2 Size (Bytes) 72K 72K Organization 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified Mapped RAM/Cache (L2) MHz 150 150, 100 6.7 ns ('6211-150) 6.7 ns ('6711-150) 10 ns ('6711-100 [Lowest-Cost Device]) Core (V) 1.8 1.8 I/O (V) 3.3 3.3 ns PLL Options CLKIN frequency multiplier BGA Package 27 x 27 mm Process Technology m Product Status Product Preview (PP) Advance Information (AI) Production Data (PD) Bypass (x1), x4 Bypass (x1), x4 256-Pin BGA (GFN) 256-Pin BGA (GFN) 0.18 m 0.18 m AI AI device compatibility The TMS320C6211 and 'C6711 devices are pin-compatible and have the same peripheral set; thus, making new system designs easier and providing faster time to market. The following list summarizes the device characteristic differences between the 'C6211 and 'C6711 devices: The 'C6211 device has a fixed-point 'C62x CPU, while the 'C6711 device has a floating-point 'C67x CPU. A 100-MHz version of the 'C6711 is available, providing the lowest-cost entry in the TMS320C6000 platform. For a more detailed discussion on the similarities/differences between the 'C6211 and 'C6711 devices, see the How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development Today with the TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively). 4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 functional block and CPU diagram 32 ROM/FLASH External Memory Interface (EMIF) I/O Devices Timer 0 Timer 1 Multichannel Buffered Serial Port 1 (McBSP1) Framing Chips: H.100, MVIP, SCSA, T1, E1 AC97 Devices, SPI Devices, Codecs Multichannel Buffered Serial Port 0 (McBSP0) 16 Host Port Interface (HPI) Enhanced DMA Controller (16 channel) L2 Memory 4 Banks 64K Bytes Total PLL (x1, x4) L1P Cache Direct Mapped 4K Bytes Total 'C6000 CPU Instruction Fetch Instruction Dispatch Instruction Decode Data Path A A Register File .L1 .S1 .M1 .D1 Control Registers Control Logic Data Path B Test B Register File In-Circuit Emulation .D2 .M2 .S2 .L2 Interrupt Control ADVANCE INFORMATION SBSRAM SRAM AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA 'C6211/'C6711 Digital Signal Processors SDRAM L1D Cache 2-Way Set Associative 4K Bytes Total Power-Down Logic The 'C6211 device has a fixed-point 'C62x CPU, while the 'C6711 device has a floating-point 'C67x CPU. For the 'C6711 device only, in addition to fixed-point instructions, these functional units execute floating-point instructions. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the 'C62x and 'C67x CPUs from other VLIW architectures. ADVANCE INFORMATION The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1 for the 'C6211 device; and see the functional block and CPU diagram and Figure 2 for the 'C6711 device). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The 'C67x CPU executes all 'C62x instructions. In addition to 'C62x fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the 'C62x/'C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The 'C62x/'C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 AAAA A A AAAA AA AAAA AAAA A AAAA A AAAA AAAA A A AAAA A A AAAA A A AAAA A AAAA AA A AAAA A AAAA AAAA A AAAA A AAAA AAAA A AAAA A AAAA AAAA A A A AAAA A A AAAA A A AAAA AA AAAA AAAA A AAAA AAAA A AAAA AA AAAA A A AAAA A A AAAA A AAAAA src1 .L1 A ST1 Data Path A src2 dst long dst long src long src long dst dst .S1 src1 8 8 32 8 Register File A (A0-A15) src2 .M1 dst src1 src2 LD1 A A DA1 DA2 LD2 .D1 .D2 dst src1 src2 2X 1X src2 src1 dst src2 .M2 src1 dst src2 Data Path B ST2 A src1 .S2 dst long dst long src long src long dst dst .L2 src2 AAAAAA AAAAAA AAAAAA AA AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA AAAAAA AA AAAAAA AA AAAAAA AAAAAA AA AAAAAA AA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AA AAAAAA AA AAAAAA AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA AAAAAA AAAAAA AA AAAAAA AA AAAAAA AAAAAA AAAAAA AAAAAA AA ADVANCE INFORMATION CPU description (continued) Register File B (B0-B15) 8 32 8 8 src1 Control Register File Figure 1. TMS320C62x CPU Data Paths POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 CPU description (continued) AAAAA A AA AAAAA AA AAA AAAAA AA AAAAA A AAAAA A AAAAA AAAAA A AAAAA A AAAAA A AA AAAAA A AA AAAAA AAA AAAAA A AAAAA AAA AAAAA AAAAA A AAAAA A AAAAA AAAAA A A AAAAA AAAAA AAAAA A AA A AA AAAAA A AAAAA AAAAA A AAA AAAAA AA AAAAA A AAAAA A AAAAA AAAAA AAAAA AA AAAAA A AA AAAAA A AA AAAAA AAA AAAAA src1 .L1 src2 dst long dst long src LD1 32 MSB ST1 8 8 long src long dst dst .S1 src1 Data Path A 32 32 8 8 src2 ADVANCE INFORMATION dst src1 .M1 src2 LD1 32 LSB AA AA AA AA DA1 DA2 LD2 32 LSB .D1 .D2 dst src1 src2 1X src2 .M2 src1 dst src2 Register File B (B0-B15) .S2 Data Path B AA AA LD2 32 MSB ST2 long src long dst dst .L2 src2 8 8 8 8 src1 Register File A (A0-A15) 2X src2 src1 dst src1 dst long dst long src AAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA A AAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA A AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAA AAAAA A 32 32 Control Register File For the 'C6711 device only, in addition to fixed-point instructions, these functional units execute floating-point instructions. Figure 2. TMS320C67x CPU Data Paths 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 signal groups description CLKIN CLKOUT2 CLKOUT1 CLKMODE0 PLLV PLLG PLLF Clock/PLL TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 Reset and Interrupts RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 RSV5 Reserved ADVANCE INFORMATION IEEE Standard 1149.1 (JTAG) Emulation RSV4 RSV3 RSV2 RSV1 RSV0 Control/Status HD[15:0] HCNTL0 HCNTL1 16 Data HPI (Host-Port Interface) Register Select Control HHWIL Half-Word Select HAS HR/W HCS HDS1 HDS2 HRDY HINT Figure 3. CPU and Peripheral Signals POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 signal groups description (continued) 32 ED[31:0] Data Memory Control CE3 CE2 CE1 CE0 EA[21:2] ADVANCE INFORMATION BE3 BE2 BE1 BE0 TOUT1 Memory Map Space Select 20 Address Bus Arbitration ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY HOLD HOLDA BUSREQ Byte Enables EMIF (External Memory Interface) Timer 1 Timer 0 TOUT0 TINP0 TINP1 Timers McBSP1 McBSP0 CLKX1 FSX1 DX1 Transmit Transmit CLKX0 FSX0 DX0 CLKR1 FSR1 DR1 Receive Receive CLKR0 FSR0 DR0 CLKS1 Clock Clock CLKS0 McBSPs (Multichannel Buffered Serial Ports) Figure 4. Peripheral Signals 10 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions SIGNAL NAME NO. TYPE IPD/ IPU A3 I IPU Clock Input CLKOUT1 D7 O IPD Clock output at device speed CLKOUT2 Y12 O IPD Clock output at half of device speed CLKMODE0 C4 I IPU Clock mode select * Selects whether the CPU clock frequency = input clock frequency x4 or x1 PLLV PLLG A4 PLL analog VCC connection for the low-pass filter C6 A A PLLF B5 A PLL low-pass filter connection to external components and a bypass capacitor TMS B7 I IPU JTAG test-port mode select TDO A8 O/Z IPU JTAG test-port data out TDI A7 I IPU JTAG test-port data in TCK A6 I IPU JTAG test-port clock DESCRIPTION CLOCK/PLL CLKIN PLL analog GND connection for the low-pass filter TRST B6 I IPD JTAG test-port reset EMU5 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 D10 I/O/Z IPU EMU1 B9 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1# EMU0 D9 I/O/Z IPU Emulation pin 0# ADVANCE INFORMATION JTAG EMULATION RESETS AND INTERRUPTS RESET A13 I IPU Device reset NMI C13 I IPD Nonmaskable interrupt * Edge-driven (rising edge) I IPU External interrupts interru ts * Edge-driven g ((rising g edge) g ) EXT_INT7 E3 EXT_INT6 D2 EXT_INT5 C1 EXT_INT4 C2 HINT J20 O IPU Host interrupt (from DSP to host) HCNTL1 G19 I IPU Host control - selects between control, address, or data registers HCNTL0 G18 I IPU Host control - selects between control, address, or data registers HHWIL H20 I IPU Host half-word select - first or second half-word (not necessarily high or low order) HOST-PORT INTERFACE (HPI) HR/W G20 I IPU Host read or write select I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a resistor in the range of 4.7 k to 5.1 k should be used.] PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these pins. A = Analog Signal (PLL Filter) # The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with an external dedicated resistor in the range of 4.7 k to 5.1 k. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION ADVANCE INFORMATION HOST-PORT INTERFACE (HPI) (CONTINUED) HD15 B14 IPU HD14 C14 IPU HD13 A15 IPU HD12 C15 IPU HD11 A16 IPU HD10 B16 IPU HD9 C16 IPU HD8 B17 HD7 A18 HD6 C17 IPU HD5 B18 IPU HD4 C19 IPD HD3 C20 IPU HD2 D18 IPU HD1 D20 IPU HD0 E20 HAS E18 I IPU Host address strobe HCS F20 I IPU Host chip select HDS1 E19 I IPU Host data strobe 1 IPU I/O/Z IPU Host-port data * U Used d ffor transfer t f off data, d t address, dd and d control t l * Also controls initialization of DSP modes at reset via pullup/pulldown resistors - Device Endian Mode HD8: 0 - Big Endian 1 - Little Endian - Boot mode HD[4:3]: 00 - HPI boot 01 - 8-bit ROM boot with default timings 10 - 16-bit 16 bit ROM boot with default timings 11 - 32-bit ROM boot with default timings IPU HDS2 F18 I IPU Host data strobe 2 HRDY H19 O IPU Host ready (from DSP to host) EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY CE3 V6 O/Z IPU CE2 W6 O/Z IPU CE1 W18 O/Z IPU CE0 V17 O/Z IPU BE3 V5 O/Z IPU BE2 Y4 O/Z IPU BE1 U19 O/Z IPU Memory space enables * Enabled by bits 28 through 31 of the word address * Only one asserted during any external data access Byte-enable control * Decoded from the two lowest bits of the internal address y y y * Byte-write enables for most types of memory * C Can be b directly di tl connected t d to t SDRAM read d and d write it maskk signal i l (SDQM) BE0 V20 O/Z IPU I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a resistor in the range of 4.7 k to 5.1 k should be used.] 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION EMIF - BUS ARBITRATION HOLDA J18 O/Z IPU Hold-request-acknowledge to the host HOLD J17 I IPU Hold request from the host BUSREQ J19 O/Z IPU Bus request output EMIF - ASYNCHRONOUS/SYNCHRONOUS DRAM/SYNCHRONOUS BURST SRAM MEMORY CONTROL Y11 I IPD EMIF input clock ECLKOUT Y10 O IPD EMIF output clock (based on ECLKIN) ARE/SDCAS/ SSADS V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe AOE/SDRAS/ SSOE W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable AWE/SDWE/ SSWE V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable ARDY Y5 I IPU Asynchronous memory ready input ADVANCE INFORMATION ECLKIN EMIF - ADDRESS EA21 U18 EA20 Y18 EA19 W17 EA18 Y16 EA17 V16 EA16 Y15 EA15 W15 EA14 Y14 EA13 W14 EA12 V14 EA11 W13 EA10 V10 EA9 Y9 EA8 V9 EA7 Y8 EA6 W8 EA5 V8 EA4 W7 EA3 V7 O/Z IPU External address (word address) EA2 Y6 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a resistor in the range of 4.7 k to 5.1 k should be used.] POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION ADVANCE INFORMATION EMIF - DATA ED31 N3 ED30 P3 ED29 P2 ED28 P1 ED27 R2 ED26 R3 ED25 T2 ED24 T1 ED23 U3 ED22 U1 ED21 U2 ED20 V1 ED19 V2 ED18 Y3 ED17 W4 ED16 V4 ED15 T19 ED14 T20 ED13 T18 ED12 R20 ED11 R19 ED10 P20 ED9 P18 ED8 N20 ED7 N19 ED6 N18 ED5 M20 ED4 M19 ED3 L19 ED2 L18 ED1 K19 I/O/Z IPU External data ED0 K18 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a resistor in the range of 4.7 k to 5.1 k should be used.] 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE IPD/ IPU DESCRIPTION TIMERS TOUT1 F1 O IPD Timer 1 or general-purpose output TINP1 F2 I IPD Timer 1 or general-purpose input TOUT0 G1 O IPD Timer 0 or general-purpose output TINP0 G2 I IPD Timer 0 or general-purpose input CLKS1 E1 I IPD External clock source (as opposed to internal) CLKR1 M1 I/O/Z IPD Receive clock CLKX1 L3 I/O/Z IPD Transmit clock DR1 M2 I IPU Receive data DX1 L2 O/Z IPU Transmit data FSR1 M3 I/O/Z IPD Receive frame sync FSX1 L1 I/O/Z IPD Transmit frame sync MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0 K3 I IPD External clock source (as opposed to internal) CLKR0 H3 I/O/Z IPD Receive clock CLKX0 G3 I/O/Z IPD Transmit clock DR0 J1 I IPU Receive data DX0 H2 O/Z IPU Transmit data FSR0 J3 I/O/Z IPD Receive frame sync FSX0 H1 I/O/Z IPD Transmit frame sync RESERVED FOR TEST RSV0 C12 O IPU Reserved (leave unconnected, do not connect to power or ground) RSV1 D12 O IPU Reserved (leave unconnected, do not connect to power or ground) RSV2 A5 O IPU Reserved (leave unconnected, do not connect to power or ground) RSV3 D3 O Reserved (leave unconnected, do not connect to power or ground) RSV4 N2 O Reserved (leave unconnected, do not connect to power or ground) RSV5 Y20 O Reserved (leave unconnected, do not connect to power or ground) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = internal pullup. [These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a resistor in the range of 4.7 k to 5.1 k should be used.] POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 ADVANCE INFORMATION MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS A17 B3 B8 B13 C5 C10 D1 D16 D19 F3 ADVANCE INFORMATION H18 J2 M18 N1 DVDD R1 S 3.3-V 3.3 V supply su ly voltage S 1 8 V supply voltage 1.8-V R18 T3 U5 U7 U12 U16 V13 V15 V19 W3 W9 W12 Y7 Y17 A9 A10 A12 B2 B19 C3 CVDD C7 C18 D5 D6 D11 D14 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) D15 F4 F17 K1 K4 K17 L4 L17 L20 R4 CVDD R17 S 1 8 V supply voltage 1.8-V ADVANCE INFORMATION U6 U10 U11 U14 U15 V3 V18 W2 W19 GROUND PINS A1 A2 A11 A14 A19 A20 B1 B4 B11 VSS B15 GND Ground pins B20 C8 C9 D4 D8 D13 D17 E2 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 Signal Descriptions (Continued) SIGNAL NAME NO. TYPE DESCRIPTION GROUND PINS (CONTINUED) E4 E17 F19 G4 G17 H4 H17 J4 K2 K20 ADVANCE INFORMATION M4 M17 N4 N17 P4 P17 P19 VSS T4 GND Ground pins T17 U4 U8 U9 U13 U17 U20 W1 W5 W11 W16 W20 Y1 Y2 Y13 Y19 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground 18 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 development support TI offers an extensive line of development tools for the TMS320C6000 generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 'C6000-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application. The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 family member devices, including documentation. See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-related products from other companies in the industry. To receive TMS320 literature, contact the Literature Response Center at 800/477-8924. See Table 2 for a complete listing of development-support tools for the TMS320C6000 DSP family. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. TMS320C6000, Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 ADVANCE INFORMATION Hardware Development Tools: Extended Development System (XDS) Emulator (supports 'C6000 multiprocessor system debug) EVM (Evaluation Module) SPRS073B - AUGUST 1998 - REVISED APRIL 2000 development support (continued) Table 2. TMS320C6000 Development-Support Tools TOOL PART NUMBER DSP/ BIOS DESCRIPTION CODE COMPOSER STUDIO IDE CODE GENERATION TOOLS TMDX320DAIS-07 TMS320 DSP Algorithm Standard Developer's Kit 6CCSFreeTool TMS320C6000 Code Composer Studio Free Evaluation Tools (FREE 30-Day Trial) TMDX324685C-07 (Windows 95/98 Windows NT) TMS320C6000 DSP Code Composer Studio IDE TMDX3246855-07 (Windows 95/98/NT) TMS320C6000 DSP Code Composer Studio IDE Compile Tools TMDX3240160-07 (Windows 95/98/NT) TMS320C6000 DSP Code Composer Studio IDE Debug Tools TMDX320006211 (DSK) TMS320C6211 DSP Starter Kit (DSK) 256KB Code Memory Limit TMDS3260A6201 TMS320C62x DSP Evaluation Module (EVM) TMDS326006201 TMS320C62x DSP EVM Bundle TMDX3260A6701 TMS320C67x DSP EVM TMDX326006701 TMS320C67x DSP EVM Bundle TMDS00510 XDS510 DSP Emulation Hardware EMULATION DRIVERS RTDX SIMULATOR TARGET HARDWARE ADVANCE INFORMATION SOFTWARE TOOLS DSK-Specific C6211 DSP EVM-Specific C6201 DSP EVM-Specific EVM-Specific EVM-Specific HARDWARE TOOLS C6201 DSP C6701 DSP C6701 DSP Any C6000 DSP via JTAG The TMS320C6000 Code Composer Studio Free Evaluation Tools can be downloaded for a free 30-day trial from the Texas Instruments web site at http://www.ti.com. A CD-ROM version of the TMS320C6000 Code Composer Studio Free Evaluation Tools (literature number SPRC020) is also available. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Code Composer Studio, TMS320, TMS320C6000, TMS320C62x, TMS320C67x, and XDS510 are trademarks of Texas Instruments. Windows and Windows NT are registered trademarks of Microsoft Corporation. 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GFN) and the device speed range in megahertz (for example, -150 is 150 MHz). Figure 5 provides a legend for reading the complete device name for any TMS320 family member. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 ADVANCE INFORMATION Device development evolutionary flow: SPRS073B - AUGUST 1998 - REVISED APRIL 2000 device and development-support tool nomenclature (continued) TMS 320 PREFIX TMX = TMP = TMS = SMJ = SM = C 6211 GFN ( ) 150 DEVICE SPEED RANGE Experimental device Prototype device Qualified device MIL-STD-883C High Rel (non-883C) 100 MHz 120 MHz 150 MHz 167 MHz DEVICE FAMILY 320 = TMS320 family 200 MHz 233 MHz 250 MHz 300 MHz TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE N = Plastic DIP J = Ceramic DIP JD = Ceramic DIP side-brazed GB = Ceramic PGA FZ = Ceramic CC FN = Plastic leaded CC FD = Ceramic leadless CC PJ = 100-pin plastic EIAJ QFP PQ = 132-pin plastic bumpered QFP PZ = 100-pin plastic TQFP PBK = 128-pin plastic TQFP PGE = 144-pin plastic TQFP GFN = 256-pin plastic BGA GGU = 144-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GHK = 288-pin plastic MicroStar BGA ADVANCE INFORMATION TECHNOLOGY C = CMOS E = CMOS EPROM F = CMOS Flash EEPROM DEVICE '1x DSP: 10 14 15 16 17 '2x DSP: 25 26 '2xx DSP: 203 204 206 209 240 '3x DSP: 30 31 32 '4x DSP: 40 44 '5x DSP: DIP PGA CC QFP TQFP BGA = = = = = = Dual-In-Line Package Pin Grid Array Chip Carrier Quad Flat Package Thin Quad Flat Package Ball Grid Array 50 51 52 53 56 57 541 542 543 545 546 548 6201 6202 6202B 6203 6204 6205 6211 6701 6711 '54x DSP: '6x DSP: Figure 5. TMS320 Device Nomenclature (Including TMS320C6211 and TMS320C6711 devices) MicroStar BGA is a trademark of Texas Instruments. 22 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the 'C6x devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the 'C6000 CPU architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on 'C6x devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of 'C6000 latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the application reports How To Begin Development Today with the TMS320C6211 DSP (literature number SPRA474) and How To Begin Development Today with the TMS320C6711 DSP (literature number SPRA522) which describe in more detail the similarities/differences between the 'C6211 and 'C6711 devices. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 23 ADVANCE INFORMATION The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the 'C62x/C67x devices, associated development tools, and third-party support. SPRS073B - AUGUST 1998 - REVISED APRIL 2000 clock PLL All of the internal 'C62x/'C67x clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock. To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 6 shows the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes. Figure 7 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode. To minimize the clock jitter, a single clean power supply should power both the 'C62x/'C67x device and the external clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section. 3.3V EMI Filter PLL CLKMODE0 C3 10 F Internal to 'C6211/'C6711 PLLMULT C4 0.1 F PLLCLK CLKIN CLKIN 1 LOOP FILTER 0 CPU CLOCK PLL Multiply Factors CPU Clock Frequency f(CPUCLOCK) 0 x1(BYPASS) 1 x f(CLKIN) 1 x4 4 x f(CLKIN) C2 PLLG CLKMODE0 PLLF Available Multiply Factors (For C1, C2, and R1 values, see Table 3.) C1 R1 NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the 'C6000 device as possible. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than the ones shown. B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter). C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U. Figure 6. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode 3.3V PLLV CLKMODE0 Internal to 'C6211/'C6711 PLL PLLMULT PLLCLK CLKIN CLKIN LOOP FILTER 1 CPU CLOCK PLLG 0 PLLF ADVANCE INFORMATION PLLV NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal. B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD. Figure 7. External PLL Circuitry for x1 (Bypass) Mode Only 24 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 clock PLL (continued) Table 3. 'C6211/'C6711 PLL Component Selection Table CLKMODE CLKIN RANGE (MHz) CPU CLOCK FREQUENCY (CLKOUT1) RANGE (MHz) CLKOUT2 RANGE (MHz) R1 () C1 (nF) C2 (pF) TYPICAL LOCK TIME (s) ADVANCE INFORMATION x4 16.3-37.5 65-150 32.5-75 60.4 27 560 75 Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 s, the maximum value may be as long as 250 s. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 25 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 absolute maximum ratings over operating case temperature range (unless otherwise noted) Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 2.3 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 90C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions CVDD ADVANCE INFORMATION DVDD Supply voltage, Core Supply voltage, I/O VSS VIH Supply ground VIL Low-level input voltage High-level input voltage IOH High level output current High-level IOL Low level output current Low-level MIN NOM MAX UNIT 1.71 1.8 1.89 V 3.14 3.30 3.46 V 0 0 0 V 2.0 V 0.8 V All signals except CLKOUT1 and CLKOUT2 -4 mA CLKOUT1 and CLKOUT2 -8 mA All signals except CLKOUT1 and CLKOUT2 4 mA CLKOUT1 and CLKOUT2 8 mA TC Operating case temperature 0 90 C TI DSP's do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. For additional power supply sequencing information, see the Power Supply Sequencing Solutions For Dual Supply Voltage DSPs application report (literature number SLVA073). electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL High-level output voltage DVDD = MIN, Low-level output voltage DVDD = MIN, II IOZ Input current VI = VSS to DVDD VO = DVDD or 0 V Off-state output current IDD2V Supply current, current CPU + CPU memory access IDD2V Supply current, current peripherals IDD3V Supply current, current I/O pins Ci Input capacitance IOH = MAX IOL = MAX MIN TYP MAX 2.4 UNIT V 0.6 V 125 uA 10 uA 'C6211, CVDD = NOM, CPU clock = 150 MHz 270 mA 'C6711, CVDD = NOM, CPU clock = 150 MHz TBD mA 'C6211, CVDD = NOM, CPU clock = 150 MHz 220 mA 'C6711, CVDD = NOM, CPU clock = 150 MHz TBD mA 'C6211, DVDD = NOM, CPU clock = 150 MHz 60 mA 'C6711, DVDD = NOM, CPU clock = 150 MHz TBD mA 5 pF Co Output capacitance 5 pF Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, refer to the TMS320C6000 Power Consumption Summary application report (literature number SPRA486). 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics 50 Vref Output Under Test CT = 30 pF IOH Typical distributed load circuit capacitance ADVANCE INFORMATION Figure 8. Test Load Circuit signal transition levels All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels. Vref = 1.5 V Figure 9. Input and Output Voltage Reference Levels for ac Timing Measurements POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 10) -100 CLKMODE = x4 NO. MIN 1 2 3 -150 CLKMODE = x1 MAX MIN MAX CLKMODE = x4 MIN MIN UNIT MAX tc(CLKIN) tw(CLKINH) Cycle time, CLKIN 40 10 26.7 6.7 ns Pulse duration, CLKIN high 0.4C 0.45C 0.4C 0.45C ns tw(CLKINL) tt(CLKIN) Pulse duration, CLKIN low 0.4C 0.45C 0.4C 0.45C ns 4 Transition time, CLKIN 5 0.6 The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns. 1 5 0.6 ns 4 2 ADVANCE INFORMATION CLKMODE = x1 MAX CLKIN 3 4 Figure 10. CLKIN Timings switching characteristics for CLKOUT1 (see Figure 11) -100 -150 NO NO. PARAMETER CLKMODE = x4 MIN 1 2 3 CLKMODE = x1 MAX MIN MAX tc(CKO1) tw(CKO1H) Cycle time, CLKOUT1 P - 0.7 P + 0.7 P - 0.7 P + 0.7 ns Pulse duration, CLKOUT1 high (P/2) - 0.5 (P/2 ) + 0.5 PH - 0.5 PH + 0.5 ns tw(CKO1L) tt(CKO1) Pulse duration, CLKOUT1 low (P/2) - 0.5 (P/2 ) + 0.5 PL - 0.5 PL + 0.5 ns 0.6 ns 4 Transition time, CLKOUT1 PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns. P = 1/CPU clock frequency in nanoseconds (ns) 0.6 1 4 2 CLKOUT1 3 4 Figure 11. CLKOUT1 Timings 28 UNIT POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for CLKOUT2 (see Figure 12) NO. 1 2 3 4 -100 -150 PARAMETER UNIT MIN MAX tc(CKO2) tw(CKO2H) Cycle time, CLKOUT2 2P - 0.7 2P + 0.7 ns Pulse duration, CLKOUT2 high P - 0.7 P + 0.7 ns tw(CKO2L) tt(CKO2) Pulse duration, CLKOUT2 low P - 0.7 P + 0.7 ns 0.6 ns Transition time, CLKOUT2 P = 1/CPU clock frequency in ns 1 4 2 ADVANCE INFORMATION CLKOUT2 3 4 Figure 12. CLKOUT2 Timings timing requirements for ECLKIN (see Figure 13) -100 NO NO. 1 2 3 4 MIN -150 MAX MIN MAX UNIT tc(EKI) tw(EKIH) Cycle time, ECLKIN 15 10 ns Pulse duration, ECLKIN high 6.8 4.5 ns tw(EKIL) tt(EKI) Pulse duration, ECLKIN low 6.8 4.5 Transition time, ECLKIN 3 ns 3 ns The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. 1 4 2 ECLKIN 3 4 Figure 13. ECLKIN Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics for ECLKOUT (see Figure 14) NO. -100 -150 PARAMETER MIN 1 2 3 4 5 tc(EKO) tw(EKOH) Cycle time, ECLKOUT E - 0.7 E + 0.7 ns Pulse duration, ECLKOUT high EH - 0.7 EH + 0.7 ns tw(EKOL) tt(EKO) Pulse duration, ECLKOUT low EL - 0.7 EL + 0.7 ns 0.6 ns td(EKIH-EKOH) td(EKIL-EKOL) Delay time, ECLKIN high to ECLKOUT high 1 3 ns 1 3 ns Transition time, ECLKOUT ADVANCE INFORMATION 6 Delay time, ECLKIN low to ECLKOUT low The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of VIH. E = ECLKIN period in ns EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns. ECLKIN 6 1 2 5 3 ECLKOUT Figure 14. ECLKOUT Timings 30 UNIT MAX POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 4 4 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 15-Figure 16) -100 NO NO. 3 4 6 MAX MIN UNIT MAX tsu(EDV-AREH) th(AREH-EDV) Setup time, EDx valid before ARE high 6 3 ns Hold time, EDx valid after ARE high 1 1 ns tsu(ARDY-EKOH) th(EKOH-ARDY) Setup time, ARDY valid before ECLKOUT high 6 2 ns Hold time, ARDY valid after ECLKOUT high 1 1 ns To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns switching characteristics for asynchronous memory cycles (see Figure 15-Figure 16) -100 NO NO. PARAMETER MIN -150 MAX MIN MAX UNIT 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS * E - 2 RS * E - 2 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH * E - 2 RH * E - 2 ns 5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE vaild 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid 2 WS * E - 2 WH * E - 2 11 1.5 WS * E - 2 WH * E - 2 6 ns ns ns 10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE vaild 2 11 1.5 6 ns RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0]. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 ADVANCE INFORMATION 7 MIN -150 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 ELCKOUT 1 2 CEx 1 2 BE[3:0] BE 1 2 EA[21:2] Address 3 4 ED[31:0] ADVANCE INFORMATION 1 2 Read Data AOE/SDRAS/SSOE 5 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 7 6 7 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 15. Asynchronous Memory Read Timing 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Hold = 2 Not Ready ECLKOUT 8 9 CEx 8 9 BE[3:0] BE 8 9 EA[21:2] Address 8 9 ED[31:0] Write Data ARE/SDCAS/SSADS 10 10 AWE/SDWE/SSWE 7 6 7 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 16. Asynchronous Memory Write Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 ADVANCE INFORMATION AOE/SDRAS/SSOE SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 17) -100 NO NO. 6 7 MIN tsu(EDV-EKOH) th(EKOH-EDV) -150 MAX MIN Setup time, read EDx valid before ECLKOUT high 6 1.5 Hold time, read EDx valid after ECLKOUT high 1 1.0 MAX UNIT ns ns The 'C6211/'C6711 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics for synchronous-burst SRAM cycles (see Figure 17 and Figure 18) -100 NO NO. 1 ADVANCE INFORMATION 2 3 4 5 8 9 10 11 12 PARAMETER -150 UNIT MIN MAX MIN MAX 2 11 1.5 6 ns 6 ns td(EKOH-CEV) td(EKOH-BEV) Delay time, ECLKOUT high to CEx valid td(EKOH-BEIV) td(EKOH-EAV) Delay time, ECLKOUT high to BEx invalid td(EKOH-EAIV) td(EKOH-ADSV) Delay time, ECLKOUT high to EAx invalid 2 Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 2 11 1.5 6 ns td(EKOH-OEV) td(EKOH-EDV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 2 11 1.5 6 ns 6 ns td(EKOH-EDIV) td(EKOH-WEV) Delay time, ECLKOUT high to EDx invalid 2 Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 2 Delay time, ECLKOUT high to BEx valid 11 2 Delay time, ECLKOUT high to EAx valid 1.5 11 Delay time, ECLKOUT high to EDx valid ns 6 1.5 11 ns 1.5 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1.5 ns ns The 'C6211/'C6711 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. 34 11 ns 6 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED) ECLKOUT 1 1 CEx BE[3:0] 2 BE1 3 BE2 BE3 4 BE4 5 EA[21:2] EA 6 ED[31:0] 7 Q1 Q2 Q3 Q4 8 8 ARE/SDCAS/SSADS 9 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 17. SBSRAM Read Timing ECLKOUT 1 1 CEx BE[3:0] 2 BE1 3 BE2 BE3 5 4 EA[21:2] ED[31:0] BE4 EA 10 Q1 8 11 Q2 Q3 Q4 8 ARE/SDCAS/SSADS AOE/SDRAS/SSOE 12 12 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. Figure 18. SBSRAM Write Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 ADVANCE INFORMATION 9 AOE/SDRAS/SSOE SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 19) -100 NO NO. 6 MIN tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high -150 MAX 6 MIN MAX 1.5 UNIT ns 7 Hold time, read EDx valid after ECLKOUT high 1 1 ns The 'C6211/'C6711 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. switching characteristics for synchronous DRAM cycles (see Figure 19-Figure 25) -100 NO NO. 1 ADVANCE INFORMATION 2 3 4 5 8 9 10 11 12 PARAMETER -150 UNIT MIN MAX MIN MAX 2 11 1.5 6 ns 6 ns td(EKOH-CEV) td(EKOH-BEV) Delay time, ECLKOUT high to CEx valid td(EKOH-BEIV) td(EKOH-EAV) Delay time, ECLKOUT high to BEx invalid td(EKOH-EAIV) td(EKOH-CASV) Delay time, ECLKOUT high to EAx invalid 2 Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 2 td(EKOH-EDV) td(EKOH-EDIV) Delay time, ECLKOUT high to EDx valid Delay time, ECLKOUT high to EDx invalid 2 td(EKOH-WEV) td(EKOH-RAS) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 2 11 1.5 6 Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 2 11 1.5 6 Delay time, ECLKOUT high to BEx valid 11 2 Delay time, ECLKOUT high to EAx valid 1.5 11 ns 6 1.5 11 1.5 11 ns ns 6 ns 6 ns 1.5 ns ns ns The 'C6211/'C6711 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS DRAM TIMING (CONTINUED) READ ECLKOUT 1 1 CEx 2 BE1 BE[3:0] EA[21:13] EA[11:2] 4 Bank 5 4 Column 5 4 3 BE2 BE3 BE4 5 6 D1 ED[31:0] 7 D2 D3 D4 AOE/SDRAS/SSOE 8 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 19. SDRAM Read Command (CAS Latency 3) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 ADVANCE INFORMATION EA12 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS DRAM TIMING (CONTINUED) WRITE ECLKOUT 1 2 CEx 2 3 4 BE[3:0] BE1 4 BE2 BE3 BE4 D2 D3 D4 5 Bank EA[21:13] 5 4 Column EA[11:2] 4 5 ADVANCE INFORMATION EA12 9 9 ED[31:0] 10 D1 AOE/SDRAS/SSOE 8 8 11 11 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 20. SDRAM Write Command 38 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS DRAM TIMING (CONTINUED) ACTV ECLKOUT 1 1 CEx BE[3:0] 4 Bank Activate 5 EA[21:13] 4 Row Address 5 EA[11:2] 4 Row Address 5 EA12 12 12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 21. SDRAM ACTV Command DCAB ECLKOUT 1 1 4 5 12 12 11 11 CEx BE[3:0] EA[21:13, 11:2] EA12 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 22. SDRAM DCAB Command POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 39 ADVANCE INFORMATION ED[31:0] SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS DRAM TIMING (CONTINUED) DEAC ECLKOUT 1 1 CEx BE[3:0] 4 5 Bank EA[21:13] EA[11:2] 4 5 12 12 11 11 EA12 ADVANCE INFORMATION ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 23. SDRAM DEAC Command REFR ECLKOUT 1 1 12 12 8 8 CEx BE[3:0] EA[21:2] EA12 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 24. SDRAM REFR Command 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 SYNCHRONOUS DRAM TIMING (CONTINUED) MRS ECLKOUT 1 1 4 MRS value 5 12 12 8 8 11 11 CEx BE[3:0] EA[21:2] ED[31:0] ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 25. SDRAM MRS Command POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 ADVANCE INFORMATION AOE/SDRAS/SSOE SPRS073B - AUGUST 1998 - REVISED APRIL 2000 HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 26) -100 -150 NO. MIN 3 toh(HOLDAL-HOLDL) E = ECLKIN period in ns Hold time, HOLD low after HOLDA low UNIT MAX E ns switching characteristics for the HOLD/HOLDA cycles (see Figure 26) NO. -100 -150 PARAMETER MIN 1 ADVANCE INFORMATION 2 4 5 tR(HOLDL-EMHZ) td(EMHZ-HOLDAL) Response time, HOLD low to EMIF Bus high impedance tR(HOLDH-EMLZ) td(EMLZ-HOLDAH) Response time, HOLD high to EMIF Bus low impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, EMIF Bus low impedance to HOLDA high UNIT 2E MAX ns 0 2E ns 2E 7E ns 0 2E ns E = ECLKIN period in ns EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. External Requestor Owns Bus DSP Owns Bus DSP Owns Bus 3 HOLD 2 5 HOLDA EMIF Bus 1 C6211/C6711 4 C6211/C6711 EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. Figure 26. HOLD/HOLDA Timing 42 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 RESET TIMING timing requirements for reset (see Figure 27) -100 -150 NO. MIN UNIT MAX Width of the RESET pulse (PLL stable) 10P ns 1 tw(RST) Width of the RESET pulse (PLL needs to sync up) 250 s 14 tsu(HD) th(HD) Setup time, HD boot configuration bits valid before RESET high Hold time, HD boot configuration bits valid after RESET high 2P ns 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable. This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times. HD[4:3] are the boot configuration pins during device reset. ADVANCE INFORMATION 15 switching characteristics during reset#|| (see Figure 27) NO. 2 3 4 5 6 7 8 9 10 11 12 13 -100 -150 PARAMETER UNIT MIN MAX tR(RSTL-ECKI) tR(RSTH-ECKI) Response time, RESET low to ECLKIN synchronized 2P + 3E 3P + 4E ns Response time, RESET high to ECLKIN synchronized 2P + 3E 3P + 4E ns td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) Delay time, RESET low to EMIF Z group high impedance 2P + 3E td(RSTL-EMIFHIV) td(RSTH-EMIFHV) Delay time, RESET low to EMIF high group invalid td(RSTL-EMIFLIV) td(RSTH-EMIFLV) Delay time, RESET low to EMIF low group invalid td(RSTL-HIGHIV) td(RSTH-HIGHV) Delay time, RESET low to high group invalid td(RSTL-ZHZ) td(RSTH-ZV) Delay time, RESET low to Z group high impedance 2P ns Delay time, RESET high to Z group valid 2P ns Delay time, RESET high to EMIF Z group valid ns 3P + 4E 2P + 3E Delay time, RESET high to EMIF high group valid ns 3P + 4E 2P + 3E Delay time, RESET high to EMIF low group valid ns ns 3P + 4E 2P Delay time, RESET high to high group valid ns ns ns 4P ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. # E = ECLKIN period in ns || EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE EMIF high group consists of: HOLDA EMIF low group consists of: BUSREQ High group consists of: HRDY and HINT Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 RESET TIMING (CONTINUED) CLKOUT1 CLKOUT2 1 14 15 RESET 2 3 4 5 6 7 8 9 ECLKIN EMIF Z Group ADVANCE INFORMATION EMIF High Group EMIF Low Group 10 11 12 13 High Group Z Group HD[4:3] EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE EMIF high group consists of: HOLDA EMIF low group consists of: BUSREQ High group consists of: HRDY and HINT Z group consists of: HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1. HD[4:3] are the boot configuration pins during device reset. Figure 27. Reset Timing 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 28) -100 -150 NO. MIN 1 2 tw(ILOW) tw(IHIGH) UNIT MAX Width of the interrupt pulse low 2E ns Width of the interrupt pulse high 2E ns E = ECLKIN period in ns 1 2 EXT_INT, NMI ADVANCE INFORMATION Figure 28. External/NMI Interrupt Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles (see Figure 29, Figure 30, Figure 31, and Figure 32) -100 -150 NO. MIN 1 Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low tw(HSTBL) tw(HSTBH) 5 ns 2 ns Pulse duration, HSTROBE low 4P ns Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low 4P ns 5 ns Hold time, select signals valid after HAS low 2 ns Setup time, host data valid before HSTROBE high 5 ns Hold time, host data valid after HSTROBE high 2 ns Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns Setup time, HAS low before HSTROBE low 2 ns 19 Hold time, HAS low after HSTROBE low 2 HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. Select signals include: HCNTL[1:0], HR/W, and HHWIL. ns 2 3 4 10 11 12 ADVANCE INFORMATION tsu(SELV-HSTBL) th(HSTBL-SELV) UNIT MAX tsu(SELV-HASL) th(HASL-SELV) 13 tsu(HDV-HSTBH) th(HSTBH-HDV) 14 th(HRDYL-HSTBL) 18 tsu(HASL-HSTBL) th(HSTBL-HASL) switching characteristics during host-port interface cycles (see Figure 29, Figure 30, Figure 31, and Figure 32) NO. PARAMETER -100 -150 MIN UNIT MAX Delay time, HCS to HRDY 1 7 ns 6 td(HCS-HRDY) td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high# 3 12 ns 7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 8 Delay time, HD valid to HRDY low 9 td(HDV-HRDYL) toh(HSTBH-HDV) 15 td(HSTBH-HDHZ) 16 17 5 2 ns 2P - 4 2P ns Output hold time, HD valid after HSTROBE high 3 12 ns Delay time, HSTROBE high to HD high impedance 3 12 ns td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12 ns td(HSTBH-HRDYH) td(HASL-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 12 ns 20 Delay time, HAS low to HRDY high 3 12 ns HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal. 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 4 3 HSTROBE 3 HCS 15 9 7 15 9 16 1st halfword 5 2nd halfword 8 17 ADVANCE INFORMATION HD[15:0] (output) 5 HRDY (case 1) 6 8 17 5 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 29. HPI Read Timing (HAS Not Used, Tied High) HAS 19 11 19 10 11 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 4 3 HSTROBE 18 18 HCS 15 7 9 15 16 9 HD[15:0] (output) 1st half-word 5 8 2nd half-word 17 5 17 5 HRDY (case 1) 20 8 HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 30. HPI Read Timing (HAS Used) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 HOST-PORT INTERFACE TIMING (CONTINUED) HAS 1 1 2 2 HCNTL[1:0] 1 1 2 2 HR/W 1 1 2 2 HHWIL 3 3 4 14 HSTROBE HCS 12 12 13 13 ADVANCE INFORMATION HD[15:0] (input) 1st halfword 5 17 2nd halfword 5 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 31. HPI Write Timing (HAS Not Used, Tied High) HAS 12 19 13 12 19 13 HBE[1:0] 11 11 10 10 HCNTL[1:0] 11 11 10 10 HR/W 11 11 10 10 HHWIL 3 14 HSTROBE 4 18 18 HCS 12 13 12 13 HD[15:0] (input) 5 1st half-word 2nd half-word 17 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 32. HPI Write Timing (HAS Used) 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 33) -100 -150 2 3 tc(CKRX) tw(CKRX) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low 5 tsu(FRH-CKRL) Setup time, time external FSR high before CLKR low 6 th(CKRL-FRH) Hold time, time external FSR high after CLKR low 7 tsu(DRV-CKRL) Setup time time, DR valid before CLKR low 8 th(CKRL-DRV) time DR valid after CLKR low Hold time, 10 tsu(FXH-CKXL) Setup time, time external FSX high before CLKX low 11 th(CKXL-FXH) Hold time, time external FSX high after CLKX low CLKR/X ext MIN 2P CLKR/X ext P - 1 CLKR int 9 CLKR ext 1 CLKR int 6 CLKR ext 3 CLKR int 8 CLKR ext 0 CLKR int 3 CLKR ext 3 CLKX int 9 CLKX ext 1 CLKX int 6 CLKX ext 3 UNIT MAX ns ns ns ns ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies to the following hardware configuration: the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. The minimum CLKR/X pulse duration is either (P-1) or 9 ns, whichever is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P-1) = 11.5 ns as the minimum CLKR/X pulse duration. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 ADVANCE INFORMATION NO. SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics for McBSP (see Figure 33) ADVANCE INFORMATION NO. -100 -150 PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input UNIT MIN MAX 4 10 2P C - 1# C + 1# ns ns 1 td(CKSH-CKRXH) 2 Cycle time, CLKR/X CLKR/X int 3 tc(CKRX) tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int 4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int -2 3 CLKX int -2 3 CLKX ext 3 9 CLKX int -1 4 CLKX ext CLKX int 3 -1 + D|| 9 4 + D|| CLKX ext 3 + D|| 9 + D|| 9 td(CKXH-FXV) Delay time, time CLKX high to internal FSX valid 12 tdis(CKXH-DXHZ) Disable time, DX high impedance im edance following last data bit from CLKX high 13 td(CKXH-DXV) time CLKX high to DX valid Delay time, 14 td(FXH-DXV) ns ns Delay time, FSX high to DX valid FSX int -1 3 ONLY applies when in data delay 0 (XDATDLY = 00b) mode FSX ext 3 9 ns ns ns ns CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum CLKR/X clock cycle. The maximum McBSP bit rate applies to the following hardware configuration: the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit. || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. D = extra delay from CLKX high to DX vaild = 0 if DXENA = 0 = extra delay from CLKX high to DX vaild = 2P if DXENA = 1 50 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 ADVANCE INFORMATION 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3) Figure 33. McBSP Timings POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 34) -100 -150 NO. MIN 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high 4 ns Hold time, FSR high after CLKS high 4 ns CLKS 1 2 FSR external CLKR/X (no need to resync) ADVANCE INFORMATION CLKR/X(needs resync) Figure 34. FSR Timing When GSYNC = 1 52 UNIT MAX POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 35) -100 -150 NO NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low MAX 12 5 Hold time, DR valid after CLKX low 4 P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT SLAVE MIN MAX 2 - 6P ns 5 + 12P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 35) NO NO. PARAMETER MASTER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid 6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T-2 T+3 L-2 L+3 -2 4 L-2 L+3 MIN MAX ns ns 6P + 4 10P + 17 ns ns 2P + 3 6P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 ADVANCE INFORMATION -100 -150 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) ADVANCE INFORMATION Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 36) -100 -150 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high UNIT SLAVE MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. MIN MAX 2 - 6P ns 5 + 12P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 36) NO NO. PARAMETER MASTER 2 th(CKXL-FXL) td(FXL-CKXH) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low 1 6 UNIT SLAVE MIN MAX L-2 L+3 MIN MAX T-2 T+3 -2 4 6P + 4 10P + 17 ns -2 4 6P + 3 10P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid H-2 H+4 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX 1 2 6 Bit 0 7 FSX DX 3 Bit(n-1) 4 DR Bit 0 (n-2) (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 55 ADVANCE INFORMATION -100 -150 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 37) -100 -150 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT SLAVE MIN MAX 2 - 6P ns 5 + 12P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 37) ADVANCE INFORMATION -100 -150 NO NO. PARAMETER MASTER 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXL-DXV) Delay time, CLKX low to DX valid 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 1 UNIT SLAVE MIN MAX T-2 T+3 H-2 H+3 -2 4 H-2 H+3 MIN MAX ns ns 6P + 4 10P + 17 ns ns 2P + 3 6P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 8 3 Bit 0 Bit(n-1) 4 Bit 0 (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ADVANCE INFORMATION DR (n-2) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 57 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 38) -100 -150 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX 12 5 Hold time, DR valid after CLKX high 4 P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. UNIT SLAVE MIN MAX 2 - 6P ns 5 + 12P ns switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 38) ADVANCE INFORMATION -100 -150 NO NO. PARAMETER MASTER 2 th(CKXH-FXL) td(FXL-CKXL) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# 3 td(CKXH-DXV) Delay time, CLKX high to DX valid tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high 1 6 UNIT SLAVE MIN MAX H-2 H+3 MIN MAX T-2 T+1 -2 4 6P + 4 10P + 17 ns -2 4 6P + 3 10P + 17 ns ns ns 7 td(FXL-DXV) Delay time, FSX low to DX valid L-2 L+4 4P + 2 8P + 17 ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). 58 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX 1 2 FSX 7 6 DX 3 Bit 0 Bit(n-1) 4 Bit 0 (n-3) (n-4) 5 Bit(n-1) (n-2) (n-3) (n-4) Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ADVANCE INFORMATION DR (n-2) POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 59 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 TIMER TIMING timing requirements for timer inputs (see Figure 39) -100 -150 NO. MIN 1 2 tw(TINPH) tw(TINPL) UNIT MAX Pulse duration, TINP high 2P ns Pulse duration, TINP low 2P ns P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. switching characteristics for timer outputs (see Figure 39) NO. -100 -150 PARAMETER MIN ADVANCE INFORMATION 3 tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high 4 Pulse duration, TOUT low P = 1/CPU clock frequency in ns. For example, when running parts at 150 MHz, use P = 6.7 ns. 2 1 TINPx 4 3 TOUTx Figure 39. Timer Timing 60 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 UNIT MAX 4P-3 ns 4P-3 ns SPRS073B - AUGUST 1998 - REVISED APRIL 2000 JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 40) -100 -150 NO. MIN 1 UNIT MAX tc(TCK) tsu(TDIV-TCKH) Cycle time, TCK 35 ns 3 Setup time, TDI/TMS/TRST valid before TCK high 10 ns 4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns switching characteristics for JTAG test port (see Figure 40) 2 -100 -150 PARAMETER td(TCKL-TDOV) Delay time, TCK low to TDO valid UNIT MIN MAX -3 12 ns ADVANCE INFORMATION NO. 1 TCK 2 2 TDO 4 3 TDI/TMS/TRST Figure 40. JTAG Test-Port Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 61 SPRS073B - AUGUST 1998 - REVISED APRIL 2000 MECHANICAL DATA GFN (S-PBGA-N256) PLASTIC BALL GRID ARRAY 27,20 SQ 26,80 24,70 SQ 23,95 24,13 TYP 1,27 0,635 1,27 0,635 ADVANCE INFORMATION Y W V U T R P N M L K J H G F E D C B A 1 3 2 5 4 7 6 9 8 10 11 13 15 17 19 12 14 16 18 20 2,32 MAX 1,17 NOM Seating Plane 0,40 0,30 0,90 0,60 0,15 M 0,70 0,50 0,15 4040185-2/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. thermal resistance characteristics (S-PBGA package) NO 1 C/W Air Flow LFPM RJC RJA Junction-to-case 6.4 N/A Junction-to-free air 25.2 0 RJA RJA Junction-to-free air 23.1 100 Junction-to-free air 21.9 250 5 RJA Junction-to-free air LFPM = Linear Feet Per Minute 20.6 500 2 3 4 62 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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