LP2996 DDR Termination Regulator General Description Features The LP2996 linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An additional feature found on the LP2996 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tristate providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. Source and sink current Low output voltage offset No external resistors required Linear topology Suspend to Ram (STR) functionality Low external component count Thermal Shutdown Available in SO-8, PSOP-8 or LLP-16 packages Applications DDR-I and DDR-II Termination Voltage SSTL-2 and SSTL-3 Termination HSTL Termination Typical Application Circuit 20057518 (c) 2012 Texas Instruments Incorporated 200575 SNOSA40I www.ti.com LP2996 DDR Termination Regulator June 29, 2012 LP2996 Connection Diagrams Top View 20057503 PSOP-8 Layout 20057502 LLP-16 Layout 20057504 SO-8 Layout Pin Descriptions SO-8 Pin or PSOP-8 Pin LLP Pin Name 1 2 GND 2 4 SD 3 5 VSENSE 4 7 VREF Buffered internal reference voltage of VDDQ/2 5 8 VDDQ Input for internal reference equal to VDDQ/2 6 10 AVIN Analog input pin 7 11, 12 PVIN Power input pin 8 14, 15 VTT Output voltage for connection to termination resistors - 1, 3, 6, 9, 13, 16 NC No internal connection EP EP Exposed pad thermal connection. Connect to Ground. Function Ground Shutdown Feedback pin for regulating VTT. Ordering Information Order Number Package Type NSC Package Drawing LP2996M SO-8 M08A 95 Units per Rail Supplied As 2500 Units Tape and Reel LP2996MX SO-8 M08A LP2996MR PSOP-8 MRA08A 95 Units per Rail LP2996MRX PSOP-8 MRA08A 2500 Units Tape and Reel LP2996LQ LLP-16 LQA16A 1000 Units Tape and Reel LP2996LQX LLP-16 LQA16A 4500 Units Tape and Reel www.ti.com 2 If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. AVIN to GND -0.3V to +6V PSOP-8 Thermal Resistance (JA) 43C/W PVIN to GND -0.3V to AVIN LLP-16 Thermal Resistance (JA) 51C/W VDDQ (Note 2) -0.3V to +6V Lead Temperature (Soldering, 10 sec) 260C Storage Temp. Range -65C to +150C ESD Rating (Note 3) 1kV Junction Temperature 150C SO-8 Thermal Resistance (JA) 151C/W Operating Range Junction Temp. Range (Note 4) AVIN to GND PVIN Supply Voltage SD Input Voltage 0C to +125C 2.2V to 5.5V 0 to AVIN 0 to AVIN Electrical Characteristics Specifications with standard typeface are for TJ = 25C and limits in boldface type apply over the full Operating Temperature Range (TJ = 0C to +125C) (Note 5). Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6). Symbol VREF Parameter VREF Voltage Conditions VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VIN = VDDQ = 2.7V Min Typ Max Units 1.135 1.235 1.335 1.158 1.258 1.358 1.185 1.285 1.385 V ZVREF VREF Output Impedance IREF = -30 to +30 A VTT VTT Output Voltage IOUT = 0A VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VIN = VDDQ = 2.7V 1.125 1.225 1.325 1.159 1.259 1.359 1.190 1.290 1.390 IOUT = 1.5A (Note 9) VIN = VDDQ = 2.3V VIN = VDDQ = 2.5V VIN = VDDQ = 2.7V 1.125 1.225 1.325 1.159 1.259 1.359 1.190 1.290 1.390 VTT Output Voltage Offset (VREF-VTT) IOUT = 0A IOUT = -1.5A (Note 9) IOUT = +1.5A (Note 9) -20 -25 -25 0 0 0 20 25 25 mV IQ Quiscent Current (Note 7) IOUT = 0A (Note 5) 320 500 A ZVDDQ VDDQ Input Impedance ISD Quiescent Current in Shutdown (Note 7) SD = 0V 115 150 A IQ_SD Shutdown Leakage Current SD = 0V 2 5 A VIH Minimum Shutdown High Level VIL Maximum Shutdown Low Level IV VTT Leakage Current in Shutdown ISENSE VSENSE Input Current TSD Thermal Shutdown TSD_HYS Thermal Shutdown Hysteresis VosTT/VTT 2.5 k 100 k V 1.9 SD = 0V VTT = 1.25V 1 (Note 8) 3 V 0.8 V 10 A 13 nA 165 Celcius 10 Celcius www.ti.com LP2996 Absolute Maximum Ratings (Note 1) LP2996 Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller. Note 3: The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. Note 4: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at JA = 151.2 C/W junction to ambient with no heat sink. Note 5: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL). Note 6: VIN is defined as VIN = AVIN = PVIN. Note 7: Quiescent current defined as the current flow into AVIN. Note 8: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction to ambient thermal resistance, JA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature and the regulator will go into thermal shutdown. Note 9: VTT load regulation is tested by using a 10 ms current pulse and measuring VTT. www.ti.com 4 LP2996 Typical Performance Characteristics Iq vs AVIN in SD Iq vs AVIN 20057520 20057521 VIH and VIL VREF vs IREF 20057522 20057523 VREF vs VDDQ VTT vs IOUT 20057524 20057525 5 www.ti.com LP2996 VTT vs VDDQ Iq vs AVIN in SD Temperature 20057526 20057527 Iq vs AVIN Temperature Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 1.8V) 20057528 20057531 Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 2.5V) Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 3.3V) 20057532 www.ti.com 20057533 6 LP2996 Maximum Sinking Current vs AVIN (VDDQ = 2.5V) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 1.8V) 20057534 20057535 Maximum Sinking Current vs AVIN (VDDQ = 1.8V) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 3.3V) 20057536 20057537 Block Diagram 20057505 7 www.ti.com LP2996 mon form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ohms, although these can be changed to scale the current requirements from the LP2996. This implementation can be seen below in Figure 1. Description The LP2996 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2996 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2996 to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). For new designs, the LP2997 or LP2998 is recommended for DDR-II applications. The LP2996 can also be used to provide a termination voltage for other logic schemes such as SSTL-3 or HSTL. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most com- www.ti.com 20057506 FIGURE 1. SSTL-Termination Scheme 8 pull-up current, therefore to turn the part on the shutdown pin can either be connected to AVIN or left open. AVIN AND PVIN AVIN and PVIN are the input supply pins for the LP2996. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. It is recommended to connect PVIN to voltage rails equal to or less than 3.3V to prevent the thermal limit from tripping because of excessive internal power dissipation. If the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where VTT is tri-stated and VREF remains active. VREF VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 F to 0.01 F is recommended. This output remains active during the shutdown state and thermal shutdown events for the suspend to RAM functionality. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2996 is designed to handle peak transient currents of up to 3A with a fast transient response. The maximum continuous current is a function of VIN and can be viewed in the TYPICAL PERFORMANCE CHARACTERISTICS section. If a transient is expected to last above the maximum continuous current rating for a significant amount of time then the output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the LP2996 is designed to handle large transient output currents it is not capable of handling these for long durations, under all conditions. The reason for this is the standard packages are not able to thermally dissipate the heat as a result of the internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal derating should always be used (please refer to the Thermal Dissipation section). If the junction temperature exceeds the thermal shutdown point than VTT will tri-state until the part returns below the hysteretic trip-point. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50k resistors. This guarantees that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5V signal, which will create a 1.25V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over temperature). VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2996 then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors. Component Selections INPUT CAPACITOR The LP2996 does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 50 F. Ceramic capacitors can also be used, a value in the range of 10 F with X5R or better would be an ideal choice. The input capacitance can be reduced if the LP2996 is placed close to the bulk capacitance from the output of the 2.5V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47uF capacitor should be placed as close to possible to the PVIN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device. SHUTDOWN The LP2996 contains an active low shutdown pin that can be used to tri-state VTT. During shutdown VTT should not be exposed to voltages that exceed AVIN. With the shutdown pin asserted low the quiescent current of the LP2996 will drop, however, VDDQ will always maintain its constant impedance of 100k for generating the internal reference. Therefore to calculate the total power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal OUTPUT CAPACITOR The LP2996 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT. As a general recommendation the output capacitor should be sized above 100 F with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the 9 www.ti.com LP2996 Pin Descriptions LP2996 maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are highlighted below: AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (between 20 kHz and 100 kHz) should be used for the LP2996. To improve the ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly increase at cold temperatures. Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100 F range, but they have excellent AC performance for bypassing noise because of very low ESR (typically less than 10 m). However, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic capacitors. Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance are critical, although their cost is typically higher than any other capacitor. 20057507 FIGURE 2. JA vs Airflow (SO-8) Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout it is possible to reduce the JA further than the nominal values shown in Figure 2 Layout is also extremely critical to maximize the output current with the LLP package. By simply placing vias under the DAP the JA can be lowered significantly. Figure 3 shows the LLP thermal data when placed on a 4-layer JEDEC board with copper thickness of 0.5/1/1/0.5 oz. The number of vias, with a pitch of 1.27 mm, has been increased to the maximum of 4 where a JA of 50.41C/W can be obtained. Via wall thickness for this calculation is 0.036 mm for 1oz. Copper. Thermal Dissipation Since the LP2996 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax - TAmax From this equation, the maximum power dissipation (PDmax) of the part can be calculated: PDmax = TRmax / JA The JA of the LP2996 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the JA of the SO-8 is 163C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 151.2C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Figure 2 shows how the JA varies with airflow for the two boards mentioned. 20057508 FIGURE 3. LLP-16 JA vs # of Vias (4 Layer JEDEC Board)) Additional improvements in lowering the JA can also be achieved with a constant airflow across the package. Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 4 shows how the JA varies with airflow. www.ti.com 10 PD = PAVIN + PVDDQ + PVTT Where, PAVIN = IAVIN * VAVIN PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ To calculate the maximum power dissipation at VTT both conditions at VTT need to be examined, sinking and sourcing current. Although only one equation will add into the total, VTT cannot source and sink current simultaneously. PVTT = VVTT x ILOAD (Sinking) or PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing The power dissipation of the LP2996 can also be calculated during the shutdown state. During this condition the output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN and the constant impedance that is seen at the VDDQ pin. 20057509 FIGURE 4. JA vs Airflow Speed (JEDEC Board with 4 Vias) Optimizing the JA and placing the LP2996 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN and VDDQ. During the PD = PAVIN + PVDDQ PAVIN = IAVIN x VAVIN PVDDQ = VVDDQ * IVDDQ = VVDDQ2 x RVDDQ 11 www.ti.com LP2996 active state (when shutdown is not held low) the total internal power dissipation can be calculated from the following equations: LP2996 Typical Application Circuits Several different application circuits have been shown in Figure 5 through Figure 14 to illustrate some of the options that are possible in configuring the LP2996. Graphs of the individual circuit performance can be found in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output current is affected by changes in AVIN and PVIN. SSTL-2 APPLICATIONS For the majority of applications that implement the SSTL-2 termination scheme it is recommended to connect all the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation and component count and selection. An example of this circuit can be seen in Figure 5. 20057510 FIGURE 5. Recommended SSTL-2 Implementation If power dissipation or efficiency is a major concern then the LP2996 has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients will be encountered. 20057511 FIGURE 6. Lower Power Dissipation SSTL-2 Implementation The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to use 2.5V, is to connect the LP2996 power rail to 3.3V. In this situation AVIN will be limited to operation on the 3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the down- www.ti.com side of higher thermal dissipation. Care should be taken to prevent the LP2996 from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V rail. 12 LP2996 20057512 FIGURE 7. SSTL-2 Implementation with higher voltage rails the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. For new designs, the LP2997 or LP2998 is recommended for DDR-II applications. DDR-II APPLICATIONS With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996 in applications utilizing DDRII memory. Figure 6 and Figure 7 show several implementations of recommended circuits with output curves displayed in the Typical Performance Characteristics. Figure 6 shows 20057513 FIGURE 8. Recommended DDR-II Termination If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current. 20057514 FIGURE 9. DDR-II Termination with higher voltage rails 13 www.ti.com LP2996 from VTT to the VSENSE pin. This has been illustrated in Figures 10 and 11. Figure 10 shows how to use two resistors to level shift VTT above the internal reference voltage of VDDQ/2. To calculate the exact voltage at VTT the following equation can be used. LEVEL SHIFTING If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times VDDQ for regulating the output voltage. Several options are available to scale the output to any voltage required. One method is to level shift the output by using feedback resistors VTT = VDDQ/2 ( 1 + R1/R2) 20057515 FIGURE 10. Increasing VTT by Level Shifting VTT = VDDQ/2 (1 - R1/R2) Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below: 20057516 FIGURE 11. Decreasing VTT by Level Shifting VREF voltage of approximately 0.75V for the termination resistors. AVIN and PVIN should be connected to a 2.5V rail for optimal performance. HSTL APPLICATIONS The LP2996 can be easily adapted for HSTL applications by connecting VDDQ to the 1.5V rail. This will produce a VTT and 20057517 FIGURE 12. HSTL Application www.ti.com 14 OUTPUT CAPACITOR SELECTION For applications utilizing the LP2996 to terminate SSTL-2 I/O signals the typical application circuit shown in Figure 11 can be implemented. 20057518 FIGURE 13. Typical SSTL-2 Application Circuit This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. Figure 12 shown below depicts an example circuit where 2 bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost. 20057519 FIGURE 14. Typical SSTL-2 Application Circuit for Motherboards In most PC applications an extensive amount of decoupling is required because of the long interconnects encountered with the DDR-SDRAM DIMMs mounted on modules. As a re- sult bulk aluminum electrolytic capacitors in the range of 1000uF are typically used. 15 www.ti.com LP2996 tor divider or one of the LP2996 signals. Because VREF and VTT are expected to track and the part to part variations are minor, there should be little difference between the reference signals of each LP2996. QDR APPLICATIONS Quad data rate (QDR) applications utilize multiple channels for improved memory performance. However, this increase in bus lines has the effect of increasing the current levels required for termination. The recommended approach in terminating multiple channels is to use a dedicated LP2996 for each channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate VREF signals can be used for each DIMM bank from the corresponding regulator with the chipset reference provided by a local resis- LP2996 PCB Layout Considerations 1. 2. 3. 4. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. For improved thermal performance excessive top side copper should be used to dissipate heat from the www.ti.com 5. 6. 16 package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing standards permit. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long SENSE traces are used. VREF should be bypassed with a 0.01 F or 0.1 F ceramic capacitor for improved performance. This capacitor should be located as close as possible to the VREF pin. LP2996 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Package (M8) NS Package Number M08A 17 www.ti.com LP2996 16-Lead LLP Package (LD) NS Package Number LQA16A 8-Lead PSOP Package (PSOP-8) NS Package Number MRA08A www.ti.com 18 LP2996 Notes 19 www.ti.com LP2996 DDR Termination Regulator Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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