Page 1 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
The PE 43 501 is a HaR P™-enhanced, high linearity, 5-bit RF
Digital Step Attenuator (DSA). This highly versatile DSA
covers a 7.75 dB attenuation range in 0.25 dB steps. The
Peregri ne 50Ω RF DSA provides a serial-addressable CMOS
control interface. It maintains high attenuation accuracy over
frequency and temperature and exhibits very low insertion loss
and low power consumption. Performance does not change
with VDD d ue to on - board regulator. This next gener ation
Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint.
The PE43501 is manufactured on Peregrine’s UltraCMOS™
pro c ess, a patented variation of silicon -on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the eco nom y an d i nte gr ation of co nventi on al
CMOS.
Pro duct Specificat ion
50 Ω RF Di gital Attenuator
5-bit, 7.75 dB, 9 kHz - 6.0 GHz
Product Description
Figure 2. Functional Schematic Dia gram
PE43501
Features
• HaRP ™-enha nced UltraCMOS™ device
• Attenuation: 0.25 dB steps to 7.75 dB
• Hi gh Li ne ar it y: Typical + 5 8 dBm IP3
• Excellent low-frequency performance
• 3.3 V or 5.0 V Power Supply Voltage
• Fast swit ch sett ling time
• Programming Modes:
• Direct Parallel
• Latc he d Par al lel
• Serial-Addressable: Program up to
eight addresses 000 - 111
• High-attenuation state @ power-up (PUP)
• CMOS Compatible
• No DC b locking capacitors required
• Packaged in a 32-lead 5x5x0.85 mm QFN
Fig ur e 1. Pa ck ag e Typ e
32-l e ad 5x 5x 0. 85 mm QFN Packag e
Control Logic Interface
RF Input RF Output
Switched Attenuator Array
Serial In
LE
CLK
A0 A1 A2
Parallel Control 5
P/S
Product Specification
PE43501
Page 2 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
012345678
Attenuation Setting (dB)
Attenuation Error (dB
)
200 MHz 900 MHz 1800 MHz 2200 MHZ
3000 MHz 4000 MHz 5000 MHz 6000 MHz
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
0 1000 2000 3000 4000 5000 6000
Frequency (MHz)
Bit Error (dB)
0.25dB State 0.5dB State 1dB State
2dB State 4dB State 7.75dB State
-0.25
0.00
0.25
0.50
0.75
1.00
012345678
Attenuation Setting (dB)
Step Error (dB)
200 MHz 900 MHz 1800 MHz 2200 MHz
3000 MHz 4000 MHz 5000 MHz 6000 MHz
123456708
1
2
3
4
5
6
7
0
8
Attenuation State
Attenuation dB
A
ttenuation
900 MHz
1800 MHz
2200 MHz
3000 MHz
5400 MHz
5800 MHz
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V
Parameter Test Condit ions Frequency Min Typical Max Units
Frequency Range 9 kHz 6 GHz
Attenuation Range 0.25 dB Step 0 – 7.75 dB
Insertion Loss 9 kHz ≤ 6 GHz 2.3 2.8 dB
Attenuation Error
0 dB - 7.75 dB Atten uatio n se tt i ngs
0dB to 3.5 dB Attenuation Settings
3.7 5 dB to 7.75 dB A tt enua tion Settings
0dB to 7.75dB Attenuation Settings
9 kH z < 4 G Hz
4 GHz ≤ 6 GHz
4 GHz ≤ 6 GHz
4 GHz ≤ 6 GHz
±(0.15+4%)
+0.2+4%
+0.3+4%
-0.2 - 4%
dB
dB
dB
dB
Return Loss 9 kHz - 6 GHz 18 dB
Relative Phase All States 9 kHz - 6 GHz 9 deg
P1dB (note 1) Input 20 MHz - 6 GHz 30 32 dBm
IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 6 GHz 58 dBm
Typical Spurious Value 1 MHz -110 dBm
Video Feed Through 10 mVpp
Switching Time 50% CTRL to 10% / 90% RF 650 ns
RF Trise/Tfall 10% / 90% RF 400 ns
Sett ling Time RF settled to within 0.05 dB of final value
RBW = 5 MHz, Averaging ON. 4 µs
Figure 3. 0.25 dB Step E rror vs. Frequency*
Figure 5. 0.25 dB Major State Bit Error
Performance Plots
Figure 4. 0.25dB Attenuation vs. Attenuation
State
*Monotonicity is held so long as Step-Error does not cross below -0.25
Figure 6. 0.25 dB Attenuation Error vs. Frequency
Note: 1. Please note Maximum Operating Pin (50Ω) of +2 3 dBm as sh ow n in Tabl e 3.
Product Specification
PE43501
Page 3 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
-70
-60
-50
-40
-30
-20
-10
0
0123456789
Freque ncy (GHz)
Return Loss (dB)
-40C 25C 85C
-60
-50
-40
-30
-20
-10
0
0123 4 56789
Frequency (GHz)
Return Loss (dB)
-40C 25C 85C
-60
-50
-40
-30
-20
-10
0
0123456789
Frequency (GHz)
Return Loss (dB)
0dB 0.25dB 0.5dB 1dB
2dB 4dB 7.75dB
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0123456789
Frequency (GHz)
Return Loss (dB)
0dB 0.25dB 0.5dB 1dB
2dB 4dB 7.75dB
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
0
0123456789
Frequency (GHz)
Insertion Loss (dBm)
-40C +25C +85C
Figure 9. Output Return Loss vs. Attenuation:
T = +25C
Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenua tion:
T = +25C
Figure 10. Input Return Loss v s. Temperature:
7.75 dB State
Figure 11. Output Return Loss vs. Temperature :
7.75 dB State Figure 12. Relative Phase vs. Frequency
0
2
4
6
8
10
12
14
16
012345678
Frequency (GHz)
Relative Phase Error (Deg)
0dB 0.25dB 0.5dB 1dB
2dB 4dB 7.75dB
Product Specification
PE43501
Page 4 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
30
35
40
45
50
55
60
65
70
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)
Input IP3 (dBm)
0dB 0.25dB 0.5dB 1dB 2dB 4dB
-1. 5
-1. 0
-0. 5
0.0
0.5
1.0
1.5
012345678
Attenuation Setting (dB)
Attenuation Error (dB)
+25C -40C +85C
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
012345678
Attenuation Setting (dB)
Attenuation Error (dB)
+25 C -40C +85C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-40 -20 0 20 40 60 80
Temperature (Deg. C)
Phase (Deg)
900 MHz 1800 MHz 3000 MHz
Figure 15. Attenuation Error vs . Attenuation
Se tting: 1800 MHz
Figure 13. Relative Phase vs. Temperature:
7.75 dB State Figure 14. Attenuation Error vs. Attenuation
Setting: 900 MHz
Figure 16. Attenuation Error vs. Attenuation
Setting: 3000 MHz
Figure 17. Input IP3 vs. Frequency
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
012345678
Attenuation Setting (dB)
Attenuation Error (dB)
+25C -40C +85C
Product Specification
PE43501
Page 5 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Figure 18. Pin Configurati on (Top View)
8
7
6
5
4
3
2
124
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
161514131211109
Exposed
Solder pad
NC
VDD
P/S
A0
GND
GND
RF1
GND
GND
GND
GND
GND
GND
GND
GND
GND
CLK
LE
A1
A2
GND
GND
RF2
GND
C0.25
C0.5
C1
C2
C4
GND
GND
SI
Table 2 . Pin Descriptions
Expose d Solder Pad Connection
The exposed solder pad on the bottom of t he pac k age
must be grounded f or pr oper dev ic e oper ation.
Pin No. Pin Name Description
1 N/C No Connect
2 VDD Power supply pin
3 P/S Serial/Parallel mode select
4 A0 Address bit A0 connection
5, 6, 8-1 7,
19, 20, 26,
27 GND Ground
7 RF1 RF1 port
18 RF2 RF2 port
21 A2 Address bit A2 connection
22 A1 Address bit A1 connection
23 LE Serial in terf ac e Latc h Enab le in put
24 CLK Serial interface Clock input
25 S I Seri al in terfac e Dat a in put
28 C4 (D4) Parallel control bit, 4 dB
29 C2 (D3) Parallel control bit, 2 dB
30 C1 (D2) Parallel control bit, 1 dB
31 C0.5 (D1) Parallel control bit, 0.5 dB
32 C0.25 (D0) Parallel control bit, 0.25 dB
Pad dl e GND Grou nd f or pr op er op er a tion
Swi tc hing Frequency
The PE 43501 has a maxim um 25 kHz switc hing r ate.
Switc hing rate is defined to be the speed at which the
DSA can be toggled across attenuation st ates.
Electrostatic Discharge (ESD) Precautions
When handling t his Ultr aCM OS™ device, obs er v e the
same pr ec autions t hat you would us e with other ESD-
sensit ive devices . Alt hough this devic e contains
circ uitry to protect it from dam age due to ES D,
precautions should be taken t o av oid ex c eeding the
specif ied rating.
Latc h-Up Avoidance
Unlike conventional CMO S devices, UltraCMOS™
devices ar e im m une to latc h- up.
Moist u re Sen sit i vit y L evel
The Moisture Sensitivity Level rating for the PE43501 in
the 32-lead 5x5 QFN package is MSL1.
Note: Ground C0. 25, C0. 5, C1 C2, C4, if not in use.
Product Specification
PE43501
Page 6 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
0
5
10
15
20
25
30
1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09
Hz
Pin dBm
Table 3. Opera ti ng Ranges Table 4. Absolute Max imum Rati ngs
Exceeding absolute m ax im um r atings may cause
permanent damage. Operation should be res tricted to
the limits in t he Operating Ranges t able. Operat ion
between operating range m ax im um and abs olute
maxim um for extended periods m ay r educ e r eliability.
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 6.0 V
VI Voltage on any Digital input -0.3 5.8 V
TST Storage temperature range -65 150 °C
VESD ESD voltage ( HBM)1
ESD voltage ( M achine Mod el) 500
100 V
V
PIN Input power (50Ω)
9 kHz ≤ 20 MHz
20 MHz ≤ 6 GHz
See fig. 19
+23
dBm
dBm
Parameter Min Typ Max Units
VDD Power Supply Voltage 3.0 3.3 V
IDD Power Supply Current 70 350 µA
Digital Input High 2.6 5.5 V
PIN Input power ( 50Ω):
9 kHz ≤ 20 MHz
20 MHz ≤ 6 GHz
See fi g. 19
+23
dBm
dBm
TOP Opera ti ng te m perat u re
range -40 25 85 °C
Digital Input Low 0 1 V
Digital Input Leakage1 15
µA
VDD Power Supply Voltage 5.0 5.5 V
Note 1. Input leakage current per Control pin
Note : 1. H u ma n B ody M od el (H BM, MIL_STD 88 3 Meth od 301 5. 7)
Figure 19. Maximum Power Handling Capability: Z0 = 50 Ω
Product Specification
PE43501
Page 7 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Table 5. Control Voltage
Table 6. Latch and Clock Specifications
Table 9. Serial Attenuation Word Truth Table
Table 8. Address Word Truth Tabl e
Table 10. Serial-Addressable Register Map
Q15 Q14 Q13 Q12 Q11 Q10
A7 A6 A5 A4 A3 A2
Q9 Q8 Q7 Q6 Q5 Q4
A1 A0 D7 D6 D5 D4
Q3 Q2 Q1 Q0
D3 D2 D1 D0
Address Word Attenuation Word
LSB (first in)
MSB (last in)
Attenuation Word is derived directly from the attenuation value. For example, to program the 3.75 dB state at
addr es s 3:
Address Word: XXXXX011
Atte nuation Word: Multiply by 4 and convert to binary → 4 * 3.75 dB → 15 → 00001111
Serial Input: XXXXX01100001111
Parallel Control Setting A tten uati on Sett ing
RF1-RF2
D4 D3 D2 D1 D0
L L L L L Reference I.L.
L L L L H 0.25 dB
L L L H L 0.5 dB
L L H L L 1 dB
L H L L L 2 dB
H L L L L 4 dB
H H H H H 7.75 dB
Table 7. Parallel Truth Table
State Bias Condition
Low 0 to +1.0 Vdc at 2 µA (typ)
High +2.6 to +5 Vdc at 10 µA (typ)
Latch Enable Function
X Shift Regi st er Cl ocked
↑ Contents of shif t register
trans ferr ed t o attenuat or cor e
Shift Clock
↑
X
Address Word Address
Setting
A7
(MSB) A6 A5 A4 A3 A2 A1 A0
X X X X X L L L 000
X X X X X L L H 001
X X X X X L H L 010
X X X X X L H H 011
X X X X X H L L 100
X X X X X H L H 101
X X X X X H H L 110
X X X X X H H H 111
Attenuation Wor d Attenuation
Setting
RF1-RF2
D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
L L L L L L L L Reference I.L.
L L L L L L L H 0.25 dB
L L L L L L H L 0.5 dB
L L L L L H L L 1 dB
L L L L H L L L 2 dB
L L L H L L L L 4 dB
L L L H H H H H 7.75 dB
Bits can either be set to logic high or logic low
D5, D6 an d D7 must be set to lo gic low
Product Specification
PE43501
Page 8 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
Programming Options
Parallel/Serial Selection
Either a parallel or serial-addressable interface can
be used to control the PE43501. The P/S b it
provides this se lectio n, with P/S=LOW selecting the
parallel interface and P/S=HIGH selecting the serial-
addressable interface.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in T abl e 7.
The parallel interface timing requirements are
defined by Fig. 21 (Parallel Interface Timing
Diagram), Table 12 (Pa rallel Interface AC
Characteristics), and switching speed (Table 1).
For latched-parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Fig. 21) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
at tenuation state control v alues will change devic e
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Serial-Addressable Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of
8-bits each. The first word is the Attenuation Word,
which controls the state of the DSA. The second
word is the Address Word, which is compared to the
static (or programmed) logical states of the A0, A1
and A2 digital inputs. If there is an address match,
the DSA changes state; otherwise its current state
will rema in un ch anged. Fig. 20 illustrates an
example timing diagram for programming a state. It
is required that all parallel control inputs be
grounded when the DSA is used in serial-
addressable mode.
The serial-addressable interface is controlled using
three CMOS-compatible signals: Serial-In (SI),
Clock (CLK), and Latch Enable (LE). The SI and
CLK inputs allow data to be serially entered into the
shift register. Serial data is clocked in LSB first,
beginning with the Attenuation Word.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. Address word and
attenuation word truth tables are listed in Table 8 &
Table 9, respectively. A programming example of the
serial-addressable register is illustrated in Table 10.
The serial-addressable timing diagram is illustrated
in Fig. 20.
Power-up Control Settings
The PE43 501 will always init ialize t o the maximum
attenuation setting (7.75 dB) on power-up for both
the serial-addressable and latched-parallel modes of
operation and will remain in this s etting unt il the user
latches in the next programming word. In direct-
parallel mode, the DSA can be preset to any state
within the 7.75 dB range by pre-setting the parallel
control pins prior to power-up. In this mode, there is
a 400-µs delay between the time the DSA is
powered-up to the time the desired state is
set. During this power-up delay, the device
attenuates to the maximum attenuation setting (7.75
dB) before defaulting to the user defined state. If the
control pins are left floating in this mode during
power-up, the dev ic e will de fault to the minimum
attenuation setting (insertion loss state).
Dynamic operation between serial-addressable and
parallel programming modes is possible.
If the DSA powers up in serial-addressable mode (P/
S = HIGH), all the parallel control inputs DI[4:0] must
be set to logic low. Prior to toggling to parallel mode,
the DSA must be programmed serially to ensure
D[7 ] is set to logic low.
If the DSA powers up in either latched or direct-
parallel mode, all parallel pins DI[4:0] must be set to
logic low prior to toggling to serial-addressable mode
(P/S = HIGH), and held low until the DSA has been
programmed serially to ensure bit D[7] is set to logic
low.
The sequencing is only required once on power-
up. Once completed, the DSA may be toggled
between serial-addressable and parallel
programming modes at will.
Product Specification
PE43501
Page 9 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Table 12. Paral lel and Direct Inte rface
AC Characteristics
Table 1 1. Ser ial- A dd ressab l e In t erf a ce
AC Characteristics
VDD = 3. 3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified
Figure 20. Serial-Addressable Timing Diagram
Figure 21. Latched-Parallel/Direc t-Parallel Timing Diagram
Symbol Parameter Min Max Unit
FCLK Serial clock frequency - 10 MHz
TCLKH Serial clock HIGH time 30 - ns
TCLKL Serial clock LOW time 30 - ns
TLESU Last serial clock rising edge
setup time to Latch Enable
rising edge 10 - ns
TLEPW Latch Ena bl e min. pu ls e wi dth 30 - ns
TSISU Serial d ata set up time 10 - ns
TSIH Serial data hold time 10 - ns
TDISU Parall el da t a set up time 10 0 - ns
TDIH Parallel data hold time 100 - ns
TASU Address setup time 100 - ns
TAH Address hold time 100 - ns
TPSSU Parallel/Serial setup time 100 - ns
TPSH Parallel/Serial hold time 100 - ns
TPD Digital register delay (internal) - 10 ns
Symbol Parameter Min Max Unit
TLEPW Latch Enable minimum
pulse width 30 - ns
TDISU Parall el data setup time 10 0 - ns
TDIH Parallel data hold time 100 - ns
TPSSU Parallel/Serial setup time 100 - ns
TPSIH Parallel/Serial hold time 100 - ns
TPD Digital register delay
(internal) - 10 ns
TDIPD Digital register delay
(internal, direct mode only) - 5 ns
VALID
T
DISU
T
DIH
DI[4:0]
LE
P/S
T
PSSU
T
PSH
T
LEPW
VALID
DO[4:0]
T
DIPD
T
PD
A[2]A[1]A[0]
TSISU
TCLKL
TLEPW
TSIH
TCLKH
SI
CLK
LE
P/S
TLESU
TPSSU TPS IH
VALID
TASU
ADD[2:0]
TAIH
DO[6:0]
VALID
DI[4:0]
TPD
TDISU TDIH
D[6]D[5]D[4]D[3]D[2]D[1]D[0] D[7]
D[5], D[6] and D[7] must be set to logic low
Bits can either be set to logic high or logic low
Product Specification
PE43501
Page 10 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
Evaluation Kit
The Di gi tal Att en ua t or E val u ation Kit boar d was
designed to ease cus t om er ev aluati on of th e
PE43501 Digital Step Attenuator.
Direct-Parallel Programming Procedure
For automated direct-parallel programming,
connect the test harness provided with the EVK
from the parallel port of the PC to the J1 & Serial
header pin and set the D0-D4 SP3T switches to
the ‘MIDDLE’ toggle position. Position the
Pa rallel/S erial (P/ S) select switch to the Para llel
(or left) position. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Direct-Parallel mode.
Using the software, enable or disable each setting
to the desired attenuation state. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
For manual direct-parallel programming,
disconnect the test harness provided with the EVK
from the J1 and Serial header pins. Position the
Pa rallel/S erial (P/ S) select switch to the Para llel
(or left) position. The LE pin on the Serial header
must be tied to logic high. Switches D0-D4 are
SP3T switches which enable the user to manually
program the parallel bits. When any input D0-D4
is toggled ‘UP’, logic high is presented to the
paralle l input. When toggled ‘DOWN’, logic low is
presented to the parallel input. Setting D0-D4 to
the ‘MID DL E’ toggle pos iti on pr esents an OPEN,
which forces an on-chip logic low. Table 7 depicts
the parallel programming truth table and Fig. 21
illust rate s the pa ralle l programming timing
diagram.
Latc he d- P ar al l el Programm ing Pr ocedure
For automated latched-parallel programming, the
procedure is identical to the direct-parallel
method. The user only must ensure that Latched-
Parallel is selected in the so ftware.
For manual latched-parallel programming, the
procedure is identical to direct-parallel except now
Figure 22. Evaluati on Board Layout
Peregr ine S pec ificat ion 101- 0312
the LE pin on the Serial header must be logic low
as the parallel bits are applied. The user must
then pulse LE from 0V to VDD and back to 0V to
latch the programming word into the DSA. LE
must be logic low prior to programming the next
word.
Seri al - A ddr essable Pr ogramm ing Pr ocedure
Po sition the Parallel/Serial (P/S) select switch to
the Serial (or right) position. Prior to
programming, the user must define an address
setting using the ADD header pin. Jump the
mi ddl e pins o n the AD D hea der A0-A2 ( or lower )
row of pins to set logic high, or jump the middle
pins to the upper row of pins to set logic low. If
the ADD pi ns are l eft op e n, the n 000 be come the
default address. The evaluation software is
written to operate the DSA in either Parallel or
Serial-Addressable Mode. Ensure that the
software is set to program in Serial-Addressable
mode. Using the software, enable or disable each
setting to the desired attenuation state. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
Not e : Refe rence Fig. 23 for Evaluat ion Board Schemat ic
Product Specification
PE43501
Page 11 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Z=50 Ohm
De-embeding tr ace
Z=50 Ohm
Z=50 Ohm
PE43XOX DSA 50 OHM 5X5 MLPQ32
_
_
_
3
1
2
4
D3
C1
100pF
C6
100pF
3
1
2
4
D0
1
2
J4
SMA
5
4
6
P/S
C3
100pF
1
2
J2
CON
2
3
1
2
4
D4
R1
0 OHM
C0
100pF
C12
100pf
3
1
2
4
D5
R2
0 OHM
1
13
35
57
7
22
44
66
88
10 10
12 12
14 14 13
13
9
911
11
J1
HEADER 14
1
2
J7
SMA
C2
100pF
C10
100pF
3
1
2
4
D6
C11
0.1uF
1GND
2VDD
3PS
4A0
5GND
6GND
7RF1
8GND
9GND
10 GND
11 GND
12 GND
13 GND
14 GND
15 GND
16 GND
17
GND
18
RF2
20
VSS
19
GND
21
A2
22
A1
23
LE
24
CLK
25
SI
26
C16
27
C8
28
C4
29
C2
30
C1
31
CP5
32
CP25
U1
1
2
J5
SMA
3
1
2
4
D1
1
2
J6
SMA
C4
100pF
C8
100pF
C9
0.1µF
3
1
2
4
D2
C5
100pF
1
2
J3
CON2
1CLOCK
2SI
3LE
4GND
SER IAL
HEADER 4
C13
100pF
C14
100pF
A0_2 A0
A1_2 A1
A2_2 A2
A2_1
VDD A1_1
VDD A0_1
VDD
ADD
HEADER3X3
VDD
VDD
VSS
P/S
D6
D3
D3
D2
D1
D1
D4
D4
D5
D5
D0
P/S
D6
D3
D2
D1
D4
D5
D0
D0
D2
D6
CLK
SI
LE
A0
A1
A2
VDD
VDD
Figure 24. Package Drawing
QFN 5x5 mm
A MAX 0.900
NOM 0.850
MIN 0.800
Figure 23. Evaluation Board Schematic
Peregr ine S pec ificat ion 102- 0381
Note: Capacitors C1-C8, C13, & C14 may be omitted. Pin 26 & 27 are ground.
On the PE43501 pin 20 (shown as VSS) mus t als o be grou nded .
Product Specification
PE43501
Page 12 of 13
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-05 │ UltraCMOS™ RFIC Solutions
Table 13. Ordering Information
Orde r Code Part Marking Description Package Shipping Method
PE43501MLI 43501 PE43501 G - 32QFN 5x5mm-75A Green 32-lead 5x5mm QFN Bulk or tape cut from reel
PE43501MLI-Z 43501 PE43501 G – 32QFN 5x5mm-3000C Green 32-lead 5x5mm QFN 3000 units / T&R
EK43501-01 43501 PE43501 – 32QFN 5x5mm-EK Evaluation Kit 1 / Box
Figure 25. Marking Specifications
43501
YYWW
ZZZZZ YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Figure 24. Tape and Reel Draw ing
Device Orientation in Tape
Top of
Device
Pin 1
Tape Feed Dire c t ion
Product Specification
PE43501
Page 13 of 13
Document No. 70-0251-05 │www. pse mi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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For a list of r epresentatives in your area, please ref er to our Web site at: www.psem i.com
Data Sheet Identification
Advance Information
The product is in a format ive or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the r ight
to change specificat ions at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify
customer s of t he intended changes by issuing a CNF
(Customer Notification Form).
The inform ation in t his dat a sheet is believed to be reliable.
Howeve r, Peregrine assum es no liability f or th e use of this
information. Use shall be entirely at t he user’s own r isk.
No pat ent rights or licenses to any circuits described in this
data sheet are im plied or granted t o any third party.
Peregrine’s products are not designed or intended f or use in
devices or system s intended for surgical implant, or in other
applications intended to support or sustain life, or in any
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Peregr ine assum es no liability for damages, including
consequential or incident al damages, arising out of the use of
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The Per egr ine name, logo, and UTSi are register ed t r ademarks
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of Peregr ine Semiconductor Corp.
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