HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N HCMOS Compatible, High CMR, 10 MBd Optocouplers Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-261A family of optically coupled gates shown on this data sheet provide all the benefits of the industry standard 6N137 family with the added benefit of HCMOS compatible input current. This allows direct interface to all common circuit topologies without additional LED buffer or drive components. The AlGaAs LED used allows lower drive currents and reduces degradation by using the latest LED technology. On the single channel parts, an enable output allows the detector to be strobed. The output of the detector IC is an open collector schottky-clamped transistor. The internal shield provides a minimum common mode transient immunity of 1000V/s for the HCPL-261A family and 15000 V/s for the HCPL-261N family. * HCMOS/LSTTL/TTL performance compatible Functional Diagram HCPL-261A/261N HCPL-061A/061N 1 8 VCC ANODE 2 7 CATHODE 3 NC 4 SHIELD * High speed: 10 MBd typical * AC and DC performance specified over industrial temperature range -40C to +85C * Available in 8 pin DIP, SOIC-8 packages * Safety approval: - UL recognized per UL1577 3750V rms for 1 minute and 5000V rms for 1 minute (Option 020) - CSA Approved - IEC/EN/DIN EN 60747-5-5 approved Applications HCPL-263A/263N HCPL-063A/063N NC * 1000 V/s minimum Common Mode Rejection (CMR) at VCM = 50 V (HCPL-261A family) and 15 kV/s minimum CMR at VCM = 1000 V (HCPL-261N family) * Low input current (3.0 mA) HCMOS compatible version of 6N137 optocoupler ANODE 1 1 8 VCC VE CATHODE 1 2 7 VO1 * Isolated line receiver 6 VO CATHODE 2 3 6 VO2 * Simplex/multiplex data transmission 5 GND ANODE 2 4 5 GND * Computer-peripheral interface SHIELD * Digital isolation for A/D, D/A conversion TRUTH TABLE (POSITIVE LOGIC) LED ON OFF ON OFF ON OFF ENABLE H H L L NC NC OUTPUT L H H H L H TRUTH TABLE (POSITIVE LOGIC) LED ON OFF OUTPUT L H * Switching power supplies * Instrumentation input/output isolation * Ground loop elimination * Pulse transformer replacement The connection of a 0.1 F bypass capacitor between pins 5 and 8 is required. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide Input Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Widebody Hermetic On-Single DualSingleDual Single Single and dV/dt VCM Current Output Channel ChannelChannelChannel Channel Dual Channel (V/s) (V) (mA) Enable Package Package Package Package Package Packages NA NA 5 YES 6N137[1]HCPL-0600[1] HCNW137[1] NO 5,000 50 YES NO 10,000 1,000 YES NO 1,000 50 YES HCPL-2602[1] 3,500 300 YES HCPL-2612[1] 1,000 50 YES HCPL-261A 3 HCPL-2630[1]HCPL-0630[1] HCPL-2601[1]HCPL-0601[1] HCNW2601[1] HCPL-2631[1]HCPL-0631[1] HCPL-2611[1]HCPL-0611[1] HCNW2611[1] HCPL-4661[1]HCPL-0661[1] HCPL-061A NO HCPL-263AHCPL-063A 1,000[2]1,000 YES HCPL-261N HCPL-061N NO HCPL-263NHCPL-063N [3] 1,000 50 12.5 HCPL-193x[1] HCPL-56xx[1] HCPL-66xx[1] Notes: 1. Technical data are on separate Avago publications. 2. 15 kV/s with VCM = 1 kV can be achieved using Avago application circuit. 3. Enable is available for single channel products only, except for HCPL-193x devices. Schematic IF HCPL-263A/263N HCPL-063A/063N HCPL-261A/261N HCPL-061A/061N ICC 8 2+ IO 6 VF VCC VO 1 ICC 8 IF1 IO1 + 7 VF1 VCC VO1 - 2 - 3 SHIELD IE 7 VE USE OF A 0.1 F BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 16). 5 SHIELD GND 3 IF2 IO2 - 6 VF2 VO2 + 4 SHIELD 2 5 GND Ordering Information HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577. Part number HCPL-261A HCPL261N HCPL-263A HCPL263N HCPL-061A HCPL061N HCPL-063A HCPL063N Option RoHS Non RoHS Compliant Compliant -000E No option -300E #300 -500E #500 -020E #020 -320E -320 -520E -520 -060E #060 -560E #560 -000E No option -300E #300 -500E #500 -020E #020 -320E #320 -520E -520 -060E #060 -360E #360 -560E -000E No option -300E #300 -500E #500 -020E #020 -320E #320 -520E -520 -000E No option -300E #300 -500E #500 -020E #020 -320E #320 -520E #520 -000E No option -500E #500 -060E #060 -560E #560 -000E No option -500E #500 Package 300mil DIP-8 300mil DIP-8 300mil DIP-8 300mil DIP-8 SO-8 SO-8 Surface Mount Gull Wing Tape & Reel X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X UL 5000 Vrms/1 Minute rating X X X X X X X X X X X X IEC/EN/DIN EN 60747-5-5 Quantity 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel X 50 per tube X 1000 per reel 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel X 50 per tube X 50 per tube X 1000 per reel 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel 50 per tube 50 per tube 1000 per reel 100 per tube 1500 per reel X 100 per tube X 1500 per reel 100 per tube 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Combination of Option 020 and Option 060 is not available. Example 1: HCPL-261A-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant. Example 2: HCPL-263N to order product of 300mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use `-XXXE`. 3 HCPL-261A/261N/263A/263N Outline Drawing Pin Location (for reference only) 9.40 (0.370) 9.90 (0.390) 8 TYPE NUMBER 7 6 5 OPTION CODE* A XXXXZ DATE CODE 7.36 (0.290) 7.88 (0.310) YYWW 1 PIN ONE 2 0.20 (0.008) 0.33 (0.013) 6.10 (0.240) 6.60 (0.260) 3 5 TYP. 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. DIMENSIONS IN MILLIMETERS AND (INCHES). 3.56 0.13 (0.140 0.005) 4.70 (0.185) MAX. 0.51 (0.020) MIN. 2.92 (0.115) MIN. 0.76 (0.030) 1.40 (0.056) * MARKING CODE LETTER FOR OPTION NUMBERS. "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) Figure 1. 8-Pin dual in-line package device outline drawing. LAND PATTERN RECOMMENDATION 9.65 0.25 (0.380 0.010) 8 7 6 1.02 (0.040) 5 6.350 0.25 (0.250 0.010) 1 2 3 10.9 (0.430) 4 1.27 (0.050) 9.65 0.25 (0.380 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 0.25 (0.300 0.010) 0.20 (0.008) 0.33 (0.013) 3.56 0.13 (0.140 0.005) 1.080 0.320 (0.043 0.013) 2.540 (0.100) BSC 0.635 0.130 (0.025 0.005) 0.635 0.25 (0.025 0.010) DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Figure 2. Gull wing surface mount option #300. 4 2.0 (0.080) 12 NOM. HCPL-061A/061N/063A/063N Outline Drawing LAND PATTERN RECOMMENDATION 8 7 6 5 XXX YWW 3.937 0.127 (0.155 0.005) 5.994 0.203 (0.236 0.008) TYPE NUMBER (LAST 3 DIGITS) 7.49 (0.295) DATE CODE 1 2 3 0.406 0.076 (0.016 0.003) 4 1.9 (0.075) 1.270 BSC (0.050) 7 * 5.080 0.127 (0.200 0.005) 3.175 0.127 (0.125 0.005) 0.64 (0.025) 45 X 0.432 (0.017) 0.228 0.025 (0.009 0.001) 1.524 (0.060) 0.203 0.102 (0.008 0.004) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH) 5.207 0.254 (0.205 0.010) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX. 0.305 MIN. (0.012) NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX. Figure 3. 8-Pin Small Outline Package Device Drawing. Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-261A and HCPL-261N families have been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-5 5 Insulation and Safety Related Specifications Parameter Symbol 8-Pin DIP (300 Mil) Value SO-8 Value Units Conditions Minimum External Air L(101) 7.1 4.9 mm Gap (External Clearance) Measured from input terminals to output terminals, shortest distance through air. Minimum External L(102) 7.4 4.8 mm Tracking (External Creepage) Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic 0.08 0.08 mm Gap (Internal Clearance) Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. Tracking Resistance (Comparative Tracking Index) DIN IEC 112/ VDE 0303 Part 1 CTI 200 200 Volts Isolation Group IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance with CECC 00802. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* Description PDIP Option 060 SO-8 Option 060 Installation classification per DIN VDE 0110, Table 1 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms Symbol I - IV I - IV I - III I - IV I - IV I - III Climatic Classification 40/85/21 40/85/21 Pollution Degree (DIN VDE 0110/39) 2 2 Unit Maximum Working Insulation Voltage VIORM 630 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1181 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 1008 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 6000 Vpeak Safety-limiting values - maximum values allowed in the event of a failure Case Temperature TS 175 150 C Input Current IS, INPUT 230 150 mA Output Power PS, OUTPUT 600 RS 10 Insulation Resistance at TS, VIO = 500 V 600 9 mW 10 9 W * Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-5, for a detailed description. 6 Absolute Maximum Ratings Parameter Symbol Min. Max. UnitsNote Storage Temperature TS -55 125 C Operating Temperature TA -40 +85 C Average Input Current IF(AVG) 10 Reverse Input Voltage VR 3 Volts Supply Voltage VCC -0.5 7 Volts Enable Input Voltage VE -0.5 5.5 Volts Output Collector Current (Each Channel) IO 50 mA Output Power Dissipation (Each Channel) PO 60 mW3 VO Volts Output Voltage (Each channel) Lead Solder Temperature (Through Hole Parts Only) Solder Reflow Temperature Profile (Surface Mount Parts Only) Recommended Operating Conditions Parameter Symbol -0.5 7 mA1 2 260C for 10 s, 1.6 mm Below Seating Plane See Package Outline Drawings section Min. Max. Units Input Voltage, Low Level VFL -3 0.8 V Input Current, High Level IFH 3.0 10 mA Power Supply Voltage VCC 4.5 5.5 Volts High Level Enable Voltage VEH 2.0 VCC Volts Low Level Enable Voltage VEL 0 0.8 Fan Out (at RL = 1 k) N 5 Output Pull-up Resistor RL 330 4k Operating Temperature TA -40 85 C 7 Volts TTL Loads Electrical Specifications Over recommended operating temperature (TA = - 40C to +85C) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions High Level Output Current IOH 3.1 100 A VCC = 5.5 V, VO = 5.5 V, VF = 0.8 V, VE = 2.0 V Low Level Output VOL 0.4 0.6 V VCC = 5.5 V, IOL = 13 mA Voltage (sinking), IF = 3.0 mA, VE = 2.0 V High Level Supply ICCH7 10 mA VE = 0.5 V** Current 9 15 Dual Channel Products*** Low Level Supply ICCL8 13 mA VE = 0.5 V** Current 12 21 Dual Channel Products*** High Level Enable Current** IEH -0.6 -1.6 mA VCC = 5.5 V, VE = 2.0 V Low Level Enable Current** IEL -0.9 -1.6 mA VCC = 5.5 V, VE = 0.5 V Input Forward Voltage VF 1.6 V Temperature Co- efficient of Forward Voltage 1.0 1.3 BVR 3 5V Input Capacitance CIN 60pF *All typical values at TA = 25C, VCC = 5 V **Single Channel Products only (HCPL-261A/261N/061A/061N) ***Dual Channel Products only (HCPL-263A/263N/063A/063N) 4 18 5, 8 4, 18 VCC = 5.5 V IF = 3.0 mA 6 IR = 100 A f = 1 MHz, VF = 0 V Note VCC = 5.5 V 4 IF = 0 mA VF /TA-1.25mV/C IF = 4 mA Input Reverse Breakdown Voltage 8 IF = 4 mA Fig. 4 4 4 Switching Specifications Over recommended operating temperature (TA = -40C to +85C) unless otherwise specified. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Input Current Threshold ITHL 1.5 3.0 mA VCC = 5.5 V, VO = 0.6 V, High to Low IO >13 mA (Sinking) 7, 10 18 Propagation Delay tPLH 52 100 ns IF = 3.5 mA Time to High Output VCC = 5.0 V, Level VE = Open, CL=15pF, Propagation Delay tPHL 53 100 ns RL = 350 Time to Low Output 9, 11, 12 4, 9, 18 Level 9, 11, 4, 10, 1218 Pulse Width Distortion PWD11 |tPHL - tPLH| 45 ns 9, 13 17, 18 Propagation Delay Skew tPSK 60 ns 24 11, 18 Output Rise Time tR 42 ns 9, 14 4, 18 Output Fall Time tF 12 ns 9, 14 4, 18 15, 16 12 15, 16 12 Propagation Delay tEHL 19 ns IF = 3.5 mA Time of Enable VCC = 5.0 V, from VEH to VELVEL = 0 V, VEH=3 V, CL=15 pF, Propagation Delay tELH 30 ns RL=350 Time of Enable from VEL to VEH *All typical values at TA = 25C, VCC = 5 V. Common Mode Transient Immunity Specifications, All values at TA = 25C Parameter Device Symbol Min. Typ. Max. Units Test Conditions Output High HCPL-261A |CMH| 1 5 kV/sVCM = 50 V Level Common HCPL-061A Mode Transient HCPL-263A Immunity HCPL-063A HCPL-261N HCPL-061N 1 5 kV/sVCM = 1000 V HCPL-263N 15 25 kV/s HCPL-063N Output Low HCPL-261A |CML| 1 5 kV/sVCM = 50 V Level Common HCPL-061A Mode Transient HCPL-263A Immunity HCPL-063A HCPL-261N HCPL-061N HCPL-263N 15 25 kV/s HCPL-063N 9 1 5 kV/sVCM = 1000 V Fig. Note VCC = 5.0 V, 17 RL = 350 , IF = 0 mA, TA = 25C VO(MIN) = 2 V 4, 13, 15, 18 Using Avago 20 4, 13, App Circuit 15 VCC = 5.0 V, 17 RL = 350 , IF = 3.5 mA, VO(MAX) = 0.8 V TA = 25C 4, 14, 15, 18 Using Avago 20 4, 14, App Circuit 15 Package Characteristics All Typicals at TA = 25C Parameter Sym. Package* Min. Typ. Max. Units Test Conditions Fig. Input-Output VISO 3750 V rms RH 50%, Momentary With- t = 1 min., OPT 020 5000 stand Voltage** TA = 25C Input-Output Resistance 5, 6 5, 7 VI-O = 500 Vdc 4, 8 Input-Output CI-O 0.6 pF f = 1 MHz, Capacitance TA = 25C 4, 8 Input-Input II-I Dual Channel 0.005 A RH 45%, Insulation t = 5 s, Leakage Current VI-I = 500 V 19 Resistance (Input-Input) RI-O10 Note 12 RI-I Dual Channel 1011 Capacitance CI-I Dual 8-pin DIP 0.03 (Input-Input) Dual SO-8 0.25 19 pF f = 1 MHz 19 *Ratings apply to all devices except otherwise noted in the Package column. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only. Notes: 1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average current does not exceed 10 mA. 2. 1 minute maximum. 3. Derate linearly above 80 C free-air temperature at a rate of 2.7 mW/C for the SOIC-8 package. 4. Each channel. 5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together. 6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 VRMS for 1 second (leakage detection current limit, II-O 5 A). This test is performed before the 100% production test for partial discharge (method b) shown in the IEC/EN/ DIN EN 60747-5-5 Insulation Characteristics Table, if applicable. 7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 6000 VRMS for 1 second (leakage detection current limit, II-O 5 A). 8. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. 9. The tPLH propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of the output pulse. 10. The tPHL propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of the output pulse. 11. Propagation delay skew (tPSK) is equal to the worst case difference in tPLH and/or tPHL that will be seen between any two units under the same test conditions and operating temperature. 12. Single channel products only (HCPL-261A/261N/061A/061N). 13. Common mode transient immunity in a Logic High level is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., Vo > 2.0 V). 14. Common mode transient immunity in a Logic Low level is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). 15. For sinusoidal voltages (|dVCM /dt|)max = fCM VCM(P-P). 16. Bypassing of the power supply line is required with a 0.1 F ceramic disc capacitor adjacent to each optocoupler as shown in Figure 19. Total lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm. 17. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device. 18. No external pull up is required for a high logic state on the enable input of a single channel product. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. 19. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only. 10 VCC = 5.5 V VO = 5.5 V VE = 2 V VF = 0.8 V 10 5 0 -60 -40 -20 0 20 40 60 80 100 80 VCC = 5 V VE = 2 V VOL = 0.6 V IF = 3.5 mA 60 40 20 0 -60 -40 -20 TA - TEMPERATURE - C VOL - LOW LEVEL OUTPUT VOLTAGE - V VO - OUTPUT VOLTAGE - V RL = 350 RL = 1 k 2.0 RL = 4 kW 1.0 0 0.5 0 1.0 1.5 2.0 Figure 7. Typical output voltage vs. forward input current. 0.6 INPUT MONITORING NODE 80 100 TA = 25 C 0.1 0.01 1.0 1.1 1.2 IF + VF - 1.3 1.4 VF - FORWARD VOLTAGE - V Figure 6. Typical diode input forward current characteristic. IO = 12.8 mA 0.4 0.3 IO = 9.6 mA IO = 6.4 mA 0.2 -60 -40 -20 0 20 40 60 80 100 Figure 8. Typical low level output voltage vs. temperature. +5 V 1 VCC 8 2 7 3 6 4 5 GND TA = 40 C IO = 16 mA 0.1 F BYPASS RL *CL RM 60 TA = 85 C 1.0 VCC = 5.5 V VE = 2 V IF = 3.0 mA 0.5 HCPL-261A/261N PULSE GEN. Z O = 50 t f = t r = 5 ns 40 10.0 TA - TEMPERATURE - C IF - FORWARD INPUT CURRENT - mA IF 20 Figure 5. Low level output current vs. temperature. 5.0 3.0 0 TA - TEMPERATURE - C Figure 4. Typical high level output current vs. temperature. 4.0 100.0 IF - INPUT FORWARD CURRENT - mA IOL - LOW LEVEL OUTPUT CURRENT - mA IOH - HIGH LEVEL OUTPUT CURRENT - A 15 OUTPUT VO MONITORING NODE *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. I F = 3.5 mA INPUT IF I F = 1.75 mA t PHL OUTPUT VO Figure 9. Test circuit for tPHL and tPLH. 11 90% 90% 10% 10% t PLH 1.5 V VOH trise tfall VOL 1.5 1.0 0.5 RL = 350 RL = 1 k RL = 4 k VCC = 5 V VO = 0.6 V 0 -60 -40 -20 0 20 40 60 100 80 60 20 VCC = 5 V IF = 3.5 mA PWD - ns 30 20 RL = 1 k RL = 350 0 20 40 60 80 100 TA - TEMPERATURE - C Figure 13. Typical pulse width distortion vs. temperature. 12 tr, tf - RISE, FALL TIME - ns 160 RL = 4 k 0 -60 -40 -20 0 VCC = 5 V IF = 3.5 mA 20 40 60 80 100 Figure 11. Typical propagation delay vs. temperature. 60 10 TPLH RL = 350 k TA - TEMPERATURE - C Figure 10. Typical input threshold current vs. temperature. 40 TPHL RL = 350 , 1 k, 4 k 40 TA - TEMPERATURE - C 50 TPLH RL = 1 k 0 -60 -40 -20 80 100 120 TPLH RL = 4 k 140 VCC = 5 V IF = 3.5 mA trise tfall RL = 4 k 120 60 RL = 1 k 40 RL = 350 20 0 -60 -40 -20 RL = 350 , 1 k, 4 k 0 20 40 60 80 100 TA - TEMPERATURE - C Figure 14. Typical rise and fall time vs. temperature. tp - PROPAGATION DELAY - ns 1.5 120 tp - PROPAGATION DELAY - ns ITH - INPUT THRESHOLD CURRENT - mA 2.0 100 TPLH RL = 4 k 80 TPLH RL = 1 k 60 TPLH RL = 350 TPHL RL = 350 , 1 k, 4 k 40 20 0 VCC = 5 V TA = 25 C 0 2 4 6 8 10 IF - PULSE INPUT CURRENT - mA Figure 12. Typical propagation delay vs. pulse input current. 12 PULSE GEN. Z O = 50 t f = t r = 5 ns INPUT VE MONITORING NODE HCPL-261A/261N VCC 8 2 7 3 6 4 5 0.1 F BYPASS RL OUTPUT VO MONITORING NODE *C L GND tE - ENABLE PROPAGATION DELAY - ns 3.5 mA IF +5 V 1 *CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE. 3.0 V INPUT VE 1.5 V t EHL t ELH OUTPUT VO 1.5 V 120 VCC = 5 V VEH = 3 V VEL = 0 V IF = 3.5 mA 90 tELH, RL = 4 k 60 tELH, RL = 1 k 30 tELH, RL = 350 tEHL, RL = 350 , 1k , 4 k 0 -60 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C Figure 16. Typical enable propagation delay vs. temperature. HCPL-261A/-261N/-061A/-061N Only. Figure 15. Test circuit for tEHL and tELH. HCPL-261A/261N IF A B VFF VCC 8 2 7 3 6 PULSE GEN. O Z = 50 VCM VO GND 4 + 0.1 F BYPASS 350 OUTPUT VO MONITORING NODE 5 _ VCM (PEAK) 0V 5V SWITCH AT A: IF = 0 mA SWITCH AT B: IF = 3.5 mA VO +5 V 0.5 V CM H VO (min.) 800 HCPL-261A/261N OPTION 060 ONLY PS (mW) 700 IS (mA) 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS - CASE TEMPERATURE - C VO (max.) CM L Figure 17. Test circuit for common mode transient immunity and typical waveforms. 13 OUTPUT POWER - PS, INPUT CURRENT - IS V CM 1 Figure 18. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN 60747-5-5. Application Information SINGLE CHANNEL PRODUCTS Common-Mode Rejection for HCPL261A/HCPL-261N Families: GND BUS (BACK) VCC BUS (FRONT) Figure 20 shows the recommended drive circuit for the HCPL-261N/261A for optimal common-mode rejection performance. Two main points to note are: N.C. ENABLE (IF USED) 0.1F OUTPUT 1 N.C. 1. The enable pin is tied to VCC rather than floating (this applies to single-channel parts only). N.C. ENABLE (IF USED) 0.1F N.C. 2. Two LED-current setting resistors are used instead of one. This is to balance ILED variation during common-mode transients. OUTPUT 2 If the enable pin is left floating, it is possible for common-mode transients to couple to the enable pin, resulting in common-mode failure. This failure mechanism only occurs when the LED is on and the output is in the Low State. It is identified as occurring when the transient output voltage rises above 0.8 V. Therefore, the enable pin should be connected to either VCC or logic-level high for best common-mode performance with the output low (CMRL). This failure mechanism is only present in single-channel parts (HCPL-261N, -261A, 061N, -061A) which have the enable function. 10 mm MAX. (SEE NOTE 16) DUAL CHANNEL PRODUCTS GND BUS (BACK) VCC BUS (FRONT) OUTPUT 1 0.1F OUTPUT 2 10 mm MAX. (SEE NOTE 16) Figure 19. Recommended printed circuit board layout. * VCC 357 (MAX.) 357 (MAX.) 74LS04 OR ANY TOTEM-POLE OUTPUT LOGIC GATE HCPL-261A/261N 1 8 2 7 3 6 VO 5 GND 4 * SHIELD VCC+ 0.01 F GND1 350 GND2 * HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1). *Higher CMR may be obtainable by connecting pins 1, 4 to input ground (Gnd1). Figure 20. Recommended drive circuit for HCPL-261A/-261N families for high-CMR (similar for HCPL-263A/-263N). 14 Also, common-mode transients can capacitively couple from the LED anode (or cathode) to the output-side ground causing current to be shunted away from the LED (which can be bad if the LED is on) or conversely cause current to be injected into the LED (bad if the LED is meant to be off ). Figure 21 shows the parasitic capacitances which exists between LED anode/cathode and output ground (CLA and CLC). Also shown in Figure 21 on the input side is an ACequivalent circuit. CMR with Other Drive Circuits Table 1 indicates the directions of ILP and ILN flow depending on the direction of the common-mode transient. CMR performance with drive circuits other than that shown in Figure 20 may be enhanced by following these guidelines: For transients occurring when the LED is on, commonmode rejection (CMRL, since the output is in the "low" state) depends upon the amount of LED current drive (IF). For conditions where IF is close to the switching threshold (ITH), CMRL also depends on the extent which ILP and ILN balance each other. In other words, any condition where common-mode transients cause a momentary decrease in IF (i.e. when dVCM /dt>0 and |IFP| > |IFN|, referring to Table 1) will cause common-mode failure for transients which are fast enough. 1. Use of drive circuits where current is shunted from the LED in the LED "off" state (as shown in Figures 22 and 23). This is beneficial for good CMRH. 2. Use of IFH > 3.5 mA. This is good for high CMRL. Using any one of the drive circuits in Figures 22-24 with IF= 10 mA will result in a typical CMR of 8 kV/s for the HCPL-261N family, as long as the PC board layout practices are followed. Figure 22 shows a circuit which can be used with any totem-pole-output TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to be used with logic devices which have low current-sinking capability. It also helps maintain the driving-gate power-supply current at a constant level to minimize ground shifting for other devices connected to the input-supply ground. Likewise for common-mode transients which occur when the LED is off (i.e. CMRH, since the output is "high"), if an imbalance between ILP and ILN results in a transient IF equal to or greater than the switching threshold of the optocoupler, the transient "signal" may cause the output to spike below 2 V (which constitutes a CMRH failure). By using the recommended circuit in Figure 20, good CMR can be achieved. (In the case of the -261N families, a minimum CMR of 15 kV/s is guaranteed using this circuit.) The balanced ILED-setting resistors help equalize ILP and ILN to reduce the amount by which ILED is modulated from transient coupling through CLA and CLC. When using an open-collector TTL or open-drain CMOS logic gate, the circuit in Figure 23 may be used. When using a CMOS gate to drive the optocoupler, the circuit shown in Figure 24 may be used. The diode in parallel with the RLED speeds the turn-off of the optocoupler LED. VCC 1 1/2 RLED 1/2 RLED 8 2 7 3 4 CLA 350 5 SHIELD VCM 6 VO 15 pF CLC + GND 74L504 (ANY TTL/CMOS GATE) 2N3906 (ANY PNP) 1 2 LED 3 4 - Figure 21. AC equivalent circuit for HCPL-261X. 15 0.01 F 420 (MAX) ILP ILN HCPL-261X VCC+ Figure 22. TTL interface circuit for the HCPL-261A/-261N families. VCC VCC HCPL-261X 820 1 HCPL-261A/261N 1N4148 2 74HC00 (OR ANY OPEN-COLLECTOR/ OPEN-DRAIN LOGIC GATE) LED 3 750 74HC04 (OR ANY TOTEM-POLE OUTPUT LOGIC GATE) 2 LED 3 4 Figure 23. TTL open-collector/open drain gate drive circuit for HCPL-261A/-261N families. 1 4 Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families. Table 1. Effects of Common Mode Pulse Direction on Transient ILED If dVCM/dt Is: then ILP Flows: and ILN Flows: positive (>0) away from LED away from LED anode through CLA cathode through CLC negative (<0) toward LED toward LED anode through CLA cathode through CLC If |ILP| < |ILN|, LED IF Current Is Momentarily: increased decreased If |ILP| > |ILN|, LED IF Current Is Momentarily: decreased increased Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when tPLH and tPHL differ in value. PWD is defined as the difference between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-1, etc.). Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of opto 16 couplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 25, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 26 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 26 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start IF to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the recommended temperature, input current, and power supply ranges. 50% 1.5 V VO TPHL IF 50% VO TPLH 1.5 V t PSK Figure 25. Illustration of propagation delay skew - tPSK. DATA INPUTS CLOCK DATA OUTPUTS t PSK CLOCK t PSK Figure 26. Parallel data transmission example. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0561EN AV02-0391EN - April 30, 2013