1White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
White Electronic Designs
512Kx32 SRAM MODULE, SMD 5962-94611
n Access Times of 15*, 17, 20, 25, 35, 45, 55ns
n Packaging
66 pin, PGA Type, 1.075" square, Hermetic
Ceramic HIP (Package 400).
68 lead, 40mm Hermetic Low Profile CQFP,
3.5mm (0.140") (Package 502)1
68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")
square (Package 510) 3.56mm (0.140") height.
68 lead, Hermetic CQFP (G1U), 23.9mm (0.940")
square (Package 519) 3.57mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 3).
68 lead, Hermetic CQFP (G1T), 23.9mm (0.940")
square (Package 524) 4.06mm (0.160") height.
nOrganized as 512Kx32, User Configurable as
1Mx16 or 2Mx8
FIG. 1 PIN CONFIGURATION FOR WS512K32N-XH1X
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
TOP VIEW
BLOCK DIAGRAM
nCommercial, Industrial and Military Temperature
Ranges
nTTL Compatible Inputs and Outputs
n 5 Volt Power Supply
n Low Power CMOS
n Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
n Weight
WS512K32-XH1X - 13 grams typical
WS512K32-XG2UX - 8 grams typical
WS512K32-XG1UX - 5 grams typical
WS512K32-XG1TX - 5 grams typical
WS512K32-XG4TX1 - 20 grams typical
August 2002 Rev. 10
FEATURES
*15ns Access Time available only in Commercial and Industrial
Temperature. This speed is not fully characterized and is subject to
change without notice.
Note 1: Package Not Recommended For New Design
2
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WS512K32-XXX
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PIN DESCRIPTION
FIG. 2 PIN CONFIGURATION FOR WS512K32-XG4TX1
TOP VIEW
BLOCK DIAGRAM
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
FIG. 3 PIN CONFIGURATION FOR WS512K32-XG2UX, WS512K32-XG1TX
AND WS512K32-XG1UX
TOP VIEW PIN DESCRIPTION
BLOCK DIAGRAM
Note 1: Package Not Recommended For New Design
I/O0-31 Data Inputs/Outputs
A0-18 Address Inputs
WE1-4 Write Enables
CS1-4 Chip Selects
OE Output Enable
VCC Power Supply
GND Ground
NC Not Connected
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WS512K32-XXX
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Parameter Symbol Min Max Unit
Operating Temperature TA-55 +125 ° C
Storage Temperature TSTG -65 +150 ° C
Signal Voltage Relative to GND VG-0.5 Vcc+0.5 V
Junction Temperature TJ150 °C
Supply Voltage VCC -0.5 7.0 V
TRUTH TABLE
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
Supply Voltage VCC 4.5 5.5 V
Input High Voltage VIH 2.2 VCC + 0.3 V
Input Low Voltage VIL -0.5 +0.8 V
Operating Temp (Mil) T
A-55 +125 °C
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
Conditions Max Unit
OE capacitance COE
V
IN
= 0 V, f = 1.0 MHz
50 pF
WE1-4 capacitance CWE
V
IN
= 0 V, f = 1.0 MHz
pF
HIP (PGA) 20
CQFP G4T 50
CQFP G2U/G1U/G1T 20
CS1-4 capacitance CCS
V
IN
= 0 V, f = 1.0 MHz
20 pF
Data I/O capacitance CI/O
V
I/O
= 0 V, f = 1.0 MHz
20 pF
Address input capacitance CAD
V
IN
= 0 V, f = 1.0 MHz
50 pF
Parameter Symbol Conditions Units
Min Max
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10µA
Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10µA
Operating Supply Current x 32 Mode ICC x 32 CS = VIL, OE = VIH, f = 5MHz, Vcc = 5.5 660 mA
Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 5.5 80 mA
Output Low Voltage VOL IOL = 8mA for 15 - 35ns, 0.4 V
IOL = 2.1mA for 45 - 55ns, Vcc = 4.5
Output High Voltage VOH IOH = -4.0mA for 15 - 35ns, 2.4 V
IOH = -1.0mA for 45 - 55ns, Vcc = 4.5
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
DATA RETENTION CHARACTERISTICS
(TA = -55°C TO +125°C)
Parameter Symbol Conditions Units
Min Max
Data Retention Supply Voltage VDR CS ³ VCC - 0.2V 2.0 5.5 V
Data Retention Current ICCDR1 VCC = 3V 28 mA
Low Power Data Retention ICCDR2 VCC = 3V 16 mA
Current (WS512K32L-XXX)
CS OE WE Mode Data I/O Power
H X X Standby High Z Standby
L L H Read Data Out Active
L H H Out Disable High Z Active
L X L Write Data In Active
This parameter is guaranteed by design but not tested.
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
4
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WS512K32-XXX
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AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
FIG. 4 AC TEST CIRCUIT
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
AC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)
AC TEST CONDITIONS
Parameter Typ Unit
Input Pulse Levels VIL = 0, VIH = 3.0 V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
Parameter Symbol -15* -17 -20 -25 -35 -45 -55 Units
Write Cycle Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Write Cycle Time tWC 1517202535 4555ns
Chip Select to End of Write tCW 1315151725 3550ns
Address Valid to End of Write t AW 1315151725 3550ns
Data Valid to End of Write t DW 1011121320 2525ns
Write Pulse Width t WP 1315151725 3540ns
Address Setup Time t AS 22222 22ns
Address Hold Time t AH 00000 55ns
Output Active from End of Write tOW122344 55ns
Write Enable to Output in High Z tWHZ18 9 111315 2020ns
Data Hold Time tDH 00000 00ns
Parameter Symbol -15* -17 -20 -25 -35 -45 -55 Units
Read Cycle Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time tRC 15 17 20 25 35 45 55 n s
Address Access Time tAA 15 17 20 25 35 45 55 n s
Output Hold from Address Change tOH 0 0 0 0000ns
Chip Select Access Time tACS 15 17 20 25 35 45 55 n s
Output Enable to Output Valid tOE 8 9 10 12 25 25 25 n s
Chip Select to Output in Low Z tCLZ12222444ns
Output Enable to Output in Low Z tOLZ10000000ns
Chip Disable to Output in High Z tCHZ11212 12 12 1520 20ns
Output Disable to Output in High Z tOHZ11212 12 12 1520 20ns
*15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change
without notice.
1. This parameter is guaranteed by design but not tested.
*15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change
without notice.
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2U, G1U and H1 packages. tAS minimum for the G4T package is 0ns.
5White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WS512K32-XXX
White Electronic Designs
WS32K32-XHX
FIG. 5 TIMING WAVEFORM - READ CYCLE
FIG. 7 WRITE CYCLE - CS CONTROLLED
FIG. 6 WRITE CYCLE - WE CONTROLLED
6
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WS512K32-XXX
White Electronic Designs
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE,
HIP (H1)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Note 1: Package Not Recommended For New Design
PACKAGE 502: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE
CQFP (G4T)1
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WS512K32-XXX
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PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Note 1: Package Not Recommended For New Design
8
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WS512K32-XXX
White Electronic Designs
PACKAGE 519: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW
PROFILE CQFP (G1U)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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WS512K32-XXX
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PACKAGE 524: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE
CQFP (G1T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
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LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = MIL-STD-883 Compliant
M = Military Screened -55°C to +125°C
I = Industrial -40°C to 85°C
C = Commercial 0°C to +70°C
PACKAGE TYPE:
H1 = Ceramic Hex-In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)
G4T1 = 40mm Low Profile CQFP (Package 502)
G1U = 23.9mm Low Profile CQFP (Package 519)
G1T = 23.9mm Low Profile CQFP (Package 524)
ACCESS TIME (ns)
IMPROVEMENT MARK:
Blank = Standard Power
N = No Connect at pin 21 and 39 in HIP for Upgrades
L = Low Power Data Retention
ORGANIZATION, 512Kx32
User configurable as 1Mx16 or 2Mx8
SRAM
WHITE ELECTRONIC DESIGNS CORP.
W S 512K 32 X - XXX X X X
Note 1: Package Not Recommended For New Design
ORDERING INFORMATION
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WS512K32-XXX
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DEVICE TYPE SPEED PACKAGE SMD NO.
512K x 32 SRAM Module 55ns 66 pin HIP (H1) 5962-94611 05HTX
512K x 32 SRAM Module 45ns 66 pin HIP (H1) 5962-94611 06HTX
512K x 32 SRAM Module 35ns 66 pin HIP (H1) 5962-94611 07HTX
512K x 32 SRAM Module 25ns 66 pin HIP (H1) 5962-94611 08HTX
512K x 32 SRAM Module 20ns 66 pin HIP (H1) 5962-94611 09HTX
512K x 32 SRAM Module 17ns 66 pin HIP (H1) 5962-94611 10HTX
512K x 32 SRAM Module 55ns 68 lead CQFP Low Profile (G4T)15962-94611 05HYX
512K x 32 SRAM Module 45ns 68 lead CQFP Low Profile (G4T)15962-94611 06HYX
512K x 32 SRAM Module 35ns 68 lead CQFP Low Profile (G4T)15962-94611 07HYX
512K x 32 SRAM Module 25ns 68 lead CQFP Low Profile (G4T)15962-94611 08HYX
512K x 32 SRAM Module 20ns 68 lead CQFP Low Profile (G4T)15962-94611 09HYX
512K x 32 SRAM Module 17ns 68 lead CQFP Low Profile (G4T)15962-94611 10HYX
512K x 32 SRAM Module 55ns 68 lead CQFP (G2U) 5962-94611 05HMX
512K x 32 SRAM Module 45ns 68 lead CQFP (G2U) 5962-94611 06HMX
512K x 32 SRAM Module 35ns 68 lead CQFP (G2U) 5962-94611 07HMX
512K x 32 SRAM Module 25ns 68 lead CQFP (G2U) 5962-94611 08HMX
512K x 32 SRAM Module 20ns 68 lead CQFP (G2U) 5962-94611 09HMX
512K x 32 SRAM Module 17ns 68 lead CQFP (G2U) 5962-94611 10HMX
512K x 32 SRAM Module 55ns 68 lead CQFP (G1U) 5962-94611 05H9X
512K x 32 SRAM Module 45ns 68 lead CQFP (G1U) 5962-94611 06H9X
512K x 32 SRAM Module 35ns 68 lead CQFP (G1U) 5962-94611 07H9X
512K x 32 SRAM Module 25ns 68 lead CQFP (G1U) 5962-94611 08H9X
512K x 32 SRAM Module 20ns 68 lead CQFP (G1U) 5962-94611 09H9X
512K x 32 SRAM Module 17ns 68 lead CQFP (G1U) 5962-94611 10H9X
Note 1: Package Not Recommended For New Design
12
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
WS512K32-XXX
White Electronic Designs
Document Title
512K x 32 SRAM Multi-Chip Package
Revision History
Rev # History
Release Date Status
Initial October 1996 Preliminary
Change (Pg. 1, 3) January 1997 Preliminary
1.1 Change Operation Supply Current from 520mA To 540mA
1.2 Change Data Retention Current from 12mA to 28mA.
Change (Pg. 1, 2, 8, 10, 11) November 1997 Preliminary
1.1 Delete G2 Package
Change (Pg. 1, 9) February 1998 Preliminary
1.1 Add SMD Case Outline M for G2T
Change (Pg. 1, 3, 8) April 1998 Preliminary
1.1 Remove Low Capacitance package option
Change (Pg. 1, 6, 8) December 1998 Preliminary
1.1 Add H1 package
Change (Pg. 1, 4, 6, 9, 10) March 1999 Preliminary
1.1 Remove H2 package
1.2 Change logo to WEDC logo
Rev 2 Change (Pg. 1, 3, 4, 8) May 1999 Final
1.1 Change status from Preliminary to Final
1.2 Make package descriptions consistent
1.3 Add 15ns as available in Commercial and Industrial Temperatures only.
Rev 4 Change (Pg. 1, 3) June 1999 Final
1.1 Change Standby Current (Isb) from 60mA to 80mA Maximum
Rev 5 Change (Pg. 1, 2, 3, 4, 7, 8) November 1999 Final
1.1 Add G1U package
Rev 6 Change (Pg. 1, 8) February 2000 Final
1.1 Change G1U lead foot length from 0.64mm to 0.84mm Ref
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Rev 7 Change (Pg. 1, 3, 9) October 2000 Final
1.1 Change Operating Supply Current from 540mA to 660mA Maximum
1.2 Add Low Power Data Retention Current of 16mA to Data Retention Characteristics table
1.3 Add Low Power Data Retention (L) option to Ordering Information
Rev 8 Change (Pg. 1, 2, 6, 7, 9, 10) October 2001 Final
1.1 Change G2T and G4T package status to Not Recommended For New Design
Rev 9 Change (Pg. 1, 2, 3, 8, 9, 10) November 2001 Final
1.1 Add G1T package
1.2 Remove Hi-Reliability Product Title
Rev 10 Change (Pg. 1, 2, 3, 4, 7, 8, 9, 10, 11) August 2002 Final
1.1 Remove G2T package
1.2 Add G2U package
1.3 Remove Package to be Developed note for G4T
