PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
1-15 2002/01.ver.A
he PJ3842B series is high performance fixed frequency
current mode controllers. This is specifically designed
for Off-Line and DC-to-DC converter applications offering
the designer a cost effective solution with minimal external
components.This integrated circuits feature a trimmed
oscillator for precise duty cycle control, a temperature
compensated reference, high gain error amplifier, current
sensing comparator,and a high current totem pole output
ideally suited for driving a power MOSF ET.
Also included are protective features consisting of input
and reference undervoltage lockouts each with hysteresis,
cycle-by-cycle current limiting , programmable output
deadtime, and a latch for single pulse metering.
This device is available in 8-pin dual-in-line plastic
packages as wel l as the 8-pin pl ast ic surfa ce mount (S OP -8).
The SOP-8 package has separate power and ground pins for
the totem pole output stage.
The PJ3842B has UVLO thresholds of 16V (on) and
1 0V (off), i deal l y s uited fo r off-l i n e con vert ers.
• T rimmed Oscillator Discharge Current for Pre cise Duty
Cy cle Co n t ro l
• C urrent Mode Operat ion t o 500KHz
• Automatic Feed Forward Compensation
• Latching P WM for C ycle-By-C ycle Current Limiting
• Internally Trimmed Reference with Undervoltage
Lockout
• High C urrent Totem P ole Output
• Input Undervolt age Lockout wit h Hyst ersis
• Low S tart -Up and Operat ing C urrent
Dev ice O pera ti ng T em p era ture P a cka ge
PJ3842BCD DIP-8
PJ3842BCS
-20℃ TO +85℃
SOP-8
The docume nt contains infor mation on a new product.Spe cific ations a nd infor ma tion he rein ar e subje ct to c hange without notice .
T
DIP-8 SOP-8
S I MPL I FIED BL O CK DI AG RA
M
FEATURES
Pin: 1. Compensation 5. Gnd
2. Voltage Feedback 6. Outp ut
3. Current Sense 7. Vcc
4. RT/CT 8. Vre f
O RDERIN G IN FORMATI O N
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
2-15 2002/01.ver.A
Rating Symbol Value Unit
Total P ower S upply and Zener C urrent (ICC+IZ) 30 mA
Output C urrent S ource or S ink (Note 1) Io 1. 0 A
Output Energy (C apacitive Load per Cycle) W 5.0 μJ
C urrent S ense and Vol tage F eedback Input s Vin -0. 3 to + 5. 5 V
Error Amp Output S ink C urrent Io 10 mA
Power Dissipation and Thermal Characteristics
Plastic Dip
Maximum P ower Dissipation @ TA=25℃
Thermal R esistance Junction to Air
Plastic Dip
Maximum Power Dissipation @ T A=25℃
Thermal R esistance Junction to Air
PD
RθJA
PD
RθJA
862
145
1.25
100
mW
℃/W
W
℃/W
Operati ng Juncti on T emperat ure TJ +150 ℃
Op er at ure A m b i en t Temp eratu re TA 0 to + 70 ℃
S torage Tem perature R ange Tstg -65 to + 150 ℃
PJ3842B
Characteristic Symbol Min Typ Ma x Uni t
RE FE RENCE SE CT I ON
R efer enc e Output Volt age (Io= 1. 0mA,TJ = 2 5 ℃) Vref 5.0 5.0 5.0 V
Line R egul at ion (VCC = 12V to 25V) R egl ine - 2. 0 20 mV
Load R egulati on (Io = 1. 0mA t o 20m A) R egl oad - 3. 0 25 mV
Temperature Stability Ts - 0.2 - mV/℃
Total Output Variati on over Line, Load , and Temperat ure Vre f 4. 82 - 5. 18 V
Output Nois e Volt age (f = 10Hz to 10kHz, TJ=25℃) Vn - 50 - µV
Long Term S tability ( TA=125.℃ for 1000 Hours ) S - 5. 0 - mV
Output S hort C ircui t C urrent Isc -30 -85 180 mA
O S CI L L ATO R SECTI O N
F requency
TJ=25℃
TA=Tlow to Thigh
Fosc
47
46
52
-
57
60
KHz
F requency C hange with Volt age (VCC =12V t o 25V) Δfos c/ΔV - 0.2 1.0 %
F requency C hange with Temperature
TA=Tlow to Thigh Δfos c/ΔT - 5.0 - %
Oscillator Voltage Swing ( P eak-to-P eak) Vosc - 1.6 - V
Discharge C urrent (Vosc= 2. 0V)
TJ=25℃
TA=Tlow to Thigh
Idischg
7.5
7.2
8.4
-
9.3
9.5
mA
Note: 1. Maximum Package powe r dissipation limits must be observed.
2. Adjust VCC above t he S t art-Up threshold before sett ing t o 15V.
3. Low dut y cycle pulse techni que are us ed duri ng test t o m ai ntain j unct ion t em perat ure as clos e t o am bient as possi ble.
Tlow = - 2 0 ℃ Thigh = +85℃
4. T his parameter is measured at the latch trip point with VFB = 0V.
ΔV Output C ompensation
5. Comparator gain is defined as : Av =
ΔV C urrent S ense Input
M
AXIMU M RATI N
G
E
LECTRICAL CHARACTERIS TICS (VCC = 15V ( Note 2) ,
R
T =10 K, CT=3.3 nF,
T
A=
T
low to
T
high( Note 3) unless otherwise
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
3-15 2002/01.ver.A
PJ3842B Characteristic Symbol
Min Typ Max
Unit
E RRO R AMPL I FIER SE CTI O N
Voltage F eedback Input (Vo= 2. 5V) VFB 2.42 2.5 2.58 V
Input B i as C urrent (VFB =5.0V) IIB - -0.1 -2.0 μΑ
Open-Loop Vol tage Gai n (Vo= 2. 0V to 4. 0V) AVOL 65 90 - dB
Unity Gain Bandwidth (TJ=25℃) BW 0.7 1.0 - MHz
P ower S upply R ej ect ion R adi o (VCC=12V to 25V) PSR R 60 70 - dB
Output C urrent
S ink (Vo= 1. 1V, VFB =2.7V)
S o urce ( Vo= 5 . 0 V, VFB =2.3V)
Isink
ISource
2.0
-0.5
12
-1.0
-
-
mA
Output Volt age Swing
Hig h St ate (R L=15K t o ground, VFB=2. 3V)
VOH
5.0
6.2
- V
L o w St at e (RL= 15K t o Vref, VFB=2.7V) VOL - 0.8 1.1
CURRE NT SE NSE SE CT IO N
C urrent S ense Input Volt age Gai n (Note 4&5) Av 2. 85 3. 0 3. 15 V/V
Maxim um C urrent S ense Input Threshol d(Not e 4) Vth 0.9 1.0 1.1 V
P ower S upply R ej ect ion R adi o
VCC=12V t o 25V, Note 4 PSRR - 70 - dB
Input B i as C urrent IIB - -2.0 -10 μΑ
P ropagation Delay(C urrent Sense Input t o Output ) tPLH(IN/OUT) - 150 300 ns
O UT PUT SE CT I ON
Output Volt age
Low S tat e (Isi nk=20m A)
(Isi nk=200m A)
High S tat e (Isource= 20mA)
(Isource= 200mA)
VOL
VOH
-
-
13
12
0.1
1.6
13.5
13.4
0.4
2.2
-
-
V
Out p ut Vo lt age wi t h UVLO Act i vat ed
VCC=6.0V,Isink=1.0mA VOL(UVLO) - 0.1 1.1 V
Output Voltage Rise T ime (CL=1.0nF,TJ=25℃) tr - 50 150 ns
Output Voltage F all Time (C L=1.0nF,TJ=25℃) tf - 50 150 ns
UNDE RVO L T AG E L O CKO UT S E CT IO N
S tart -Up Thres hold
PJ3842B Vth
14.5
16
17.5 V
Minimum Operating Voltage After T urn-On
PJ3842B VCC(min)
8.5
10
11.5 V
PW M S E CT I O N
Du ty Cy cl e
Maximum
Minimum
DCmax
DCmin
94
-
96
-
-
0
%
TOTAL DEVICE
P ower S upply C urrent
Start-Up, VCC= 14V
Operati ng (Note 2)
ICC
-
-
0.25
12
0.5
17
mA
P ower S upply Zener Volt age (ICC=25mA) Vz 30 36 - V
E
LECTRICAL CHARACTERIS TICS
(V
CC = 15V
(
Not e 2
)
, RT
=10
CT
=3 .3 nF TA=Tlo w to T high
(
Not e 3
)
unless ot herwise
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
4-15 2002/01.ver.A
FI G URE 1- O UT PUT DE AD TI ME vers u s
O S CI L L ATO R FREQUE NCY
FI G URE 2- T I MI NG RESIST O R versus
O S CI L L ATO R FREQUE NCY
FI G URE 3-O S CI L L ATO R DI S CH ARGE CURRENT
versus T E MPE RAT URE F IG URE 4 -MAXI MUM O UT PUT DUT Y CYCL E
v ers us TI MI N G RESI STO R
FI G URE 5-E RRO R AMP S MAL L SI G NAL FI G URE 6-E RRO R AMP L ARG E SI G NAL
T RANS I E NT RESP ONSE T RANSI E NT RE S P ONSE
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
5-15 2002/01.ver.A
FI G URE 7-E RRO R AMP O PE N-L OO P G AI N AND
PH AS E v ersus FREQUENCY
FI G URE 8-CURRE NT SENSE I NPUT T H RES H O L D
versus E RRO R AMP O UT PUT VOLTAG E
FI G URE 9-RE FERENCE VO LT AG E CH ANG E
versus S O URCE CURRE NT FI G URE 10 -RE FE RE NCE SH ORT CIRCUI T
CURRE NT v ers u s TE MPE RAT URE
FI G URE 11 - RE FE RE NCE L O AD REG UL AT I O N FI G URE 12 -RE FE RE NCE LI NE RE G ULATI O N
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
6-15 2002/01.ver.A
FI G URE 13 -OUTP UT S ATURATI O N VOL T AG E
versus L O AD CURRE NT
FI G URE 14 -OUTP UT WAVE F ORM
FI G URE 15 -OUTP UT CRO SS CONDUCTI O N
FI G URE 16 -S UPPL Y CURRENT v ers u s SUPPL Y
VOLTAGE
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
7-15 2002/01.ver.A
FI G URE 17 -RE PRE S E NTAT I VE BL O CK DI AG RAM
Pi n n u m b ers ad j acen t to t erm inals are fo r t h e 8 pin du al- i n -l in e pack ag e.
Pin num bers in parent hesi s are for the S OP -14 package.
FI G URE 18 -T IMI NG DI AG RAM
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully fun ctional be for e
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators.Each has built-in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The large hysteresis and
low st art-up curr ent of t he P J3842B makes i t i deall y sui ted in
off-li ne convert e r appl ic at ions where e ffici ent boots trap s tart-
up technique (Figure 33). 36 V zener is connected as a shunt
regulator from VCC to ground.Its purpose is to protect the IC
from excessive voltage that can occur during system start-up.
The m ini mum operat ing vol tage for the PJ 3842B i s 11V.
U ND ERVOLT AGE LO CKOU T
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
8-15 2002/01.ver.A
Output
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFET’ s. It is capable o f up to ±1.0A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active.This characteristic eliminates the need for an
external pul l-down resist or.
The SOP-8 surface mount package provides separate pins
for Vc(output supply) and Power Ground.Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes part icularly us e ful when reducing t he Ipk(m ax)
clamp l evel. The separate Vc suppl y input al lows the designer
added fiexlbility in tailoring the drive voltage independent of
Vcc.A zen er clamp is typically connected to this input when
driving power MOSFETs in systems where Vcc is greater
than 20V. Figure 25 shows proper power and control ground
connect ions i n a current sensi ng power MOS F ET appli cat ion.
Reference
The 5.0V bandgap reference is trimmed to±2.0% on the
PJ3842B.Its promary purpose to supply charging current to
the oscillator timing capacitor.The reference has short circuit
protection and is capable of providing in excess of 20mA for
poweri ng addi tional cont rol s ystem circuit ry.
Desi g n Considera ti ons
Do n o t a ttemp t to co n s tru ct the co n v er ter o n wi rewra p o r
plug-in prototype boards. High frequency circuit layout
techniques are imperative to prevent pulsewidth jitter.This is
usually caused by excessive noise pick-up imposed on the
Current Sense or Voltage Feedback inputs.Noise immunity
can be improved by lowering circuit impedances at these
points.The printed circuit layout should contain a ground
plane with lowcurrent signal and high-current switch and
output grounds returning separate paths back to the input
filter capacitor.Ceramic bypass capacitors(0.1μF) connect ed
direct ly to Vcc, Vc, and Vre f may be requi r ed dependi ng upon
circuit layout . This provides a low impedance path for
filtering the high frequency noised. All high current loops
shoul d be kept as short as possi ble usi ng heavy copper runs to
minimize radiated EMI. The Error Amp compensation
circuitry and the converter output voltage divider should be
located close to the IC and as far as possible from the power
swit ch and other noi se generati ng com ponent s.
FIG URE 19- CONT INUOUS CURRE NT W AVE FRO MS
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current,This instability is
independent of the regulators closed loop characteristics and
is caused by the simultaneous operating conditions of fixed
frequency and peak current detecting. Figure 19A shows the
phenomenon graphically, At t0 , switch conduction begins ,
causing the inductor current to rise at a slope of m1. T his
slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2,
until the next oscillator cycle. This unstable condition can be
shown if a perturbation is added to the control voltage ,
resulting in a small Δl (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn-on(t2) is increased by Δl+Δl m2/m1.
Th e m i n imum cu rr ent at t h e n ex t cy cle (t3) d ecreas es t o (Δ
l+ Δl m2/m1)(m2/m1). This perturbation is multiplied by
m2/m1 on each succeeding cy cle , alternat ely increasing and
decreasing the inductor current at switch turn-on, Several
oscillator cycles may be required before the inductor current
reach es zero cau s i n g t h e p ro ces s to co mm en ce agai n . If m 2/m1
is greater than 1, the converter will be unstable . Figure 19B
shows that by adding an artificial ramp that is synchronized
with the PWM clock to the control voltage . the Δl
perturbation will decrease to zero on succeeding cycles. T his
compensating ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability . With m2/2 slope
compensation , the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added t o ei ther the Volt age F eedback or Current S ens e i nputs
(F igure 32).
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
9-15 2002/01.ver.A
FI G URE 2 0-E XT E RNAL CLO CK
SYNCHRONIZATION
FI G URE 21 -E XT E RNAL DUT Y CYCL E CL AMP AND
MUL T I UNI T SYNCH RONIZAT I O N
The diode clamp is requ ired if the Sync ampli tu de is large en ou gh to
the cause the bottom side of CT to go more than 300mV be low
ground.
FI G URE 22 -ADJUS T ABL E RE DUCT IO N O F CL AMP
LEVEL
1.44 RB
f= DMAX=
(RA+RB) RA+2RB
FI G URE 23 -S O FT -ST ART CI RCUIT
FI G URE 24 -ADJUS T ABL E B UFFE RE D RE DUCTI O N
OF CLAMP LEVEL WITH SOFT-STAR
Isoft-Start=3600c in µF
FI G URE 25 -CURRE NT S E NSI NG PO WE R MOSFET
Virtually lossless current sensing can be achieved with the
implementation of a SENSEFET power switch.For proper operation
during over current conditions.a reduction of the Ipk(max) clamp
le vel must be imple mented.R efe r to F igur e 22 and 24
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
10-15 2002/01.ver.A
FI G URE 26 -CURRE NT WAVE F ORM S P IK E
SUPPRESSION
FI G URE 27 -MO S FE T PARASI T I C OSCI L L AT IO NS
The addition of R C filte r will eliminate instability caused
by the leading edge splik on the cur re nt wave form.
FI G URE 28 -B IP OLAR T RANS I S T O R DRI VE
FI G URE 29 -ISO L ATE D MO S FET DRI VE
The totem- pole output c an fur nish nega tive ba se c urr ent for
enhanced transis tor turn-off,with the addit io ns of capacitor C1.
FI G URE 30 -L AT CH E D S H UT DO W N
FI G URE 31 -E RRO R AMPL I FI E R CO MPE NSAT I O N
The MCR101 SCR must be selected for a holding of less than 0.5mA at TA
(min).The simple two transistor circuit can be used in place of the SCR as
shown.All resistors are 10K.
Error Amp compensation circuit for stabilizing any currentmode topology
except for boost and fly back converters operating with continuous inductor
current.
Error Amp compensation circuit for stabilizing any currentmode topology
except for boost and fly back converters operating with continuous inductor
current.
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
11-15 2002/01.ver.A
FI G URE 32-SLO PE COMPENSATI O N
The buffered oscil lat or ramp can resis ti vel y s ummed with ei ther t he v ol tage
feedback or current sense inp uts to provide slo pe compensation.
FIGURE 33-27 WATT O FF-LINE RE GULATI ON
T1 -Pri mary : 4 5 Tu rns # 2 6 A W G
S econdary ±12V :9 Turns #30 AW G (2 st rands ) Bi filiar W ound L1- 15μH at 5. 0A, C oilcra ft 27156.
S econdary 5. 0V: 4 Turns (si x s trands) #26 Hexfiliar W ound L2. L3-25μH at 1. 0A, C oil craft 27157.
S econdary F eedback : 10 Turns #30 AWG (2 st rands) Bifiliar W ound
C ore: F erroxcube EC 35-3C8
B obbi n : F erroxcube EC 35PC B 1
Gap :≌0. 10” for a prim ary i nduct ance of 1. 0m H
Line R egul at ion: 5. 0V
±12V
Vin= 95 to 130 Vac = 50mV or ±0. 5%
= 24mV or ±0. 1%
Load R egulati on: 5. 0V
±12V
Vin= 115Vac, Iout =1. 0A t o 4. 0A
Vin= 115Vac, Iout =100m A t o 300mA
= 300mV or ±3. 0%
= 60mV or ±0. 25%
Output R i pple: 5. 0V
±12V
Vin=115Vac 40mVp-p
80 Vp-p
Efficiency Vin=115Vac 70%
All outputs are at nominal load currents unless otherwise noted.
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
12-15 2002/01.ver.A
FI G URE 21 -33 W AT T O F F-L INE FL YB ACK CO NVE RT E R
WI T H SOF T -S T ART AND P RIMARY PO WER LI MIT I NG
T1
Coilcraft 11-464-16, 0.025” gap
in each leg
Baobbin :
Coilcraft 37-573
Windings:
Primary, 2 each:
75 turns #26 Awg Bifilar wound
Feedback:
15 turns #26 Awg
Secondary , 5.0V:
6 turns #22 Awg Bifiar wound
Secondary , 5.0V:
14 turns #24 Awg Bifiar wound
L1
Coilcraft Z7156. 15μF @ 5.0A
L2,L3
Coilcraft Z7157. 25μF @ 1.0A
TEST CONDITIONS RESULTS
Line R egul at ion 5. 0V Vin= 95 to 135 Vac, Io= 3. 0A 20mV 0. 40%
Line R egul at ion± 12V Vin= 95 to 135 Vac, Io= ±0. 75A 52mV 0. 26%
Line R egul at ion 5. 0V Vin= 115 Vac, Io= 1. 0 t o 4. 0A 476mV 9. 5%
Line R egul at ion± 12V Vin= 115 Vac, Io= ±0. 4 to ±0. 9A 300mV 2. 5%
Line R egul at ion 5. 0V Vin= 115 Vac, Io= 3. 0A 45 mVp-p
P.A.R.D.
Line R egul at ion± 12V Vin= 115 Vac, Io= ±0. 75A 75 mV p-p
P.A.R.D.
Efficiency Vin= 115 Vac, Io 5. 0V= 3. 0A
Io ±12=±0.75A 74%
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
13-15 2002/01.ver.A
PIN F UNCTI ON D ES CRIPTION
Pin N o. Funct ion Des cri pt io n
8-Pin
1
2
3
4
5
6
7
8
Compensation
Vo ltag e F eed b ack
C urrent S ense
RT/CT
Gnd
Output
Vcc
Vref
This pin i s t he Error Ampl ifi er output and i s made available for loop
compensation
This is the inverting input of the Error Amplifier. It is normally
connected to the switching power supply output through a resistor
divider.
A voltage proport ional t o inductor current is connect ed t o thi s i nput.
The PWM uses this information to terminate the output switch
conduction.
The Oscillator Frequency and maximum Output duty are
programmed by connecting resistor RT to Vref and capacitor CT to
ground operat ion t o 500kHz i s possibl e.
This pin is the combined control circuitry and power ground (8-pin
p ack age o n l y ).
This output direct ly drives the gate of a power MOS FET. P eak current
up to 1. 0A are s oured and sunk by t his pin.
T his pin is the positive supply of the control IC .
This pin is the reference output . It provides charging current for
cap aci t o r CT through res ist or RT.
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
14-15 2002/01.ver.A
O PE RAT I NG DE S CRI PT IO N
The P J3842B s eri es are high per formance, fi xed frequency, current mode cont roll ers, They are s pe cifi c al ly desi gned for Off-Line
and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components . A
repr esentat ive block diagram is shown in F igure 17.
OSCILLATOR
The oscillator frequency is programmed by the values selected for the timing components RT and CT . Capacitor CT is charged
from the 5.0V reference through resistor RT to approximately 2.8V and discharge to 1.2V by an internal current sink.During the
dis charge of C T , the oscillator generates an internal blanking pulse that holds the cente r input of t he NOR gat e hi gh. T hi s caus es
the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator
Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT . Note that many values of RT
and C T
will give the same oscillator fr equency but only onne combi nat ion will yield a specific output deadtime at a given fr equency. T he
oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at TJ
=25℃. These internal circuit refinements minimum variations of oscillator frequency and maximum output duty cycle. The
result s are s hown in F i gure 3 and 4.
In many noise sensitive applications it may be desir able to fr equen cy-lock the conve rter to an external syst em clock. T hi s can be
accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking. The free-running oscillator
frequency shoul d be set about 10% less than the clock frequency . A method for m ulti unit synchronization is shown in F igure 21.
By tail o ri n g the clo ck w av efo rm , accur at e Ou t p u t d u t y cy cle clam p i n g can b e ach i eved .
E RROR A MPLIFIE R
A fully compensated Error Ampli fier with access to the inverting input and output is provided. It features a typical DC voltage
gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phase margin (Figure 7). The non-inverting input is
internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the
invert ing i nput. The m axi mum input bias current i s -2. 0μA whi ch can caus e an output volt age error that i s equal to t he product of
the input bi as current and t he equi val ent i nput divi der source resi stance.
The Error Amp Output (P in 1) i s provi ded for external loop compensat ion (F igure 31). T he output vol tage is offset by two diode
drops (≈1. 4V) and di vided by three be fore i t connect s to t he i nverting i nput of t he C urrent S ense Com parator. This guarantees t hat
no drive pulses appear at the Output(Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is
operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum
feedback resistance is limited by the amplifier's source current (0.5mA) and the required output voltage (VOH) to reach the
co m p arator’s 1 .0 V cl am p lev el:
Rf(MIN ) = [3. 0 (1. 0V)+ 1. 4V] / 0. 5mA = 8800Ω
CURRE NT SE NSE CO MPARAT O R AND PW M L AT CH
The P J3842B operate as a curr ent m ode controll er, whereby output s wit ch conducti on is i nitiated by the oscillator and terminated
when t he peak i nduct or curr ent reaches t he t hr es hold l evel est abl ished by t he Error Am plifi e r Output/ C ompensati on (P i n 1). Thus
the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch
configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is
converted to a voltageby inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This
voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak
inductor current under norm al ope rat ing condi tions is cont rol led by t he vol tage at pin 1 where:
IPK = [V (P i n 1) - 1. 4 V] / 3 R S
Abnorm al operat ing condit ions occur when the power suppl y output is overl oaded or if out put vol tage s ensi ng is l ost, Under thes e
conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch
curr ent is:
I
PK (MAX) = 1.0V / RS
When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the
power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external
diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to
nois e pi ckup can res ult i f there i s an exces sive reduct ion of t he IPK (max) cl am p v o l tag e.
A narrow spike on the leadi ng edge of t he cur rent wave form can usuall y be observed and may c ause the power suppl y to exhibi t
an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output
rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike
duration will usually eliminate the instability: refer to Figure 26.
PJ3842B
Hi gh Per f or m a nce Cur r ent Mode Cont r oll e r
15-15 2002/01.ver.A
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.07 9.32 0.357 0.367
B 6.22 6.48 0.245 0.255
C 3.18 4.43 0.125 0.135
D 0.35 0.55 0.019 0.020
G 2.54BSC 0.10BSC
J 0.29 0.31 0.011 0.012
K 3.25 3.35 0.128 0.132
L 7.75 8.00 0.305 0.315
M - 10° - 10°
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.196
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27BSC 0.05BSC
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019