© 2005 Fairchild Semiconductor Corporation DS01 1602 www.fairchildsemi.com
May 1993
Revised February 2005
74LVX08 Low Voltage Quad 2-Input AND Gate
74LVX08
Low Voltage Quad 2-Input AND Gate
General Descript ion
The L VX08 contains four 2-input AND gates. The inputs tol-
erate voltages up to 7V allowing the interface of 5V sys-
tems to 3V systems.
Features
■Input voltage level translation from 5V to 3V
■Ideal for low power/low noise 3.3V applications
■Guaranteed simultaneous switching noise level and
dynamic thresh ol d per for man ce
Ordering Code:
Devices also available in Tape and Reel. Specify by appending su ffix le tter “X” to the ordering co de.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicat es Pb-Free package (per JED EC J -STD-0 20B). Devic e availa ble in Tape an d R eel only.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Package Description
Number
74LVX08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LVX08MTCX_NL
(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pin Names Description
An, Bn Inputs
OnOutputs
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74LVX08
Absolute Maximum Ratings(Note 2) Recommended Operating
Conditions (Note 3)
Note 2: The “Absolute Maximum Ratings” are those v alues beyon d which
the saf ety of the device cannot be guarante ed. The device s hould not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “R ecomm ended Ope rating Condition s” tabl e will d efine th e cond itions
for actu al device operation.
Note 3: Unu s ed inputs m us t be held HIG H or LOW. They may no t float.
DC Electrical Characteristics
Noise Characteristics (Note 4)
Note 4: Input tr
tf
3 ns
Supply Voltage (VCC)
0.5V to
7.0V
DC Input Diode Current (IIK)
VI
0.5V
20 mA
DC Input Voltage (VI)
0.5V to 7V
DC Output Diode Current (IOK)
VO
0.5V
20 mA
VO
VCC
0.5V
20 mA
DC Output Voltage (VO)
0.5V to VCC
0.5V
DC Output Source
or Sink C urrent (IO)
r
25 mA
DC VCC or Ground Current
(ICC or IGND)
r
50 mA
Storage Temper atu re (TSTG)
65
q
C to
150
q
C
Power Dissipation 180 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 240
q
C
Supply Voltage (VCC) 2.0V to 3.6V
Input Voltage (VI)0V to 5.5V
Output Voltage (VO) 0V to VCC
Operating Temperature (TA)
40
q
C to
85
q
C
Input Rise and Fall Time (
'
t/
'
V) 0 ns/V to 100 ns/V
Symbol Parameter VCC TA
25
q
C TA
40
q
C to
85
q
CUnits Conditions
Min Typ Max Min Max
VIH HIGH Level Input Voltage 2.0 1 1.5
3.0 2.0 2.0 V
3.6 2.4 2.4
VIL LOW Level Input Voltage 2.0 0.5 0.5
3.0 0.8 0.8 V
3.6 0.8 0.8
VOH HIGH Level Output Voltage 2.0 1.9 2.0 1.9 VIN
VIL or VIH IOH
50
P
A
3.0 2.9 3.0 2.9 V IOH
50
P
A
3.0 2.58 2.48 IOH
4 mA
VOL LOW Level Output Voltage 2.0 0.0 0.1 0.1 VIN
V IL or VIH IOL
50
P
A
3.0 0.0 0.1 0.1 V IOL
50
P
A
3.0 0.36 0.44 IOL
4 mA
IIN Input Leakage Current 3.6
r
0.1
r
1.0
P
AV
IN
5.5V or GND
ICC Quiescent Supply Current 3.6 2.0 20.0
P
AV
IN
VCC or GND
Symbol Parameter VCC TA
25
q
CUnits CL (pF)
(V) Typ Limit
VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.5 V 50
VOLV Quiet Output Minimum Dynamic VOL 3.3
0.3
0.5 V 50
VIHD Minimum HIGH Level Dynamic Input Voltage 3.3 2.0 V 50
VILD Maximum LOW Level Dynamic Input Voltage 3.3 0.8 V 50
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74LVX08
AC Electrical Characteristics
Note 5: Parameter guaranteed by design. tOSLH
|t PLHm
tPLHn|, tOSHL
|t PHLm
tPHLn|
Capacitance
Note 6: CPD is defined as t he v alue of the int ernal equ iv alent capacit anc e which is calcula te d f rom t he opera tin g c urrent co ns umption without load.
Symbol Parameter VCC TA
25
q
C TA
40
q
C to
85
q
CUnits CL (pF)
(V) Min Typ Max Min Max
tPLH Propagation De lay Ti m e 2.7 6.3 11.4 1.0 13.5
ns
15
tPHL 8.8 14.9 1.0 17.0 50
3.3
r
0.3 4.8 7.1 1.0 8.5 15
7.3 10.6 1.0 12.0 50
tOSLH Output to Output Skew 2.7 1.5 1.5 ns 50
tOSHL (Note 5) 3.3 1.5 1.5
Symbol Parameter TA
25
q
C TA
40
q
C to
85
q
CUnits
Min Typ Max Min Max
CIN Input Capacitance 4 10 10 pF
CPD Power Dissipation 18 pF
Capacitance (Note 6)
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74LVX08
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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74LVX08
Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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74LVX08 Low Voltage Quad 2-I nput AND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
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