GaAs, pHEMT, MMIC, Medium Power
Amplifier, 24 GHz to 35 GHz
Data Sheet
HMC1131
Rev. A Document Feedback
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Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
High saturated output power (PSAT): 25 dBm
High output third-order intercept (IP3): 35 dBm
High gain: 22 dB (24 GHz to 27 GHz)
High output power for 1 dB compression (P1dB): 24 dBm
DC supply: 5 V at 225 mA
Compact 24-lead, 4 mm × 4 mm LCC package
APPLICATIONS
Point-to-point radios
Point-to-multipoint radios
VSAT and SATCOM
FUNCTIONAL BLOCK DIAGRAM
1
NIC
2
GND
3
RFIN
4
GND
5
NIC
6
NIC
18
NIC
17
GND
16
RFOUT
15
GND
14
NIC
13
NIC
24
NIC
23
V
DD
1
22
V
DD
2
21
V
DD
3
20
V
DD
4
19
NIC
7
NIC
8
V
GG
1
9
NIC
10
NIC
11
V
GG
2
12
NIC
1.5kΩ
1.5kΩ
HMC1131
PACKAGE
BASE
13105-001
Figure 1.
GENERAL DESCRIPTION
The HMC1131 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transfer (pHEMT), monolithic microwave
integrated circuit (MMIC), driver amplifier that operates from
24 GHz to 35 GHz. The HMC1131 provides 22 dB of gain at the
24 GHz to 27 GHz range, 35 dBm output IP3, and 24 dBm of
output power at 1 dB gain compression, while requiring 225 mA
from a 5 V supply. The HMC1131 is capable of supplying 25 dBm
of saturated output power and is housed in a compact, 4 mm ×
4 mm ceramic leadless chip carrier (24-lead LCC). The HMC1131
is an ideal driver amplifier for a wide range of applications,
including point-to-point radios, from 24 GHz to 35 GHz.
HMC1131* Product Page Quick Links
Last Content Update: 11/01/2016
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•AN-1363: Meeting Biasing Requirements of Externally
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•Broadband Biasing of Amplifiers General Application Note
•MMIC Amplifier Biasing Procedure Application Note
•Thermal Management for Surface Mount Components
General Application Note
Data Sheet
•HMC1131: GaAs, pHEMT, MMIC, Medium Power
Amplifier, 24 GHz to 35 GHz Data Sheet
Reference Materials
Press
•Medium-Power Driver Amplifier Delivers High Gain and
Output Power for Easy Integration in Communications
Systems
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•HMC1131 Material Declaration
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HMC1131 Data Sheet
Rev. A | Page 2 of 14
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Electrical Specifications ................................................................... 3
24 GHz to 27 GHz Frequency Range ......................................... 3
27 GHz to 35 GHz Frequency Range ......................................... 3
Absolute Maximum Ratings ............................................................ 4
ESD Caution...................................................................................4
Pin Configuration and Function Descriptions ..............................5
Interface Schematics .....................................................................6
Typical Performance Characteristics ..............................................7
Applications Information .............................................................. 11
Evaluation PCB ........................................................................... 12
Typical Application Circuit ........................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
9/15—Rev. 0 to Rev. A
Changes to Features Section and General Description Section ........ 1
Change to Gain Parameter, Table 1 ................................................ 3
7/15—Revision 0: Initial Version
Data Sheet HMC1131
Rev. A | Page 3 of 14
ELECTRICAL SPECIFICATIONS
24 GHz TO 27 GHz FREQUENCY RANGE
TA = 25°C, VDD1 = VDD2 = VDD3 = VDD4 = 5 V, IDD = 225 mA, unless otherwise stated. Adjust VGG1 and VGG2 between −2 V to 0 V to
achieve IDD = 225 mA typical.
Table 1.
Parameter Symbol Min Typ Max Unit
FREQUENCY RANGE 24 27 GHz
GAIN 18 22 dB
Gain Variation Over Temperature 0.031 dB/°C
RETURN LOSS
Input 8 dB
Output 7 dB
OUTPUT
Output Power for 1 dB Compression P1dB 20 23 dBm
Saturated Output Power PSAT 27 dBm
Output Third-Order Intercept1 IP3 34 dBm
SUPPLY CURRENT
Total Supply Current IDD 225 mA
Total Supply Current vs. VDD2 4 V
5 V
1 Measurement taken at POUT/tone = 10 dBm.
2 The amplifier operates over the full voltage ranges shown. VGG1 and VGG2 are adjusted to achieve IDD = 225 mA at 5 V.
27 GHz TO 35 GHz FREQUENCY RANGE
TA = 25°C, VDD1 = VDD2 = VDD3 = VDD4 = 5 V, IDD = 225 mA, unless otherwise stated. Adjust VGG1 and VGG2 between −2 V to 0 V to
achieve IDD = 225 mA typical.
Table 2.
Parameter Symbol Min Typ Max Unit
FREQUENCY RANGE 27 35 GHz
GAIN 18 20 dB
Gain Variation Over Temperature 0.031 dB/°C
RETURN LOSS
Input 8 dB
Output 7 dB
OUTPUT
Output Power for 1 dB Compression P1dB 21 24 dBm
Saturated Output Power PSAT 25 dBm
Output Third-Order Intercept1 IP3 35 dBm
SUPPLY CURRENT
Total Supply Current IDD 225 mA
Total Supply Current vs. VDD2 4 V
5 V
1 Measurement taken at POUT/tone = 10 dBm.
2 The amplifier operates over the full voltage ranges shown. VGG1 and VGG2 are adjusted to achieve IDD = 225 mA at 5 V.
HMC1131 Data Sheet
Rev. A | Page 4 of 14
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Drain Bias Voltage (VDD) 5.5 V
RF Input Power (RFIN) 12 dBm
Channel Temperature 175°C
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 22 mW/°C)
1.97 W
Thermal Resistance, RTH (Junction to
Ground Paddle)
45.5°C/W
Operating Temperature −40°C to +85°C
Storage Temperature −65°C to +150°C
ESD Sensitivity, Human Body Model (HBM) Class 0,
passed 150 V
Maximum Peak Reflow Temperature 260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Data Sheet HMC1131
Rev. A | Page 5 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
NIC
2
GND
3
RFIN
4
GND
5
NIC
6
NIC
18 NIC
17 GND
16 RFOUT
15 GND
14 NIC
13 NIC
24 NIC
23 VDD1
22 VDD2
21 VDD3
20 VDD4
19 NIC
7
NIC
8
VGG1
9
NIC
10
NIC
11
VGG2
12
NIC
HMC1131
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD MUST BE CONNECTED
TO RF/DC GROUND.
13105-100
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 5 to 7, 9, 10, 12 to 14,
18, 19, 24
NIC Not Internally Connected. However, all data was measured with these pins connected to RF/dc
ground externally.
2, 4, 15, 17 GND Ground. These pins must be connected to RF/dc ground.
3 RFIN RF Input. This pin is ac-coupled and matched to 50 Ω.
8 VGG1 Gate Bias Pin for the First and Second Stages. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF
are required for this pin.
11 VGG2 Gate Bias Pin for the Third and Fourth Stages. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF
are required for this pin.
16 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω.
20 to 23 VDD4 to VDD1 Drain Bias Voltage Pins. External bypass capacitors of 100 pF, 10 nF, and 4.7 μF are required for
these pins.
EPAD Exposed Pad. The exposed pad must be connected to RF/dc ground.
HMC1131 Data Sheet
Rev. A | Page 6 of 14
INTERFACE SCHEMATICS
1.5kΩ
RFIN
13105-025
Figure 3. RFIN Interface Schematic
GND
13105-026
Figure 4. GND Interface Schematic
VGG1, VGG2
13105-027
Figure 5. VGG1/VGG2 Interface Schematic
1.5kΩ
RFOUT
13105-028
Figure 6. RFOUT Interface Schematic
VDD1, VDD2,
VDD3, VDD4
13105-029
Figure 7. VDD1 to VDD4 Interface Schematic
Data Sheet HMC1131
Rev. A | Page 7 of 14
TYPICAL PERFORMANCE CHARACTERISTICS
30
–30
–20
–10
0
10
20
23 25 27 29 31 33 35 37
RESPONSE (dB)
FRE Q UE NCY ( GHz)
S22
S21
S11
13105-002
Figure 8. Response (Broadband Gain and Return Loss) vs. Frequency
0
–35
–30
–25
–20
–15
–10
–5
24 25 27 29 31 33 3526 28 30 32 34 36
INPUT RETURN LOSS ( dB)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-003
Figure 9. Input Return Loss vs. Frequency at Various Temperatures
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
P1d B ( dBm)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-004
Figure 10. P1dB vs. Frequency at Various Temperatures
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
GAI N (dB)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-005
Figure 11. Gain vs. Frequency at Various Temperatures
0
–35
–30
–25
–20
–15
–10
–5
24 25 27 29 31 33 3526 28 30 32 34 36
OUTPUT RE TURN LOSS ( dB)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-006
Figure 12. Output Return Loss vs. Frequency at Various Temperatures
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
P1d B ( dBm)
FRE Q UE NCY ( GHz)
5V
4V
13105-007
Figure 13. P1dB vs. Frequency at Various Supply Voltages
HMC1131 Data Sheet
Rev. A | Page 8 of 14
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
PSAT (d Bm)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-008
Figure 14. PSAT vs. Frequency at Various Temperatures
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
P1d B ( dBm)
FRE Q UE NCY ( GHz)
250mA
225mA
200mA
175mA
13105-009
Figure 15. P1dB vs. Frequency at Various Supply Currents
40
20
22
24
26
28
30
32
34
36
38
24 25 27 29 31 33 3526 28 30 32 34 36
OUTPUT IP3 (dBm)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-010
Figure 16. Output IP3 vs. Frequency at Various Temperatures,
POUT/Tone = 10 dBm
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
PSAT (d Bm)
FRE Q UE NCY ( GHz)
5V
4V
13105-011
Figure 17. PSAT vs. Frequency at Various Supply Voltages
30
12
14
16
18
20
22
24
26
28
24 25 27 29 31 33 3526 28 30 32 34 36
PSAT (d Bm)
FRE Q UE NCY ( GHz)
250mA
225mA
200mA
175mA
13105-012
Figure 18. PSAT vs. Frequency at Various Supply Currents
40
20
22
24
26
28
30
32
34
36
38
24 25 27 29 31 33 3526 28 30 32 34 36
OUTPUT IP3 (dBm)
FRE Q UE NCY ( GHz)
250mA
225mA
200mA
175mA
13105-013
Figure 19. Output IP3 vs. Frequency at Various Supply Currents,
POUT/Tone = 10 dBm
Data Sheet HMC1131
Rev. A | Page 9 of 14
40
20
22
24
26
28
30
32
34
36
38
24 25 27 29 31 33 3526 28 30 32 34 36
OUTPUT IP3 (dBm)
FRE Q UE NCY ( GHz)
5V
4V
13105-014
Figure 20. Output IP3 vs. Frequency for Various Supply Voltages,
POUT/Tone = 10 dBm
70
60
50
40
30
20 4 8 12 16
610 14
OUTPUT IM3 (dBc)
P
OUT
/TONE (dBm)
34GHz
32GHz
30GHz
28GHz
13105-015
Figure 21. Output Third-Order Intermodulation (IM3) vs.
POUT/Tone at VDD = 5 V
27
19
21
20
22
23
24
25
26
175 200 225 250
GAI N (dB) , P1d B ( dBm), P
SAT
(d Bm)
I
DD
(mA)
P1dB
GAIN
P
SAT
13105-016
Figure 22. Gain, P1dB, and PSAT vs. Supply Current (IDD) at 30.5 GHz
70
60
50
40
30
20 4 8 12 16
610 14
OUTPUT IM3 (dBc)
POUT/TONE (dBm)
34GHz
32GHz
30GHz
28GHz
13105-017
Figure 23. Output Third-Order Intermodulation (IM3) vs.
POUT/Tone at VDD = 4 V
30
25
20
15
10
5
0
400
370
340
310
280
250
220
–15 –11 –7 –3 159
–13 –9 –5 –1 37
P
OUT
(d Bm) , GAIN (d B) , PAE ( %)
I
DD
(mA)
INPUT POWE R ( dBm)
I
DD
GAIN
PAE
P
OUT
13105-018
Figure 24. Power Compression at 30.5 GHz
(PAE Is Power Added Efficiency)
27
19
21
20
22
23
24
25
26
4.0 4.6 4.84.2 4.4 5.0
GAI N (dB) , P1d B ( dBm), PSAT (dBm)
VDD (V)
P1dB
GAIN
PSAT
13105-019
Figure 25. Gain, P1dB, and PSAT vs. Supply Voltage (VDD) at 30.5 GHz
HMC1131 Data Sheet
Rev. A | Page 10 of 14
0
–60
–50
–40
–30
–20
–10
24 25 27 29 31 33 3526 28 30 32 34 36
REVERSE ISOLATIO N (dB)
FRE Q UE NCY ( GHz)
TA = –40° C
TA = +25°C
TA = +85°C
13105-020
Figure 26. Reverse Isolation vs. Frequency at Various Temperatures
25
0
5
10
15
20
170 175 180 185 190 195 200 205 215210 220 225
INPUT I P 3 ( dBm)
IDD ( mA)
14dBm
10dBm
12dBm
13105-021
Figure 27. Input IP3 vs. IDD over POUT/Tone at 30 GHz,
VDD = 5 V, IDD = 225 mA, IDD2 = Fixed, and IDD1 Varied from 0 mA to 50 mA
2.0
0.6
0.8
1.0
1.2
1.4
1.6
1.8
–12 –9 –6 –3 –0 36 9
POWER DISSIPATI O N (W)
INPUT POWE R ( dBm)
32GHz
33GHz
34GHz
30GHz
28GHz
27GHz
13105-022
Figure 28. Power Dissipation (PDISS) at 85°C vs. Input Power for
Various Frequencies
170 175 180 185 190 195 200 205 215210 220 225
I
DD
(mA)
40
0
5
10
15
20
25
30
35
OUT P UT I P 3 ( dBm)
14dBm
10dBm
12dBm
13105-023
Figure 29. Output IP3 vs. IDD over POUT/Tone at 30 GHz,
VDD = 5 V, IDD = 225 mA, IDD2 = Fixed, and IDD1 Varied from 0 mA to 50 mA
25
0
5
10
15
20
170 175 180 185 190 195 200 205 210 215 220 225
GAI N ( dB)
I
DD
(mA)
13105-024
Figure 30. Gain vs. IDD over POUT/Tone = 14 dBm at 30 GHz,
VDD = 5 V, IDD = 225 mA, IDD2 = Fixed, and IDD1 Varied from 0 mA to50 mA
Data Sheet HMC1131
Rev. A | Page 11 of 14
APPLICATIONS INFORMATION
The HMC1131 is a GaAs, pHEMT, MMIC, medium power
amplifier consisting of four gain stages in series. VGG1 is the gate
bias pin for the first and second stages, while VGG2 is the gate
bias pin for the third and fourth stages. A simplified block
diagram is shown in Figure 31.
All measurements for this device were taken using the evaluation
printed circuit board (PCB) in its default configuration. Unless
otherwise noted, the VGG1, VGG2, and VDD1 to VDD4 pins were
tied together during measurement, respectively.
The following is the recommended bias sequence during
power-up:
1. Connect to ground.
2. Set VGG1 and VGG2 to −2 V.
3. Set VDD1 through VDD4 to 5 V.
4. Increase VGG1 and VGG2 to achieve a quiescent
IDD = 225 mA.
5. Apply the RF signal.
The following is the recommended bias sequence during
power-down:
1. Turn the RF signal off.
2. Decrease VGG1 and VGG2 to −2 V to achieve a quiescent
IDD = 0 mA (approximately).
3. Decrease VDD1 through VDD4 to 0 V.
4. Increase VGG1 and VGG2 to 0 V.
The VDDx = 5 V and IDD = 225 mA bias conditions are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown was taken using the
recommended bias conditions. Operation of the HMC1131 at
different bias conditions may result in performance that differs
from that shown in Figure 27 and Figure 30. Biasing the
HMC1131 for higher drain current typically results in higher
P1dB, OIP3, and gain but at the expense of increased power
consumption.
13105-032
V
DD
1 V
DD
2
V
GG
1
I
DD
1
A
I
DD
1
B
RFIN
V
DD
3 V
DD
4
V
GG
2
I
DD
2
A
I
DD
2
B
RFOUT
I
DD
1 = I
DD
1
A
+ I
DD
1
B
I
DD
2 = I
DD
2
A
+ I
DD
2
B
Figure 31. Simplified Block Diagram
HMC1131 Data Sheet
Rev. A | Page 12 of 14
EVALUATION PCB
Generate the evaluation PCB used in this application with
proper RF circuit design techniques. Signal lines at the RF port
must have 50 Ω impedance, and the package ground leads and
exposed paddle must be connected directly to the ground plane
similar to what is shown in Figure 32. Use a sufficient number
of via holes to connect the top and bottom ground planes.
TP6TP5
TP4
TP3
TP2
TP1
U1
+
C21
+
C20
+
C19
+
C18
+
C17
+
C16
+
C15
C9
C8
C14
C13 C12
C11
C10
C7
C6
C5 C4
C3
C2
C1
VG1VCTRLVG2
VD4VD3VD2VD1
THRU CAL
RFOUTRFIN
600-00145-00-1
TP7
13105-031
Figure 32. 600-00145-00-1 Evaluation PCB
Bill of Materials
Table 5. Evaluation Board (EV1HMC1131LC4) Bill of Materials
Item Description Manufacturer1
J1, J2 PCB mount, K connector
TP1 to TP7 DC pin
C1 to C6 100 pF capacitors, 0402 package
C8 to C13 10000 pF capacitors, 0402 package
C15 to C20 2.2 µF capacitors, 0402 package
U1 HMC1131LC4 Analog Devices, Inc.
PCB 600-00145-00-1 evaluation board, Rogers 4350 or Arlon 25FR circuit board material 600-00145-00-1, Analog Devices, Inc.
1 Blank cells in the manufacturer column left blank intentionally for they are user selectable.
Data Sheet HMC1131
Rev. A | Page 13 of 14
TYPICAL APPLICATION CIRCUIT
1
NIC
2
GND
3
RFIN
4
GND
5
NIC
6
NIC
18
NIC
17
GND
16
RFOUT
15
GND
14
NIC
13
NIC
24
NIC
23
V
DD
1
22
V
DD
2
21
V
DD
3
20
V
DD
4
19
NIC
7
NIC
8
V
GG
1
9
NIC
10
NIC
11
V
GG
2
12
NIC
1.5kΩ
1.5kΩ
HMC1131
V
DD
1C17
4.7µF
+C10
0.01µF C3
100pF
V
DD
2C15
4.7µF
+C8
0.01µF C1
100pF
V
DD
4
V
DD
3
C2
100pF +
C9
0.01µF C16
4.7µF
C4
100pF +
C11
0.01µF C18
4.7µF
V
GG
1C20
4.7µF
+C13
0.01µF C6
100pF
V
GG
2
C5
100pF +
C12
0.01µF C19
4.7µF
RFIN RFOUT
13105-030
Figure 33. Typical Application Circuit
HMC1131 Data Sheet
Rev. A | Page 14 of 14
OUTLINE DIMENSIONS
12
0.50
BSC
2.50 REF
BOTTOM VIEW
TOP VIEW
SIDE VIEW
SEATING
PLANE
1.02 MAX
2.50 SQ
1
24
7
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-03-2015-A
0.36
0.30
0.24
PIN 1
(0.32×0.32)
EXPOSED
PAD
P
KG-000000
PIN 1
INDICATOR
4.13
4.00 SQ
3.87
3.10 BSC
Figure 34. 24-Terminal Ceramic Leadless Chip Carrier [LCC]
(HE-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Lead Finish Package Description Package Option Branding3
HMC1131LC4 −40°C to +85°C MSL3 Gold over Nickel 24-Terminal LCC HE-24-1
XXXX
131H1
HMC1131LC4TR −40°C to +85°C MSL3 Gold over Nickel 24-Terminal LCC HE-24-1
XXXX
131H1
EV1HMC1131LC4 Evaluation Board
1 The HMC1131LC4 and the HMC1131LC4TR are RoHS Compliant.
2 See the Absolute Maximum Ratings section.
3 XXXX is the 4-digit lot number.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13105-0-9/15(A)
