TLV2542IDRG4 - Texas Instruments - Datasheet.Directory

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

DMaximum Throughput . . . 140/200 KSPS

DBuilt-In Conversion Clock

DINL/DNL: ±1 LSB Max, SINAD: 72 dB,

SFDR: 85 dB, fi = 20 kHz

DSPI/DSP-Compatible Serial Interface

DSingle Supply: 2.7 Vdc to 5.5 Vdc

DRail-to-Rail Analog Input With 500 kHz BW

DThree Options Available:

− TLV2541: Single Channel Input

− TLV2542: Dual Channels With

Autosweep

− TLV2545: Single Channel With

Pseudo-Differential Input

DLow Power With Autopower Down

− Operating Current: 1 mA at 2.7 V, 1.5 mA

at 5 V

Autopower Down: 2 μA at 2.7 V, 5 μA

at 5 V

DSmall 8-Pin MSOP and SOIC Packages

TOP VIEW

TLV2541

VREF

GND

AIN

SDO

VDD

SCLK

VREF

GND

AIN0

SDO

SCLK

VDD

AIN1

VREF

GND

AIN(+)

SDO

SCLK

VDD

AIN(−)

TOP VIEW

TLV2542

TOP VIEW

TLV2545

description

The TLV2541, TLV2542, and TLV2545 are a family of high performance, 12-bit, low power, miniature, CMOS

analog-to-digital converters (ADC). The TLV254x family operates from a single 2.7-V to 5.5-V supply. Devices

are available with single, dual, or single pseudo-differential inputs. Each device has a chip select (CS), serial

clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most

popular host microprocessors (SPI interface). When interfaced with a TMS320t DSP, a frame sync signal (FS)

can be used to indicate the start of a serial data frame on CS for all devices or FS for the TLV2541.

TLV2541, TLV2542, and TLV2545 are designed to operate with very low power consumption. The power saving

feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link

to modern host processors with SCLK up to 20 MHz. The maximum SCLK frequency is dependent upon the

mode of operation (see Table 1). The TLV254x family uses the built-in oscillator as the conversion clock,

providing a 3.5-μs conversion time.

AVAILABLE OPTIONS

PACKAGED DEVICES

TA8-MSOP

(DGK)

8-SOIC

(D)

TLV2541CDGK (AGZ)

0°C to 70°CTLV2542CDGK (AHB)

0C to 70 C

TLV2545CDGK (AHD)

TLV2541IDGK (AHA) TLV2541ID

−40°C to 85°CTLV2542IDGK (AHC) TLV2542ID

40 C to 85 C

TLV2545IDGK (AHE) TLV2545ID

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

functional block diagram

S/H

SDO

VREF

LOW POWER

SAR ADC

VDD

OSC Conversion

Clock

CONTROL

LOGIC

Mux

S/H

LOW POWER

12-BIT

SAR ADC

OSC Conversion

Clock

CONTROL

LOGIC

AIN

SCLK

VREF

AIN0

AIN1

SCLK

SDO

VDD

GNDGND

TLV2541 TLV2542

S/H

LOW POWER

12-BIT

SAR ADC

OSC Conversion

Clock

CONTROL

LOGIC

VREF

AIN (+)

AIN (−)

SCLK

SDO

VDD

GND

TLV2545

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Terminal Functions

TLV2541

TERMINAL

I/O

DESCRIPTION

NAME NO. I/O DESCRIPTION

AIN 4 I Analog input channel

CS 1 I Chip select. A high-to-low transition on the CS input removes SDO from 3-state within a maximum setup time.

CS can be used as the FS pin when a dedicated DSP serial port is used.

FS 7 I DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.

GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK 5 I Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until CS falling edge

or FS rising edge, whichever occurs first. The output format is MSB first.

When FS is not used (FS = 1 at the falling edge of CS): The MSB is presented to the SDO pin after CS falling edge

and output data is valid on the first falling edge of SCLK.

When CS and FS are both used (FS = 0 at the falling edge of CS): The MSB is presented to the SDO pin after the

falling edge of CS. When CS is tied/held low, the MSB is presented on SDO after the rising FS. Output data is valid

on the first falling edge of SCLK. (This is typically used with an active FS from a DSP using a dedicated serial port.)

VDD 6 I Positive supply voltage

VREF 2 I External reference input

TLV2542/45

TERMINAL

I/O

DESCRIPTION

NAME NO. I/O DESCRIPTION

AIN0 /AIN(+) 4 I Analog input channel 0 for TLV2542—Positive input for TLV2545.

AIN1/AIN (−) 5 I Analog input channel 1 for TLV2542—Inverted input for TLV2545.

CS 1 I Chip select. A high-to-low transition on CS removes SDO from 3-state within a maximum delay time. This pin can

be connected to the frame sync of a DSP using a dedicated serial port.

GND 3 I Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK 7 I Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO 8 O The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when CS is high

and presents output data after the CS falling edge until the LSB is presented. The output format is MSB first. SDO

returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.

VDD 6 I Positive supply voltage

VREF 2 I External reference input

detailed description

The TLV2541, TLV2542, and TLV2545 are successive approximation (SAR) ADCs utilizing a charge

redistribution DAC. Figure 1 shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process

starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is

balanced, the conversion is complete and the ADC output code is generated.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

detailed description (continued)

GND/AIN(−)

ADC Code

AIN

Charge

Redistribution

DAC

Control

Logic

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB LSB

D15−D4 D3−D0

Conversion result (OD11−OD0) Don’t care

The output data format is binary (unipolar straight binary).

binary

Zero-scale code = 000h, Vcode = GND

Full-scale code = FFFh, Vcode = VREF − 1 LSB

pseudo-differential inputs

The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a

maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

Each cycle may be started by either CS, FS, or a combination of both. The internal state machine requires one

SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered

up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever

CS (pin 1) is high to ensure proper operation.

TLV2541

DControl via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB

should be read on the first falling SCLK edge after CS is low. Output data changes on the rising edge of

SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a

DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock referenced to

ground) and CPHA = 1 (data is valid on the falling edge of the serial clock). At least one falling edge transition

on SCLK is needed whenever CS is brought high.

DControl via FS (CS is tied/held low)—The MSB is presented after the rising edge of FS. The falling edge

of FS is the start of the cycle. The MSB should be read on the first falling edge of SCLK after FS is low. This

is the typical configuration when the ADC is the only device on the DSP serial port.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

control and timing (continued)

DControl via both CS and FS—The MSB is presented after the falling edge of CS. The falling edge of FS is

the start of the sampling cycle. The MSB should be read on the first falling SCLK edge after FS is low. Output

data changes on the rising edge of SCLK. This configuration is typically used for multiple devices connected

to a TMS320 DSP.

TLV2542/5

All control is provided using CS (pin 1) on the TLV2542 and TLV2545. The cycle is started on the falling edge

transition provided by either a CS signal from an SPI microcontroller or FS signal from a TMS320 DSP. Timing

is similar to the TLV2541, with control via CS only.

TLV2542 channel MUX reset cycle

The TLV2542 uses CS to reset the analog input multiplexer. A short active CS cycle (4 to 7 SCLKs) resets the

MUX to AIN0. When the CS cycle time is greater than 7 SCLKs in duration, as in the case for a complete

conversion cycle (CS is low for 16 SCLKs plus maximum conversion time), the MUX toggles to the next channel

(see Figure 4 for timing). One dummy conversion cycle is recommended after power up before attempting to

reset the MUX.

sampling

The converter sample time is 12 SCLKs in duration, beginning on the fifth SCLK received after the converter

has received a high-to-low CS transition (or a high-to-low FS transition for the TLV2541).

conversion

The TLV2541, TLV2542, and TLV2545 complete conversions in the following manner. The conversion is started

after the 16th SCLK falling edge and takes 3.5 μs to complete. Enough time (for conversion) should be allowed

before a rising CS or FS edge so that no conversion is terminated prematurely.

TLV2542 input channel selection is toggled on each rising CS edge. The MUX channel can be reset to AIN0

via CS as described in the earlier section and in Figure 4. The input is sampled for 12 SCLKs, converted, and

the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between

samples to avoid prematurely terminating the cycle, which occurs on a rising CS transition if the conversion is

not complete.

The SDO data presented during a cycle is the result of the conversion of the sample taken during the previous

cycle.

timing diagrams/conversion cycles

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

1 2 3 4 5 6 12 13 14 15 16 1

OD8 OD7 OD6 OD5 OD0

SDO

t(sample) tc

t(powerdown)

OD10OD11 OD9

Figure 2. TLV2541 Timing: Control via CS (FS = 1)

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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timing diagrams/conversion cycles (continued)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

1 2 3 4 5 6 12 13 14 15 16 1

OD9 OD8OD11 OD10 OD7 OD6 OD0

SDO

t(sample) tc

t(powerdown)

Figure 3. TLV2541 Timing: Control via CS and FS or FS Only

SCLK

2 3 4 5 1 12 16

ÎÎÎÎÎÎ

SDO

t(powerdown)

1 4 161241

t(sample)

>8 SCLKs, MUX Toggles to AIN1

AIN0 Result

<8 SCLKs, MUX

Resets to AIN0

ÎÎÎÎÎÎÎ

t(sample)

ÎÎÎ

OD11 OD0

Figure 4. TLV2542 Reset Timing

OD8

SCLK

1 2 3 4 5 6 12 13 14 15 16

OD7 OD6 OD5 OD0

ÎÎÎÎÎÎ

SDO

t(sample) tc

t(powerdown)

OD9

OD10 OD9OD11 OD10 OD11

Figure 5. TLV2542 and TLV2545 Timing

using CS as the FS input

When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the

CS input if this is the only device on the serial port. This saves one output terminal from the DSP. (Output data

changes on the falling edge of SCLK. This is the default configuration for the TLV2542 and TLV2545.)

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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using CS as the FS input (continued)

SCLK and conversion speed

The input frequency of SCLK can range from 100 kHz to 20 MHz maximum. The ADC conversion uses a

separate internal oscillator with a minimum frequency of 4 MHz. The conversion cycle takes 14 internal oscillator

clocks to complete. This leads to a 3.5-μs conversion time. For a 20-MHz SCLK, the minimum total cycle time

is given by: 16x(1/20M)+14x(1/4M)+one SCLK = 4.35 μs. An additional SCLK is added to account for the

required CS and/or FS high time. These times specify the minimum cycle time for an active CS or FS signal.

If violated, the conversion terminates, invalidating the next data output cycle. Table 1 gives the maximum SCLK

frequency for a given supply voltage and operational mode.

control via pin 1 (CS, SPI interface)

All devices are compatible with this mode operation. A falling CS initiates the cycle (for TLV2541, the FS input

is tied to VDD). CS remains low for the entire cycle time (sample+convert+one SCLK) and can then be released.

NOTE:

IMPORTANT: A single SCLK is required whenever CS is high.

control via pin 1 (CS, DSP interface)

All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the

CS input of the ADC. A falling edge on the CS input initiates the cycle. (For the TLV2541, the FS input can be

tied to VDD, although better performance can be achieved when using the FS input for control. Refer to the next

section.) The CS input should remain low for the entire cycle time (sample+convert+one SCLK) and can then

be released.

NOTE:

IMPORTANT: A single SCLK is required whenever CS is high. This should be of little consequence,

since SCLK is normally always present when interfacing with a DSP.

control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)

Only the TLV2541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a

general-purpose I/O pin from the DSP. The FS signal from the DSP is connected directly to the FS input of the

ADC. A falling edge on CS, if used, releases the MSB on the SDO output. When CS is not used, the rising FS

edge releases the MSB. The falling edge on the FS input while SCLK is high initiates the cycle. The CS and

FS inputs should remain low for the entire cycle time (sample+convert+one SCLK) and can then be released.

reference voltage

An external reference is applied via VREF

. The voltage level applied to this pin establishes the upper limit of the

analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed the

positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output

is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal

to or lower than GND.

power down and power up

Autopower down is built into these devices in order to reduce power consumption. The actual power savings

depends on the inactive time between cycles and the power supply (loading) decoupling/storage capacitors.

Power-down takes effect immediately after the conversion is complete. This is fast enough to provide some

power savings between cycles with longer than 1 SCLK inactive time. The device power goes down to 5 μA

within 0.5 μs. To achieve the lowest power-down current (deep powerdown) of 1 μA requires 2-ms inactive time

between cycles. The power-down state is initiated at the end of conversion. These devices wake up immediately

at the next falling edge of CS or the rising edge of FS.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

0.95 mA

2 μA

ICC

With 1-μF/0.1-μF Capacitor Between Supply and Ground

(

Powerdown

)

− Powerdown time − S

0.5 μS

2 mS

VDD = 2.7 V

1 μA

5 μA

VDD = 5 V

1 μA

1.5 mA

Table 1. Modes of Operation and Data Throughput

CONTROL PIN(s)/DEVICE

MAX SCLK (MHz)

(50/50 duty cycle)

APPROXIMATE

CONVERSION

THROUGHPUT

(ksps)

VDD = 2.7 V VDD = 4.5 V VDD = 2.7 V VDD = 4.5 V

CS control only (TLV2541 only)

For SPI interface†10 15 175 200

For DSP interface (Use CS as FS)‡5 8 140 175

CS and FS control (TLV2541 only)§

DSP interface 15 20 200 200

†See Figure 29(a).

‡See Figure 29(b).

§See Figure 29(c).

absolute maximum ratings over operating free-air temperature (unless otherwise noted)¶

Supply voltage range, GND to VDD −0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range −0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range −0.3 V to VDD+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA:C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

¶Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VDD 2.7 3.3 5.5 V

Positive external reference voltage input, VREFP (see Note 1) 2 VDD V

Analog input voltage (see Note 1) 0 VDD V

High level control input voltage, VIH 2.1 V

Low-level control input voltage, VIL 0.6 V

Setu

time

CS fallin

e before first SCLK fallin

VDD = REF = 4.5 V 40

Setup time

CS falling edge before first SCLK falling edge

tsu(CSL-SCLKL) VDD = REF = 2.7 V 70 ns

Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL) 5 ns

Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH) (TLV2541 only) 0.5 7 SCLKs

Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLV2541 only) 0.35 SCLKs

Hold time, FS high after SCLK falling edge, th(SCLKL-FSL) (TLV2541 only) 0.65 SCLKs

Pulse width CS high time, tw(H_CS) 100 ns

Pulse width FS high time, tw(H_FS) (TLV2541 only) 0.75 SCLKs

SCLK cycle time, VDD = 3.6 V to 2.7 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 90 10000 ns

SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle) 50 10000 ns

Pulse width low time, tw(L_SCLK) 0.4 0.6 SCLK

Pulse width high time, tw(H_SCLK) 0.4 0.6 SCLK

Hold time, hold from end of conversion to CS high, th(EOC-CSH) (EOC is internal, indicates end of conversion

time, tc)0.05 μs

Active CS cycle time to reset internal MUX to AIN0, t(reset cycle) (TLV2542 only) 4 7 SCLKs

Delay time delay from CS falling edge to SDO valid t

VDD = REF = 4.5 V, 25-pF load 40

Delay time, delay from CS falling edge to SDO valid, td(CSL-SDOV) VDD = REF = 2.7 V, 25-pF load 70 ns

Delay time, delay from FS falling edge to SDO valid, t

L-

)

VDD = REF = 4.5 V, 25-pF load 1

Delay time

delay from FS falling edge to SDO valid

td(FSL

SDOV)

(TLV2541 only) VDD = REF = 2.7 V, 25-pF load 1ns

Dela

time, dela

from SCLK risin

e to SDO valid, VDD = REF = 4.5 V, 25-pF load 11

Delay time

delay from SCLK rising edge to SDO valid

td(SCLKH-SDOV) VDD = REF = 2.7 V, 25-pF load 21 ns

Delay time, delay from 17th SCLK rising edge to SDO 3-state, VDD = REF = 4.5 V, 25-pF load 30

Delay time

delay from 17th SCLK rising edge to SDO 3 state

td(SCLK17H-SDOZ) VDD = REF = 2.7 V, 25-pF load 60 ns

Conversion time, tcConversion clock = internal

oscillator 2.1 2.6 3.5 μs

Sampling time, t(sample) See Note 2 300 ns

Operating free air temperature T

TLV2541/2/5C 0 70

°C

Operating free-air temperature, TATLV2541/2/5I −40 85 °C

NOTES: 1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied

to GND convert as all zeros(000000000000).

2. Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 kΩ), where RS is the source output impedance.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

electrical characteristics over recommended operating free-air temperature range,

VDD = VREF = 2.7 V to 5.5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

High level output voltage

VDD = 5.5 V, IOH = −0.2 mA at 30-pF load 2.4

VOH High-level output voltage VDD = 2.7 V, IOH = -20 μA at 30-pF load VDD−0.2 V

Low level output voltage

VDD = 5.5 V, IOL = 0.8 mA at 30-pF load 0.4

VOL Low-level output voltage VDD = 2.7 V, IOL = 20 μA at 30-pF load 0.1 V

Off-state out

ut current VO = VDD

CS V

1 2.5

IOZ

Off

state output current

(high-impedance-state) VO = 0 CS = VDD −1−2.5 μA

IIH High-level input current VI = VDD 0.005 2.5 μA

IIL Low-level input current VI = 0 V −0.00

52.5 μA

Operating supply current

CS at 0 V

VDD = 4.5 V to 5.5 V 1.3 1.5

ICC Operating supply current CS at 0 V VDD = 2.7 V to 3.3 V 0.85 0.95 mA

Autopower-down current

(powerdown)

≥ 0.5

For all digital inputs,

0≤ VI ≤ 0.3 V or VI ≥ VDD− 0.3 V,

SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref

μA

power

own

) ≥ 0

5 μs

VDD = 2.7 V to 3.3 V, Ext ref 2

ICC(AUTOPWDN)

Deep autopower-down current

(powerdown)

≥ 2 ms

For all digital inputs,

0≤ VI ≤ 0.3 V or VI ≥ VDD− 0.3 V,

SCLK = 0, VDD = 4.5 V to 5.5 V, Ext ref

μA

power

own

) ≥ 2 ms

VDD = 2.7 V to 3.3 V 1

Selected analo

ut channel Selected channel at VDD 1

Selected analog input channel

leakage current Selected channel at 0 V −1μA

Input capacitance

Analog inputs 20 45 50

CiInput capacitance Control Inputs 5 25 pF

Input on resistance

VDD = 5.5 V 500

Input on resistance VDD = 2.7 V 600 Ω

Autopower down 0.5 SCLK

†All typical values are at VDD = 5 V, TA = 25°C.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ac specifications (fi = 20 kHz)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SINAD

Signal to noise ratio +distortion

200 KSPS, VDD = VREF = 5.5 V 70 72

SINAD Signal-to-noise ratio +distortion 150 KSPS, VDD = VREF = 2.7 V 68 71 dB

THD

Total harmonic distortion

200 KSPS, VDD = VREF = 5.5 V −84 −80

THD Total harmonic distortion 150 KSPS, VDD = VREF = 2.7 V −84 −80 dB

ENOB

Effective number of bits

200 KSPS, VDD = VREF = 5.5 V 11.8

Bits

ENOB Effective number of bits 150 KSPS, VDD = VREF = 2.7 V 11.6 Bits

SFDR

Spurious free dynamic range

200 KSPS, VDD = VREF = 5.5 V −84 −80

SFDR Spurious free dynamic range 150 KSPS, VDD = VREF = 2.7 V −84 −80 dB

Analog Input

Full-power bandwidth, −3 dB 1 MHz

Full-power bandwidth, −1 dB 500 kHz

external reference specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Reference input voltage VDD = 2.7 V to 5.5 V 2 VDD V

V 55 V

CS = 1, SCLK = 0 100 MΩ

Reference input impedance

VDD = 5.5 V CS = 0, SCLK = 20 MHz 20 25 kΩ

Reference input impedance

V 27 V

CS = 1, SCLK = 0 100 MΩ

VDD = 2.7 V CS = 0, SCLK = 20 MHz 20 25 kΩ

Reference current

VDD = VREF = 5.5 V, CS = 0, SCLK = 20 MHz 100 400

μA

Reference current VDD = VREF = 2.7 V, CS = 0, SCLK = 20 MHz 50 200 μA

V V 55 V

CS = 1, SCLK = 0 5 15

Reference input capacitance

VDD = VREF = 5.5 V CS = 0, SCLK = 20 MHz 20 45 50

Reference input capacitance

V V 27 V

CS = 1, SCLK = 0 5 15 pF

VDD = VREF = 2.7 V CS = 0, SCLK = 20 MHz 20 45 50

VREF Reference voltage VDD = 2.7 V to 5.5 V VDD V

dc specification, VDD = VREF = 2.7 V to 5.5 V, SCLK frequency = 20 MHz at 5 V, 15 MHz at 3 V (unless otherwise

noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INL Integral linearity error (see Note 4) ±0.6 ±1 LSB

DNL Differential linearity error See Note 3 ±0.5 ±1 LSB

Offset error (see Note 5)

See Note 3

TLV2541/42 ±1.5

LSB

EOOffset error (see Note 5) See Note 3 TLV2545 ±2.5 LSB

Gain error (see Note 5)

See Note 3

TLV2541/42 ±2

LSB

EGGain error (see Note 5) See Note 3 TLV2545 ±5LSB

Total unadjusted error (see Note 6)

See Note 3

TLV2541/42 ±2

LSB

EtTotal unadjusted error (see Note 6) See Note 3 TLV2545 ±5LSB

NOTES: 3. Analog input voltages greater than that applied to VREF convert as all ones (111111111111).

4. Linear error is the maximum deviation from the best straight line through the A/D transfer characteristics.

5. Zero error is the difference between 000000000000 and the converted output for zero input voltage: full-scale error is the difference

between 111111111111 and the converted output for full-scale input voltage.

6. Total unadjusted error comprises linearity, zero, and full-scale errors.

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎÎ

OD0

SCLK

VIH

OD11

SDO

t(sample)

4 12

tw(L_SCLK)

OD8

ÎÎÎÎÎ

VIL

tsu(CSL-SCLKL)

tw(H_SCLK)

th(EOC-CSH)

tw(H_CS)

t(powerdown)

th(SCLKL-FSL)

tsu(FSH-SCLKL)

tw(H_FS)

td(CSL-FSH)

td(CSL-SDOV)

td(SCLKH-SDOV)

td(SCLK17H-SDOZ)

Figure 6. TLV2541 Critical Timing (Control via CS and FS or FS only)

OD10 OD0

SCLK

SDO

t(sample)

4 1612

OD9

td(SCLKH-SDOV)

td(CSL-SDOV)

td(SCLK17H-SDOZ)

OD11

ÎÎÎÎÎÎÎ

t(powerdown)

tsu(CSL−SCLKL)

th(EOC−CSH)

Figure 7. TLV2541 Critical Timing (Control via CS only, FS = 1)

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

PARAMETER MEASUREMENT INFORMATION

ÎÎÎÎ

SCLK

SDO

t(sample)

td(SCLK17H-SDOZ)

1 1 12 164

t(reset cycle)

MUX = AIN0

OD11 OD0

ÎÎÎÎÎ

OD11

td(CSL-SDOV)

th(EOC-CSH)

td(SCLKH-SDOV)

td(CSL-SDOV)

tw(H_CS)

Figure 8. TLV2542 Reset Cycle Critical Timing

OD11 OD0

SCLK

VIH

SDO

t(sample) tc

4 1612

tw(L_SCLK)

ÎÎÎÎÎ

VIL

tw(H_SCLK)

th(EOC-CSH)

t(powerdown)

th(SCLKL-CSL)

td(CSL-SDOV)

td(SCLKH-SDOV)

td(SCLK17H-SDOZ)

OD8

tw(H_CS)

tsu(CSL-SCLKL)

Figure 9. TLV2542 and TLV2545 Conversion Cycle Critical Timing

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

Figure 10

0.6

−40 25

INL − Integral Nonlinearity − LSB

INTEGRAL NONLINEARITY

FREE-AIR TEMPERATURE

0.7

0.65

VDD = REF = 2.7 V

150 KSPS

TA − Free-Air Temperature − °C

Figure 11

0.5

−40 25

INL − Integral Nonlinearity − LSB

INTEGRAL NONLINEARITY

FREE-AIR TEMPERATURE

0.6

0.55

VDD = REF = 5.5 V

200 KSPS

TA − Free-Air Temperature − °C

Figure 12

0.3

0.2

−40 25

DNL − Differential Nonlinearity − LSB

0.4

0.5

DIFFERENTIAL NONLINEARITY

FREE-AIR TEMPERATURE

0.6

0.1

VDD = REF = 2.7 V

150 KSPS

TA − Free-Air Temperature − °C

Figure 13

0.3

0.25

−40 25

DIFFERENTIAL NONLINEARITY

FREE-AIR TEMPERATURE

0.35

VDD = REF = 5.5 V

200 KSPS

DNL − Differential Nonlinearity − LSB

TA − Free-air Temperature − °C

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

Figure 14

0.3

0.2

−40 25

Offset Error − LSB

0.4

0.5

OFFSET ERROR

FREE-AIR TEMPERATURE

0.1

VDD = REF = 2.7 V

150 KSPS

TA − Free-Air Temperature − °C

Figure 15

0.85

0.8

−40 25

Gain Error − LSB

0.9

GAIN ERROR

FREE-AIR TEMPERATURE

VDD = REF = 5.5 V

200 KSPS

TA − Free-Air Temperature − °C

1.4

1.2

−40 25

Supply Current − mA

1.5

SUPPLY CURRENT

FREE-AIR TEMPERATURE

VDD = REF = 5.5 V

200 KSPS

1.3

Figure 16

TA − Free-Air Temperature − °C

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

−0.5

−1

INL − Integral Nonlinearity − LSB

0.5

Digital Output Codes

INTEGRAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

4095

VDD = REF = 2.7 V

150 KSPS

Figure 17

−0.5

−1

DNL − Differential Nonlinearity − LSB

0.5

Digital Output Codes

4095

VDD = REF = 2.7 V

150 KSPS

Figure 18

DIFFERENTIAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

−0.5

−1

INL − Integral Nonlinearity − LSB

0.5

Digital Output Codes

INTEGRAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

4095

VDD = REF = 5.5 V

200 KSPS

Figure 19

−0.5

−1

DNL − Differential Nonlinearity − LSB

0.5

Digital Output Codes

DIFFERENTIAL NONLINEARITY ERROR

DIGITAL OUTPUT CODES

4095

VDD = REF = 5.5 V

200 KSPS

Figure 20

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

−60

−80

0 20 40 60 80 100

Magnitude − dB

−40

−20

f − Input Frequency − KHz

2048 POINTS FAST FOURIER TRANSFORM (FFT)

−120

−140

−100

VDD = REF = 2.7 V

150 KSPS

fi = 20 kHz

Figure 21

−60

−80

0 20 40 60 80 100

Magnitude − dB

−40

−20

f − Input Frequency − KHz

2048 POINTS FAST FOURIER TRANSFORM (FFT)

−120

−140

−100

VDD = REF = 5.5 V

200 KSPS

fi = 20 kHz

Figure 22

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

Figure 23

65 040

SINAD − Signal-To-Noise + Distortion − dB

f − Input Frequency − KHz

SIGNAL-TO-NOISE + DISTORTION

INPUT FREQUENCY

10 20 30 50 70 80

VDD = REF = 2.7 V

150 KSPS

Figure 24

65 040

SINAD − Signal-To-Noise + Distortion − dB

f − Input Frequency − KHz

SIGNAL-TO-NOISE + DISTORTION

INPUT FREQUENCY

20 80 100

VDD = REF = 5.5 V

200 KSPS

Figure 25

11.6

11.4

11 040

ENOB − Effective Number Of Bits − Bits

11.8

f − Input Frequency − KHz

EFFECTIVE NUMBER OF BITS

INPUT FREQUENCY

11.2

10 20 30 50 70 80

VDD = REF = 2.7 V

150 KSPS

Figure 26

11.6

11.4

11 040

ENOB − Effective Number Of Bits − Bits

11.8

f − Input Frequency − KHz

EFFECTIVE NUMBER OF BITS

INPUT FREQUENCY

11.2

20 80

VDD = REF = 5.5 V

200 KSPS

11.9

11.7

11.5

11.3

11.1

100

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

TYPICAL CHARACTERISTICS

Figure 27

−79

−81

−85 040

THD − Total Harmonic Distortion − dB

−77

−75

f − Input Frequency − KHz

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY

−83

20 80

VDD = REF = 2.7 V

150 KSPS

−76

−78

−80

−82

−84

70503010

Figure 28

−78

−82

−90 040

THD − Total Harmonic Distortion − dB

−74

−70

f − Input Frequency − KHz

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY

−86

20 80

−72

−76

−80

−84

−88

100

VDD = REF = 5.5 V

200 KSPS

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

SPI PORT

TLV2541

AIN

10 kΩ

VDD

SDO

VDD

SCLK

EXT

Reference

VREF

GND

VDD

MISO

SCLK

(a)

DSP

TLV2541

AIN

10 kΩ

VDD

SDO

VDD

SCLK

EXT

Reference

VREF

GND

VDD

FSX

CLKR

(b)

DSP

TLV2541

AIN

SDO

VDD

SCLK

EXT

Reference

VREF

GND

VDD

FSX

CLKX

(c)

GPIO

CLKX

FSR

CLKR

Figure 29. Typical TLV2541 Interface to a TMS320 DSP

TLV2541, TLV2542, TLV2545

2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS245E −MARCH 2000 − REVISED APRIL 2010

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

APPLICATION INFORMATION

TLV2542/45

TMS320

CLKR

AIN 0/AIN (+)†

10 kΩ

VDD

SDO

SCLK

VDD

GND

10 kΩ

EXT

Reference

VREF

AIN 1/AIN (−)†

†For TLV2545 only

FSR

FSX

CLKX

DSP

Figure 30. Typical TLV2542/45 Interface to a TMS320 DSP

PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TLV2541CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2541IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2541IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2541IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2541IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2542CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2012

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TLV2542IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2542IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2542IDR ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2542IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2545CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2545CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2545ID ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2545IDG4 ACTIVE SOIC D 8 75 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

TLV2545IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2545IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2545IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

TLV2545IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS

& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Aug-2012

Addendum-Page 3

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TLV2541CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLV2541IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLV2541IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV2542CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLV2542IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

TLV2542IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TLV2545IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV2541CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

TLV2541IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

TLV2541IDR SOIC D 8 2500 367.0 367.0 35.0

TLV2542CDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

TLV2542IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

TLV2542IDR SOIC D 8 2500 367.0 367.0 35.0

TLV2545IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Aug-2012

Pack Materials-Page 2

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