NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM 200 pin Unbuffered DDR2 SO-DIMM Based on DDR2-400/533 32Mx16 SDRAM Features * 200-Pin Small Outline Dual In-Line Memory Module (SO-DIMM) * 32Mx64 and 64Mx64 Unbuffered DDR2 SO-DIMM based on 32Mx16 DDR SDRAM devices. * Performance: PC2-3200 PC2-4200 5A 37B Speed Sort DIMM Latency fCK Clock Frequency tCK Clock Cycle fDQ DQ Burst Frequency * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - DIMM Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (256MB) 13/10/2 Addressing (512MB) * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 84-ball FBGA Package Unit 3 4 200 266 5 3.75 ns 400 533 MHz MHz * Intended for 200 MHz and 266MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * SDRAMs have 4 internal banks for concurrent operation * Module has one physical bank * Differential clock inputs Description NT256T64UH4A0FM, NT256T64UH4A0FN, NT512T64UH8A0FM, and NT512T64UH8A0FN are unbuffered 200-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as one rank of 32x64 and two ranks of 64x64 high-speed memory array. Modules use four 32Mx16 (256MB) or eight 32Mx16 (512MB) 84-ball FBGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 2.66" long space-saving footprint. The DIMM is intended for use in applications operating up to 200 MHz (266MHz) clock speeds and achieves high-speed data transfer rates of up to 400 MHz (533MHz). Prior to any access operation, the device latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information Part Number NT256T64UH4A0FM -5A NT256T64UH4A0FN -5A NT256T64UH4A0FM -37B NT256T64UH4A0FN -37B NT512T64UH8A0FM -5A NT512T64UH8A0FN -5A NT512T64UH8A0FM -37B NT512T64UH8A0FN -37B REV 1.2 11/02/2005 Speed Organization Power Leads DDR2-400 PC2-3200 200MHz (5ns @ CL = 3) Green 32Mx64 DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) 1.8V DDR2-400 PC2-3200 200MHz (5ns @ CL = 3) 64Mx64 DDR2-533 PC2-4200 266MHz (3.75ns @ CL = 4) Note Gold Green Green Green 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Pin Description CK0, Differential Clock Inputs CKE0, CKE1 DQ0-DQ63 Clock Enable Row Address Strobe Bidirectional data strobes - Column Address Strobe , Data input/output DQS0-DQS7 Differential data strobes DM0-DM7 Input Data Masks Write Enable VDD Power (1.8V) Chip Selects VREF Ref. Voltage for SSTL_18 inputs A0-A12 Row Address Inputs A0-A9 Column Address Inputs VSS Column Address Input/Auto-precharge SCL Serial Presence Detect Clock Input BA0, BA1 SDRAM Bank Address Inputs SDA Serial Presence Detect Data input/output ODT0, ODT1 Active termination control lines SA0, SA1 A10/AP NC VDDSPD Serial EEPROM positive power supply Ground Serial Presence Detect Address Inputs No Connect Pinout Pin Front 1 VREF 2 VSS 51 3 VSS 4 DQ4 53 5 DQ0 6 DQ5 7 DQ1 8 VSS 9 VSS 11 Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS 57 DQ19 58 DQ23 107 BA0 108 157 DQ48 158 DQ52 10 DM0 59 VSS 60 VSS 109 110 159 DQ49 160 DQ53 12 VSS 61 DQ24 62 DQ28 111 13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 15 VSS 16 DQ7 65 VSS 66 VSS 115 17 DQ2 18 VSS 67 DM3 68 19 DQ3 20 DQ12 69 NC 70 21 VSS 22 DQ13 71 VSS 72 23 DQ8 24 VSS 73 DQ26 25 DQ9 26 DM1 75 27 VSS 28 VSS 77 29 VDD 112 VDD 161 VSS 162 VSS 114 ODT0 163 NC 164 CK1 116 (A13) 165 VSS 166 118 VDD 167 168 VSS 117 VDD DQS3 119 ODT1 120 NC 169 DQS6 170 DM6 VSS 121 VSS 122 VSS 171 VSS 172 VSS 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS 30 CK0 79 CKE0 80 CKE1 129 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 (A15) 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 (BA2) 86 (A14) 135 DQ34 136 DQ39 185 DM7 186 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7 39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS 41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 49 Note: All pin assignments are consistent for all 8-byte unbuffered versions. REV 1.2 11/02/2005 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Input/Output Functional Description Symbol CK0 Type Polarity Function (SSTL) The positive line of the differential pair of system clock inputs which drives the input to the Positive on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the rising Edge edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to the Edge on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, to be executed by the SDRAM. , , VREF Supply , , define the operation Reference voltage for SSTL-18 inputs ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11, A12 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS7 - DM0 - DM7 (SSTL) Input On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.2 11/02/2005 Supply Serial EEPROM positive power supply. 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Functional Block Diagram (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D0 BA0-BA1 A0-A12 D2 D1 D3 BA0-BA1 : SDRAMs D0-D3 VDDSPD VDD/VDDQ VREF VSS VDDID A0-A12 : SDRAMs D0-D3 : SDRAMs D0-D3 : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 CKE1 N.C. : SDRAMs D0-D3 Notes : 1. 2. 3. 4. REV 1.2 11/02/2005 SPD D0-D3 D0-D3 D0-D3 CK0 CK1 2 loads 2 loads Serial PD SCL WP A0 A1 A2 SA0 SA1 SA2 SDA DQ wiring may differ from that described in this drawing . DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to V DDQ. 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Functional Block Diagram (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 LDQS DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D0 D4 A0-A12 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 D1 BA0-BA1 LDQS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D6 LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 BA0-BA1 : SDRAMs D0-D3 A0-A12 : SDRAMs D0-D3 : SDRAMs D0-D3 : SDRAMs D0-D3 CKE0 CKE : SDRAMs D0-D3 CKE1 N.C. ODT0 ODT : SDRAMs D0-D3 ODT1 ODT : SDRAMs D4-D7 VDDSPD VDD/VDDQ VREF VSS VDDID CK0 SPD D0-D3 D0-D3 D0-D3 2 loads CK1 2 loads : SDRAMs D0-D3 Notes : 1. 2. 3. 4. REV 1.2 11/02/2005 Serial PD SCL WP DQ wiring may differ from that described in this drawing. DQ/DQS/DM/CKE/S relationships are maintained as shown. DQ/DQS/DM/DQS resistors are 22+/- 5% Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to V DDQ. A0 A1 SA0 SA1 A2 SDA 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Serial Presence Detect (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) SPD Entry Value Byte Description DDR2 -400 (-5A) DDR2 -533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2 -400 (-5A) DDR2 -533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks, Package, and Height 1 rank, Height=30mm 60 6 Data Width of Assembly 7 Reserved 8 Voltage Interface Level of this Assembly 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 11 DIMM Configuration Type Non-Parity 00 12 Refresh Rate/Type 7.8 s/self 82 13 Primary DDR2 SDRAM Width X16 10 14 Error Checking DDR2 SDRAM Device Width N/A 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time from Clock at CL=4 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density per Rank 32 Address and Command Setup Time Before Clock (tIS) 0.35ns 0.25ns 35 25 33 Address and Command Hold Time After Clock (tIH) 0.475ns 0.375ns 47 37 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 15 10 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 27 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge delay (tRTP) 39 Reserved REV 1.2 11/02/2005 X64 40 Undefined 00 SSTL_1.8V 05 5ns 3.75ns 50 0.6ns 0.5ns 60 3D 50 Undefined 00 4,8 0C 4 04 3,4,5 38 <3.80mm 01 SODIMM (67.6mm) 04 Latencies Supported Normal DIMM 00 Support weak driver 01 5ns 3.75ns 50 0.6ns 0.5ns 60 5ns 3D 50 50 256MB 40 15ns 10ns Note 22 3C 7.5ns 28 1E 7.5ns 1E Undefined 00 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Serial Presence Detect (256MB - 1 Rank, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) SPD Entry Value Byte Description DDR2-400 (-5A) DDR2-533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2-400 (-5A) The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Minimum Core Cycle Time (tRC) 60ns 3C Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tQHS) 0.35ns 0.3ns 23 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 2D 8ns 46-61 Reserved 62 SPD Reversion 63 Checksum for Byte 0-62 73-91 Module Part number 92-255 Reserved Note: 1. 1E 28 -- 1.2 Checksum Data Module Manufacturing Location Note 80 Undefined 64-71 Manufacturer's JEDEC ID Code 72 DDR2-533 (-37B) 12 53 0F NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- undefined -- 1 Module part number: NT256T64UH4A0FM-5A 4E543235365436345548344130464D2D354120 NT256T64UH4A0FM-37B 4E543235365436345548344130464D2D3337420 NT256T64UH4A0FN-5A 4E543235365436345548344130464E2D354120 NT256T64UH4A0FN-37B 4E543235365436345548344130464E2D3337420 REV 1.2 11/02/2005 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Serial Presence Detect (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 1 of 2) SPD Entry Value Byte Description DDR2400 (-5A) DDR2533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2400 (-5A) DDR2533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 DDR2-SDRAM 08 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Rank, Package, and Height 2 rank, Height=30mm 61 6 Data Width of this Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 24 Maximum Data Access Time from Clock at CL=4 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 10ns 28 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density per Rank 256MB 40 32 Address and Command Setup Time Before Clock (tIS) 0.35ns 0.25ns 35 25 33 Address and Command Hold Time After Clock (tIH) 0.475ns 0.375ns 47 37 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 15 10 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 27 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge delay (tRTP) 39 Reserved REV 1.2 11/02/2005 5ns 3.75ns 50 0.6ns 0.5ns 60 3D 50 Non-Parity/ECC 00 7.8 s/self 82 X16 10 NA 00 Undefined 00 4,8 0C 4 04 3,4,5 38 <3.80mm 01 SODIMM (67.6mm) 04 Latencies Supported Normal DIMM 00 Support weak driver 01 5ns 3.75ns 50 0.6ns 0.5ns 60 5ns 3D 50 50 15ns 10ns Note 22 3C 7.5ns 28 1E 7.5ns 1E Undefined 00 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Serial Presence Detect (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) (Part 2 of 2) SPD Entry Value Byte Description DDR2400 (-5A) DDR2533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2400 (-5A) DDR2533 (-37B) The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Minimum Core Cycle Time (tRC) 60ns 3C Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 42 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tDQS) 0.35ns 0.3ns 23 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 2D 8ns 46-61 Reserved 80 Undefined 1E 28 -- 62 SPD Revision 63 Checksum for Byte 0-62 Checksum Data 64-71 Manufacturer's JEDEC ID Code NANYA 7F7F7F0B00000000 72 1.2 Module Manufacturing Location 73-91 Module Part number 92-255 Reserved Note: 1. Note 12 54 10 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 1 Module part number: NT512T64UH8A0FM-5A 4E543531325436345548384130464D2D354120 NT512T64UH8A0FM-37B 4E543531325436345548384130464D2D3337420 NT512T64UH8A0FN-5A 4E543531325436345548384130464E2D354120 NT512T64UH8A0FN-37B 4E543531325436345548384130464E2D3337420 REV 1.2 11/02/2005 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on I/O pins relative to Vss -0.5 to +2.3 V Voltage on VDD pins relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V TSTG Storage Temperature (Plastic) -55 to +100 C VIN, VOUT VDD Parameter Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 s DC Electrical Characteristics and Operating Conditions Symbol Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 V VSS, VSSQ VREF Parameter Supply Voltage, I/O Supply Voltage Input Reference Voltage VTT Termination Voltage 0 0 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Symbol Parameter Notes Min Max Units VIH (AC) Input High (Logic1) Voltage VREF + 0.250 - V 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 On Die Termination (ODT) Current Symbol Parameter IODTO Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING IODTT Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING REV 1.2 11/02/2005 Min Max Units EMRS(1) State 5 7.5 mA/DQ A6=0, A2=1 2.5 3.75 mA/DQ A6=1, A2=0 10 15 mA/DQ A6=0, A2=1 5 7.5 mA/DQ A6=1, A2=0 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC2-3200 PC2-4200 (-5A) (-37B) Unit Notes IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 280 320 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 300 380 mA 1 Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 20 20 mA 1 Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK address and control inputs changing once per clock cycle 128 160 mA 1 IDD2Q Precharge quiet standby current 140 120 mA 1 Active Power-Down Standby Current: one bank active; power-down mode; IDD3PF CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 52 64 mA 1 Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 20 20 mA 1 Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE IDD3N VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 140 168 mA 1 Operating Current: one bank; Burst = 4; reads; continuous burst; address IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 380 520 mA 1 Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 380 520 mA 1 IDD2P IDD2N IDD3PS (MIN); IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 520 600 mA 1 IDD6 Self-Refresh Current: CKE 0.2V 20 20 mA 1 IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 840 880 mA 1 Note: 1. Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.2 11/02/2005 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 2 Ranks, 32Mx16 DDR2 SDRAMs) Symbol Parameter/Condition PC2-3200 PC2-4200 (-5A) (-37B) Unit Notes IDD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 420 488 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; tRC = tRC (MIN); CL= 4; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 440 548 mA 1 Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 40 40 mA 1 Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK address and control inputs changing once per clock cycle 256 320 mA 1 IDD2Q Precharge quiet standby current 280 240 mA 1 Active Power-Down Standby Current: one bank active; power-down mode; IDD3PF CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=0 104 128 mA 1 Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); MRS(12)=1 40 40 mA 1 Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE IDD3N VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 280 336 mA 1 Operating Current: one bank; Burst = 4; reads; continuous burst; address IDD4R and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 4; tCK = tCK (MIN); IOUT = 0mA 520 688 mA 1 Operating Current: one bank; Burst = 4; writes; continuous burst; address IDD4W and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL= 4; tCK = tCK (MIN) 520 688 mA 1 IDD2P IDD2N IDD3PS (MIN); IDD5 Auto-Refresh Current: tRC = tRFC (MIN) 660 768 mA 1 IDD6 Self-Refresh Current: CKE 0.2V 40 40 mA 1 IDD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 980 1048 mA 1 Note: 1. Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.2 11/02/2005 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol -5A (DDR2-400) Parameter -37B (DDR2-533) Unit Min. Max. Min. DQ output access time from CK/ -0.6 0.6 -0.5 0.5 ns DQS output access time from CK/ -0.5 0.5 -0.45 0.45 ns tCH CK high-level width 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined Min(tCL, by clk high (tCH) or clk low (tCL) time tCH) - Min(tCL, tCH) - tCK tAC tDQSCK tCK Clock cycle time tDH DQ and DM input hold time(differential data strobe) Max. 5 8 3.75 8 ns 0.275 - 0.225 - ns tDS DQ and DM input setup time(differential data strobe) 150 - 100 - ns tIPW Input pulse width 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK - tAC max - tAC max ns tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max tAC min tAC max ns DQS-DQ skew (DQS & associated DQ signals) - 0.35 - 0.3 ns tQHS Data hold Skew Factor - 0.45 - 0.4 ns tQH Data output hold time from DQS tHP tQHS - tHP tQHS - ns tDQSQ tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - tCK tWPST Write postamble 0.4 0.6 0.4 0.6 tCK tWPRE Write preamble 0.35 - 0.35 - tCK 0.475 - 0.375 - ns 0.35 - 0.35 - ns tDQSL,(H) tIH tIS Address and control input hold time Address and control input setup time tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 tCK tRRD Active bank A to Active bank B command 10 - 10 - ns tDelay tREFI Minimum time clocks remains ON after CKE asynchronously drops Low 7.8 s Average Periodic Refresh Interval (0C TCASE 85C) 3.9 3.9 s tRFC Auto-Refresh to Active/Auto-Refresh command period 11/02/2005 ns 7.8 OCD drive mode output delay REV 1.2 tIS+tCK+ tIH Average Periodic Refresh Interval (85C < TCASE 95C) tOIT tCCD tIS+tCK+ tIH 0 12 0 105 to 2 12 105 - 2 ns ns - tCK 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -5A (DDR2-400) Parameter tWR Write recovery time without Auto-Precharge WR Write recovery time with Auto-Precharge -37B (DDR2-533) Unit Min. Max. Min. Max. 15 - 15 - ns tWR/tCK tWR/tCK WR + tRP - WR + tRP - tCK - 7.5 - ns tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay 10 tRTP Internal read to precharge command delay 7.5 7.5 ns tRFC + 10 tRFC + 10 ns 200 200 tCK tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tXP Exit precharge power down to any Non- read command 2 - 2 - tCK 2 - tCK tXARD Exit active power down to read command 2 tXARDS Exit active power down to read command 6 - AL 6 - AL tCK 3 3 tCK tCKE CKE minimum pulse width ODT tAOND tAON tAONPD tAOFD ODT turn-on delay 2 2 2 2 tCK ODT turn-on t (max) t (max) tAC(min) AC tAC(min) AC +1 +1 ns ODT turn-on (Power down mode) 2tCK + 2tCK + tAC(min) tAC(min) tAC(max) tAC(max) +2 +2 +1 +1 ns ODT turn-off delay 2.5 2.5 2.5 2.5 tCK ODT turn-off t (max) t (max) tAC(min) AC tAC(min) AC +0.6 +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK + 2.5tCK + tAC(min) tAC(min) t (max) t AC AC(max) +2 +2 +1 +1 ns tANPD ODT to power down entry latency 3 - 3 - tCK tAXPD ODT power down exit latency 8 - 8 - tCK ns tAOF Speed Grade Definition tRAS Row Active Time 40 70000 45 70000 tRC Row Cycle Time 55 - 60 - ns RAS to CAS delay 15 - 15 - ns Row Precharge Time 15 - 15 - ns tRCD tRP REV 1.2 11/02/2005 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Package Dimensions (256MB, 1 Rank, 32Mx16 DDR2 SDRAMs) FRONT 67.60 (2X) 1.80 2.15 1 39 41 11.40 30.00 20.00 6.00 4.00 63.60 199 Detail A Detail B 4.20 47.40 2.45 2.70 BACK SIDE 3.00 MAX 1.00+/- 0.10 Detail B 0.45 0.60 1.00+/- 0.1 2.55 4.00+/-0.10 0.25 MAX Detail A Note: All dimensions are typical with tolerances of +/- 0.15 unless otherwise stated. Units: Millimeters (Inches) REV 1.2 11/02/2005 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Package Dimensions (512MB - 2 Ranks, 32Mx16 DDR2 SDRAMs) " " $ % # "! !! &' "# ( ) 6, -) REV 1.2 11/02/2005 *+ ,-(,- . /01 2 3 ( . ,1 -(4 + 5, --(3 .2 - - * .-$ ,13 -% 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT256T64UH4A0FM / NT512T64UH8A0FM NT256T64UH4A0FN / NT512T64UH8A0FN (Green) 256MB: 32M x 64 / 512MB: 64M x 64 PC2-3200 / PC2-4200 Unbuffered DDR2 SO-DIMM Revision Log Rev Date 0.1 12/2003 Preliminary. Modification 0.2 10/2004 Added Idd values 1.0 01/2005 Official version 1.1 03/2005 Added DDR2-667 spec. 1.2 09/2005 Removed DDR2-667 spec. update SPD, maximum rating, & timing spec Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c)2005 REV 1.2 11/02/2005 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.