Errata SLAZ016D - June 2005 - Revised March 2012 MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet 1 Current Version See Appendix A for prior silicon revisions. CPU4 FLASH15 FLL3 PORT3 TA12 TA16 TAB22 TB2 TB14 TB16 US13 US14 US15 WDG2 XOSC9 ADC18 ADC13 H ADC10 I MSP430F4351IPZ Devices ADC9 MSP430F4351IPN Rev: ADC25 The checkmark means that the issue is present in the specified revision. MSP430F435IPN I MSP430F435IPZ H MSP430F4361IPN I MSP430F4361IPZ H MSP430F436IPN I MSP430F436IPZ H MSP430F4371IPN I MSP430F4371IPZ H MSP430F437IPN I MSP430F437IPZ H MSP430F447 G MSP430F448 G MSP430F4481 G MSP430F449 G MSP430F4491 G SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated 1 Package Markings 2 www.ti.com Package Markings PN80 LQFP (PN), 80 Pin PZ100 LQFP (PZ) 100 Pin 2 MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback Detailed Bug Description www.ti.com 3 Detailed Bug Description ADC9 ADC12 Module Function Interrupt vector register Description If the ADC12 uses a different clock than the CPU (MCLK) and more than one ADC interrupt is enabled, the ADC12IV register content may be unpredictable for one clock cycle. This happens if, during the execution of an ADC interrupt, another ADC interrupt with higher priority occurs. Workaround * * Read out ADC12IV twice and use only when values are equal. or Use ADC12IFG to determine which interrupt has occurred. ADC10 ADC12 Module Function Unintended start of conversion Description Accessing ADC12OVIE or ADC12TOVIE at the end of an ADC12 conversion with BIS/BIC commands can cause the ADC12SC bit to be set again immediately after it was cleared. This might start another conversion, if ADC12SC is configured to trigger the ADC (SHS = 0). Workaround If ADC12SC is configured to trigger the ADC, the control bits ADC12OVIE and ADC12TOVIE should be modified only when the ADC is not busy (ADC12BUSY = 0). ADC13 ADC12 Module Function Current consumption after clearing ADC12ON while ADC is busy Description If the ADC12ON bit is cleared while the ADC is busy, the ADC core might not be completely turned off and still consume current. Workaround * * Wait until ADC12BUSY is reset before clearing the ADC12ON bit. This is recommended for all protected bits in the ADC12CTLx registers. or Clear CONSEQx bits. With CONSEQx = 0 and ENC = 0, the ADC12 is reset. SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated 3 Detailed Bug Description www.ti.com ADC18 ADC12 Module Function Incorrect conversion result in extended sample mode Description The ADC12 conversion result can be incorrect if the extended sample mode is selected (SHP = 0), the conversion clock is not the internal ADC12 oscillator (ADC12SSEL > 0), and one of the following two conditions is true: * The extended sample input signal SHI is asynchronous to the clock source used for ADC12CLK and the undivided ADC12 input clock frequency exceeds 3.15 MHz. or * The extended sample input signal SHI is synchronous to the clock source used for ADC12CLK and the undivided ADC12 input clock frequency exceeds 6.3 MHz. Workaround * * * * Use the pulse sample mode (SHP = 1). or Use the ADC12 internal oscillator as the ADC12 clock source. or Limit the undivided ADC12 input clock frequency to 3.15 MHz. or Use the same clock source (such as ACLK or SMCLK) to derive both SHI and ADC12CLK, to achieve synchronous operation, and also limit the undivided ADC12 input clock frequency to 6.3 MHz. ADC25 ADC12 Module Function Write to ADC12CTL0 triggers ADC12 when CONSEQ = 00 Description If ADC conversions are triggered by the Timer_B module and the ADC12 is in singlechannel single-conversion mode (CONSEQ = 00), ADC sampling is enabled by write access to any bit(s) in the ADC12CTL0 register. This is contrary to the expected behavior that only the ADC12 enable conversion bit (ADC12ENC) triggers a new ADC12 sample. Workaround When operating the ADC12 in CONSEQ = 00 and a Timer_B output is selected as the sample and hold source, temporarily clear the ADC12ENC bit before writing to other bits in the ADC12CTL0 register. The following capture trigger can then be re-enabled by setting ADC12ENC = 1. CPU4 CPU Module Function PUSH #4, PUSH #8 Description The single operand instruction PUSH cannot use the internal constants (CG) 4 and 8. The other internal constants (0, 1, 2, -1) can be used. The number of clock cycles is different: PUSH #CG uses address mode 00, requiring 3 cycles, 1-word instruction PUSH #4/#8 uses address mode 11, requiring 5 cycles, 2-word instruction Workaround Workaround implemented in assembler. No fix planned. 4 MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback Detailed Bug Description www.ti.com FLASH15 Flash Module Function Programming Description Programming of flash memory can lead to unpredictable behavior under the following constellation: MCLK frequency is lower than 8 kHz, and the FTG frequency is 475 kHz. In general, when the duration of a program cycle (30 x tFTG) is less than half a MCLK period, this problem occurs. Workaround The duration of a program cycle (30 x tFTG) must be longer than half a MCLK period. FLL3 FLL+ Module Function FLLDx = 11 for /8 may generate an unstable MCLK frequency Description When setting the FLL to higher frequencies using FLLDx = 11 (/8), the output frequency of the FLL may have a larger frequency variation (for example, averaged over 2 seconds) and a lower average output frequency than expected when compared to the other FLLDx bit settings. Workaround None PORT3 Digital I/O Module, Port 1/2 Function Port interrupts can be lost Description Port interrupts can be lost if they occur during CPU access of the P1IFG and P2IFG registers. Workaround None TA12 Timer_A Module Function Interrupt is lost (slow ACLK) Description Timer_A counter is running with slow clock (external TACLK or ACLK) compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before the Timer_A counter has incremented again. Therefore, the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt is lost. Workaround Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterward. TA16 Timer_A Module Function First increment of TAR erroneous when IDx > 00 Description The first increment of TAR after any timer clear event (POR/TACLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TACLK). This is independent of the clock input divider settings (ID0, ID1). All following TAR increments are performed correctly with the selected IDx settings. Workaround None SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated 5 Detailed Bug Description www.ti.com TAB22 Timer_A/Timer_B Module Function Timer_A/B register modification after Watchdog Timer PUC Description Unwanted modification of the Timer_A/B registers TACTL and TAIV can occur when a PUC is generated by the Watchdog Timer (WDT) in watchdog mode and any Timer_A/B counter register TACCRx/TBCCRx is incremented/decremented (Timer_A/B does not need to be running). Workaround Initialize TACTL/TBCTL register after the reset occurs using a MOV instruction (BIS/BIC may not fully initialize the register). TAIV/TBIV is automatically cleared following this initialization. Example code: MOV.W #VAL, &TACTL or MOV.W #VAL, &TBCTL Where, VAL = 0, if Timer is not used in application; otherwise, user defined per desired function. TB2 Timer_B Module Function Interrupt is lost (slow ACLK) Description Timer_B counter is running with slow clock (external TBCLK or ACLK) compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by 1 with the occurring compare interrupt (if TBR = CCRx). Due to the fast MCLK, the CCRx register increment (CCRx = CCRx + 1) happens before the Timer_B counter has incremented again. Therefore, the next compare interrupt should happen at once with the next Timer_B counter increment (if TBR = CCRx + 1). This interrupt is lost. Workaround Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterward. TB14 Timer_B Module Function PWM output Description The PWM output unit may behave erroneously if the condition for changing the PWM output (EQUx or EQU0) and the condition for loading the shadow register TBCLx happen at the same time. Depending on the load condition for the shadow registers (CLLD bits in TBCCTLx), there are four possible error conditions: 1. Change CCRx register from any value to CCRx = 0 (for example, sequence for CCRx = 4 3 2 0 0 0) 2. Change CCRx register from CCRx = 0 to any value (for example, sequence for CCRx = 0 0 0 2 3 4) 3. Change CCRx register from any value to current SHD0 (CCR0) value (for example, sequence for CCRx = 4 2 5 SHD0 3 8) 4. Change CCRx register from current SHD0 (CCR0) value to any value (for example, sequence for CCRx = 4 2 SHD0 5 3 8) Workaround No general workaround available 6 MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback Detailed Bug Description www.ti.com TB16 Timer_B Module Function First increment of TBR erroneous when IDx > 00 Description The first increment of TBR after any timer clear event (POR/TBCLR) happens immediately following the first positive edge of the selected clock source (INCLK, SMCLK, ACLK, or TBCLK). This is independent of the clock input divider settings (ID0, ID1). All following TBR increments are performed correctly with the selected IDx settings. Workaround None US13 USART0, USART1 Module Function Unpredictable program execution Description USART interrupts requested by URXS can result in unpredictable program execution if this request is not served within two bit times of the received data. Workaround Ensure that the interrupt service routine is entered within two bit times of the received data. US14 USART0, USART1 Module Function Lost character start edge Description When using the USART in UART mode with UxBR0 = 0x03 and UxBR1 = 0x00, the start edge of received characters may be ignored due to internal timing conflicts within the UART state machine. This condition does not apply when UxBR0 > 0x03. Workaround None US15 USART0, USART1 Module Function UART receive with two stop bits Description USART hardware does not detect a missing second stop bit when SPB = 1. The framing error flag (FE) is not set under this condition, and erroneous data reception may occur. Workaround None (configure USART for a single stop bit, SPB = 0) WDG2 Watchdog Module Function Incorrectly accessing a flash control register Description If a key violation is caused by incorrectly accessing a flash control register, the watchdog interrupt flag is set in addition to a correctly generated PUC. Workaround None XOSC9 LFXT1 Module Function XT1 oscillator may not function as expected in high-frequency (HF) mode Description XT1 oscillator does not work correctly in high-frequency mode at supply voltages below 2 V with crystal frequency > 4 MHz. Workaround None. When XT1 oscillator is used in HF mode with crystal frequency > 4 MHz, ensure a supply voltage > 2.2 V. SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback MSP430F43x, F43x1, F44x, F44x1 Device Erratasheet Copyright (c) 2005-2012, Texas Instruments Incorporated 7 www.ti.com Appendix A Prior Versions None 8 Prior Versions SLAZ016D - June 2005 - Revised March 2012 Submit Documentation Feedback Copyright (c) 2005-2012, Texas Instruments Incorporated Revision History www.ti.com Revision History Changes from C Revision (January 2012) to D Revision ............................................................................................... Page * Added MSP430F4481 and MSP430F4491 ........................................................................................... 1 NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 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