SEMICONDUCTOR
1
August 1996
HS-1212RH
Radiation Hardened, Dual, High Speed
Low Power, Video Closed Loop Buffer
Features
• Electrically Screened to SMD# 5962F9683101VPA
• MIL-PRF-38535 Class V Compliant
• User Programmable For Closed-Loop Gains of +1, -1
or +2 Without Use of External Resistors
• Standard Operational Amplifier Pinout
• Low Supply Current. . . . . . . . . . 5.9mA/Op Amp (Typ)
• Excellent Gain Accuracy. . . . . . . . . . . . . .0.99V/V (Typ)
• Wide -3dB Bandwidth . . . . . . . . . . . . . . . 340MHz (Typ)
• Fast Slew Rate . . . . . . . . . . . . . . . . . . . . 1155V/µs (Typ)
• High Input Impedance . . . . . . . . . . . . . . . . . . 1MΩ (Typ)
• Excellent Gain Flatness (to 50MHz) . . . . ±0.02dB (Typ)
• Fast Overdrive Recovery. . . . . . . . . . . . . . . <10ns (Typ)
• Total Gamma Dose. . . . . . . . . . . . . . . . . . 300K RAD(Si)
• Latch Up . . . . . . . . . . . . . . . . . . . None (DI Technology)
Applications
• Flash A/D Driver
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
• RF/IF Signal Processing
• Imaging Systems
Description
The HS-1212RH is a dual closed loop buffer featuring user
programmable gain and high speed performance. Manufac-
tured on Harris’ proprietary complementary bipolar UHF-1
(DI bonded wafer) process, this device offers wide -3dB
bandwidth of 340MHz, very fast slew rate , excellent gain flat-
ness and high output current. These devices are QML
approved and are processed and screened in full compli-
ance with MIL-PRF-38535.
A unique f eature of the pinout allows the user to select a v olt-
age gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via connec-
tions to the inputs, as described in the “Application Informa-
tion” section. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
Detailed Electrical Specifications are contained in SMD
#5962F9683101VPA, available on the Harris Web site or
AnswerFAX Systems (Document #968310).
ACross Reference Table is available on the Harris Website
for conversion of Harris Par t Numbers to SMDs. The address
is (http://www.semi.harris.com/datasheets/smd/smd_xref.
html). SMD numbers must be used to order Radiation Hard-
ened Products.
Pinout
HS-1212RH
CERDIP
MIL-STD-1835 GDIP1-T8
TOP VIEW
Ordering Information
PART NUMBER TEMP. PACKAGE PKG.
5962F96830101VPA -55 to 125 8 Ld CERDIP GDIP1-T8
HFA1212IP
(Samples) -40 TO 85 8 Ld PDIP E8.3
HA5023EVAL Evaluation Board
OUT1
-IN1
+IN1
V-
1
2
3
4
8
7
6
5
V+
OUT2
-IN2
+IN2
+
-
+-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996 File Number 4228
2
Application Information
HS-1212RH Advantages
The HS-1212RH features a novel design which allows the
user to select from three closed loop gains, without any
external components. The result is a more flexible product,
f ewer part types in inventory, and more efficient use of board
space. Implementing a dual, gain of 2, cable driver with this
IC eliminates the four gain setting resistors, which frees up
board space for termination resistors.
Like most newer high performance amplifiers, the HS-
1212RH is a current f eedback amplifier (CFA). CFAs offer high
bandwidth and slew r ate at low supply currents , b ut can be dif-
ficult to use because of their sensitivity to feedback capaci-
tance and parasitics on the inverting input (summing node).
The HS-1212RH eliminates these concerns by bringing the
gain setting resistors on-chip. This yields the optimum place-
ment and value of the feedback resistor, while minimizing
feedback and summing node parasitics. Because there is no
access to the summing node, the PCB parasitics do not
impact perf ormance at gains of +2 or -1 (see “Unity Gain Con-
siderations” for discussion of parasitic impact on unity gain
performance).
The HS-1212RH’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
Closed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2, with
gain selection accomplished via connections to the inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded through a 50Ω resistor.
The table below summarizes these connections:
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HS-1212RH. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance associ-
ated with attaching the -Input lead to the PCB results in
approximately 6dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
Table 1 lists five alternate methods for configuring the HS-
1212RH as a unity gain buffer, and the corresponding perfor-
mance. The implementations vary in complexity and involve
perf ormance trade-offs . The easiest approach to implement is
simply shorting the two input pins together, and applying the
input signal to this common node. The amplifier bandwidth
decreases from 430MHz to 280MHz, but excellent gain flat-
ness is the benefit. A drawback to this approach is that the
amplifier input noise voltage and input offset voltage terms
see a gain of +2, resulting in higher noise and output offset
voltages. Alternately, a 100pF capacitor between the inputs
shorts them only at high frequencies, which prevents the
increased output offset voltage but deliv ers less gain flatness.
Another straightforward approach is to add a 620Ω resistor
in series with the amplifier’s positive input. This resistor and
the HS-1212RH input capacitance form a low pass filter
which rolls off the signal bandwidth before gain peaking
occurs. This configuration was employed to obtain the data
sheet AC and transient parameters for a gain of +1.
Pulse Overshoot
The HS-1212RH utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent sup-
ply current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added distor tion
f or signals swinging below ground, and an increased overshoot
on the negative portion of the output waveform (see Figure 6,
Figure 9, and Figure 12). This overshoot isn’t present for small
bipolar signals (see Figure 4, Figure 7, and Figure 10) or large
positive signals (see Figure 5, Figure 8 and Figure 11).
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB). The use of lo w
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
GAIN
(ACL)
CONNECTIONS
+INPUT -INPUT
-1 50Ω to GND Input
+1 Input NC (Floating)
+2 Input GND
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH PEAKING (dB) BW (MHz) ±0.1dB GAIN FLATNESS (MHz)
Remove -IN Pin 4.5 430 21
+RS= 620Ω0 220 27
+RS= 620Ωand Remove -IN Pin 0.5 215 15
Short +IN to -IN (e.g., Pins 2 and 3) 0.6 280 70
100pF Capacitor Between +IN and -IN 0.7 290 40
HS-1212RH
3
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the Evalua-
tion Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly ter-
minated transmission line will degrade the amplifier’s phase
margin resulting in frequency response peaking and possi-
ble oscillations . In most cases , the oscillation can be a voided
by placing a resistor (RS) in series with the output prior to
the capacitance.
Figure 1 details star ting points for the selection of this resis-
tor . The points on the curve indicate the R S and CL combina-
tions for the optimum bandwidth, stability, and settling time,
but experimental fine tuning is recommended. Picking a
point abov e or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate
areas of underdamped performance.
RS and CL for m a low pass network at the output, thus limit-
ing system bandwidth well below the amplifier bandwidth of
350MHz. By decreasing RS as CL increases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases.
Evaluation Board
The perf ormance of the HS-1212RH may be ev aluated using
the HA5023 Evaluation Board, slightly modified as follows:
1. Remove the two feedback resistors, and leave the con-
nections open.
2. a. For AV = +1 evaluation, remove the gain setting
resistors (R1), and leave pins 2 and 6 floating.
b. For AV = +2, replace the gain setting resistors (R1) with
0Ω resistors to GND.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.
0 100 200 300 400
0
10
20
30
40
50
LOAD CAPACITANCE (pF)
SERIES OUTPUT RESISTANCE (Ω)
AV=+2
150 250 35050
AV=+1
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
−5V
10µF 0.1µF
50Ω
GND
GND
R1+5V
0.1µF10µF
50Ω
IN
OUT
∞ (AV=+1)
or 0Ω (AV=+2)
NOTE: R1=
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
+
−
(NOTE) 1
2
3
4
8
7
6
5
FIGURE 3A. TOP LAYOUT
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
HS-1212RH
4
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
FIGURE 4. SMALL SIGNAL PULSE RESPONSE FIGURE 5. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 6. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 7. SMALL SIGNAL PULSE RESPONSE
FIGURE 8. LARGE SIGNAL POSITIVE PULSE RESPONSE FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE
TIME (5ns/DIV.)
OUTPUT VOLTAGE (mV)
200
150
100
50
0
-50
-100
-150
-200
AV = +2
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
AV = +2
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
AV = +2
TIME (5ns/DIV.)
OUTPUT VOLTAGE (mV)
200
150
100
50
0
-50
-100
-150
-200
AV=+1
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
AV = +1
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
AV = +1
HS-1212RH
5
FIGURE 10. SMALL SIGNAL PULSE RESPONSE FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 12. LARGE SIGNAL BIPOLAR PULSE RESPONSE FIGURE 13. FREQUENCY RESPONSE
FIGURE 14. FULL POWER BANDWIDTH FIGURE 15. GAIN FLATNESS
Typical Performance Curves
(Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
TIME (5ns/DIV.)
OUTPUT VOLTAGE (mV)
200
150
100
50
0
-50
-100
-150
-200
AV = -1
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
AV = −1
TIME (5ns/DIV.)
OUTPUT VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
AV = -1
PHASE
GAIN
1 10 100 600
FREQUENCY (MHz)
6
3
0
-3
-6
-9
NORMALIZED GAIN (dB)
AV = -1
AV = +1
AV = +2
AV = +1
AV = +2
-90
-180
-270
-360
0
NORMALIZED PHASE (DEGREES)
VOUT = 200mVP-P
+RS = 620Ω (+1)
+RS = 0Ω (-1, +2)
VOUT = 4VP-P (+1)
VOUT = 5VP-P (-1, +2)
+RS = 620Ω (+1)
6
3
0
-3
-6
-9
1 10 100 300
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
AV = -1
AV = +2
AV = +1
1 10 100
FREQUENCY (MHz)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
NORMALIZED GAIN (dB)
VOUT = 200mVP-P
+RS = 620Ω (+1)
+RS = 0Ω (-1, +2)
AV = +1AV = -1
AV = +2
HS-1212RH
6
FIGURE 16. REVERSE ISOLATION FIGURE 17. ALL HOSTILE CROSSTALK
FIGURE 18. 2nd HARMONIC DISTORTION vs POUT FIGURE 19. 3rd HARMONIC DISTORTION vs POUT
FIGURE 20. SETTLING RESPONSE FIGURE 21. INPUT NOISE CHARACTERISTICS
Typical Performance Curves
(Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
0.3 1 10 100
FREQUENCY (MHz)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
GAIN (dB)
AV = -1
AV = +1
AV = +2
0.3 1 10 100 500
FREQUENCY (MHz)
-110
-100
-90
-10
-20
-80
-70
-30
-40
-50
-60
CROSSTALK (dB)
AV = +2
RL = ∞
RL = 100Ω
-40
15
OUTPUT POWER (dBm)
DISTORTION (dBc)
-10 -5 0 5 10
-70
-65
-60
-55
-50
-45 20MHz
10MHz
-10 -5 0 5 10 15
-70
-65
-60
-55
-50
-45
-40
OUTPUT POWER (dBm)
DISTORTION (dBc)
20MHz
10MHz
13 33 53 73 93 113 153 173133
TIME (ns)
0.10
0.05
0
-0.05
-0.10
SETTLING ERROR (%)
AV = +1 20
16
12
8
4
20
16
12
8
4
0
0.1 1 10 100
FREQUENCY (kHz)
NOISE VOLTAGE (nV/√Hz)
0
NOISE CURRENT (pA/√Hz)
ENI
INI
HS-1212RH
7
FIGURE 22. OUTPUT VOLTAGE vs TEMPERATURE
Typical Performance Curves
(Continued) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified
3.6
3.5
3.4
3.3
3.2
3.1
2.9
2.8
2.7
2.6
-50 -25 0 25 50 75 100 125
TEMPERATURE (oC)
OUTPUT VOLTAGE (V)
3.0 +VOUT (RL= 50Ω)
|-VOUT| (RL= 50Ω)
+VOUT (RL= 100Ω)
|-VOUT| (RL= 100Ω)
AV = -1
HS-1212RH
8
Burn-In Circuit
HS-1212RH CERDIP
NOTES:
1. R1 = 1kΩ,±5% (Per Socket).
2. C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum.
3. D1 = D2 = 1N4002 or Equivalent (Per Board).
4. D3 = D4 = 1N4002 or Equivalent (Per Socket).
5. |(-V)| + |(+V)| = 11V ±1.0V.
6. 10mA. < | ICC, IEE | < 16 mA.
7. -50mV < VOUT < +50mV.
Irradiation Circuit
HS-1212RH CERDIP
NOTES:
1. R1 = 1kΩ,±5%
2. C1 = 0.01µF
3. V+ = +5.0V ±0.5V
4. V- = -5.0V ±0.5V
V+
C1 D1
D2 C2
V- D4
D3
1
2
3
4
8
7
6
5
+
-
+-
R1
R1
C1
C1
V-
1
2
3
4
8
7
6
5
+
-
+-
R1
R1
V+
HS-1212RH
9
Sales Office Headquarters
For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS
NORTH AMERICA
Harris Semiconductor
P. O. Box 883, Mail Stop 53-210
Melbourne, FL 32902
TEL: 1-800-442-7747
(407) 729-4984
FAX: (407) 729-5321
EUROPE
Harris Semiconductor
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Harris Semiconductor PTE Ltd.
No. 1 Tannery Road
Cencon 1, #09-01
Singapore 1334
TEL: (65) 748-4200
FAX: (65) 748-0400
SEMICONDUCTOR
Die Characteristics
DIE DIMENSIONS:
69 mils x 92 mils x 19 mils
1750µm x 2330µm x 483µm
METALLIZATION:
Type: Metal 1: AICu(2%)/TiW Type: Metal 2: AICu(2%)
Thickness: Metal 1: 8kű0.4kÅThickness: Metal 2: 16kű0.8kÅ
PASSIVATION:
Type: Nitride
Thickness: 4kű0.5kÅ
TRANSISTOR COUNT: 180
SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)
Metallization Mask Layout
HS-1212RH
NC
+IN1
-IN1
V+
OUT1
NC
-IN2
OUT2
NC
NC
+IN2
NC
NC
V-
HS-1212RH
