MOTOROLA SEMICONDUCTOR TECHNICAL DATA Preliminary Information Low Voltage 1:10 Differential HSTL Clock Fanout Buffer The Motorola MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. Order Number: MC100ES8111/D Rev 0, 06/2002 MC100ES8111 LOW-VOLTAGE 1:10 DIFFERENTIAL HSTL CLOCK FANOUT DRIVER Features: 1:10 differential clock fanout buffer 50 ps maximum device skew1 * * * * * * * * * SiGe technology Supports DC to 400 MHz operation1 of clock or data signals 1.5V HSTL compatible differential clock outputs PECL and HSTL compatible differential clock inputs FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A 3.3V power supply for device core, 1.5V or 1.8V HSTL output supply Supports industrial temperature range Standard 32 lead LQFP package Functional Description The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 400 MHz1. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC termination to GND (0V). The output supply voltage can be either 1.5V or 1.8V, the core voltage supply is 3.3V. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state (true outputs logic low, inverted outputs logic high). The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 1. AC specifications are design targets and subject to change Motorola, Inc. 2002 CLK_SEL Q4 Q4 Q5 Q5 Q6 Q6 17 Q1 Q1 Q2 Q2 VCCO 16 VCC0 Q2 26 15 Q7 Q3 Q3 Q2 27 14 Q7 Q4 Q4 Q1 28 13 Q8 Q5 Q5 Q1 29 12 Q8 Q6 Q6 Q0 30 11 Q9 Q7 Q7 Q0 31 10 Q9 Q8 Q8 VCCO 32 MC100ES8111 9 1 2 Q9 Q9 OE Figure 1. MC100ES8111 Logic Diagram 3 4 5 6 7 VCCO 8 GND CLK1 18 CLK1 CLK1 19 CLK1 OE 20 OE VCC 21 CLK0 1 22 CLK0 0 23 CLK_SEL CLK0 24 25 VCC CLK0 Q3 Q0 Q0 VCC Q3 MC100ES8111 Figure 2. 32-Lead Package Pinout (Top View) Table 1. PIN CONFIGURATION Pin I/O Type Function CLK0, CLK0 Input HSTL Differential HSTL reference clock signal input CLK1, CLK1 Input PECL Differential PECL reference clock signal input CLK_SEL Input LVCMOS Reference clock input select OE Input LVCMOS Output enable/disable. OE is synchronous to the input reference clock which eliminates possible output runt pulses when the OE state is changed. Q[0-9], Q[0-9] Output ECL/PECL Differential clock outputs GND Supply Negative power supply VCC VCCO Supply Positive power supply of the device core (3.3V) Supply Positive power supply of the HSTL outputs. All VCCO pins must be connected to the postive power supply (1.5V or 1.8V) for correct DC and AC operation. Table 2. FUNCTION TABLE Control Default CLK_SEL 0 CLK0, CLK0 (HSTL) is the active differential clock input CLK1, CLK1 (PECL) is the active differential clock input OE 0 Q[0-9], Q[0-9] are active. Deassertion of OE can be asynchronous to the reference clock without generation of output runt pulses. Q[0-9] = L, Q[0-9] =H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses. MOTOROLA 0 1 2 TIMING SOLUTIONS MC100ES8111 Table 3. Absolute Maximum Ratingsa Symbol Min Max Unit VCC VCCO Supply Voltage -0.3 3.6 V Supply Voltage -0.3 3.1 V VIN VOUT DC Input Voltage -0.3 V DC Output Voltage -0.3 VCC + 0.3 VCC + 0.3 IIN DC Input Current 20 mA 50 mA 125 C IOUT TS Characteristics DC Output Current Storage temperature -65 Condition V TFunc Functional temperature range TA = -40 TJ = +110 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol Characteristics Min Typ Max 0 Unit VTT MM Output termination voltage ESD Protection (Machine model) 200 V HBM ESD Protection (Human body model) 2000 V CDM ESD Protection (Charged device model) TBD V LU Latch-up immunity 200 mA CIN Input Capacitance JA Thermal resistance junction to ambient JESD 51-3, single layer test board 4.0 JESD 51-6, 2S2P multilayer test board JC TJ Thermal resistance junction to case Operating junction temperaturea (continuous operation) MTBF = 9.1 years Condition V pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 C/W C/W C/W C/W C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 C/W C/W C/W C/W C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 C/W MIL-SPEC 883E Method 1012.1 110 C a. Operating junction temperature impacts device life time. Maximum continues operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this datasheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES8111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES8111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. TIMING SOLUTIONS 3 MOTOROLA MC100ES8111 Table 5. DC Characteristics (VCC = 3.3V5%, VCCO=1.5V0.1V or VCCO=1.8V0.1V, TJ = 0C to + 110C)a Symbol Characteristics Min Clock input pair CLK0, CLK0 (HSTL differential signals) VDIF Differential input voltageb 0.2 Differential cross point voltagec 0.25 VX, IN VIH VIL IIN Input high voltage Typ Max 0.68 - 0.9 VCC-1.3 Unit Condition V VX+0.1 V V Input low voltage Input Current VX-0.1 150 mA V VIN = VX 0.1V Clock input pair CLK1, CLK1 (PECL differential signals) VPP Differential input voltaged 0.15 1.0 V Differential operation Differential cross point voltagee 1.0 VCC-0.6 VCC-0.880 V Differential operation VCMR VIH VIL IIN Input voltage high VCC-1.165 VCC-1.810 Input voltage low Input Currenta V VCC-1.475 150 mA V 0.8 V 150 mA 0.9 V VIN = VIH or VIN LVCMOS control inputs OE, CLK_SEL VIL VIH Input voltage low IIN Input Current Input voltage high 2.0 V VIN = VIH or VIN HSTL clock outputs (Q[0-9], Q[0-9]) VX,OUT VOH VOL Output differential crosspoint Output High Voltage 0.68 0.75 1 V Output Low Voltage 0.4 V Supply current ICC Maximum Quiescent Supply Current without output termination current 100 TBD mA VCC pin (core) ICCOf Maximum Quiescent Supply Current, outputs terminated 50 to VTT TBD TBD mA VCCO pins (outputs) W a. DC characteristics are design targets and pending characterization. b. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. c. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. d. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. e. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. f. ICC includes current through the output resistors (all outputs terminated to VTT). MOTOROLA 4 TIMING SOLUTIONS MC100ES8111 Table 6. AC Characteristics (VCC = 3.3V5%, VCCO = 1.5V0.1V or VCCO = 1.8V0.1V, TJ = 0C to + 110C) a b Symbol Characteristics Min Clock input pair CLK0, CLK0 (HSTL differential signals) VDIF Differential input voltagec (peak-to-peak) 0.4 Differential cross point voltaged 0.68 VX, IN fCLK VCMR fCLK V TBD MHz TBD ps 0.2 1.0 V 1 VCC-0.6 0-400 Differential input crosspoint voltagef Input Frequency VOL Output differential crosspoint 0-400 0.68 Output High Voltage 0.75 TBD ps Differential 0.9 V 1 V Output Low Voltage 0.5 V 50 ps Differential ps Differential tsk(PP) tJIT(CC) Output-to-output skew (part-to-part) TBD Output cycle-to-cycle jitter TBD g. h. 0.5 V Output-to-output skew DCO Output duty cycle TBD TBD % DCfref= 50% tr, tf Output Rise/Fall Time 0.05 TBD ns 20% to 80% Output disable time 2.5T + tPD 3.5T + tPD ns T=CLK period Output enable time 3T + tPD 4T + tPD ns T=CLK period tPDLg tPLDh f. V Differential Differential output voltage (peak-to-peak) e. Condition MHz VO(P-P) tsk(O) a. b. c. d. Unit V tPD Propagation Delay CLK1 to Q[0-9] HSTL clock outputs (Q[0-9], Q[0-9]) VX,OUT VOH Max 0.9 Input Frequency tPD Propagation Delay CLK0 to Q[0-9] Clock input pair CLK1, CLK1 (PECL differential signals) VPP Differential input voltagee (peak-to-peak) Typ 50 AC characteristics are design targets and pending characterization. AC characteristics apply for parallel output termination of 50 to VTT. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VDIF (DC) specification. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high). Propagation delay OE assertion to output enabled (active). TIMING SOLUTIONS 5 MOTOROLA MC100ES8111 CLKx CLKx 50% OE tPDL (OE to Qx[]) tPLD (OE to Qx[]) Qx[] Outputs disabled Qx[] Figure 1. MC100ES8111 AC test reference Differential Pulse Generator Z = 50 ZO = 50 ZO = 50 W RT = 50 DUT MC100ES8111 RT = 50 VTT=GND VTT=GND Figure 2. MC100ES8111 AC test reference CLK0,1 VDIF=1.0V CLK0,1 VX=0.75V CLK0,1 CLK0,1 Q[0-9] Q[0-9] Q[0-9] Q[0-9] tPD (CLK0,1 to Q[0-9]) VCMR=VCC-1.3V tPD (CLK0,1 to Q[0-9]) Figure 3. MC100ES8111 AC reference measurement waveform (HSTL input) MOTOROLA VPP=0.8V Figure 4. MC100ES8111 AC reference measurement waveform (PECL input) 6 TIMING SOLUTIONS MC100ES8111 OUTLINE DIMENSIONS A -T-, -U-, -Z- FA SUFFIX LQFP PACKAGE CASE 873A-02 ISSUE A 4X A1 32 0.20 (0.008) AB T-U Z 25 1 -U- -T- B V AE P B1 DETAIL Y 17 8 V1 AE DETAIL Y 9 4X -Z- 9 0.20 (0.008) AC T-U Z S1 S DETAIL AD G -AB- 0.10 (0.004) AC AC T-U Z -AC- BASE METAL EE EE EE EE F 8X M_ R J M N D 0.20 (0.008) SEATING PLANE SECTION AE-AE W K X DETAIL AD TIMING SOLUTIONS Q_ GAUGE PLANE H 0.250 (0.010) C E 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MOTOROLA MC100ES8111 Motorola reserves the right to make changes without further notice to any products herein. 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