Order Number: 315514-002
Revision 2. 5
82573 Family of GbE Controllers
Datasheet
Product Feature s
PCIe*
— x1 PCIe* interface on ICH7 or MCH devices
— Peak bandwidth: 2 Gb/s per direction
— Power management
— High bandwidth density per pin
MAC
— Optimized transmit and receive queues
— IEEE 802.3x compliant flow control with
software controlled pause times and threshold
values
— Caches up to 64 packet descriptors per queue
— Programmable host memory receive buffers
(256 bytes to 16 KB) and cache line size (16
bytes to 256 bytes)
— 32 KB c onfig urable t ransmit an d receive FIFO
buffer
— Mechanism available for red uci ng interrupts
generated by transmit and receive operation
— Descripto r ri ng managem en t hardw are for
transmit and receive
— Optimized descriptor fetching and write-back
mechanisms
— Wide, pipelined internal data path architecture
PHY
— Integrated PHY for 10/100/1000 Mb/s full and
half duplex operation
— IEEE 802.3ab auto negotiation support
— IEEE 802.3ab PHY compliance and
compatibility
— DSP architectu re implemen ts digital
adaptive equalization, echo cancellation,
and cross-talk cancellation
Host Offloading
— Transmi t and receive IP, TCP and U DP
checksum off-loading capabilities
— Transmit TCP segmentation, IPv6 offloading,
and advanced p a c ket filter ing
— IEEE 802.1q VLAN support with VLAN tag
insertion, stripping and packet filtering for up
to 4096 VLAN tags
— Descripto r ri ng managem en t hardw are for
transmit and receive
Manageability
— Intel® Active Management T echnology (Intel®
AMT) support (82573E only)
— Alerting Standards Format 2.0 and advanced
pass through support (82573E/V only)
— Boot ROM Preboot eXecution Environment
(PXE) Flash interfa ce supp ort
— Compliance with PCI Power Management 1.1
and Advanced Configuration and Power
Interface (ACPI) 2.0 regi s t er s et c o mpliant
— Wa ke on LAN support
Additional
— Three activity and link indication outputs that
directly drive LEDs
— Programmable LEDs
— Internal PLL for clock generation that can use
a 25 MHz crystal
— Power saving feature for the 82573L. During
the L1 and L2 link states, the 82573L asserts
the Clock Request signal (CLKREQ#) to
indicate that its PCIe* reference clock can be
gated
— On-chip po w er c o n t rol circuitry
— Loopback capabilities
— JTAG (IEEE 1149.1) Test Access Port (TAP)
built in silicon
Technology
— Lead-free 196-pin Thin and Fine Pitch Ball Gri d
Array (TF-BGA) pac k age
— Operating temperature: 0° C to 70° C (with
external re gu lators)
— Operating temperature: 0° to 55° C (with on-
die 2.5V regulator)
— Storage temperature -40° C to 125° C
2
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Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel proces so r nu mb er s are not a measure of perfor manc e. Pro ces so r num be r s differ entiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details.
This document contains information on products in the design phase of development. The information here is subject to change witho ut notice. Do not
fina lize a desig n with this informa tion.
The 82573 GbE Cont rollers may c ontain design de fects or err ors known as errata which may caus e t he p r odu c t to deviate from p ublished specifications.
Current characterized errata are available on request.
Hyper-Threading Technology requires a compute r system with an Intel® Pentium® 4 processor supporting HT Technology and a HT Technology enabled
chipset, BIOS and operating system. Performance will vary depending on the specific har dwar e and software you use. See http://www.intel.com/
products/ht/Hyperthreading_more.htm for a d d i tional information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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*Other names and brands may be claimed as the property of others.
Copyrigh t © 2007, Inte l Cor poration. All Rig ht s Reserve d.
3
Datasheet—82573
Contents
1.0 Introduction..............................................................................................................7
1.1 Document Scope.................................................................................................8
1.2 Reference Docume nt s ............................. ............ ........... ........... ............ ........... ....8
1.3 82573 Architecture .............................................................................................9
1.4 Product Codes for the 82573............................................................................... 1 0
2.0 Signal Descriptions.................................................................................................. 10
2.1 Signal Typ e Defini tions.. ........... ........... ................... ............ ................... ........... .. 10
2.2 PCIe* Data Signals............................................................................................ 11
2.3 PCIe* Miscellaneous Signals ............................................................................... 11
2.4 Non-Volatile Memory Interface Signals................................................................. 12
2.5 Miscellaneo us Sig nal s .......... .... ........... ................... ............ ........... ............ ......... 12
2.5.1 Reset and Power-down Signals................................................................. 12
2.5.2 System Management Bus (SMBus ) Signal s ......... ............ ........... ........... ...... 13
2.5.3 LED Signals........................................................................................... 13
2.5.4 Other Signal s.... ... ............ ................... ........... ............ ........... ................. 13
2.6 PHY Analog and Crystal Si gn als..... .... ........... ........... ................... ............ ........... .. 14
2.7 Test Signals...................................................................................................... 15
2.7.1 MAC Test Signals.. ............ ........... ............ ........... ........... ................... ...... 15
2.7.2 PHY Test Signals .................. ................... ........... ........... ............ ........... .. 15
2.7.3 Other Test Signals................... ................... ............ ........... ............ ......... 15
2.8 Power Sign als .. .... ................... ........... ............ ................... ........... ............ ......... 16
2.8.1 Power Support Signals .. .... ........... ................... ............ ........... ........... ...... 16
2.8.2 Digital and Analo g Pow er Supp ly Si gn als ............... .... ................... ........... .. 16
2.9 Grounds and No Connects .................................................................................. 16
3.0 Voltage, Temperature, and Timing Specifications .................................................... 17
3.1 Absolut e Maximum Ratings............... ........... ................... ........... ............ ........... .. 17
3.2 Recommended Operating Conditions.................................................................... 17
3.3 Power Supp ly Connect ions................... ............ ................... ........... ............ ......... 17
3.3.1 External LVR Power Delivery.................................................................... 18
3.3.2 Power Sequen cin g wit h Ext e rnal Re gulators ........... ........... ............ ............. 19
3.3.3 Internally Generated Power Delivery......................................................... 20
3.3.4 Internal LVR Power Sequencing................................................................ 21
3.4 DC and AC Specifica tions...... ............ ........... ........... ................... ............ ........... .. 25
3.5 External Interfaces ............................................................................................ 28
3.5.1 Crystal.................................................................................................. 28
3.5.2 External Clock Oscillator ......................................................................... 28
3.5.3 Non-Volatile Memory (NVM) Interface: EEPROM ......................................... 29
4.0 Package and Pinout Information ............................................................................. 30
4.1 Package Information.......................................................................................... 30
4.2 Thermal Specifi cati on s .. ... ............ ................... ........... ............ ........... ................. 32
4.3 Pinout In formation .................. ........... ................... ............ ........... ................... .. 33
4.3.1 PCIe Bus Interface Signals.......................................................................33
4.3.2 Non-Volatile Memory Interface Signals...................................................... 34
4.3.3 Miscellan eous Sig nal s ... ........... ............ ........... ............ ........... ................. 34
4.3.4 PHY Signals................. ........... ............ ................... ........... ............ ......... 35
4.3.5 Test Signals........................................................................................... 35
4.3.6 Power Supp ly Sign als........ .... ........... ........... ................... ............ ........... .. 36
4.4 Visual Pin Assignments....................................................................................... 38
82573—Datasheet
4
Figures
1 82573 Block Diagram................................................................................................. 9
2 Minimum Requirem en ts for Pow er Supp ly Sequen cin g ..................... ........... ............ .......20
3 Power Supply Sequ encing... ........... ............ ........... ................... ........... ............ ...........21
4 82573 2.5V and 1.2V LVR Schematic ..........................................................................25
5 External Clock Oscillator Connectivity to the 82573.......................................................29
6 82573 Controller TF-BGA Package Ball Pad Dimensions..................................................30
7 82573 Mechanical Specifications.................................................................................31
8 82573E and 82573V Gigabit Ethernet Controller Pinout..................................................38
9 82573L Gigabit Ethernet Controller Pinout....................................................................39
5
Datasheet—82573
Tables
1 Absolute Maximum Ratings ....................................................................................... 17
2 Recommende d Operat ing Con di tion s......... ........... ........... ............ ................... ........... .. 17
3 3.3V External Supp ly Volt age Ramp and Sequencin g Recommen datio ns . ............ ........... .. 18
4 2.5V External Supp ly Volt age Ramp and Sequencin g Recommen datio ns . ............ ........... .. 18
5 1.2V External Supp ly Volt age Ramp and Sequencin g Recommen datio ns . ............ ........... .. 19
6 3.3V Internal Powe r Supp ly Parameters ............... .... ........... ............ ........... ........... ...... 20
7 82573 Bill of Materials (BOM) of Components for Internal Regulator................................ 22
8 2.5V Internal LVR Specification .................................................................................. 22
9 1.2V Internal LVR Specification .................................................................................. 23
10 PNP Specification ..................................................................................................... 23
11 82573E and 82573V Maximum Measured External Power Characteristics ......................... 25
12 82573E and 82573V Typical Measured External Power Characteristics ............................. 26
13 82573E and 82573V 2.5 V In te rnal Power Regulat or Numb ers..... .... ........... ............ ......... 26
14 82573L Maximum Measured Power Characteristics ....................................................... 27
15 82573L Mea sure d Power Charact eristi c s........... ............ ........... ........... ............ ........... .. 27
16 DC Specifi cati on s ................ ................... ........... ........... ............ ................... ........... .. 27
17 LED DC Specifi cations.......... ........... ........... ................... ............ ........... ................... .. 28
18 Crystal Specifications................................................................................................ 28
19 Specification for External Clock Oscillator .................................................................... 29
20 NVM Interface Timing Specifications for EEPROM.......................................................... 29
21 Thermal Resistance Values........................................................................................33
22 PCIe Data Signals .................................................................................................... 33
23 PCI Express Miscellaneous Signals..............................................................................34
24 Non-Volatile Memory Interface Signals........................................................................ 34
25 Reset and Powe r-down Si gn als ............ ................... ........... ............ ........... ................. 34
26 SMBus Signals......................................................................................................... 34
27 LED Signals........................ ................... ........... ........... ................... ............ ........... .. 34
28 Other Signals .......................................................................................................... 34
29 Analog and Crystal Sig nal s ... ... ............ ................... ........... ............ ........... ................. 35
30 82573E/V MAC Test Sig nal s..... .... ............ ........... ........... ............ ................... ........... .. 35
31 82573L MAC Te st Signal s. ........... ............ ........... ........... ............ ................... ........... .. 35
32 PHY Test Interface Signals ........................................................................................ 35
33 82573E/V Other Test Signals.....................................................................................36
34 Power Support Signals.............................................................................................. 36
35 Power Signals.......................................................................................................... 36
36 Ground Sign als... ............ ................... ........... ............ ........... ................... ........... ...... 37
37 82573E/V No Con ne ct Sig nal s.. .... ................... ............ ........... ........... ................... ...... 37
38 82573 L No Conne ct Sig nals..... .... ................... ............ ........... ................... ........... ...... 37
82573—Datasheet
6
Revision History
Date Revision Description
Jan 2007 2.5 Updated the PHY_REF signal description in Section 2.6.
Oct 2006 2.4
Added do cu me nt or de r nu mb er.
Corrected the AUX_PWR pin (C6) description for the 82573E/V.
Updated Table 18 “Crystal Specifications ”.
Updated the visual pin assignments for the 82573L.
Major edit all sections.
August 2006 2.3 Chapter 1, Introduction, corrected note.
3.5.1, Removed line item
3.5.2, Corrected title Heading
June 2006 2.2 Rev ise d Section 3.3, ’PC Ie Mi sce ll an e ou s S ign a ls" , updated Intel logo.
Feb 2006 2.1 Added Section 5.2, ’Thermal Specifications".”
Sept 2005 2.0 Integrated 82573L information into this document.
June 2005 1.5 Initial public release.
7
Datasheet—82573
1.0 Introduction
Note: Unless sp eci ficall y no ted , 825 73 re fers to th e Int el ® 82 573E, 8257 3V and 82 573 L GbE
controllers.
82573 Gb E c ontrollers are single, compact components w it h integr ated Gigabit
Ethernet Media Access Control (MAC) and Physical Layer (PHY) functions. These
devices use PCIe* architecture (Revision 1.0a). For desktop , workstation, and value
server network designs with critical space constraints, the 82573 enables a GbE
imple m entatio n in a very small ar ea .
The 8257 3 provides a st andard IEEE 802.3 Ethernet in terface for 10 00BASE -T,
100BA SE -TX, and 10BASE-T application s (8 02. 3, 802.3u , an d 802.3ab, respectively).
In addition to managing MAC and PHY Ethernet l a yer functions, the 82573 mana ges
PCIe* packet traffic across its transaction, link, and physical and logical layers.
The 82573E contains a dedicated microcontroller for manageability with an on-board
Intel® Acti ve Mana gement Technol ogy (In tel® AMT) enabling network. This enables
manageability implementations required by information technology personnel for out-
of-band management, remote troub lesh ooting and recov ery, asset management, and
non-volatile storage. Intel® AMT is the first step towards a com plete Intel® Cross-
Platform Manageability Program (Intel® CPMP), which is a business and technology
initiative to deliver consistent management capabilities, protocols, and interfaces
across all Intel platforms.
The 8257 3E and 82573V GbE contro llers ha ve an integrat ed System Manageme nt Bus
(SMBus) port enabling industry standards, such as the Alert Standard Forum (ASF) 2.0.
With SMBus, management packets can be routed to or from a management processor.
In additi on, integrated ASF 2.0 circuitry provides alerting and capabilities with
standar dized interf a c es .
The 8257 3 w ith PCIe* arch itecture i s des igned for hig h performan c e and low memory
latency. The device is optimized to connect to a system I/O Control Hub (ICH7) using
one PCIe* lane. Alternati vely, the 82573 is able to connect to a Memory Control Hub
(MCH) device with a PCIe* interface.
Wide internal data paths eliminate performance bottlenecks by efficiently handling
large address and data words. The 82573 efficiently handles packets with minimum
latency by combinin g a parallel and pipelined logic arch itecture optimized for GbE and
independent transmit and receive queues. The 82573 also includes advanced interrupt
handling features and uses efficient ring buffer descriptor data structures, with up to 64
packet descri ptors per qu eue cached on chi p. A 32-KB on-ch ip pack et buffer maintains
superior performance . In addition , using hardware acceleration, the 82573 offloads
tasks from the host (for example, TCP/UDP/IP checksum calculations and TCP
segmentation).
The 82573L features low power management. During the L1 and L2 link states, the
82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe*
reference clock can be gated.
The 8257 3 is pac k aged in a 15 mm X 15 mm, 196-B a ll Grid Arra y (BGA).
82573—Datasheet
8
1.1 Document Scope
This do cume nt co nt ains target ed data she et spe cif icat ions fo r t he 82 573 GbE con troll er,
including signal descriptions, DC and AC parameters, packaging data, and pinout
information.
1.2 Re ference Documents
Thi s ap pl ic a tion a s s um e s tha t the des i gner is a c quain ted with hi gh-sp eed design an d
board layout techniques . The following documents provide addi tional information:
• IEEE Standard 802. 3, 2000 Edition . Insti tute o f Electri cal and El ectron ics Eng ineers
(IEEE).
• PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group.
• PCI Express Card El ectromechan ical Specific atio n, Revisi on 1.0 a. PCI Special
Intere st Grou p.
• PCI Bus Power Management Int erface Speci fi c ation, Revisi on 1.1. PCI Spe c ial
Intere st Grou p.
• Intel Ethernet Con troll er Timing Device Selection Guide. In tel Cor poration.
• 82573 NVM Map an d Programming Inf ormation Gu ide. Intel Corp oration.
• 82573/8 2562 Dual Footprint Desi gn Guide. Int el Corporation .
• PCIe* Family of Gigabit Ethernet Controllers Software Developer’s Manual. Intel
Corporation.
• 82573 Family GbE Controllers Specification Update. Intel Corporation.
9
Datasheet—82573
1.3 82573 Architecture
Note: The 82573L do es not support manageability.
Figur e 1. 82573 Block Di agram
VLA
N
PCIe* Core NVM
Slave
Access
Logic
DMA Function
Descriptor Management
Control
Status
Logic
Statistics
32 KB
Packet
RAM
Manage-
ability
(82573E/
82573V only)
Transmit
Switch
Receive
Filters
MAC
PHY
82573—Datasheet
10
1.4 Product Codes for the 82573
2.0 Signal Descriptions
2.1 Sig nal Type Definitions
The signal s of the 82573 are electrically defined as follows:
Device Top Markin g Leaded/
Unleaded Product Features
82573E RC82573E Leaded
82573E with Intel® AMT includes:
• Intel® AMT
•ASF 2.0
•Advanced Pass Through (APT)
82573E PC82573E Lead Free
82573E with Intel® AMT includes:
• Intel® AMT
•ASF 2.0
•APT
82573V RC82573V Leaded 82573V Baseline includes:
•ASF 2.0
•APT
82573V PC82573V Lead Free 82573V Baseline includes:
•ASF 2.0
•APT
82573L RC82573L Leaded 82573L:
• Low-power
• No management
82573L PC82573L Lead Free 82573L:
• Low-power
• No management
Name Definition
IInput
Standard input only digital signal.
OOutput
Standard outpu t on ly digital sign al.
I/O I/O
Standard I/O digital signal.
TS Tri-state
Bi-directional three-state digital input/output signal.
OD
Open Drain
Wired-OR with other agents.
The signaling agent asserts the open drain signal, but the signal is returned to the inactive state by
a weak pul l-u p resisto r. Th e pul l-u p resisto r mi gh t re qui r e tw o or thr ee cl oc k pe r i ods to fu l ly
restore the signal to the de-asserted state.
AAnalog
PCIe, SerDes, or PHY analog signal.
PPower
Power connection, voltage reference, or other reference connection.
11
Datasheet—82573
2.2 PCIe* Data Signals
2.3 PCIe* Miscellaneous Signals
B Input Bias
PU Pull Up
This signal requires a pull-up resistor.
PD Pull Down
This signal requires a pull-down resistor.
Signal Type Name and Function
PE_CLKn
PE_CLKp A(In)
PCIe Differential Reference Clock
The reference clock is furnished by the system and has a 300 ppm frequency
tolerance. It is used as reference clock for PCIe transmit and receive circuitry
and is used by the PCIe core PLL to generate 125 MHz and 250 MHz clocks for
the PCIe* core lo gic.
PE_T0n
PE_T0p A(0ut)
PCIe* Serial Data Output
These signals connect to corresponding PERn and PERp signals on a system
mothe rboa r d or a PCIe * con n e ctor. Series AC cou pli n g cap a cit ors a re required
at the 82573 device end. The PCIe* dif ferential outputs are clo cked at 2.5 Gb/s.
PE_R0n
PE_R0p A(In)
PCIe Seria l Da t a Input
Thes e signals connect to cor resp onding PETn and PETp signa ls on a sy stem
motherboard or a PCIe* c onnector. The PCIe* differen t ial in puts are clocked at
2.5 Gb/s.
Signal Type Name and Function
PE_RST# I Reset
This sign al ind i ca te s wh e t h er or no t the PCIe * pow e r an d clock are availabl e.
PE_WAKE# OD
Wake
This signal is driven to zero when it receives a wake-up packet and either the PME
enable bit of the Power Management Control/Status Register is set to 1b or the
Advanced Po wer Ma nag ement enabled bit of the Wake Up Control Register eq ual s
1b.
AUX_
PRESENT
(AUX_PWR)1
1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT in the
82573E/V and AUX_PWR in the 82573L.
I
Auxiliary Power Present
AUX_PRESENT must be pulled up to 3.3V standby power if the 82573 is powered
from standby supplies. This signal must be pulled down if auxiliary power is not
used.
CLKREQ#
(82573L only) OD
Clock Requ est.
The Clock Request (CLKREQ#) signal is located at ball P9 of the 82573L. When it is
sampled high, this open-drain signal alerts the system that the 82573L does not
need the PCIe* differential reference clock. During normal operation, the 82573L
keeps CLKREQ# asserted (low), and the system supplies this clock to the device on
the PE_CLKp and PE_CLKn signals. The 82573L deasserts CLKREQ# (high) when it
is in an electrical idle state (L1 and L2), and the system might choose to continue
supplying the reference clock or gate it conserving platform power. The CLKREQ#
signal should be connected to the clock driver that supplies the 82573L PCIe*
clock . If oth e r dev ice s us e th e sam e CLKREQ# sign al , a pu ll-u p resistor sh ou ld be
used to ensure that no device pulls this signal low when it is powered off.
Name Definition
82573—Datasheet
12
2.4 Non-Volatile Memory Interface Signals
2.5 Miscellaneous Signals
2.5.1 Reset and Power-down Signals
Signal Type Name and Function
NVM_SI I/O
NVM Serial Data Output
The data output pin is used for input to th e non-v olatile memory device. This pin is
occasionally used as input during arbitration. This signal has an internal pull-up
resistor.
NVM_SO I NVM Serial Da t a Input
The data input pin is used for output from the non-volatile memory device to the
82573. This signal has an internal pull-up resistor.
NVM_SK O
TS NVM Serial Clock
The serial clock provides the clock rate for the memory interface.
NVM_CS# I/O NVM Chip Enable
This signal is used to enable the device. This signal has an internal pull-up resistor.
NVM_REQ O NVM Arbitration Request.
This signal is used to request use of the NVM interface.
NVM_PROT I/PU NVM Protection Ena ble.
This pin should be connected to ground to disable NVM protection; otherwise, NVM
protection is enabled. This signal has an internal pull-up resistor.
NVM_TYPE I/PU
NVM Devic e Type
If the device uses a Flash, this pin should be connected to a pull-down resistor. If
the 82573 is connected to an EEPROM, this pin can be connected to an external
pull -up r es i stor. This signal h as a n internal pull-up resistor of 30 KΩ ±50%.
NVM_SHARED# I/PU NVM Shared Enable
This pin should be connected to a pull-down resistor to enable sharing of SPI Flash
with ICH. This signal has an internal pull-up resistor.
Signal Type Name and Function
LAN_PWR_
GOOD I
LAN Power Good
This signal indicates that stable power is availabl e to the 82573. When the signal is
low, LAN_PWR_GOOD acts as a master reset of the entire device. LAN_PWR_GOOD
should be connected to a power supervisor driven from auxiliary power. The signal
should go active approximately 80 ms after all power rails are within their
operating ranges.
A PCIe* reset must only occur after LAN Power Good is active.
DEVICE_OFF# I Device Off
This asynchronously disables the 82573, including voltage regulator control
outputs if selected in external control.
13
Datasheet—82573
2.5.2 System Management Bus (SMBus) Signals1
Note: The si gnals list ed in the followin g table sh ould not be conn ected whe n using an 82573L.
Refer to the 82573/ 82562 Du al Footpr int Desig n G uide reference schematics for more
information.
2.5.3 LED Signals
2.5.4 Other Signals
1. The 82573L does not suppo r t the Sys tem Manag ement Bus (SMBus).
Signal Type Name and Function
SMB_CLK I/O SMBus Clock
The SMBus Clock signal is an open drain signal for the serial SMBus interface.
SMB_DAT I/O SMBus Data
The SMB Data signal is an open drain signal for the serial SMBus interface.
SMB_ALRT#/
ASF_PWR_
GOOD I/O SMBus Alert/PC I Power Good
The SMBus Alert signal is an open drain signal for serial SMBus interface. In ASF
mode, this signal acts as the PCI Power Good input signal.
Signal Type Name and Function
LED0# O LED0
This pin provides a signal for programmable LED indication.
LED1# O LED1
This pin provides a signal for programmable LED indication.
LED2# O LED2
This pin provides a signal for programmable LED indication.
Signal Type Name and Function
THERMn
THERMp OThermal Test Pins
These pins are used for thermal testing. They can be connected to test p oints.
FUSEV P Fuse Supply
This sh ou ld be con n e ct e d to 2.5 V fo r n or m a l operat ion.
82573—Datasheet
14
2.6 PHY Analog and Crystal Signals
Signal Type Name and Function
MDI0n
MDI0p A
Media Dependent Interface [0]
1000BASE-T:
In MDI conf i guration, MDIp0/MDIn0 co r r espon ds to BI_DA+ /-, and in MDI-X
configuration, MDIp0/MDIn0 corresponds to BI_DB+/-.
100BASE-TX:
In MDI conf i guration, MDIp0/MD In0 i s us ed for the tr a nsmit pair, and in MDI-X
configuration, MDIp 0/MDIn0 is used for the receive p a ir.
10BASE-T:
In MDI conf i guration, MDIp0/MD In0 i s us ed for the tr a nsmit pair, and in MDI-X
configuration, MDIp 0/MDIn0 is used for the receive p a ir.
MDI1n
MDI1p A
Media Dependent Interface [1]
1000BASE-T:
In MDI conf igur a t i on, M D Ip1/MD In1 corresponds t o BI_DB+/-, and in MDI -X
configuration, MDIp1/MDIn1 corresponds to BI_DA+/-.
100BASE-TX:
In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI- X
configuration, MDIp1/MDI n1 is used for the trans mit pair.
10BASE-T:
In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI- X
configuration, MDIp1/MDI n1 is used for the trans mit pair.
MDI2n
MDI2p A
Media Dependent Interface [2]
1000BASE-T:
In MDI configuration, MDIp2/MDIn2 co rr e spon ds to BI_DC+/-, an d in MDI -X
configuration, MDIp2/MDIn2 corresponds to BI_DD+/-.
100BASE-TX:
Unused.
10BASE-T:
Unused.
MDI3n
MDI3p A
Media Dependent Interface [3]
1000BASE-T:
In MDI conf i guration, MDIp3/MDIn3 co rr espon ds to BI_DD+ /-, and in MDI-X
configuration, MDIp3/MDIn3 corresponds to BI_DC+/-.
100BASE-TX:
Unused.
10BASE-T:
Unused.
PHY_REF A Reference Input
This signal is used as the analog reference input for the PHY. It should be
connected to a pull-down, 4.99 K Ω, 1% resisto r.
XTAL1 I
Crystal One
The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel
resonant crystal with a f requency toler ance of 30 ppm. The ot her end of the crystal
should be co n n ected to XTAL2.
XTAL2 O Crystal Two
Crystal Two is the output of an internal os cill ator c ircu it us ed to drive a c rystal into
oscillation.
15
Datasheet—82573
2.7 T est Signals
2.7.1 MAC Test Signals
2.7.2 PHY Test Signals
2.7.3 Other Test Signals
Signal Type Name and Function
TEST_EN I F actory Test Pin
A 1 KΩ pull-down resistor sh ould be attac hed to gr oun d fr om this pi n for norma l
operation.
ALT_CLK125 NC Alternate 125 MHz Clock
This sign al sh oul d n ot b e co n nect e d. Thi s sign a l has an intern a l pull-up resis t or.
JTAG_TCK I JTAG Test Acce ss Port Clock
This signal has an internal pull-down resistor.
JTAG_TDI I JTAG Test Acce ss Port Test Da ta In
This signal has an internal pull-up resistor.
JTAG_TD O O/OD JTAG Test Acce ss Port Test Da ta Out
JTAG_TMS I JTAG Te st A cce ss Port Mode Select
This signal has an internal pull-up resistor.
CLK_VIEW NC Clock Vi ew
The Clock View signal is an output for the clock signals required for IEEE testing.
This signal has an internal pull-up resistor.
TEST[16:0] for
the 82573E/V
TEST[10:0] for
the 82573L
Rsvd
Test Pin[16:0]
These test pins are for the 82573E/V only. These signals have internal pull-up
resistor. For normal operation, these p i ns shou ld be left unconnect ed .
Test Pin[10:0]
These test pins are for the 82573L only. These signals have internal pull-up
resistor. For normal operation, these p i ns shou ld be left unconnect ed .
Signal Type Name and Function
PHY_HSDACn
PHY_HSDACp
(82573E/V)
PHY_TESTn
PHY_TESTp
(82573L only)1
1. These signals are used in all three devices and have the same functionality but are de noted as PHY_HSDACn
and PHY_HSDACp in the 82573E/V and PHY_TESTn and PHY_TESTp in the 82573L.
A(Out) PHY Differential Test Port
These signals are use d fo r fac t ory test purposes only.
PHY_TSTPT PHY Test Port
This signal is used for factory test purposes only. This pin must be left
unconnected for normal operation.
Signal Type Name and Function
SDP[3:0] NC These signals are use d for factory test purpos es only and have internal pull - up
resistors.
82573—Datasheet
16
2.8 Power Signals
2.8.1 Power Support Signals
2.8.2 Digital and Analog Power Supply Signals
2.9 Grounds and No Connects
Signal Type Name and Function
CTRL_25 P
2.5 V Co ntrol
This is the voltage control signal for external 2.5V. It is only active when the
EN25REG signal is low (disabled). When external 2.5V and 1.2V supplies are used,
CTRL_25 can be left floating or can be connected to ground through a 3.3 KΩ
resistor.
CTRL_12 P
1.2 V Co ntrol
This is the voltage control signal for external 1.2V. When external 2.5V and 1.2V
supplies are used, CTRL_12 can be left floating or can be connected to ground
through a 3.3 KΩ resistor.
EN25REG I/PU
Enable 2.5V Regulator
When this signal is high, the internal 2.5V regulator is enabled. When it is low , the
internal 2.5V regulator is disables and the CTRL_25 signal is active. This signal
should be pulled up to the 3.3V power rail.
Signal Type Name and Function
VCC33 P 3.3V Power Supply
This signal is used for I/O circuits.
VCC25 P 2.5V Analog Power Supply
These signals are us ed for PHY analog, PHY I/O, PCIe* analog and p hase lo ck loop
circuits. All 2.5V pins should be connected to a single power supply.
VCC12 P 1.2V Digital Power Supply
These signals are used for core d i g it al , P H Y digital, PCIe* digital and clock circuits.
All 1.2V pins should be connected to a single power supply.
IREG25_IN
(82573E/V)
VCC3.3_REG25
(82573L only)1
1. This signal is used in all three devices and has the same functionality but is denoted as IREG25_IN for the
82573E/V and VCC3.3_REG25 for the 82573L.
PIREG25_IN
3.3V power supply for internal 2.5V regulator. When external 2.5V and 1.2V
supplies are used, IREG25_IN should be connected to 3.3V.
VCC25_OUT P VCC25_OUT
2.5V output supply from internal power supply. When external 2.5V and 1.2V
supplies are used, VCC25_OUT can be left floating.
Signal Type Name and Function
VSS P Ground
These sign a ls con n e ct to g rou n d.
VSS is also referred to as GND.
NC
No Connect
These pins are reserved by Intel and might have factory test functions. F or normal
operation, do not connect any circuitry to these pins. Do not connect pull-up or
pull -do wn r es i st ors.
17
Datasheet—82573
3.0 Voltage, Temperature, and Timing Specifications
3.1 Absolute Maximum Ratings
3.2 Recommended Operating Conditions
3.3 Power Supply Connections
There are th ree options in providing power to the 82573:
• Con necting the 82573 to three external power supplies with nominal v oltages of
3.3V, 2.5V, and 1.2V. This is c overed in Section 3.3.1.
• Powering the 82573 with only an external 3.3V supply and using internal power
regulators from the 82573 combined with external PNP transistors to supply the
2.5V an d 1.2V level s . Th i s is cover e d in Section 3.3.3.
• Using the 2.5V in ternal (on-di e) regulator co mbined with an external PNP transis tor
to supply the 1.2V level. This is covered in Section 3.3.3.
Tabl e 1. Absol ute Maximum Ratin gs1
1. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings
in this table are exceeded for an indefinite duration. These values should not be used as the limits for normal
device operations. This specification is not guaranteed by de sign or sim ulatio ns.
Symbol Parameter Min Max Unit
Tstg Storage temperature -40 125 °C
VCC (3.3) DC supply voltage on 3.3V pins
with respect to VSS -0.3 6.6 V
VCC (2.5) DC supply voltage on 2.5V pins
with respect to VSS2
2. During normal device power up and power down, the 2.5V and 1.2V supplies must not ramp before the 3.3V.
-0.3 5.0 V
VCC (1.2) DC supply voltage on 1.2V pins
with respect to VSSb-0.3 2.4 V
Vin Input voltage (digital inputs) -1.0 VCC (3.3) + 0.3
(less than 6.6 V) V
AVin Analog input voltage (digital
inputs) -1.0 VCC (2.5) + 0.3
(less than 5.0 V) V
RPUD Pull-up/pull-down Resistor Value 15 50 KΩ
Table 2. Recommended Opera t ing Con d itions
Symbol Parameter Condition Min Typical Max Units
TOP
Operating Temperature with
external regulators 070°C
Operating temperature with
on-die 2.5V regulator 055°C
VPERIF Periphery Voltage Range 3.3 V ± 3% 3.0 3.3 3.6 V
VDCore Digital V o ltage Range 1.2 V ± 5% 1.14 1.2 1.26 V
VAAnalo g VDD Rang e 2.5 V ± 5% 2.375 2.5 2.625 V
82573—Datasheet
18
3.3.1 External LVR Power Delivery
The fo llow ing po wer su pp ly req uir ement s app ly t o desi gns w her e th e 8 2573 is s upp li ed
by external voltage regulators . These systems do not u s e the internal regulator logic
built into the 82573 as described in Section 3.3.3.
Table 3. 3.3V External Supply Voltage Ramp and Sequencing Recommendations
Parameter Description Min Max Unit
Rise Time Rise time from 10% to 90% 5 1001ms
Monotonicity Voltage dip allowed in ramp 300 mV
Slope R amp rate at any time between 10% to 90%
Minimu m = (0.8 * Vm in ) / (M a x im u m Ri se Tim e)
Maxim u m = (0 .8 * V max) / (Mini m u m Ri se Time) 1500 mV/ms
Operational Range Voltage range for normal operating conditions 3 3.6 V
Ripple Maximum voltage ripple at a bandwidth of 50 MHz 100 mVpk-pk
Overshoot Maximum voltage allowed2660 mV
Capacitance Minimum capacitance 25 µF
1. Good design practices achieve voltage ramps to within the regulation bands in approx imat e ly 2 0 ms or les s.
2. Excessive overshoot can affect long term reliability.
Table 4. 2.5V External Supply Voltage Ramp and Sequencing Recommendations
Parameter Description Min Max Unit
Rise Time Rise time from 10% to 90% 2.5 1001ms
Monotonicity Voltage dip allowed in ramp 200 mV
Slope R amp rate at any time between 10% to 90%
Minimu m = (0.8 * Vm in ) / (M a x im u m Ri se Tim e)
Maxim u m = (0 .8 * V max) / (Mini m u m Ri se Time) 1500 mV/ms
Operational Range Voltage range for normal operating conditions 2.375 2.625 V
Operational Range Voltage range for normal operating conditions -5 +5 %
Ripple Maximum voltage ripple at a bandwidth of 50 MHz 60 mVpk-pk
Undershoot Maximum voltage allowed will not exceed 10% of
nominal supply
Overshoot Maximum voltage allowed2480 mV
Output
Capacitance Capacitance r ang e when us ing a PNP circuit 4.7 25 µF
Input Capacitance Capacitance range when using a PNP circuit 4.7 µF
Capacitance ESR Equivalent series resistance of output capacitance310 mΩ
ICTRL Maximum output current rating with respect to
CTRL_25 20 mA
1. Good design practices achieve voltage ramps to within the regulation bands in approx imat e ly 2 0 ms or les s.
2. Excessive overshoot can affect long term reliability.
3. Tantalum capacitors must not be used.
19
Datasheet—82573
3.3.2 Power Sequencing with External Regulators
The foll owing powe r-on and po wer-off sequ ence should be applied when external power
supplies are in use. Designs must comply with the required power sequence to avoid
risk of either latch-up or forward biased internal diodes.
Generally, the 82573 power sequencin g s ho uld power up the three po wer ra ils in the
following order: 3.3V Æ 2.5V Æ 1.2 V. H owever, if this general guidel ine is n ot f ol lowe d,
there are sp ecific requireme nts that must be adhered t o. The se requirem ents are listed
in the following two su bs ecti ons.
3.3.2.1 Ext ern al LVR Powe r Up Seq uencing and Tracking
Sequencing of the external suppl ies during power up might be necessary to ensure t hat
the 82573 is not elec trically o verstressed and does not latch-up. Thes e requirements
are shown in Figure 2.
The 8257 3 c ore voltage (1 .2V) cannot exceed the 3.3V supp ly by more than 0.5 V at
any time during th e power up . Th e 82573 core voltage ( 1. 2V) cannot exceed the 2.5 V
supply by more than 0.5 V at any time during the power up. The core voltage is not
requ ir ed to be gin rampin g be fore th e 3.3V or th e 2.5V sup p ly.
The 82 573 analog v oltage (2. 5V) can not exceed the 3.3V s upply by more than 0.5 V at
any time during the power up. The analog voltage is not requi red to begin ramping
before the 3.3V supply.
Tabl e 5. 1.2 V Exte rnal Supply Voltage Ramp and Sequencing Re commendations
Parameter Description Min Max Unit
Rise Time Rise time from 10% to 90% 1.51
1. Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
ms
Monotonicity Voltage dip allowed in ramp 120 mV
Slope Ramp rate at any time between 10% to 90%
Minimu m = (0 .8 * Vmi n ) / (M a ximum Rise Time)
Maxi mum = (0.8 * Vmax ) / (M i n i mu m Ri se Time) 1500 mV/ms
Operational R ang e Voltage range for normal operating conditions 1.14 1.26 V
Operational R ang e Voltage range for normal operating conditions -5 +5 %
Ripple Maximum voltage ripple at a bandwidth of 50 MHz 60 mVpk-pk
Undershoot Maximum voltage allowed will not exceed 10% of
nominal supply
Overshoot Maximum voltage allowed2
2. Excessive overshoot can affect long term reliability.
500 mV
Output
Capacitance Capacitance range when using a PNP circuit 4.7 25 µF
Input Capacitance Capacitance range when using a PNP circuit 4.7 µF
Capacitance ESR Equivalent series resistance of output capacitance3
3. Tantalum capacitors must not be used.
10 mΩ
ICTRL Maximum output current rating with respect to
CTRL_12 20 mA
82573—Datasheet
20
• If the 1 .2V and 2. 5V ra ils pow er up bef ore 3.3V, t hey shoul d nev er exc eed the 3 .3V
supply by more than 0.3 V.
• At power down, all th ree suppli es s hould be turned off simultaneously. If the 3.3V
supply powers down f irs t, the 1.2V and 2.5V supplies must never exceed t he 3.3V
supply by more than 0.3 V.
3.3.2.2 E x ter na l LVR Power Down Sequencing
There are no spe cif ic p ower d own se quen cin g and tracking requi rements fo r the 82 573
silicon. The risk of latch-up or electrical overstress is small since the only charge storing
in decoupling capacitors is left in the system.
3.3.3 Internally Generated Power Delivery
The 82573 has tw o internal linear vol tage regulator controllers. The cont rollers use
external t ransistors to gen erate 2 of the 3 required voltages: 2.5V (nominal) and 1.2V
(nominal). These two voltages are stepped down from a 3.3V source.
Figure 2. Minimum Requirements for Power Supply Sequencing
Max Difference
≤ 0.3 V
Max Difference
≤ 0.3 V
Max Differenc e ≤ 0.3 V
Max Difference ≤ 0.3 V
1.2V (Core Supply)
2.5V
3.3V 3.3V
2.5V
1.2V (Core Supply)
Table 6. 3 . 3V Inte rnal Power Suppl y Parameters
Parameter Description Min Max Units
Rise T ime Time fr om 10% t o 9 0 % mar k 5 ms
Monotonicity Voltage dip allowed in ramp - 300 mV
Slope
Ramp rate at any given time between
10% and 90%
Min: 0.8*V(min)/Rise time (max)
Max: 0.8*V(max)/Rise time (min)
- 1500 mV/ms
Operational R ange Voltage range for normal operating
conditions 3.0 3.6 V
Ripple1
1. The peak to peak output rippled is measured at 20 MHz bandwidth within the operational range.
Maxim u m voltage rippl e (pe a k t o pe a k) - 10 0 mV
Overshoot Maximum overshoot allowed - 660 mV
Overshoot Settling
Time
Maximum overshoot allowed duration.
(At that time delta voltage should be
lower t h a n 5 mV fr om steady stat e
voltage)
-3ms
21
Datasheet—82573
3.3.4 Internal LVR Power Sequencing
All supplies should rise monotonically. Sequencing of the supplies is controlled by the
82573.
3.3.4.1 Power Up Sequencing and Tracking
During power up, the sequencing and tracking of the internally controlled supplies
(2.5V and 1.2V) are controlled by the 82573. No specific motherboard requirements
are necessary to prevent electrical overstress or latch-up.
The 8257 3 analog volt age (2. 5V) nev er exc eeds the 3. 3V supp ly at any tim e during the
power up . Thi s is beca us e the 2 .5 V suppl y is generated from th e 3.3V s upply w hen th e
internal voltage regulat or co ntrol logic is be ing use d. Figure 3 shows the internal LVR
circuit. The 2.5V supply tr ac ks the 3.3V ramp .
The 82573 c ore voltage (1 .2V) nev er exceeds the 3.3V at any time during the power
up . This is beca use the 2. 5V supply is generate d from the 3. 3V supply when the
internal voltage regulat or co ntrol logic is be ing use d. Figure 3 shows the internal LVR
circuit. The 1.2V ramp is de laye d internally to preven t it from exc eedin g the 2.5V and
3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.
The delay is approxim a ted by Tramp(3.3V)*0.25 < Tdelay(1.2V) < Tramp(3.3V)*0.75.
Tramp is defined to the r a m p r a te of the 3.3V input to the inte r na l vol ta ge regulator
circuit.
• It is recommended that the voltag e on a lower voltage rail neve r ex c eed the
voltage on a higher voltage rail during power on.
• There are n o minimum time requir ements between the v oltage r ails as long as they
power up in sequence: 3.3V → 2.5V → 1.2V.
• All 3 supplies must be stable for at least 80 ms before LAN_PWR_GOOD is
asserted. 100 ms is preferable if possible.
• A PCIe* reset must occur after LAN Power Good is active.
3.3.4.2 Inter na l LVR Pow er Dow n Sequencing
There are n o spec ific powe r down sequ encin g and t r ack ing req uireme nts for th e 8257 3
device. The risk of latch-up or electrical overstress is small because the only charge
storing in decoupling capacitors is left in the system.
Figure 3. Power Supply Sequencing
0
Voltage
1.2V
2.5V
3.3V
Minimum 80 ms Time
LAN_PWR_GOOD
82573—Datasheet
22
3.3.4.3 Internal Voltage Regulators Components for the 82573
3.3 .4.4 2.5V Internal LVR Specification
Table 7. 82573 Bill of Materials (BOM) of Components for Internal Regulato r
Description Quantity
Recommended Component
Manufacturer P art Numb er Package
PNP Transistor
For 1.2V LVR 1 Philips BCP-69-16 SOT-223
PNP Transistor
For 2.5V LVR 1 Philips BCP-69-16 SOT-223
Table 8. 2.5V Internal LVR Specification1
1. The use of tantalum capacitors is not recommended.
Parameter Value Units Comments
Minimum Maximum
Input Voltage 3.0 3.6 V
Input Voltage Slew Rate 5 ms
Input Capacitance 4.7 µF
Input Capacitance ESR 10 mΩ
Load Current 1 - A VOUT = 2.500 V
Output Voltage Tolerance -5 +5 %
Output Capacitance 4.7 µF
Output Capacitance ESR 10 mΩ
Current Consumption During Power Up 0.5 mA
Current Consumption During Power Down 0.5 mA
Maximum Undershoot < 10 % of nominal supply
Peak to Peak Output Ripple 120 mV ±60 mV at 20 MHz
bandwidth
PSRR 20 dB
External PNP hFE 100
23
Datasheet—82573
3.3.4.5 1.2V Internal LVR Specification
3.3.4.6 PNP Transistor Specification for Internal LVR
Table 9. 1.2V Internal LVR Specification1
1. The use of tantalum capacitors is not recommended.
Parameter
Value
Units Comments
Minimum Maximu
m
Input Voltage 3 .0 3.6 V
Input Voltage Slew Rate 5 ms
Input Capacitance 4.7 µF
Input Capacitance ESR 10 mΩ
Load Cur r en t 1 - A VOUT = 1.200 V
Output Voltage Tolerance -5 +5 %
Output Capacitance 4.7 µF
Output Capacitance ESR 10 mΩ
Current Consumption During Po wer Up 0.5 mA
Current Consumption During Power Down 0.5 mA
Maxi mum Unde r sh oot < 10 % o f nomina l su pply
Peak to Peak Output Ripple 120 mV ±60 mV at 20 MHz
bandwidth
PSRR 20 dB
External PNP hFE 100
Table 10. PNP Specification (Sheet 1 of 2)
Symbol Description Min Max Units
Vce,sat Collector-Emitter Saturation Voltage - 0.5 V
Ic(max) Collector Current, Maximum Sustained - 1000 mA
IbBase Current, Maximum Sustained - 10 mA
Vbe Base-Emitter on Voltage - 1 V
Tjmax Maximum Junction Temperature - 125 °C
82573—Datasheet
24
3.3.4.7 I nternal LVR Boar d Schema ti c
When using the internal voltage regulator controllers bu il t into the 82573, resisto rs
might need to be placed in series with the emitter in order to prevent the PNP
transistors from overheating. These series resistors dissipate a portion of the power
that wou ld otherwise be dissipated by th e PNP devices. Th e val ue and power rating of
the resistors must be carefully chosen to balance thermal limits against the PNP
characteristics against total current draw. The regulator must never drop below the
minimum Vce and out of the li near region.
The effective resistance of the pass resistors should equal approximately 1 Ω and have
a combined power dissipation rating of 0.5 Watts for the 82573. Figure 4 shows the
recommended implementation.
Power
Dissipation Maximum Total Power Dissipat i on - 1.35 W
hFE DC Current Gain 100 - -
fTCurrent Gain Product Bandwidth 10 - MHz
Table 10. PNP Specification (Sheet 2 of 2)
Symbol Description Min Max Units
25
Datasheet—82573
3.4 DC an d AC Specifications
Figur e 4. 82573 2.5V and 1.2V L VR Schematic
Table 11. 82573E and 82573V Maximum Measured External Power Characteristics1
1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.
System
State Link State 82573E Power (mW)
with Intel® AMT 8257 3 V Pow er ( mW)
without Intel® AMT
S0 1000 Mbps Active
(Maximum Power) 1548 1426
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1.2V Voltage Regulator
2.5V Voltage Regulator
regulator is used.
82573—Datasheet
26
Table 12. 82573E and 82573V Typical Measured External Power Characteristics1
1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.
System
State Link State 3.3V
Current
(mA)
2.5V
Current
(mA)
1.2V
Current
(mA)
82573E/V
Power
(mW)2 3
2. For 10/100 Mb/s non-stress mode with Intel® AMT, add 12 mW to this number (for example,
using IDE-R functionality) .
3. For 10/100 Mb/s stress mode active Intel® AMT, add 120 mW to this number (for example, using
IDE-R functionality).
S0
1000 Mb/s:
Intel® AMT
(82573E only) 12 297 551 1443.3
1000 Mb/s Active 12 297 490 1370.1
1000 Mb/s Idle 12 276 380 1185.6
100 Mb/s Active 11 130 144.5 534.7
100 Mb/s Idle 11 107 101 425
10 Mb/s Active 7 167 125.5 591.2
10 Mb/s Idle 7 76 82 311.5
No Link (SPD) 3 40 73 197.5
Sx
100 Mb/s Idle (wake) 11 104 93.5 408.5
10 Mb/s Idle (wake) 7 72 74.5 292.5
No Link (no wake) 3 364
4. The current use is slightly higher in the device off state than in the no link state. This occurs since
a PHY reset is required in the device off state, which overrides the PHY power down.
64.5 177.3
Device Off 3 42d48.5 173.1
Table 13. 82573E and 82573V 2.5V Internal Power Regulator Numbers
System
State Link State 3.3V
Current
(mA)
2.5V
Current (mA)
(on- die 2.5V
regulator)
1.2V
Current
(mA)
82573E/V
Power
(mW)
S0
1000 Mb/s: Active with
Full Management 313 Internal 607 1760
1000 Mb/s Active 313 Internal 506 1638
1000 Mb/s Idle 294 Internal 404 1453
100 Mb/s Active 142 Internal 145 642
100 Mb/s Idle 119 Internal 101 513
10 Mb/s Active 173 Internal 126 722
10 Mb/s Idle 84 I nternal 83 376
D0 No Link (SPD) 44 Internal 73 233
Sx
D3 100 Mb/s Idle
(wake) 116 Internal 94 493
D3 10 Mb/s Idle
(wake) 80 Internal 75 354
D3 No Link (no wake) 40 Internal 64 209
Device Off 45 Internal 49 207
27
Datasheet—82573
Table 14. 82573L Maximum Measured Power Charact eristics1
1. Maximum conditions refer to fast silicon, high temperature and nominal VCC.
System
State Link Sta te 82573L (mW)
S0 1000 Mb/ s Active (Maximum Power) 1296
Table 15. 82573L Measured Powe r Characteristics
System
State Link St ate 3.3V
Current (mA) 2.5V
Current (mA) 1.2V
Current (mA) 82573L
Power (mW)
S0
1000 Mb/s Active 14.8 288.5 372.5 1217
1000 Mb/s Idle 14.8 243.2 294.0 1010
100 Mb/s Active 14.0 121.3 111.5 483
100 Mb/s Idle 14.2 78.8 58.5 314
10 Mb/s Active 10.5 169 118 504
10 Mb/s Idle 10.3 143.5 91.8 194
D0 No Link (SPD) 6.2 7.0 12.3 53
Sx
D3 100 Mb/s Idle (wake) 14.2 78.8 49.3 303
D3 10 Mb/s Idle (wake) 10.5 45.7 31.0 186
D3 No Link (no wake) 6.2 7.3 12.2 53
Table 16. D C Speci fications
Symbol Parameter Condition Min Max Unit
Vih Input High Voltage 2.0 V
Vil Input Low Voltage 0.8 V
Vhy Input Hysteresis 100 mV
Voh Outp ut High Vo ltage 2.4 V
Vol Output Low Voltage 0.4 V
Ilkg Input Leakage Current 0 < Vin < VCCP ±50 µA
Rpup/
Rpdn Internal Pull Up and Pull
Down Resist or 15 50 KΩ
Cin/out Pin Capacitance Input and bi-directional buffer 2.5 pF
Cout Output Pin Capacitance Out put only buffer 2.0 pF
82573—Datasheet
28
3.5 External Interfaces
3.5.1 Crystal
The quartz crystal is strongly recommended as a low cost and high performance choice
with the 82573 de vice. Quart z c r ystals are the mainstay of frequency control
components and are availabl e from numero us vend ors in many package type s with
va r i ous specific a tion option s .
3.5.2 External Clock Oscillator
If an extern al oscillator is used to pro vide a clock to the 82 573, the co nnectio n s hown
in the figure below must be used. The XTAL2 output signal of the 82573 must not be
connected. The XTAL1 input signal receives the output of the oscillator directly. AC
coupling is not recommended.
Table 1 7. LED DC Specifications
Symbol Parameter1
1. Outputs are inputs/outputs in test mode.
Condition Min Max Unit
Voh Output High Voltage at 12 mA 2.4 V
Vol Output Low Voltage at 12 mA 0.4 V
Ioz 3-state Output Leakage
Current Voh = VDD or VSS ±10 mV
Ios Output Short Current VDD = 3.6 V, Vo = VDD,
VDD = 3.6 V, Vo = VSS µA
Cin/out Pin Capacitance2
2. This parameter is characterized but not tested.
Input and bi-directional buffer 2.5 pF
Table 18. Crystal Specifications
Parameter Name Symbol Recommended Value Max/M in Range Condi tions
Frequency fo25.000 MHz - at 25 °C
Vibration mo de - Fundamental - -
Frequency Tolerance ∆f/fo at 25 °C ±30 ppm at 25 °C
Temperature Tolerance ∆f/fo±30 ppm -
Operating Temperature Topr 0 °C to +70 °C -
Equiva lent Series
Resistance (E S R) Rs40 Ω50 Ω (max) at 25 MHz
Load Capacitance Cload 20 pF -
Shunt Capacitance Co6 pF -
Max Drive Level DL 500 µW 1 mW -
Nominal Drive Level DL 200 µW 500 µW -
Aging f/fo±5 ppm per year ±5 ppm per year -
Board Capacitance Cs4 pF 1
1. This value can change up to 10%.
-
External Capacitors C1, C2 22 pF -
Board Resistan ce Rs0.1 Ω1 Ω-
29
Datasheet—82573
3.5.3 Non-Volatile Memory (NVM) Interface: EEPROM
Figur e 5. External Cl ock Oscillator Con ne c tivity to the 8257 3
Table 19. Specification fo r E x t ernal Clock Osc illator
Parameter Name Symbol Value Conditions
Frequency fo25.0 MHz at 25 °C
Swing Vp-p 3.3 ± 0.3 V -
Frequency Tolerance ∆f/fo±30 ppm 0 °C to +70 °C
Operating Temperature Topr -20 °C to +70 °C 0 °C to +70 °C
Aging ∆f/fo±5 ppm per year -
Table 20 . NVM Interfac e Ti mi ng Specif ic a t io n s fo r E EPR OM (Sh eet 1 of 2)
Symbol Parameter Min Typ Max Units
tSCK SCK clock
frequency 022.1MHz
tRU Input rise time 2.5 2 µs
tFI Input fall time 2.5 2 µs
tWH SCK high time1200 250 ns
tWH SCK low timea200 250 ns
tCS CS high time 250 ns
tCSS CS setup time 250 ns
tCSH CS hold time 250 ns
tSU Data-in setup
time 50 ns
tHData-in hold
time 50 ns
tVOutput Valid 0 200 ns
3.3
V
82563EB/82564EB
XTAL1
XTAL2
82573
82573—Datasheet
30
4.0 Package and Pinout Information
This section describes the 82573 physical characteristics and pin-to-signal mapping.
4.1 Package Information
The 82573 device is a lead-free 196-pin thin and F ine Pitch Ball Grid Arra y (TF-BGA)
measuring 15 mm by 15 mm. The n ominal ball pit c h is 1.0 mm.
tHO Output hold
time 0ns
tDIS Output disable
time 250 ns
tWC Wr i t e cy cle time 10 ms
1. 50% duty cycle.
Table 20. NVM Interface Timing Specifications for EEPROM (Sheet 2 of 2)
Symbol Parameter Min Typ Max Units
Figure 6. 82573 Controller TF-BGA Package Ball Pad Dimensions
0.4 mm
Solder Resist Opening
0.55 mm
Metal Diameter
Detail Area
31
Datasheet—82573
Figur e 7. 82573 Mechanical Specif ications
82573—Datasheet
32
4.2 Thermal Specifications
The case temperature (T C) is calculated us ing the eq uation:
TC = TA + P (⎝JA - ⎝JC)
Junction te m pe rature (TJ) is calcu la ted using the equa tion:
TJ = TA + P ⎝JA
The power consumption (P) is calculated by using the typical ICC and nominal VCC
where TA represents the ambient temperature. T he t hermal resis tan c es are listed in
Table 21.
33
Datasheet—82573
Thermal resistances are determined empirically with test devices mounted on standard
thermal test boards. Real system designs may hav e di fferent char act eristics due to
board thickness, arra ngement of gro un d planes, and proximity of other components.
The case temperature measure m ents shou ld be used to ass ure that the 82573 is
oper ating u nder recomm ended conditions . The use of a heat sink device is not
required.
4.3 Pinout Information
4.3.1 PCIe Bus Interface Signals
Ta ble 21. Thermal Resistance Values
Symbol Parameter Value at Specified Airflow (m/s) Units
0123
TJ Maximum junction temperature 127.1 122.1 119.3 117.5 C
⎝JA Thermal resistance, junction-to-
ambient 26.0 23.7 22.4 21.6 C/Watt
⎝JC Thermal resistance, junction-to-
case 6.1 6.1 6.1 6.1 C/Watt
Table 22. PCIe Data Signals
Signal Pin Signal Pin Signal Pin
PE_CLKn G2 PE_T0n C1 PE_R0n F1
PE_CLKp G1 PE_T0p D1 PE_R0p F2
82573—Datasheet
34
4.3.2 Non-Volatile Memory Interface Signals
4.3.3 Miscellaneous Signals
Table 23. PCI Express Mis cellaneou s Signals
Signal Pin Signal Pin Signal Pin
PE_RST# P7 PE_WAKE# P10
AUX_PRESENT
(82573E/V) /
AUX_PWR
(82573L)1
1. This signal is used in all thre e de vices and has the same f unctionality but is denote d as AUX_PRESENT
in the 82573E/V or AUX_PWR in the 82573L.
C6
CLKREQ# (82573L
only) P9
Table 24. Non-Volatile Memory Interface Signals
Signal Pin Signal Pin Signal Pin
NVM_SI A9 NVM_CS# B10 NVM_TYPE A6
NVM_SO B9 NVM_REQ B4 NVM_SHARED# D3
NVM_SK C9 NVM_PROT A5
Table 25. Reset and Power-down Signals
Signal Pin Signal Pin Signal Pin
LAN_PWR_GOOD P5 DEVICE_OFF# L7
Table 26. SMBus Signals
Signal Pin Signal Pin Signal Pin
SMB_CLK P11 SMB_DAT M11 SMB_ALRT#/
ASF_PWR_
GOOD N11
Table 27. LED Signals
Signal Pin Signal Pin Signal Pin
LED0# B11 LED1# C11 LED2# A12
Table 28. Other Signals
Signal Pin Signal Pin Signal Pin
THERMn L2 THERMp L3
35
Datasheet—82573
4.3.4 PHY Signals
4.3.5 Test Signals
Tabl e 29. Analog and Crystal Signals
Signal Pin Signal Pin Signal Pin
MDI0n C14 MDI2n F14 PHY_REF D12
MDI0p C13 MDI2p F13 XTAL1 K14
MDI1n E14 MDI3n H14 XTAL2 J14
MDI1p E13 MDI3p H13
Table 30. 82573E/V MAC Test Signals1
1. These test signals do not apply to the 82573L.
Signal Pin Signal Pin Signal Pin
TEST_EN A13 TEST1 H2 TEST9 M3
ALT_CLK125 N10 TESTPT2 H3 TEST10 N2
JTAG_TCK N5 TESTPT3 J1 TEST11 P1
JTAG_TDI P4 TESTPT4 J2 TEST12 N3
JTAG_TDO P6 TEST5 J3 TEST13 M8
JTAG_TMS N4 TEST6 K1 TEST14
(82573E/V only) P9
CLK_VIEW L14 TEST7 L1 TEST15
(82573E/V only) E3
TEST0 H1 TEST8 M1 TEST16
(82573E/V only) A14
Table 31. 82573L MAC Test Signals1
1. These test signals do not apply to the 82573E or 82573V devices.
Signal Pin Signal Pin Signal Pin
TEST_EN A13 CLK_VIEW L14 TEST5 J3
ALT_CLK125 N10 TEST0 H1 TEST6 K1
JTAG_TCK N5 TEST1 H2 TEST7 L1
JTAG_TDI P4 TESTPT2 H3 TEST8 M1
JTAG_TDO P6 TESTPT3 J1 TEST9 M3
JTAG_TMS N4 TESTPT4 J2
Ta ble 32. PHY Test In terface Signal s
Signal Pin Signal Pin Signal Pin
PHY_HSDACn B13 PHY_HSDACp B12 PHY_TSTPT B14
82573—Datasheet
36
4.3.6 Power Supply Signals
Table 33. 82573E/V Other Test Signals1
1. These test signals do not apply to the 82573L.
Signal Pin Signal Pin Signal Pin
SDP[0] A8 SDP[1] B8 SDP[2] C8
SDP[3] C7
Table 34. Power Support Sign al s
Signal Pin Signal Pin Signal Pin
CTRL_25 A4 CTRL_12 P3 EN25REG B5
Table 35. Power Signals
Signal Pin Signal Pin Signal Pin
VCC33 A7 VCC25 J12 VCC12 J6
VCC33 D9 VCC25 K13 VCC12 J7
VCC33 F3 VCC25 L12 VCC12 J8
VCC33 J4 VCC25 M4 VCC12 J9
VCC33 M10 VCC25 N7 VCC12 J10
VCC33 N6 VCC25_OUT B1 VCC12 J11
VCC33 N8 VCC25_OUT B2 VCC12 K3
VCC33 P2 VCC12 A10 VCC12 K4
VCC33 P12 VCC12 C4 VCC12 K5
IREG25_IN A2 VCC12 C5 VCC12 K6
IREG25_IN A3 VCC12 F12 VCC12 K7
FUSEV M2 VCC12 G6 VCC12 K8
VCC25 A11 VCC12 G12 VCC12 K9
VCC25 B6 VCC12 G13 VCC12 K10
VCC25 G3 VCC12 H6 VCC12 K11
VCC25 G5 VCC12 H7 VCC12 L5
VCC25 H4 VCC12 H8 VCC12 L9
VCC25 H5 VCC12 H11 VCC12 L10
VCC25 J5 VCC12 H12
37
Datasheet—82573
Table 36. G round Signals
Signal Pin Signal Pin Signal Pin
VSS A1 VSS E5 VSS G4
VSS B3 VSS E6 VSS G7
VSS C2 VSS E7 VSS G8
VSS C10 VSS E8 VSS G9
VSS C12 VSS E9 VSS G10
VSS D2 VSS E10 VSS G11
VSS D4 VSS F4 VSS G14
VSS D5 VSS F5 VSS H9
VSS D6 VSS F6 VSS H10
VSS D7 VSS F7 VSS K2
VSS D8 VSS F8 VSS N1
VSS D13 VSS F9 VSS N12
VSS E2 VSS F10 VSS P8
VSS E4 VSS F11
Tabl e 37. 82573E/V No Con nect Signals1
1. These test signals do not apply to the 82573L.
Signal Pin Signal Pin Signal Pin
NC B7 NC K12 NC M9
NC C3 NC L4 NC M12
NCD10NCL6NCM13
NCD11NCL8NCM14
NC D14 NC L11 NC N9
NC E1 NC L13 NC N13
NCE11NCM5NCN14
NCE12NCM6NCP13
NCJ13NCM7NCP14
Tabl e 38. 82573L No Conn ect Signals 1 (Sheet 1 of 2)
Signal Pin Signal Pin Signal Pin
NC A8 NC E12 NC M9
NC A14 NC J13 NC M12
NC B7 NC K12 NC M13
NC B8 NC L4 NC M14
NC C3 NC L6 NC N2
NC C7 NC L8 NC N3
NC C8 NC L11 NC N9
NC D10 NC L13 NC N13
82573—Datasheet
38
4.4 Visual Pin Assignment s
Figure 8. 82573E and 82573V Gigabit Ethernet Controller Pinout
NCD11NCM5NCN14
NCD14NCM6NCP1
NC E1 NC M7 NC P13
NC E3 NC M8 NC P14
NC E11
1. These test signals do not apply to the 82573E or 82573V devices.
Table 38. 82573L No Connect Signal s1 (Sheet 2 of 2)
Signal Pin Signal Pin Signal Pin
VCC25_
OUT PE_T0n PE_TR0p NC PE_R0n PE_CLKp TEST0 TEST3 TEST11VSS
TEST8TEST7TEST6VSS
VCC25_
OUT VSS VSS VSS PE_R0p PE_CLKn TEST1 TEST4 VCC33TEST10FUSEVTHERMnVSS
IREG25_IN
VSS NC NVM_
SHARED TEST15 VCC33 VCC25 TEST2 TEST5 CTRL_12
TEST12TEST9
THERMp
VCC12
IREG25_IN
NVM_REQ VCC12 VSS VSS VSS VSS VCC25 VCC33 JTAG_TDI
JTAG_TMS
VCC25
NCVCC12CTRL_25
EN25REG VCC12 VSS VSS VSS VCC25 VCC25 VCC25 LAN_PWR_
GOOD
JTAG_
TCK
NCVCC12VCC12
NVM_
PROT
VCC25 AUX_
PRESENT VSS VSS VSS VCC12 VCC12 VCC12 JTAG_TDO
VCC33NCNCVCC12
NVM_
TYPE
NC SDP[3] VSS VSS VSS VSS VCC12 VCC12 PE_RST#VCC25NC
DEVICE_
OFF#
VCC12VCC33
SDP[1] SDP[2] VSS VSS VSS VSS VCC12 VCC12 VSSVCC33TEST13NCVCC12SDP[0]
NVM_SO VCC33 VSS VSS VSS VSS VCC12 TEST14NCNCVCC12VCC12
NVM_SI
VSS NC VSS VSS VSS VSS VCC12 ALT_CLK125
VCC33
VCC12VCC12
LED0# LED1# NC NC VSS VSS VCC12 VCC12 SMB_CLK
SMB_ALRT#/
ASF_PWR_
GOOD
SMB_DATNCVCC12VCC25
PHY_
HSDACp VSS PHY_REF NC VCC12 VCC12 VCC12 VCC25 VCC33VSSNCVCC25NCLED2#
MDI0p VSS MDI1p MDI2p VCC12 MDI3p NC NCNCNCNCVCC25TEST_EN
MDI0n NC MDI1n MDI2n VSS MDI3n XTAL2 NC
NC
NC
CLK_VIEW
XTAL1TEST16
ABCDE FGHJ KLMNP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC12 NVM_CS#
NVM_SK
PE_WAKE#
PHY_
HSDACn
PHY_
TSTPT
39
Datasheet—82573
Figur e 9. 82573L Gigabit Ethernet Control ler Pinout
VCC25_
OUT PE_T0n PE_TR0p NC PE_R0n PE_CLKp TEST0 TEST3 NCVSSTEST8TEST7TEST6VSS
VCC25_
OUT VSS VSS VSS PE_R0p PE_CLKn TEST1 TEST4 VCC33TEST10FUSEVTHERMnVSS
VCC3.3_
REG25
VSS NC NVM_
SHARED NC VCC33 VCC25 TEST2 TEST5 CTRL_12
NCTEST9
THERMp
VCC12
VCC3.3_
REG25
NVM_REQ VCC12 VSS VSS VSS VSS VCC25 VCC33 JTAG_TDI
JTAG_TMS
VCC25
NCVCC12CTRL_25
EN25REG VCC12 VSS VSS VSS VCC25 VCC25 VCC25 LAN_PWR_
GOOD
JTAG_
TCK
NCVCC12VCC12
NVM_
PROT
VCC25 AUX_PWR VSS VSS VSS VCC12 VCC12 VCC12 JTAG_TDO
VCC33NCNCVCC12
NVM_
TYPE
NC NC VSS VSS VSS VSS VCC12 VCC12 PE_RST#VCC25NC
DEVICE_
OFF#
VCC12VCC33
NC NC VSS VSS VSS VSS VCC12 VCC12 VSSVCC33NCNCVCC12NC
NVM_SO VCC33 VSS VSS VSS VSS VCC12 CLK_REQ#NCNCVCC12VCC12
NVM_SI
VSS NC VSS VSS VSS VSS VCC12 ALT_CLK125
VCC33
VCC12VCC12
LED0# LED1# NC NC VSS VSS VCC12 VCC12 RSVDRSVDRSVDNCVCC12VCC25
PHY_
HSDACp VSS PHY_REF NC VCC12 VCC12 VCC12 VCC25 VCC33VSSNCVCC25NCLED2#
MDI0p VSS MDI1p MDI2p VCC12 MDI3p NC NCNCNCNCVCC25TEST_EN
MDI0n NC MDI1n MDI2n VSS MDI3n XTAL2 NC
NC
NC
CLK_VIEW
XTAL1NC
ABCDE FGHJ KLMNP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC12 NVM_CS#
NVM_SK
PE_WAKE#
PHY_
HSDACn
PHY_
TSTPT
