Cover 88EM8040/88EM8041 Power Factor Correction Controller for Flyback Topology Datasheet Customer Use Only Doc. No. MV-S104983-01, Rev. A October 5, 2009 Marvell. Moving Forward Faster Document Classification: Proprietary 88EM8040/88EM8041 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: Preliminary Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 1999-2009. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending--Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S104983-01 Rev. A Page 2 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary 88EM8040/88EM8041 Power Factor Correction Controller for Flyback Topology Datasheet PRODUCT OVERVIEW The Marvell(R) 88EM8040/88EM8041 device is a high performance Power Factor Correction (PFC) Controller for flyback applications. Both devices work at fixed frequencies, 88EM8040 at 60kHz while 88EM8041 at 120kHz. It can be used in a wide variety of universal input PFC flyback converters with an output power range of up to 150W without using any external driver. General Features Patented DSP control with adaptive loop coefficient Continuous Conduction Mode (CCM) operation Average current mode control Adaptive control loop achieves high power factor for a wide range of voltage and load conditions Adaptive over current protection for universal voltage Fixed frequency of operation High power factor and low harmonic distortion for a wide range of load conditions Up to 2A driver capability Minimal external components required Under voltage lockout (UVLO) Over voltage protection (OVP) Thermal shutdown Input line frequency range from 45Hz to 65Hz Marvell advanced mixed signal technology ensures the lowest Total Harmonic Distortion (THD) in the industry. The IC operates under average Continuous Conduction Mode (CCM). The 88EM8040/88EM8041 PFC controller improves the steady state and transient performance through Marvell's innovative Digital Signal Processing (DSP) solution. The proprietary adaptive over-current protection has the ability to ensure almost constant power constraint and provides safety provisions including open loop and over voltage protection protocols. The internal voltage loop compensation and current loop control guarantees system stability and thus reduces the external component count and costs. Applications Universal input PFC flyback converters AC/DC adaptors and battery charger The 8-pin SOIC package further facilitates the application design process, saving board space. The resultant simple system design and minimum cost makes 88EM8040/88EM8041 the ideal choice for any flyback application with PFC. Figure 1: PFC Flyback Circuit Diagram DR2 V DCin Bridge Retifier diode PFC C in Np Csn Rsn R gate R sen Load C O2 Dsn AC IN Vout N S2 Drain Q1 Rcs Ra Rb Rc OCP SW SGND Ccs 88EM8040/ 8041 ISNS VIN R S1 PGND R S4 C S2 VDD FB R S2 C S1 R S5 Opto-Coupler CVDD R f1 Copyright (c) 2009 Marvell October 5, 2009, Preliminary Vref R S3 Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 3 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 4 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Table of Contents Table of Contents Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configurations ...........................................................................................................................................11 1.2 Pin Descriptions ..............................................................................................................................................11 2 Electrical Specifications ............................................................................................................. 13 2.1 Absolute Maximum Ratings ...........................................................................................................................13 2.2 Recommended Operating Conditions .............................................................................................................14 2.3 Electrical Characteristics ................................................................................................................................15 3 Functional Description................................................................................................................ 19 3.1 Overview .........................................................................................................................................................19 3.2 Signal Process and Functions.........................................................................................................................20 4 Functional Characteristics ......................................................................................................... 21 4.1 VDD Characteristics ........................................................................................................................................21 4.2 VFB Characteristics for Over Voltage Protection .............................................................................................23 4.3 Switching Frequency Characteristics ..............................................................................................................24 4.4 Over Current Threshold Characteristics..........................................................................................................25 5 Design and Applications Information ........................................................................................ 27 5.1 Input Voltage Resistor Divider on VIN Pin.......................................................................................................28 5.2 Isolated Voltage Loop and Output Voltage Feedback on FB Pin ....................................................................30 5.2.1 Resistor Divider Design for Output Voltage ......................................................................................31 5.2.2 Compensation Network Design ........................................................................................................31 5.2.3 RS2 and Rf1 Design .........................................................................................................................33 5.3 Current Sensing and Over Current Protection ................................................................................................34 5.3.1 Current Sensing Through ISNS Pin ..................................................................................................34 5.3.2 Average Current Signal and Over Power Limitation .........................................................................35 5.3.3 Cycle by Cycle Current Protection through OCP Pin........................................................................36 5.3.4 Peak Current and Average Current Relationship .............................................................................38 5.4 SW Pin to MOSFET Gate ...............................................................................................................................39 5.5 VDD, Signal Ground (SGND) and Power Ground (PGND) .............................................................................39 5.6 90W/20V Signal Stage PFC Adaptor Schematic and Bill of Materials (BOM).................................................41 Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 5 88EM8040/88EM8041 Datasheet 6 Mechanical Drawings .................................................................................................................. 43 6.1 Mechanical Drawings ......................................................................................................................................43 7 Part Order Numbering/Package Marking .................................................................................. 45 7.1 Part Order Numbering ..................................................................................................................................45 7.2 Package Markings...........................................................................................................................................46 A Revision History .......................................................................................................................... 47 Doc. No. MV-S104983-01 Rev. A Page 6 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary List of Figures List of Figures Figure 1: 1 PFC Flyback Circuit Diagram ............................................................................................................3 Signal Description ........................................................................................................................... 11 Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11 2 Electrical Specifications ................................................................................................................. 13 3 Functional Description.................................................................................................................... 19 Figure 3: 4 5 Top Level Block Diagram..................................................................................................................19 Functional Characteristics.............................................................................................................. 21 Figure 4: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21 Figure 5a: IDD vs. VDD (VDD_ON) ........................................................................................................................21 Figure 5b: IDD vs. VDD (VDD_ON)........................................................................................................................21 Figure 6a: IDD Operation (IDD_OP) vs. Temperature ........................................................................................22 Figure 6b: IDD Operation (IDD_OP) vs. Temperature ........................................................................................22 Figure 7: VDD On/Off vs. Temperature ...........................................................................................................22 Figure 8: IDD vs. VFB (OVP) .............................................................................................................................23 Figure 9: VFB_OVP vs. Temperature ..............................................................................................................23 Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................23 Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................23 Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24 Figure 13: Switching Frequency vs. Temperature .............................................................................................24 Figure 14: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................25 Figure 15: Over Current (VIOVER) vs. Temperature .........................................................................................25 Figure 16: VIOVER_CYC_ON/OFF vs. Temperature ........................................................................................26 Design and Applications Information ............................................................................................ 27 Figure 17: Internal Block for Zero-cross Detection, Brown-out Protection .........................................................28 Figure 18: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29 Figure 19: Input Voltage Resistor Divider Layout Guidelines ............................................................................30 Figure 20: Secondary Compensation Network with Opt-coupler .......................................................................30 Figure 21: Bode Plot of Compensation Network at Secondary Side .................................................................32 Figure 22: Bias Current for Offset Voltage on FB Pin ........................................................................................33 Figure 23: Current Sensing Circuit.....................................................................................................................34 Figure 24: Current Sensing and Cycle by Cycle Over Current Protection Circuit ..............................................36 Figure 25: Current Sensing and Cycle by Cycle Over Current Protection Waveforms ......................................36 Figure 26: SW Pin Layout Guidelines ................................................................................................................39 Figure 27: VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................40 Figure 28: 90W/20V Single Stage PFC Adaptor Schematic ..............................................................................41 Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 7 88EM8040/88EM8041 Datasheet 6 Mechanical Drawings ...................................................................................................................... 43 Figure 29: 7 A 8-Lead SOIC Mechanical Drawing ...................................................................................................43 Part Order Numbering/Package Marking....................................................................................... 45 Figure 30: 88EM8040/88EM8041 Sample Ordering Part Number ....................................................................45 Figure 31: 88EM8040/88EM8041 Package Marking .........................................................................................46 Revision History ............................................................................................................................... 47 Doc. No. MV-S104983-01 Rev. A Page 8 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary List of Tables List of Tables 1 2 Signal Description ............................................................................................................................ 11 Table 1: Pin Descriptions ................................................................................................................................11 Table 2: Pin Descriptions ................................................................................................................................12 Electrical Specifications .................................................................................................................. 13 Table 3: Absolute Maximum Ratings ..............................................................................................................13 Table 4: Recommended Operating Conditions...............................................................................................14 Table 5: Electrical Characteristics ..................................................................................................................15 3 Functional Description..................................................................................................................... 19 4 Functional Characteristics............................................................................................................... 21 5 Design and Applications Information ............................................................................................. 27 Table 6: Comparison Between Average Current Mode and Critical Transition Mode Control........................27 Table 7: Current Sensing Circuit.....................................................................................................................35 Table 8: Current Sensing Resistor Selection Reference ................................................................................35 6 Mechanical Drawings ....................................................................................................................... 43 7 Part Order Numbering/Package Marking........................................................................................ 45 Table 9: A 88EM8040/88EM8041 Part Order Options .......................................................................................45 Revision History ............................................................................................................................... 47 Table 10: Revision History ................................................................................................................................47 Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 9 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 10 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Signal Description Pin Configurations 1 Signal Description 1.1 Pin Configurations Figure 2: SOIC-8 Pin Diagram (Top View) 1.2 PGND 1 8 SW SGND 2 7 VDD ISNS 3 6 OCP VIN 4 5 FB Pin Descriptions Table 1: Pin Descriptions Pi n # P in N a m e P i n Ty p e P in D e s c r i p t io n 1 PGND Ground Power Ground 2 SGND Ground Signal Ground 3 ISNS Input Current Sense 4 VIN Input Voltage Input 5 FB Input Feedback 6 OCP Input Over Voltage Current Protection 7 VDD Supply IC Supply Voltage 8 SW Output Switch Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 11 88EM8040/88EM8041 Datasheet Table 2: Pin Descriptions P in # P in N a m e Pi n F u nc t io n 1 PGND Power Ground Connected to the source of the primary MOSFET. The PCB trace from the power ground to the source of the primary MOSFET must be kept as short as possible. To avoid any switching noise interruption on signal processing, PGND and SGND remain seperate inside the IC. 2 SGND Signal Ground Must be connected to the power ground with the Kelvin sensing connection, so that SGND has dedicated trace and connections and provides noiseless environment for the signal processing. 3 ISNS Current Sense Sense resistor varies from 0.15 at 120W rated load to 0.44 for 40W rated load. Used for current shaping and for over current protection. 4 VIN Voltage Input * Connects to resistive divider at input AC line "phase" to GND. Voltage applied is a half rectified sine wave scaled down by the input resistive divider. * Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is recommended to be designed from the input AC "phase" to GND in order to reduce the standby power. Higher impedance is preferred with the right PCB design on this pin signal. * Voltage is compared with a threshold reference (VVIN_BR) to detect the zero-cross location of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is used to generate the current reference. * Brown-out protection1 function is also provided by this pin. A resistor devider with a 100:1 ratio from the highside resistor to the lowside resistor is corresponding to the "brown-out protection" input voltage as 50V (RMS). Increasing that raio will increase the "brown-out voltage". Please refer to footnote1 for further explaination. 5 FB Feedback It is connected to the emitter of the transistor on the secondary side of the opto coupler (referred to within the Appication Information section). The output voltage is scaled to 2.5V with 100% rated value. Transition from soft start to normal regulation at 87.5% rated VFB. Over voltage shutdown SW gate signal at 107% rated VFB and recover once below VFB_OVP. There is another threshold (VFB_OVP_LATCH) as 3.77V on the FB pin. When FB Voltage reaches VFB_OVP_LATCH, SW signal is shutdown and latched until another VDD power on reset. 6 OCP Over Current Protection Used to turn off the MOSFET when it is pulled as logic low 7 VDD IC Supply Voltage Nominal voltage is typical 12V and the Under Voltage Lock Out (UVLO) for VDD <VDD_UVLO (Table 5). Start voltage of IC is VDD_On (Table 5) and maximum voltage is 16V (Table 5). It should be clamped by a zener for protection in the system design. 8 SW Switch PWM gate signal for the switch. Connects to the gate of external MOSFET. It is the DSP core output for ON/OFF time buffered through the internal adaptive driver. 1. Brown-out voltage is determined by Ra, Rb and Rc as shown in Figure 1. Please refer to page 29 for a further understanding. Doc. No. MV-S104983-01 Rev. A Page 12 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Sy m b o l P a r a m e t er Min Max U n i ts VDD Power Supply (Voltage to PGND=SGND) -0.3 18 V VIsns Voltage at ISNS pin -0.5 3 V VOCP Voltage at OCP pin -0.3 5.5 V VVIN Voltage at VIN pin -0.3 5.5 V VFB Voltage at FB pin -0.3 5.5 V ISW Driver Current (Instantaneous Peak) 2 A JA Thermal Resistance SOIC-8 156.5 C/W Thermal Resistance DIP-8 89.5 C/W 85 C 125 C 150 C 2 kV TA Operating Ambient Temperature Range2 TJ Maximum Junction Temperature TSTOR Storage Temperature Range VESD ESD Rating3 -40 -65 1. Exceeding the absolute maximum rating may damage the device. 2. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5k in series with 100pF. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 13 88EM8040/88EM8041 Datasheet 2.2 Table 4: Recommended Operating Conditions Recommended Operating Conditions1 Sy m b o l P a r a m e te r M in TA Operating Ambient Temperature2 TJ Junction Temperature Ty p Max U ni ts -40 85 C -20 125 C 1. This device is not guaranteed to function outside the specified operating temperature range. 2. Over the -40C to 80C operating temperature ranges are assured by design, characterization, and correlation with statistical process controls. Doc. No. MV-S104983-01 Rev. A Page 14 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C. Sy m b o l Parameter C on d it io n s M in Ty p Max Units 7.0 12 16 V VDD Supply VDD Supply Voltage VDD_ON VDD Power On Threshold VDD_UVLO VDD Power Off Threshold (UVLO) VDD_UVLO_HYS VDD_UVLO Hysteresis IDD_QST VDD Quiescent Current1 VDD = 12V IDD_OP VDD Operating Current VDD = 12V; CGate = 1nF FSW = 118kHz VIN=0 After VDD is powered up and running 11.9 V 7.0 V 4.8 5 V 95 A 5.2 mA Thermal Shutdown TSD Thermal Shutdown 150 C TSD_HYS Hysteresis for Thermal Shutdown 25 C 10.0 V Adaptive Output Gate Driver VG_HI Minimum Gate High Voltage2 VDD = 12V CGate = 1nF Sourcing 500mA VG_LO Maximum Gate Low Voltage3 VDD = 12V CGate = 1nF Sinking 500mA RDSON Gate Drive Resistance Sourcing 75mA T=25 C 2.4 Gate Drive Resistance Sinking 20mA T=25 C 2.0 ISW_PK Driver Peak Current CGate = 10 nF VDD = 12 V tR Rise Time CGate = 1 nF 35 ns CGate = 10 nF 125 ns CGate = 1 nF 35 ns CGate = 10 nF 145 ns tF DMAX Fall Time Maximum Duty Cycle 2.0 V A 97 Copyright (c) 2009 Marvell October 5, 2009, Preliminary 2.0 % Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 15 88EM8040/88EM8041 Datasheet Table 5: Electrical Characteristics (Continued) NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C. Sy m b o l Parameter DMIN Minimum Duty Cycle C on d it io n s M in Ty p Max 3.0 Units % Feedback/Overvoltage VFB_REG Normal Regulation Reference IC powered on 2.55 V VFB_OVP Over Voltage Protection Threshold At 107% of VFB_REG. 2.71 V VFB_OVP_HYS Over Voltage Protection Hysteresis VFB_OVP_LATCH Over Voltage Protection Latch 0.108 V 3.77 V Current Sensing and Current Protection4 VIOVER_TH1 Over Current Threshold Zone 15 Peak value of half-sine voltage at VIN: 1.26<VIN<1.89Vpk6 397 mV VIOVER_TH2 Over Current Threshold Zone 25 Peak value of half-sine voltage at VIN: 1.89<VIN<2.59Vpk7 329 mV VIOVER_TH3 Over Current Threshold Zone 35 Peak value of half-sine voltage at VIN: 2.59< VIN<3.43Vpk8 269 mV VIOVER_TH4 Over Current Threshold Zone 45 Peak value of half-sine voltage at VIN: 3.43<VIN<3.85Vpk9 202 mV VIOVER_CYC_ON Cycle by cycle current protection logic input (OCP pin) threshold for SW on10 1.68 V VIOVER_CYC_OFF Cycle by cycle current protection logic input (OCP pin) threshold for SW off11 1 V 88EM8040 Switching Frequency Oscillator FSW Frequency (Average Mode) kHz 88EM8041 Switching Frequency Oscillator FSW Frequency 118 kHz 1. Quiescent Current: VDD power supply current before VDD first time reaches VDD_On. 2. Considering the voltage drop on the internal driver MOSFET during current sourcing. 3. Considering the voltage drop on the internal driver MOSFET during current sinking. Doc. No. MV-S104983-01 Rev. A Page 16 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Electrical Specifications Electrical Characteristics 4. To achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four zones of input voltage levels. A margin of 50% compared to the rated current is considered for the threshold current values. 5. Threshold of negative voltage drop across Rsns due to instantaneous current 6. With input divider ratio of 1/100, these values are equivalent to 90 Vrms<Vline<135 Vrms. 7. With input divider ratio of 1/100, these values are equivalent to 135 Vrms<Vline<185 Vrms. 8. With input divider ratio of 1/100, these values are equivalent to 185 Vrms<Vline<245 Vrms. 9. With input divider ratio of 1/100, these values are equivalent to 245 Vrms<Vline<275 Vrms. 10.When OCP pin is above VIOVER_CYC_ON as 1.68V, then SW is controlled by the PWM block for on and off. 11.When OCP pin is below VIOVER_CYC_OFF as 1V, then SW is turned off and released at the next switching cycle if OCP pin is above VIOVER_CYC_ON Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 17 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 18 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Functional Description Overview 3 Functional Description 3.1 Overview The 88EM8040/88EM8041 is a high performance, low-cost with minimum component count Power Factor Correction (PFC) Controller. The device is used for controlling Universal input flyback converters in systems or standalone products. The high performance of 88EM8040/88EM8041 is accompanied with its small size and simplicity of application. Figure 3 shows the top level block diagram. Figure 3: Top Level Block Diagram 88EM8040/8041 Over Temperature Clock Oscillator Current Protection Protection Management I_over Fault Driver Disable Current Amplifier ISNS T_over Vo_over I_over MUX Switcher & ADC FB Output Voltage Level Detect Gate Driver DSP Core State Machine SW Vo_over Zero Cross Detect VIN Current Protection Threshold Selection PGND SGND Note Power Distribution and Bandgaps Serial Data Interface VDD OCP I_over, Vo_over, and T_over are the over current, over voltage, and over temperature signals respectively. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Startup Setting or Frequency Setting Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 19 88EM8040/88EM8041 Datasheet 3.2 Signal Process and Functions The 88EM8040/88EM8041 boost power board includes three inputs: Resistive divider signal from AC line voltage Feedback from the output DC bus Voltage across the current sense resistor The input phase voltage to ground (half rectified sine wave) scaled down by the input resistive divider is applied to pin VIN. This signal used for estimation of the AC line voltage and regeneration of the AC sine wave. It is also used for voltage level detection that produces adaptive multiple thresholds for the over current limit and guarantees a constant power limit from the AC source. Signal from the DC bus voltage through the muxed 12-bit Analog-to-Digital Converter (ADC) provides the feedback data for the voltage PI control loop. HF switching current pulse signal is retrieved from the voltage drop across the current sense resistor that is negative to GND. This signal after HF noise filter and fixed gain amplification, is transferred through the muxed 12-bit ADC to the digital current loop and the current error amplifier. The reference current for the current control PI loop is provided by multiplying the voltage error amplifier output and the regenerated sinusoidal line voltage information. Doc. No. MV-S104983-01 Rev. A Page 20 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Functional Characteristics VDD Characteristics 4 Functional Characteristics The following applies unless otherwise noted: VIN = 60Hz half-wave sinusoidal from 0V to the peak voltage (VPK) given in the test conditions of each graph. TA = 25C. All measurement readings are typical. 4.1 VDD Characteristics Figure 4: IDD Quiescent (IDD_QST) vs. VDD 100 90 80 IDD (A) 70 60 50 40 30 20 10 0 0 2 4 6 8 10 12 VDD (V) Test Conditions: VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Figure 5a: IDD vs. VDD (VDD_ON) Figure 5b: IDD vs. VDD (VDD_ON) 7 6 VDD Falling VDD Rising 5 VDD Falling 6 VDD Rising 5 IDD (mA) IDD (mA) 4 3 4 3 2 2 1 1 0 0 0 2 4 6 8 10 12 14 16 0 2 4 6 VDD (V) Test Conditions: VIN = 0V FSW = 118kHz VFB = 0V CGate = 1nF V_Isns = 0V Test Conditions: VIN = 0V FSW = 118kHz Copyright (c) 2009 Marvell October 5, 2009, Preliminary 8 10 12 14 16 VDD (V) VFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 21 88EM8040/88EM8041 Datasheet Figure 6b: IDD Operation (IDD_OP) vs. Temperature 7 7 6 6 5 5 IDD (mA) IDD (mA) Figure 6a: IDD Operation (IDD_OP) vs. Temperature 4 3 4 3 2 2 1 1 0 0 -40 -20 0 20 40 60 80 -40 -20 0 Test Conditions: VFB = 0V CGate = 1nF V_Isns = 0V VDD = 12V VIN = 0V FSW = 118kHz 20 40 60 80 Temperature (C) Temperature (C) Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Figure 7: VDD On/Off vs. Temperature 14 12 ON VDD (V) 10 8 OFF 6 4 Hysteresis 2 0 -40 -20 0 20 40 60 80 Temperature (C) Test Conditions: VIN = 0V FSW = 118kHz FFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104983-01 Rev. A Page 22 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Functional Characteristics VFB Characteristics for Over Voltage Protection 4.2 VFB Characteristics for Over Voltage Protection Figure 8: IDD vs. VFB (OVP) Figure 9: VFB_OVP vs. Temperature 3.0 5.5 OVP Threshold 2.5 5.0 Recovery Threshold 4.5 V F B (V ) IDD (mA) 2.0 4.0 1.5 1.0 VFB Falling 3.5 0.5 VFB Rising 0.0 3.0 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 -40 3.0 -20 0 Test Conditions: VDD = 12V VIN = 0V Test Conditions: FSW = 118kHz CGate = 1nF V_Isns = 0V 20 40 60 80 Temperature ( C) VFB (V) Figure 10: VFB_OVP Hysteresis vs. Temperature VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Figure 11: VFB_OVP_LATCH vs. Temperature 4.0 0.30 3.5 0.25 3.0 2.5 VFB (V) VFB (V) 0.20 0.15 2.0 1.5 0.10 1.0 0.05 0.5 0.00 0.0 -40 -20 0 20 40 60 80 -40 -20 0 Test Conditions: VDD = 12V VIN = 0V FSW = 118kHz CGate = 1nF V_Isns = 0V Test Conditions: VDD = 12V VIN = 0V Copyright (c) 2009 Marvell October 5, 2009, Preliminary 20 40 60 80 Temperature (C) Temperature ( C) FSW = 118kHz CGate = 1nF V_Isns = 0V Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 23 88EM8040/88EM8041 Datasheet Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature 3.0 2.9 2.8 VFB (V) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -40 -20 0 20 40 60 80 Temperature (C) Test Conditions: VDD = 12V VIN = 2V 4.3 FSW = 118kHz CGate = 1nF V_Isns = 0V Switching Frequency Characteristics Figure 13: Switching Frequency vs. Temperature 140 FSW (8041) Frequency (kHz) 120 100 80 FSW (8040) 60 40 20 0 -40 -20 0 20 40 60 80 Temperature (C) Test Conditions: VDD = 12V VIN = 0V VFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104983-01 Rev. A Page 24 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Functional Characteristics Over Current Threshold Characteristics 4.4 Over Current Threshold Characteristics Figure 14: Over Current (VIOVER) vs. Input Voltage VIN Peak Value) 0.45 0.40 0.35 V CS (V ) 0.30 0.25 0.20 0.15 0.10 0.05 0.00 0 1 1 2 2 3 3 4 4 5 5 VIN (V) Test Conditions: VDD = 12V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Figure 15: Over Current (VIOVER) vs. Temperature 450 VIN = 1.5V 400 VIN = 2.25V 350 VCS (V) 300 VIN = 3V 250 VIN = 3.7V 200 150 100 50 0 -40 -20 0 20 40 60 80 Temperature ( C) Test Conditions: VDD = 12V FSW = 118kHz VFB = 2.4V CGate = 1nF V_Isns = 0V Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 25 88EM8040/88EM8041 Datasheet Figure 16: VIOVER_CYC_ON/OFF vs. Temperature 2 VIOVER_CYC_ON 1.8 1.6 Viover (V) 1.4 1.2 VIOVER_CYC_OFF 1 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 Temperature (C) Test Conditions: VDD = 12V VIN = 0V VFB = 2.4V CGate = 1nF V_Isns = 0V Doc. No. MV-S104983-01 Rev. A Page 26 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information 5 Design and Applications Information The flyback (isolated buck/boost) topology is used to simplify the two stage front-end design to a single isolated Power Factor Correction (PFC) conversion stage. Compared to the two stage PFC structure, a single stage PFC is a more cost effective solution. The 88EM8040/88EM8041 chip control algorithm uses Average Current Mode Control for power factor correction applications with low harmonic distortion and good noise immunity. The IC senses the output voltage and forces it to follow the reference voltage to produce a stable DC output voltage matching the design requirements. It also senses the primary current and forces the average signal of the primary current to follow the sinusoidal current reference, therefore achieving power factor correction. Compared to other competitors parts operating under Critical Transition Mode Control, the 88EM8040/88EM8041 has many advantages as shown in Table 6l Table 6: Comparison Between Average Current Mode and Critical Transition Mode Control C r iti c a l Tr a n s m it io n M o d e C on t r o l Av e r a g e C u r r e n t M o d e C o n t r o l High peak current on switch Low peak current on switch High diode peak current at secondary side Low diode peak current at secondary side Variable switching frequency with lowest switching frequency at peak input voltage Fixed switching frequency Big transformer Small transformer Low efficiency High efficiency Low power factor / higher THD at high line low load High power factor / lowerer THD at high line low load due to adaptive loop control Difficult to achieve high power Easy to achieve high power High cost Low cost Marvell's innovative PFC control technology improves the performance of the isolated flyback converter used in PFC applications. The flyback PFC solution based on the 88EM8040/88EM8041 provides customers with a simple structure, low cost without sacraficing performance compared with the other industry solutions currently on the market. The following sections provides guidelines for the application design, component selection, and board layout all in order to improve flyback single stage PFC performance. There are three analog input signals and one logic input signal listed below are required from the power train to the controller IC 88EM8040/88EM8041. 1. 2. 3. 4. Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through the input voltage resistor divider. This is for the line frequency zero-cross detection for PFC. Output voltage signal at FB pin is the output voltage through the resistor divider plus the compensation and opto-coupler to feedback on FB pin. This is for the voltage loop regulation. Current sensing signal through the sensing resistor to the ISNS pin. This is for the average current mode control to achieve a good sinusoidal current waveform and high power factor. The input over current protection (OCP) signal is a logic signal instead of an analog signal. It is used to shut down the output at the SW pin when it is pulled low. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 27 88EM8040/88EM8041 Datasheet The output signal from the 88EM8040/88EM8041 is the PWM gate drive signal from the SW pin. The switching frequency on the 88EM8040 device is fixed to 60kHz while the 88EM8041 is fixed to 120kHz. Both device tolerances are shown in the electrical characteristics table. 5.1 Input Voltage Resistor Divider on VIN Pin An accurate peak detection signal and zero-cross detection for regenerating the input sinusoidal voltage is the most important issue for a proper current shaping and total harmonic distortion (THD) improvement. If the threshold reference is too high, near the peak area, the calculation may lose accuracy because of the low slope. On the other hand, if the threshold reference is too low, there could be an error on zero-cross detection due to the possible distortions near the zero-crossing. For a universal input voltage range (85Vac~270Vac) the optimum accuracy would be achieved if the threshold level is around 30 degree of the line cycle. Figure 17: Internal Block for Zero-cross Detection, Brown-out Protection VDCin 88EM8040 /8041 Brown-Out Protection Vline _ pk AC IN Predictive Sinusoidal AC Voltage Phase ( ) Ra Rb VIN Rc Peak detecting pulse Zero Crossing Power Limit Threshold Selection To get a proper sinusoidal AC voltage, UVLO, and peak voltage detection, we need to choose the right value for the sensing resistors: Ra, Rb, and Rc, as shown in Figure 17. If the value is too small there will be higher power loss and if the value is too big the resistor will not properly work due to the picking noise of the VIN signal. The recommended values are shown below: Ra + Rb ------------------ = 100 --------- = 1.8M ----------------Rc 1 18k Equation (1) For the input voltage resistor divider, the appropriate combination based on the voltage / power rating of the resistors should also be considered. Doc. No. MV-S104983-01 Rev. A Page 28 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information Input Voltage Resistor Divider on VIN Pin Figure 18: Peak Detecting Signal for Predictive Sinusoidal AC Voltage Vline_pk Vline_pk VVIN_BR = 0.72V (Typ.) V ( ) = Vline_pk x sin Half line cycle Half line cycle N M N Peak detecting Pulse As can be seen in Figure 17, the internal peak detecting circuit generates peak detecting pulse through the inside comparator which has a threshold voltage of 0.72V (typical). Processing of this pulse in DSP core calculates the mid-point (peak point) and the zero-crossing point of the sinusoidal waveform. The phase angle of is calculated using the width of the high and low signal M&N. N = ( - 2) Equation (2) M = ( + 2 ) Equation (3) = (M - N) 4 Equation (4) Peak value of the sinusoidal waveform is introduced by the relation: V line_pk = V ( ) sin ( ) Equation (5) The signal that appears on the VIN pin is a half sinusoidal voltage waveform and its peak line value has to be higher than VVIN_BR of 0.72V (typical) for normal operation. Whenever the VVIN_BR is less than 0.72V at the peak line value, it is considered as a Brown-out condition. The IC only generates 6% duty during the brown-out condition. To adjust the brown-out protection point, the resistance value of Ra, Rb and Rc can be changed. With the recommended resistor values in Equation (1) the brown-out protection voltage is 72V peak value, which is around a 50V RMS value for the input line voltage. The layout of Ra, Rb and Rc should be kept as close as possible to the VIN pin, as shown in Figure 19 in order to have a proper layout on the input voltage resistor divider and to avoid noise picking. It is also recommended that a 0.1nF-10nF capacitor is connected between the VIN pin and ground with the layout also close to this pin. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 29 88EM8040/88EM8041 Datasheet Figure 19: Input Voltage Resistor Divider Layout Guidelines Ra OCP ISNS Cc PGND 88EM8040/ 8041 Rb Rc SW SGND VIN VDD FB Keep layout of Rb, Rc and Cc as close as possible to Vin pin to keep high noise immunization 5.2 Isolated Voltage Loop and Output Voltage Feedback on FB Pin The88EM8040/88EM8041 IC integrates the voltage loop into digital DSP core. This internal voltage loop has the lower corner frequency for the PFC requirement. The FB pin is the internal voltage loop feedback signal input. The voltage reference of the IC is 2.5V for the rated output voltage. The Flyback PFC is an isolated power system, which needs the opto-coupler device transferring the output voltage amplitude signal to the FB pin. Since the CTR (Current Transfer Ratio) parameter of this opto-coupler has a big tolerance and shifts with the temperature, an additional voltage reference and compensation is required at the secondary side. This secondary voltage loop circuit can use a low voltage adjustable shunt regulator such as the TLV431 or a dual op-amp with a reference voltage such as the TSM1014 to constitute the error amplifier with compensation network. Figure 20 shows the typical voltage feedback loop circuit. Figure 20: Secondary Compensation Network with Opt-coupler VOut RS4 VFB VDD CS2 CS1 R S2 R S5 1 2 Verr Vref R f1 Doc. No. MV-S104983-01 Rev. A Page 30 RS3 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information Isolated Voltage Loop and Output Voltage Feedback on FB Pin It is well known that a single stage PFC with flyback topology is not easy to maintain enough stability while at the same time keeping a good sinusoidal current waveform and power factor under a wide input voltage and load condition. In order to achieve enough stability as the first criteria, the compensation network at the secondary should be designed properly, which will be described in the following paragraph. In order to achieve a good sinusoidal current waveform and power factor, the voltage loop regulation coefficient should also be designed properly corresponding to the different input voltages. The adaptive voltage loop coefficient is designed inside the IC to select different voltage regulation parameters. This achieves a much better power factor and sinusoidal current waveform compared to any of the single stage PFC power system on the market now. This is why there is also another voltage loop regulation designed inside of the IC while an external voltage loop compensation is designed at the secondary side of the flyback system. 5.2.1 Resistor Divider Design for Output Voltage The design of RS3 and RS4 is based on the rated output voltage and the power loss of the resistor divider. In order to keep low power consumption on the resistor divider and good signal to noise immunity, a minimal total resistance of 20k (Typical) is recommended for the pair of resistors RS3 and RS4. The relation among the output voltage, reference voltage and resistor divider is as; R S3 V out x ----------------------- = V ref R S3 + R S4 Equation (6) If the output voltage is designed as 20V, reference voltage is 2.5V and RS4 is selected as 15.4k, the value RS3 is calculated from equation (6) as 2.21 k. 5.2.2 Compensation Network Design1 The compensation network should be designed by selecting the value of RS5, CS1 and CS2. A typical compensation network is constructed in Figure 20. The transfer function is derived as; 1 + sR S5 C S1 V err ( s ) 1 H ( s ) = -------------------- = -------------------------------------- x ----------------------------------------------------V OUT ( s ) R S4 ( C S1 + C S2 ) C s1 C s2 s 1 + s ------------------------ R S5 C S1 + C S2 Equation (7) Equation (7) is simplifed as; ( s + z ) H ( s ) = K x ---------------------s ( s + p ) Equation (8) Where: 1 1 1 K = ------------------ ; z = ------------------ ; p = --------------------------------R S5 C S1 C S1 C S2 R S4 C S2 ------------------------ R S5 C S1 + C S2 Equation (9) The criteria to design the network in Figure 20 is to provide enough DC gain and attenuate the double line frequency ripple by properly selecting the right zero and pole parameters. In order to meet these criteria, zero z should be placed below the double line frequency (100/120Hz) and pole 1. Please refer to the 88EM8041 90W application note for a detailed derivation of open-loop transfer function for the overall flyback circuit. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 31 88EM8040/88EM8041 Datasheet p should be placed above the double line frequency. The magnitude of the gain around the double line frequency should below the unity gain, which is 0db axis in the bode plot, in order to attenuate the double line frequency ripple. The following is a design example of this network: RS4=15.4k, RS5=2k, CS1=4.7F and CS2=47nF. This produces a zero and pole as: z = 16.94Hz, p = 1.71kHz. The bode plot is shown in Figure 21. The magnitude of the gain at 100Hz to 120Hz is about -18dB, therefore the double line frequency ripple is attenuated. The parameters are designed to maintain the stability for the single stage PFC system. Figure 21: Bode Plot of Compensation Network at Secondary Side magnitude (db) 100 50 0 -50 -4 10 -2 10 0 10 2 10 4 10 6 10 Frequency (Hz) 0 Phase (degree) -20 -40 -60 -80 -100 -4 10 -2 10 0 10 2 10 4 10 6 10 Frequency (Hz) In order to decrease the time for the transconductance error amplifier at the secondary to quit the saturation process and reduce the output voltage overshoot at startup, a Zener diode is required. The zener diode is connected between the error amplifier output terminal to ground. This reduces the overshoot and improves the startup performance, because the zener provides a bias current before the transconductance error amplifier sinks current. Because of the tolerance of the opto-coupler CTR, the output voltage of the error amplifier under a steady state should not become too low so as to keep the sufficient output regulation capability. In the 20V/90W reference design, a 6.8V Zener is selected and output of the error amplifier is set as about 5 to 6 volts under steady state. The output voltage of the transconductance error amplifier is around one third of the rated output voltage under steady state. Doc. No. MV-S104983-01 Rev. A Page 32 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information Isolated Voltage Loop and Output Voltage Feedback on FB Pin 5.2.3 RS2 and Rf1 Design The RS2 and Rf1 design is mainly based on the opto-couplers current transfer ratio(CTR) Which should be around 100% to 200%. RS2 is designed to produce around 1mA current at the LED side of the opto-coupler. Rf1 is designed to produce 2.5V feedback voltage to close the loop under a stead state. If Rf1 is designed at 1.24k, the current at transistor side of the opto-coupler should be designed at 2mA (typical). This should have enough signal to noise ratio in the practical design. The feedback resistor (Rf1) should be kept close to the opto-coupler to avoid noise in the layout. The output of PFC Flyback has double line frequency ripple voltage. At the steady state operation condition, the FB pin voltage transferred from secondary side also has this double line frequency ripple voltage. The ripple voltage amplitude on the FB pin is determined by the output voltage ripple amplitude and the gain from the output voltage to the FB pin (referred in the previous section Section 5.2.2, Compensation Network Design, on page 31). It is noticed that there is an attenuated ripple appearing at the output of the amplifier with the minus phase shift from the output voltage ripple. Therefore, the ratio of ripple voltage amplitude over the DC voltage value of FB pin is bigger than the ratio of output ripple over DC output voltage. If the output ripple voltage is too big in certain applications, the FB pin voltage peak value might trigger the internal FB OVP threshold, which is about 7% on the top of the reference value. This will heavily distort the input current waveform and disturb the stability of the system. In order to solve this issue, it is recommended to use a constant offset voltage circuit, as show in Figure 22. This circuit consists of a diode (ZD1), and two resistors (Rf2 and Rf3). This will provide a bias current from the bias winding so as to produce a bias voltage on the FB pin. Therefore, the ripple voltage amplitude of the FB pin is decreased below the FB OVP threshold. In the 90W reference design, the winding bias voltage provides 1mA (typical) offset current to the FB pin and the ripple voltage amplitude on the FB pin can decrease to be around half of that with this bias circuit. Rf2 can be calculated by equation (10), in which VFB is 2.5V reference voltage. If the cathode voltage VZD1 is 9.1V, Rf2 is calculated as 6.8k V ZD1 - V FB ---------------------------- = 1mA R f2 Equation (10) Figure 22: Bias Current for Offset Voltage on FB Pin OCP SW SGND ISNS 88EM8040 /8041 VIN VOut PGND RS4 CS2 VDD FB Opto- Coupler RS2 CS1 RS5 VZD1 Rf3 CV CC Rf2 CVDD C vout Rf1 Copyright (c) 2009 Marvell October 5, 2009, Preliminary Vref + RS3 - Z D1 Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 33 88EM8040/88EM8041 Datasheet 5.3 Current Sensing and Over Current Protection 5.3.1 Current Sensing Through ISNS Pin The voltage drop on the current sense resistor should be kept very small in order to reduce the power consumption on the sense resistor. In flyback topology, the drain to source current flows through the transformer, MOSFET and current sense resistor (Rsen). This is shown in Figure 23. The average current mode control single stage solution requires two signals of flyback: the peak current signal to avoid the transformer saturation including a short circuit condition, and the average current sense signal to achieve the right PFC operation. The voltage drop (Vsen) across resistor (Rsen) represents the flyback peak current signal. The voltage of (VCS), after RCS and CCS low pass filter, represents the average current signal of the primary side of the flyback converter. Figure 23: Current Sensing Circuit DR2 VDCin VOUT Np Csn Rsn NS2 Cin Vsen Dsn Drain Q1 Rsen Rcs Ccs OCP SW S GND I SNS Vcs 88EM8040 VIN /8041 VDD P GND FB The resistor (Rsen) should be designed such as the example in Table 7 where Rsen is designed for a 90W adaptor. The specification are: output power = 90W, input voltage range = 85-264V, output voltage = 20V, output current= 4.5A, 30% margin of over current on top of the normal current. Doc. No. MV-S104983-01 Rev. A Page 34 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information Current Sensing and Over Current Protection Table 7: Current Sensing Circuit Input Power Pin 90W Minimum input voltage Vinmin 85V Maximum average input current I inmax = 1.49A P in 2 x --------------V inmin Over current threshold Zone 1 VIOVERTH1 0.391V Over current margin Imargin 30% Current sensing resistor calculation V IOVERTH1 R sns = ---------------------------------------------------i inmax x ( 1 + I m arg in ) 0.2 Current sensing resistor selection Rsns 0.2 Table 8 shows the reference value of the current sensing resistor. In the practical design, the current sensing resistor value could be fine tuned around the value shown in the table based on the specification and the primary inductance of the flyback transformer. Table 8: 5.3.2 Current Sensing Resistor Selection Reference Input Power (W) 36 72 90 120 Current Sensing Resistor () 0.40 - 0.45 0.20 - 0.27 0.15 - 0.20 0.12 - 0.15 Average Current Signal and Over Power Limitation To convert flyback peak current into an average current signal, an RC filter is required. Figure 24 shows how adding two more components will result in an average current signal. This average current signal, VCS is fedback onto the ISNS pin and used to achieve a sinusoidal current waveform by an internal current control loop. It is also used to achieve power limitation. The corner frequency of the RC filter is recommended approximately 1/10~1/6 of the switching frequency. Rcs is recommended as the value of 187 for the purpose of blocking negative and surge voltages. A single stage PFC operates at 120kHz (typical), Ccs is designed as 47nF which results in a corner frequency of 18kHz. The internal IC block is designed to perform the over power limitation as shown in the electrical characteristics table. The corner frequency of the low pass filter is designed as; 1 f corner = ----------------------2R cs C cs Equation (11) Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 35 88EM8040/88EM8041 Datasheet 5.3.3 Cycle by Cycle Current Protection through OCP Pin In order to get the cycle by cycle current protection to avoid the transformer saturation, a circuit with a low base to emitter parasitic capacitance NPN transistor is recommended in the design, as shown in Figure 24. The sensing voltage through Rsen should trigger and turn on the transistor of Q2 during the over current condition. Q2 then pulls the OCP pin to low and turns off the gate signal to the external MOSFET. In order to get proper protection, a -2mV/C (typical) temperature coefficient of (Vbe) should be considered. The lowest voltage (Vbe) will be set to the junction temperature of 80C. Figure 24: Current Sensing and Cycle by Cycle Over Current Protection Circuit DR2 VDCin VOUT Np Csn Cin Rsn NS2 Q2 Vsen Dsn Q1 R1 R2 Rsen Drain Csen Rcs Ccs OCP SW S GND I SNS Vcs VIN 88EM8040 / 8041 VDD FB Figure 25: Current Sensing and Cycle by Cycle Over Current Protection Waveforms D D GND Vcs avg cs V Vcs LEB (Leading Edge current) avg Vsen Vsen Vsen Vcsavg avg Vsen Power limit OCP OCP Doc. No. MV-S104983-01 Rev. A Page 36 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information Current Sensing and Over Current Protection V be 0.65V - 2mV x ( 80 - 25 ) = 0.54V The highest Vbe voltage will be set to the junction temperature of -25C. Equation (12) V be 0.65V - 2mV x ( - 25 - 25 ) = 0.75V Equation (13) The voltage Vbe is supposed to have some tolerance margin to select the resistor of Rsen without any unpredicted cycle by cycle over current protection. The recommended equation is: 0.50V R sen ---------------peak I ds Equation (14) The minimum saturation current point of Ilim for the transformer should satisfy: 0.75V I lim = -------------R sen Equation (15) Ilim should have enough margins considering transformer saturation condition at lower ambient temperature. R1 and R2 should be selected properly in Figure 24, in order to make the cycle by cycle current limiting work correctly. R1 and R2 act as voltage dividers to setup the right current limitation threshold. Actually R2 also works as controlling base current of that transistor, the same time, R1 works to discharge the parasitic capacitance of that transistor. In the practical design, the R1 and R2 need to choose properly based on the power rating of the system. The value of R1 is recommended as 500~2K and R2 as 500~2k. Please note that a small value of the capacitor parallel with the Rsns resistor is very helpful to filter the noise in order to guarantee this OCP circuit to function properly. When the MOSFET turns on, external COSS of the MOSFET starts discharging. This causes switching loss increases and makes the leading edge current. Figure 25 shows that this current creates unwanted over current making the system not function properly. This phenomenon can be avoided by adding one capacitor Csen. The leading edge current timing is less than 300nS (typical). Csen can be calculated as; 1 f sen = ---------------------------- 1MHz 2R sen C sen Equation (16) Csen is recommended to have a value of 0.22F/25V. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 37 88EM8040/88EM8041 Datasheet 5.3.4 Peak Current and Average Current Relationship The relationship between the flyback peak and the average current signals are described in the following equation. Figure 25 explains this in detail. Current sensing signal across Rsen resistor is calculated as V sen = R sen x I ds Equation (17) The average current sensing signal during MOSFET switching on is V sen I ins = V sen - R sen -----------2 avg Equation (18) The switching frequency peak to peak ripple is V line D I ins = -------------------Lm fs Equation (19) The average current sensing signal during the whole switching cycle is V cs avg = V sen avg xD Equation (20) Doc. No. MV-S104983-01 Rev. A Page 38 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Design and Applications Information SW Pin to MOSFET Gate 5.4 SW Pin to MOSFET Gate The 88EM8040/88EM8041 provides a maximum 2A drive current, which is the strongest driver capability in comparison with the other similar part on the market. A default resistor of 10 is designed to go between the SW pin and the gate of the external MOSFET. The gate driver loop is subject to fast rise and the layout trace should be kept as short as possible in order to minimize the parasitic inductance, as shown in Figure 26. Figure 26: SW Pin Layout Guidelines DR2 VDCin VOUT Np Csn Rsn NS2 Dsn Rgate Q1 Drain Keep this trace as short as possible in layout OCP SW SGND ISNS 88EM8040 /8041 VIN VDD 5.5 PGND FB VDD, Signal Ground (SGND) and Power Ground (PGND) VDD is the IC power supply pin. It has a typical input voltage value of 12V and a maximum operating voltage of 16V. A Zener clamp circuit of 16V is recommended in order to guarantee that the voltage on VDD will not go any higher than 16V. The IC begins to function when VDD powers on at 12V. Once the IC powers on, it keeps functioning as long as the VDD is higher than VDD_UVLO, which is 7V (typical). In a practical design, an electrolytic capacitor 220F (typical) is recommended to connect between VDD and ground in order to retain the IC functionality during startup. That capacitor will need to keep the VDD higher than 7V before the bias transformer winding takes over and provides enough energy for the power IC. A 0.01-0.1F ceramic capacitor is strongly recommended to be placed between the VDD and IC ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the noise to VDD and clamping the VDD voltage during the switching of the internal driver circuit. SGND is directly connected to the system ground by a Kelvin connection trace. The system ground is the source of the MOSFET, as shown in Figure 27. PGND connects to the system ground separately and can not share the same trace with SGND. This is due to pulse current on PGND while driving the external MOSFET on and off. This pulse current produces pulse voltage drops on the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the same trace. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 39 88EM8040/88EM8041 Datasheet Figure 27: VDD Decoupling Capacitor and Ground Layout Guidelines DR2 VDCin VOUT Np Csn Rsn NS2 Dsn Rgate Q1 Drain Using Kelvin sensing connection for SGND with separate trace from PGND OCP SW SGND ISNS VIN 88EM8040 /8041 FB PGND C Keep this trace right beside IC and as short as possible VDD Doc. No. MV-S104983-01 Rev. A Page 40 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary October 5, 2009, Preliminary Copyright (c) 2009 Marvell Document Classification: Proprietary T101B 2 2 1 1 C109 100uF R120 20K ZD102 9.1V ZD106 15V 4- R129 1K ZD101 18V R130C 2.5M R130B 2.5M R130 2.5M C108 C107 470uF 0.1uF 50MH LF2 ZD107 18V C110 0.1uF Q103 2N7002 R305 9.1M CX1 0.47uF R117 R115 Q107 1.1K 5.1K BCX54 ZD105 6.2V CY1 1nF R304 9.1M 10MH LF1 R303 9.1M D103 US1D R302 9.1M R114 5.1K GTD 1 501 VARA1 240V 4A250V R301 9.1M Socket N L J1 R106A 620K R106B 620K R106C 620K Q108 MMBT4403 D104 1N4148 R107 D101 R116 802 1N4148 2K NTC2 100k t L101 50uH C105 1uF R127 12K R108 C103 18K 220pF BD1 GBL406 1 Q102 STD1NK60 R132 100K 3 2 + ISNS Q109 MMBT4401 R128 12K R122 12K 3 4 C102 47nF 1 R110 300 R111 1.21K U200B LTV817B 5 C104 0.1uF FB SW 8 C120 4.7nF R112 5.1K 2 R105 5.1 R135 820K ZD104 0.1uF R118 360 SGND PGND 2 C106 0.22uF R101 0.15 88EM8041 IC101 VDD 7 t NTC1 10K SDI/FSET VIN R109 300K 6 4 3 R104 187 R134 820K Q105 MMBT4401 R119 1.1K C101 0.68uF R133 1M 3 1 R103 5.1 Q101 IPB60R199 D120 US1J R125 100K R126 100K 2 R207 2K Q106 R102 MMBT4403 10K R124 100K R123 100K 9 5 6 C220 1nF ZD201 6.8V 7 C211 0.1uF D200 VF40120C 10 VCC R209 2K Cvout GND Cv- Cc+ Cc- Vref D220 ES1002FL 10 R221 R220 2 D201 VF40120C 2 TSM1014 IC200 Ccout 1 3 1 3 C212 4.7uF 5 D202 1N4148 U200A LTV817B R206 11K 2 1 R208 2K T101A 250uH 8 4 3 2 1 + + + + R200 15K C210 R204 C209 R201 C207 0.1uF 1.5K 0.1uF 1K 10nF R203 30K RS200 0.01 R202 1K C201 C202 C203 C204 C206 2700uF 2700uF 2700uF 2700uF 0.1uF C208 0.1uF VO- VO+ 5.6 6 FS1 90W/20V Signal Stage PFC Adaptor Schematic and Bill of Materials (BOM) Design and Applications Information 90W/20V Signal Stage PFC Adaptor Schematic and Bill of Materials (BOM) Figure 28: 90W/20V Single Stage PFC Adaptor Schematic Doc. No. MV-S104983-01 Rev. A Page 41 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 42 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Mechanical Drawings 6 Figure 29: 8-Lead SOIC Mechanical Drawing Document Classification: Proprietary Mechanical Drawings Copyright (c) 2009 Marvell October 5, 2009, Preliminary 6.1 All dimensions in mm. See Section 7, Part Order Numbering/Package Marking, on page 45 for package marking and pin 1 location. Mechanical Drawings Mechanical Drawings Page 43 Doc. No. MV-S104983-01 Rev. A Notes: 88EM8040/88EM8041 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S104983-01 Rev. A Page 44 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary Part Order Numbering/Package Marking Part Order Numbering 7 Part Order Numbering/Package Marking 7.1 Part Order Numbering Figure 30 shows the part order numbering scheme. For complete ordering information, contact your Marvell FAE or sales representative. Figure 30: 88EM8040/88EM8041 Sample Ordering Part Number 88EM804X xx-SAG2C000-xxxx Custom code (optional) Part number Custom code Custom code Temperature code C = Commercial Custom code Environmental code 2 = Green Halogen Free Package code The standard ordering part number for the respective solution is shown in Table 9. Table 9: 88EM8040/88EM8041 Part Order Options1 P a c k a g e Ty p e Part Order Number 8-Pin SOIC 88EM8040xx-SAG2C000 8-Pin SOIC 88EM8040xx-SAG2C000-T (Tape and Reel) 8-Pin SOIC 88EM8041xx-SAG2C000 8-Pin SOIC 88EM8041xx-SAG2C000-T (Tape and Reel) 1. Please note that the 88EM8040 device is 60kHz and the 88EM8041 device is 120kHz. Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 45 88EM8040/88EM8041 Datasheet 7.2 Package Markings Figure 31 shows a typical package marking and pin 1 location. Figure 31: 88EM8040/88EM8041 Package Marking MRVL Marvell company abbreviation 804X Abbreviated part number XXXX = 4 character abbreviated part number YWWG Pin 1 location Date code and assembly house code Y = last digit of year WW = work week G = assembly house code Note: The above example is not drawn to scale. Location of markings are approximate. Doc. No. MV-S104983-01 Rev. A Page 46 Copyright (c) 2009 Marvell Document Classification: Proprietary October 5, 2009, Preliminary A Table 10: Revision History Revision History D o cu m e n t Ty p e D o c u m e n t R e v is i o n Release 8040/41 Rev. A * * * * Revised EC table with new values. Reworked Application and Design Section Revised Mechanical Drawing Updated Part Ordering Release 8041 Rev. - First Release Copyright (c) 2009 Marvell October 5, 2009, Preliminary Doc. No. MV-S104983-01 Rev. A Document Classification: Proprietary Page 47 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster