Low Voltage, 1.15 V to 5.5 V, 8-Channel
Bidirectional Logic Level Translators
ADG3308/ADG3308-1
Rev. C
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FEATURES
Bidirectional logic level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 1 μA
No direction pin
APPLICATIONS
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communication devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
Portable POS systems
Low cost serial interfaces
FUNCTIONAL BLOCK DIAGRAM
A1 Y1
GND
V
CCY
V
CCA
A8 Y8
A7 Y7
A6 Y6
A5 Y5
A4 Y4
A3 Y3
A2 Y2
EN
ADG3308/ADG3308-1/
ADG3308-2
0
4865-001
Figure 1.
GENERAL DESCRIPTION
The ADG3308/ADG3308-1/ADG3308-2 are bidirectional level
translators containing eight bidirectional channels. They can be
used in multivoltage digital system applications, such as a data
transfer between a low voltage DSP controller and a higher
voltage device. The internal architecture allows the device to
perform bidirectional level translation without an additional
signal to set the direction in which the translation takes place.
The voltage applied to VCCA sets the logic levels on the A side
of the device, and VCCY sets the levels on the Y side. For proper
operation, VCCA must always be less than VCCY. The VCCA
compatible logic signals applied to the A side of the device
appear as VCCY compatible levels on the Y side. Similarly, VCCY
compatible logic levels applied to the Y side of the device appear
as VCCA compatible logic levels on the A side.
The enable pin (EN) provides three-state operation on both the
A side and the Y side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. For normal operation, EN should be driven high.
The ADG3308 is available in a compact 20-lead TSSOP and
a 20-lead LFCSP, the ADG3308-1 is available in a 20-ball
WLCSP, and the ADG3308-2 is available in a backside-coated
20-ball WLCSP. The EN pin is referred to the VCCY supply
voltage for the ADG3308 and to the VCCA supply voltage for the
ADG3308-1 and ADG3308-2.
The ADG3308/ADG3308-1/ADG3308-2 are guaranteed to
operate over the 1.15 V to 5.5 V supply voltage range and the
extended −40°C to +85°C temperature range.
PRODUCT HIGHLIGHTS
1. Bidirectional logic level translation.
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.
3. No direction pin.
4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308),
20-ball WLCSP (ADG3308-1), and backside-coated 20-ball
WLCSP (ADG3308-2).
ADG3308/ADG3308-1
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circ uits ..................................................................................... 12
Ter mi no log y .................................................................................... 15
Theory of Operation ...................................................................... 16
Level Translator Architecture ................................................... 16
Input Driving Requirements..................................................... 16
Output Load Requirements ...................................................... 16
Enable Operation ....................................................................... 16
Power Supplies ............................................................................ 16
Data Rate ..................................................................................... 17
Applications..................................................................................... 18
Layout Guidelines....................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/07—Rev. B to Rev. C
Updated Outline Dimensions....................................................... 19
7/07—Rev. A to Rev. B
Added Backside-Coated WLCSP Package ......................Universal
Changes to Input Driving Requirements Section ...................... 16
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 20
7/06—Rev. 0 to Rev. A
Added WLCSP Package…………………………..……Universal
Added Figure 4………………………………………………......7
Updated Outline Dimensions……………………………….…19
Changes to Ordering Guide………………………………....…19
1/05—Revision 0: Initial Version
ADG3308/ADG3308-1
Rev. C | Page 3 of 20
SPECIFICATIONS
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 1
Table 1.
Parameter Symbol Conditions Min Typ2Max Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage3VIHA VCCA = 1.15 V VCCA − 0.3 V
V
IHA VCCA = 1.2 V to 5.5 V 0.65 × VCCA V
Input Low Voltage3VILA 0.35 × VCCA V
Output High Voltage VOHA VY = VCCY, IOH = 20 μA, see Figure 29 VCCA − 0.4 V
Output Low Voltage VOLA VY = 0 V, IOL = 20 μA, see Figure 29 0.4 V
Capacitance3CAf = 1 MHz, EN = 0, see Figure 34 10 pF
Leakage Current ILA, HIGH-Z VA = 0 V or VCCA, EN = 0, see Figure 31 ±1 μA
Y Side
Input High Voltage3VIHY 0.65 × VCCY V
Input Low Voltage3VILY 0.35 × VCCY V
Output High Voltage VOHY VA = VCCA, IOH = 20 μA, see Figure 30 VCCY − 0.4 V
Output Low Voltage VOLY VA = 0 V, IOL = 20 μA, see Figure 30 0.4 V
Capacitance3CY f = 1 MHz, EN = 0, see Figure 35 6.8 pF
Leakage Current ILY, H I GH-Z VY = 0 V or VCCY, EN = 0, see Figure 32 ±1 μA
Enable (EN)
Input High Voltage3VIHEN
ADG3308 (TSSOP, LFCSP) 0.65 × VCCY V
ADG3308-1/ADG3308-2 (WLCSP) VCCA = 1.15 V VCCA − 0.3 V
V
CCA = 1.2 V to 5.5 V 0.65 × VCCA V
Input Low Voltage3VILEN
ADG3308 (TSSOP, LFCSP) 0.35 × VCCY V
ADG3308-1/ADG3308-2 (WLCSP) 0.35 × VCCA V
Leakage Current ILEN VEN = 0 V or VCCY, VA = 0 V, see Figure 33 ±1 μA
Capacitance3CEN 4.5 pF
Enable Time3tEN RS = RT = 50 Ω, VA = 0 V or
VCCA (A→Y), VY = 0 V or VCCY (Y→A),
see Figure 36
1 1.8 μs
SWITCHING CHARACTERISTICS3
3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V
A→Y Level Translation R
S = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay tP, A →Y 6 10 ns
Rise Time tR, A→Y 2 3.5 ns
Fall Time tF, A →Y 2 3.5 ns
Maximum Data Rate DMAX, A→Y 50 Mbps
Channel-to-Channel Skew tSKEW, A→Y 2 4 ns
Part-to-Part Skew tPPSKEW, A→Y 3 ns
Y→A Level Translation R
S = RT = 50 Ω, CL = 15 pF, see Figure 38
Propagation Delay tP, Y →A 4 7 ns
Rise Time tR, Y→A 1 3 ns
Fall Time tF, Y →A 3 7 ns
Maximum Data Rate DMAX, Y→A 50 Mbps
Channel-to-Channel Skew tSKEW, Y→A 2 3.5 ns
Part-to-Part Skew tPPSKEW, Y→A 2 ns
ADG3308/ADG3308-1
Rev. C | Page 4 of 20
Parameter Symbol Conditions Min Typ2Max Unit
1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V
A→Y Level Translation R
S = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay tP, A →Y 8 11 ns
Rise Time tR, A→Y 2 5 ns
Fall Time tF, A →Y 2 5 ns
Maximum Data Rate DMAX, A→Y 50 Mbps
Channel-to-Channel Skew tSKEW, A→Y 2 4 ns
Part-to-Part Skew tPPSKEW, A→Y 4 ns
Y→A Level Translation R
S = RT = 50 Ω, CL = 15 pF, see Figure 38
Propagation Delay tP, Y →A 5 8 ns
Rise Time tR, Y→A 2 3.5 ns
Fall Time tF, Y →A 2 3.5 ns
Maximum Data Rate DMAX, Y→A 50 Mbps
Channel-to-Channel Skew tSKEW, Y→A 2 3 ns
Part-to-Part Skew tPPSKEW, Y→A 3 ns
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V
A→Y Level Translation R
S = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay tP, A →Y 9 18 ns
Rise Time tR, A→Y 3 5 ns
Fall Time tF, A →Y 2 5 ns
Maximum Data Rate DMAX, A→Y 40 Mbps
Channel-to-Channel Skew tSKEW, A→Y 2 5 ns
Part-to-Part Skew tPPSKEW, A→Y 10 ns
Y→A Level Translation R
S = RT = 50 Ω, CL = 15 pF, see Figure 38
Propagation Delay tP, Y →A 5 9 ns
Rise Time tR, Y→A 2 4 ns
Fall Time tF, Y →A 2 4 ns
Maximum Data Rate DMAX, Y→A 40 Mbps
Channel-to-Channel Skew tSKEW, Y→A 2 4 ns
Part-to-Part Skew tPPSKEW, Y→A 4 ns
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V
A→Y Level Translation R
S = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay tP, A →Y 12 25 ns
Rise Time tR, A→Y 7 12 ns
Fall Time tF, A →Y 3 5 ns
Maximum Data Rate DMAX, A→Y 25 Mbps
Channel-to-Channel Skew tSKEW, A→Y 2 5 ns
Part-to-Part Skew tPPSKEW, A→Y 15 ns
Y→A Level Translation R
S = RT = 50 Ω, CL = 15 pF, see Figure 38
Propagation Delay tP, Y →A 14 35 ns
Rise Time tR, Y→A 5 16 ns
Fall Time tF, Y →A 2.5 6.5 ns
Maximum Data Rate DMAX, Y→A 25 Mbps
Channel-to-Channel Skew tSKEW, Y→A 3 6.5 ns
Part-to-Part Skew tPPSKEW, Y→A 23.5 ns
ADG3308/ADG3308-1
Rev. C | Page 5 of 20
Parameter Symbol Conditions Min Typ2Max Unit
2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V
A→Y Level Translation R
S = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay tP, A →Y 7 10 ns
Rise Time tR, A→Y 2.5 4 ns
Fall Time tF, A →Y 2 5 ns
Maximum Data Rate DMAX, A→Y 60 Mbps
Channel-to-Channel Skew tSKEW, A→Y 1.5 2 ns
Part-to-Part Skew tPPSKEW, A→Y 4 ns
Y→A Level Translation R
S = RT = 50 Ω, CL = 15 pF, see Figure 38
Propagation Delay tP, Y →A 5 8 ns
Rise Time tR, Y→A 1 4 ns
Fall Time tF, Y →A 3 5 ns
Maximum Data Rate DMAX, Y→A 60 Mbps
Channel-to-Channel Skew tSKEW, Y→A 2 3 ns
Part-to-Part Skew tPPSKEW, Y→A 3 ns
POWER REQUIREMENTS
Power Supply Voltages VCCA VCCA ≤ VCCY 1.15 5.5 V
V
CCY 1.65 5.5 V
Quiescent Power Supply Current ICCA VA = 0 V or VCCA, VY = 0 V or VCCY,
VCCA = VCCY = 5.5 V, EN = VCCY
0.17 1 μA
I
CCY VA = 0 V or VCCA, VY = 0 V or VCCY,
VCCA = VCCY = 5.5 V, EN = VCCY
0.27 1 μA
Three-State Mode Power Supply Current IHIGH-ZA VCCA = VCCY = 5.5 V, EN = 0 0.1 1 μA
I
HIGH-ZY VCCA = VCCY = 5.5 V, EN = 0 0.1 1 μA
1 Temperature range is −40°C to +85°C (B Version) for the TSSOP, the LFCSP, the WLCSP, and the backside-coated WLCSP.
2 All typical values are at TA = 25°C, unless otherwise noted.
3 Guaranteed by design; not subject to production test.
ADG3308/ADG3308-1
Rev. C | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter Rating
VCCA to GND −0.3 V to +7 V
VCCY to GND VCCA to +7 V
Digital Inputs (A) −0.3 V to (VCCA + 0.3 V)
Digital Inputs (Y) −0.3 V to (VCCY + 0.3 V)
EN to GND −0.3 V to +7 V
Operating Temperature Range
Extended Industrial Range (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
20-Lead TSSOP 78°C/W
20-Lead LFCSP 30.4°C/W
20-Ball WLCSP 100°C/W
20-Ball Backside-Coated WLCSP 100°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 260°C (+0°C/−5°C)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any
one time.
ESD CAUTION
ADG3308/ADG3308-1
Rev. C | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Y8
GND
Y7
EN
V
CCA
A1
A2
A5
A6 Y6
V
CCY
A7
A8
Y1
Y2
Y3
Y4
Y5
A3
A4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ADG3308
TOP VIEW
(Not to Scale)
0
4865-002
04865-003
A2
A3
A4
A5
A6
PIN 1
INDICATOR
1
2
3
4
5
13 Y5
14 Y4
15 Y3
12 Y6
11 Y7
6
A7
7
A8
8
EN
10
Y8
9
GND
18 V
CCY
19 V
CCA
20 A1
17 Y1
16 Y2
TOP VIEW
(Not to Scale)
ADG3308
T
HE EXPOSED PAD CAN BE TIED TO
G
ND OR IT CAN BE LEFT FLOATING.
DO NOT TIE IT TO V
CCA
OR V
CCY
.
ADG3308-1/
ADG3308-2
TOP VIEW
(Not to Scale)
(BALLS AT THE BOTTOM)
BALL a1
INDICATOR
Y1 A1 V
CCA
1234
Y3 A3 A2
Y5 A5 A4
Y7 A7 A6
V
CCY
Y2
Y4
Y6
Y8
a
b
c
d
eGND EN A8
04865-057
Figure 2. 20-Lead TSSOP Figure 3. 20-Lead LFCSP Figure 4. 20-Ball WLCSP
Table 3. Pin Function Descriptions
Pin/Ball No.
TSSOP LFCSP WLCSP Mnemonic Description
1 19 a4 VCCA Power Supply. Power supply voltage input for the A1 I/O pin to the A8 I/O pin
(1.15 V ≤ VCCA < VCCY).
2 20 a3 A1 Input/Output A1. Referenced to VCCA.
3 1 b4 A2 Input/Output A2. Referenced to VCCA.
4 2 b3 A3 Input/Output A3. Referenced to VCCA.
5 3 c4 A4 Input/Output A4. Referenced to VCCA.
6 4 c3 A5 Input/Output A5. Referenced to VCCA.
7 5 d4 A6 Input/Output A6. Referenced to VCCA.
8 6 d3 A7 Input/Output A7. Referenced to VCCA.
9 7 e4 A8 Input/Output A8. Referenced to VCCA.
10 8 e3 EN Active High Enable Input.
11 9 e2 GND Ground.
12 10 e1 Y8 Input/Output Y8. Referenced to VCCY.
13 11 d2 Y7 Input/Output Y7. Referenced to VCCY.
14 12 d1 Y6 Input/Output Y6. Referenced to VCCY.
15 13 c2 Y5 Input/Output Y5. Referenced to VCCY.
16 14 c1 Y4 Input/Output Y4. Referenced to VCCY.
17 15 b2 Y3 Input/Output Y3. Referenced to VCCY.
18 16 b1 Y2 Input/Output Y2. Referenced to VCCY.
19 17 a2 Y1 Input/Output Y1. Referenced to VCCY.
20 18 a1 VCCY Power Supply. Power supply voltage input for the Y1 I/O pin to the Y8 I/O pin
(1.65 V ≤ VCCY ≤ 5.5 V).
ADG3308/ADG3308-1
Rev. C | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25 30 35 40 45 50
DATA RATE (Mbps)
T
A
= 25°C
1 CHANNEL
C
L
= 50pF
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 3.3V, V
CCY
= 5V
I
CCA
(mA)
04865-004
Figure 5. ICCA vs. Data Rate (A→Y Level Translation)
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35 40 45 50
DATA RATE (Mbps)
T
A
= 25°C
1 CHANNEL
C
L
= 50pF
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 3.3V, V
CCY
= 5V
I
CCY
(mA)
04865-005
Figure 6. ICCY vs. Data Rate (A→Y Level Translation)
0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40 45 50
DATA RATE (Mbps)
I
CCA
(mA)
T
A
= 25°C
1 CHANNEL
C
L
= 15pF
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 3.3V, V
CCY
= 5V
04865-006
Figure 7. ICCA vs. Data Rate (Y→A Level Translation)
0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25 30 35 40 45 50
DATA RATE (Mbps)
I
CCY
(mA)
T
A
= 25°C
1 CHANNEL
C
L
= 15pF
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 3.3V, V
CCY
= 5V
04865-007
Figure 8. ICCY vs. Data Rate (Y→A Level Translation)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
13 23 33 43 53 63 73
CAPACITIVE LOAD (pF)
I
CCY
(mA)
20Mbps
10Mbps
5Mbps
1Mbps
T
A
= 25°C
1 CHANNEL
V
CCA
= 1.2V
V
CCY
= 1.8V
04865-012
Figure 9. ICCY vs. Capacitive Load at Pin Y
for A→Y (1.2 V→1.8 V) Level Translation
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
13 23 33 43 53
CAPACITIVE LOAD (pF)
ICCA (mA)
20Mbps
10Mbps
5Mbps
1Mbps
TA = 25°C
1 CHANNEL
VCCA = 1.2V
VCCY = 1.8V
0
4865-013
Figure 10. ICCA vs. Capacitive Load at Pin A
for Y→A (1.8 V→1.2 V) Level Translation
ADG3308/ADG3308-1
Rev. C | Page 9 of 20
0
1
2
3
4
5
6
7
8
9
I
CCY
(mA)
13 23 33 43 53 63 73
CAPACITIVE LOAD (pF)
T
A
=25°C
1 CHANNEL
V
CCA
= 1.8V
V
CCY
= 3.3V
30Mbps
20Mbps
10Mbps
5Mbps
50Mbps
04865-016
Figure 11. ICCY vs. Capacitive Load at Pin Y
for A→Y (1.8 V→3.3 V) Level Translation
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
I
CCA
(mA)
13 23 33 43 53
CAPACITIVE LOAD (pF)
50Mbps
T
A
= 25°C
1 CHANNEL
V
CCA
= 1.8V
V
CCY
= 3.3V
5Mbps
10Mbps
20Mbps
30Mbps
04865-017
Figure 12. ICCA vs. Capacitive Load at Pin A
for Y→A (3.3 V→1.8 V) Level Translation
0
2
4
6
8
10
12
I
CCY
(mA)
13 23 33 43 53 63 73
CAPACITIVE LOAD (pF)
T
A
= 25°C
1 CHANNEL
V
CCA
= 3.3V
V
CCY
= 5V
50Mbps
30Mbps
20Mbps
10Mbps
5Mbps
04865-020
Figure 13. ICCY vs. Capacitive Load at Pin Y
for A→Y (3.3 V→5 V) Level Translation
0
2
4
6
ICCA (mA)
13 23 33 43 53
CAPACITIVE LOAD (pF)
TA =25°C
1 CHANNEL
VCCA = 3.3V
VCCY = 5V
50Mbps
20Mbps
10Mbps
5Mbps
1
3
5
7
0
4865-021
30Mbps
Figure 14. ICCA vs. Capacitive Load at Pin A
for Y→A (5 V→3.3 V) Level Translation
0
1
2
3
4
5
6
7
8
9
10
13 23 33 43 53 63 73
CAPACITIVE LOAD (pF)
RISE TIME (ns)
TA = 25°C
1 CHANNEL
DATA RATE = 50kbps VCCA = 1.2V, VCCY = 1.8V
VCCA = 1.8V, VCCY = 3.3V
VCCA = 3.3V, VCCY = 5V
04865-023
Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
13 23 33 43 53 63 73
CAPACITIVE LOAD (pF)
FALL TIME (ns)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
V
CCA
= 1.2V, V
CCY
= 1.8V
04865-024
Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)
ADG3308/ADG3308-1
Rev. C | Page 10 of 20
0
1
2
3
4
5
6
7
8
9
10
13 18 23 28 33 38 43 48 53
RISE TIME (ns)
CAPACITIVE LOAD (pF)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
0
4865-025
Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation)
13 18 23 28 33 38 43 48 53
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FALL TIME (ns)
CAPACITIVE LOAD (pF)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.2V, V
CCY
= 1.8V V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
04865-026
Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation)
0
2
4
6
8
10
12
14
13 23 33 43 53 63 73
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
0
4865-027
Figure 19. Propagation Delay (tPLH) vs. Capacitive Load
at Pin Y (A→Y Level Translation)
0
2
4
6
8
10
12
13 23 33 43 53 63 73
PROPAGATION DELAY (ns)
CAPACITIVE LOAD (pF)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
04865-028
Figure 20. Propagation Delay (tPHL) vs. Capacitive Load
at Pin Y (A→Y Level Translation)
0
1
2
3
4
5
6
7
8
9
13 18 23 28 33 38 43 48 53
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
04865-029
Figure 21. Propagation Delay (tPLH) vs. Capacitive Load
at Pin A (Y→A Level Translation)
0
1
2
3
4
5
6
7
8
9
13 18 23 28 33 38 43 48 53
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
T
A
= 25°C
1 CHANNEL
DATA RATE = 50kbps
V
CCA
= 1.2V, V
CCY
= 1.8V
V
CCA
= 1.8V, V
CCY
= 3.3V
V
CCA
= 3.3V, V
CCY
= 5V
04865-030
Figure 22. Propagation Delay (tPHL) vs. Capacitive Load
at Pin A (Y→A Level Translation)
ADG3308/ADG3308-1
Rev. C | Page 11 of 20
T
A
= 25°C
DATA RATE = 25Mbps
C
L
= 50pF
1 CHANNEL
5ns/DIV
400mV/DIV
04865-037
Figure 23. Eye Diagram at Y Output
(1.2 V→1.8 V Level Translation, 25 Mbps)
5ns/DIV
200mV/DIV
T
A
= 25°C
DATA RATE = 25Mbps
C
L
= 50pF
1 CHANNEL
04865-038
Figure 24. Eye Diagram at A Output
(1.8 V→1.2 V Level Translation, 25 Mbps)
T
A
= 25°C
DATA RATE = 50Mbps
3ns/DIV
500mV/DIV
C
L
= 50pF
1 CHANNEL
04865-039
Figure 25. Eye Diagram at Y Output
(1.8 V→3.3 V Level Translation, 50 Mbps)
T
A
= 25°C
DATA RATE = 50Mbps
C
L
= 15pF
1 CHANNEL
3ns/DIV
400mV/DIV
04865-040
Figure 26. Eye Diagram at A Output
(3.3 V→1.8 V Level Translation, 50 Mbps)
T
A
= 25°C
DATA RATE = 50Mbps
C
L
= 50pF
1 CHANNEL
3ns/DIV
1V/DIV
04865-041
Figure 27. Eye Diagram at Y Output
(3.3 V→5 V Level Translation, 50 Mbps)
T
A
= 25°C
DATA RATE = 50Mbps
C
L
= 15pF
1 CHANNEL
3ns/DIV
800mV/DIV
04865-042
Figure 28. Eye Diagram at A Output
(5 V→3.3 V Level Translation, 50 Mbps)
ADG3308/ADG3308-1
Rev. C | Page 12 of 20
TEST CIRCUITS
ADG3308/
ADG3308-1
/
ADG3308-2
Ax Yx
GND
V
CCA
V
CCY
EN
K1
K2
I
OH
I
OL
0.1µF
0.1µF
04865-043
Figure 29. VOH/VOL Voltages at Pin A
ADG3308/
ADG3308-1
/
ADG3308-2
Yx
xA
GND
V
CCY
V
CCA
EN
K1
K2
I
OH
I
OL
0.1µF 0.1µF
04865-044
Figure 30. VOH/VOL Voltages at Pin Y
ADG3308/
ADG3308-1
/
ADG3308-2
Ax Yx
GND
VCCA VCCY
K
0.1µF
0.1µF
A
EN
04865-045
Figure 31. Three-State Leakage Current at Pin A
ADG3308/
ADG3308-1
/
ADG3308-2
Ax Yx
GND
VCCA VCCY
K
0.1µF
0.1µF
EN
A
04865-046
Figure 32. Three-State Leakage Current at Pin Y
ADG3308/
ADG3308-1
/
ADG3308-2
Ax Yx
GND
V
CCA
V
CCY
K
0.1µF
0.1µF
EN A
04865-047
Figure 33. EN Pin Leakage Current
ADG3308/
ADG3308-1
/
ADG3308-2
Ax Yx
GND
V
CCA
V
CCY
EN
CAPACITANCE
METER
04865-048
Figure 34. Capacitance at Pin A
ADG3308/
ADG3308-1
/
ADG3308-2
Ax Yx
GND
V
CCA
V
CCY
EN
CAPACITANCE
METER
04865-049
Figure 35. Capacitance at Pin Y
ADG3308/ADG3308-1
Rev. C | Page 13 of 20
90%
VEN
VY/VA
t
EN1
VA/VY
VCCY
0V
VCCA/VCCY
0V
VCCY/VCCA
0V
10%
VEN
VY/VA
t
EN2
VA/VY
VCCY
0V
0V
VCCY/VCCA
0V
SIGNAL SOURCE
VEN
RT
50Ω
1MΩ
VA
15pF
ADG3308/
ADG3308-1
/
ADG3308-2
EN GND
RS
50Ω
0.1µF
1MΩ
VCCA
Ax VY
VCCY
xY
K2
Z0 = 50Ω
K1
10µF
+
0.1µF 10µF
+
Y→A DIRECTION
SIGNAL SOURCE
VEN
RT
50Ω
VA
ADG3308/
ADG3308-1
/
ADG3308-2
EN GND
RS
50Ω
0.1µF
VCCA
Ax
1MΩ
VY
50pF
1MΩ
VCCY
xY
K2
Z0 = 50Ω
K1
10µF
+
0.1µF 10µF
+
A
→Y DIRECTION
VCCA/VCCY
NOTES
1.
t
EN IS WHICHEVER IS LARGER BETWEEN
t
EN1 AND
t
EN2
IN BOTH A→Y AND Y→A DIRECTIONS.
04865-050
Figure 36. Enable Time
ADG3308/ADG3308-1
Rev. C | Page 14 of 20
50%
50%
10%
90%
VA
VY
tF, A→YtR, A→Y
tP, A→YtP, A→Y
ADG3308/
ADG3308-1
/
ADG3308-2
GND
SIGNAL
SOURCE
VA
RT
50Ω
RS
50Ω
EN
VCCA VCCY
VY
50pF
Z0 = 50Ω
xY xA
0.1µF 10µF
+
0.1µF 10µF
+
04865-051
Figure 37. Switching Characteristics (A→Y Level Translation)
50%
50%
10%
90%
V
Y
V
A
t
F, Y→A
t
R, Y→A
t
P, Y→A
t
P, Y→A
ADG3308/
ADG3308-1
/
ADG3308-2
GND
SIGNAL
SOURCE
V
Y
R
T
50Ω
R
S
50Ω
EN
V
CCA
V
CCY
V
A
15pF
Z
0
= 50Ω
xY xA
0.1µF 10µF
+
0.1µF 10µF
+
04865-052
Figure 38. Switching Characteristics (Y→A Level Translation)
ADG3308/ADG3308-1
Rev. C | Page 15 of 20
TERMINOLOGY
VIHA
Logic input high voltage at Pin A1 to Pin A8.
VILA
Logic input low voltage at Pin A1 to Pin A8.
VOHA
Logic output high voltage at Pin A1 to Pin A8.
VOLA
Logic output low voltage at Pin A1 to Pin A8.
CA
Capacitance measured at Pin A1 to Pin A8 (EN = 0).
ILA, HIGH-Z
Leakage current at Pin A1 to Pin A8 when EN = 0 (high
impedance state at Pin A1 to Pin A8).
VIHY
Logic input high voltage at Pin Y1 to Pin Y8.
VILY
Logic input low voltage at Pin Y1 to Pin Y8.
VOHY
Logic output high voltage at Pin Y1 to Pin Y8.
VOLY
Logic output low voltage at Pin Y1 to Pin Y8.
CY
Capacitance measured at Pin Y1 to Pin Y8 (EN = 0).
ILY, HIGH-Z
Leakage current at Pin Y1 to Pin Y8 when EN = 0 (high
impedance state at Pin Y1 to Pin Y8).
VIHEN
Logic input high voltage at the EN pin.
VILEN
Logic input low voltage at the EN pin.
CEN
Capacitance measured at EN pin.
ILEN
Enable (EN) pin leakage current.
tEN
Three-state enable time for Pin A1 to Pin A8/Pin Y1 to Pin Y8.
tP, A → Y
Propagation delay when translating logic levels in the A→Y
direction.
tR, A→Y
Rise time when translating logic levels in the A→Y direction.
tF, A → Y
Fall time when translating logic levels in the A→Y direction.
DMAX, A→Y
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
Table 1.
tSKEW, A→Y
Difference between propagation delays on any two channels
when translating logic levels in the A→Y direction.
tPPSKEW, A→Y
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A→Y direction.
tP, Y → A
Propagation delay when translating logic levels in the Y→A
direction.
tR, Y→A
Rise time when translating logic levels in the Y→A direction.
tF, Y → A
Fall time when translating logic levels in the Y→A direction.
DMAX, Y→A
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
Table 1.
tSKEW, Y→A
Difference between propagation delays on any two channels
when translating logic levels in the Y→A direction.
tPPSKEW, Y→A
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the Y→A direction.
VCCA
VCCA supply voltage.
VCCY
VCCY supply voltage.
ICCA
VCCA supply current.
ICCY
VCCY supply current.
IHIGH-ZA
VCCA supply current during three-state mode (EN = 0).
IHIGH-ZY
VCCY supply current during three-state mode (EN = 0).
ADG3308/ADG3308-1
Rev. C | Page 16 of 20
THEORY OF OPERATION
The ADG3308/ADG3308-1/ADG3308-2 level translators allow
the level shifting necessary for data transfer in a system where
multiple supply voltages are used. The device requires two
supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the
logic levels on each side of the device. When driving the A pins,
the device translates the VCCA compatible logic levels to VCCY
compatible logic levels available at the Y pins. Similarly, because
the device is capable of bidirectional translation, when driving
the Y pins the VCCY compatible logic levels are translated to the
VCCA compatible logic levels available at the A pins. When
EN = 0, the A1 pin to the A8 pin and the Y1 pin to the Y8 pin
are three-stated. When EN is driven high, the ADG3308/
ADG3308-1/ADG3308-2 go into normal operation mode and
perform level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3308/ADG3308-1/ADG3308-2 consist of eight
bidirectional channels. Each channel can translate logic levels
in either the A→Y or the Y→A direction. They use a one-shot
accelerator architecture, ensuring excellent switching charac-
teristics. Figure 39 shows a simplified block diagram of a
bidirectional channel.
ONE-SHOT GENERATOR
6kΩ
6kΩ
Y
V
CCA
V
CCY
T2T1
T3T4
AP
N
U1 U2
U4 U3
0
4865-053
Figure 39. Simplified Block Diagram of an
ADG3308/ADG3308-1/ADG3308-2 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), whereas the
translation in the Y→A direction is performed using the U3
inverter and U4 inverter. The one-shot generator detects a rising
or falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS transistors
(T1 and T2) for a rising edge, or the NMOS transistors (T3 and
T4) for a falling edge. This charges/discharges the capacitive load
faster, resulting in fast rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3308/ADG3308-1/
ADG3308-2, the circuit that drives the input of the device
should be able to ensure rise/fall times of less than 3 ns when
driving a load consisting of a 6 kΩ resistor in parallel with the
input capacitance of the ADG3308/ADG3308-1/ADG3308-2
channel.
OUTPUT LOAD REQUIREMENTS
The ADG3308/ADG3308-1/ADG3308-2 level translators are
designed to drive CMOS-compatible loads. If current-driving
capability is required, it is recommended to use buffers between
the ADG3308/ADG3308-1/ADG3308-2 outputs and the load.
ENABLE OPERATION
The ADG3308/ADG3308-1/ADG3308-2 provide three-state
operation at the A I/O pins and the Y I/O pins by using the
enable (EN) pin, as shown in Table 4.
Table 4. Truth Table
EN Y I/O Pins A I/O Pins
0 High-Z1High-Z1
1 Normal operation2Normal operation2
1 High impedance state.
2 In normal operation, the ADG3308/ADG3308-1/ADG3308-2 perform level
translation.
When EN = 0, the ADG3308/ADG3308-1/ADG3308-2 enter
into three-state mode. In this mode, the current consumption
from both the VCCA and VCCY supplies is reduced, allowing the
user to save power, which is critical, especially in battery-
operated systems. The EN input pin can only be driven with
VCCY compatible logic levels for the ADG3308, whereas the
ADG3308-1/ADG3308-2 can be driven with either VCCA- or
VCCY compatible logic levels.
POWER SUPPLIES
For proper operation of the device, the voltage applied to the
VCCA must always be less than or equal to the voltage applied
to VCCY. To meet this condition, the recommended power-up
sequence is VCCY first and then VCCA. The ADG3308/ADG3308-1/
ADG3308-2 operate properly only after both supply voltages
reach their nominal values. It is not recommended to use the part
in a system where, during power-up, VCCA may be greater than
VCCY due to a significant increase in the current taken from the
VCCA supply. For optimum performance, the VCCA and VCCY pins
should be decoupled to GND as close as possible to the device.
ADG3308/ADG3308-1
Rev. C | Page 17 of 20
DATA RATE
The maximum data rate at which the device is guaranteed to
operate is a function of the VCCA and VCCY supply voltage
combination and the load capacitance. It represents the maximum
frequency of a square wave that can be applied to the I/O pins,
ensuring that the device operates within the data sheet
specifications in terms of output voltage (VOL and VOH) and
power dissipation (the junction temperature does not exceed the
value specified under the Absolute Maximum Ratings section).
Table 5 shows the guaranteed data rates at which the ADG3308/
ADG3308-1/ADG3308-2 can operate in both directions (A→Y
level translation or Y→A level translation) for various VCCA and
VCCY supply combinations.
Table 5. Guaranteed Data Rates1
VCCY
VCCA 1.8 V (1.65 V to 1.95 V) 2.5 V (2.3 V to 2.7 V) 3.3 V (3.0 V to 3.6 V) 5 V (4.5 V to 5.5 V)
1.2 V (1.15 V to 1.3 V) 25 Mbps 30 Mbps 40 Mbps 40 Mbps
1.8 V (1.65 V to 1.95 V) 45 Mbps 50 Mbps 50 Mbps
2.5 V (2.3 V to 2.7 V) 60 Mbps 50 Mbps
3.3 V (3.0 V to 3.6 V) 50 Mbps
5 V (4.5 V to 5.5 V)
1 The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.
ADG3308/ADG3308-1
Rev. C | Page 18 of 20
APPLICATIONS
The ADG3308/ADG3308-1/ADG3308-2 are designed for digital
circuits that operate at different supply voltages; therefore, logic
level translation is required. The lower voltage logic signals are
connected to the A pins, and the higher voltage logic signals to
the Y pins. The ADG3308/ADG3308-1/ADG3308-2 can provide
level translation in both directions (A→Y or Y→A) on all eight
channels, eliminating the need for a level translator IC for each
direction. The internal architecture allows the ADG3308/
ADG3308-1/ADG3308-2 to perform bidirectional level
translation without an additional signal to set the direction in
which the translation is made. It also allows simultaneous data
flow in both directions on the same part, for example, when two
channels translate in the A→Y direction while the other two
translate in the Y→A direction. This simplifies the design by
eliminating the timing requirements for the direction signal
and reduces the number of ICs used for level translation.
Figure 40 shows an application where a 3.3 V microprocessor
can read or write data to and from a 1.8 V peripheral device
using an 8-bit bus.
V
CCA
A1
A2
A3
A4
EN GND
Y4
Y3
Y2
Y1
V
CCY
MICROPROCESSOR/
MICROCONTROLLER/
DSP
3.3V 1.8V
PERIPHERAL
DEVICE
100nF 100nF
I/O
H
1
I/O
H
4
I/O
H
3
I/O
H
2
I/O
L
1
I/O
L
4
I/O
L
3
I/O
L
2
GND
GND
A5
A6
A7
A8Y8
Y7
Y6
Y5
ADG3308/
ADG3308-1
/
ADG3308-2
I/O
H
5
I/O
H
8
I/O
H
7
I/O
H
6
I/O
L
5
I/O
L
8
I/O
L
7
I/O
L
6
04865-056
Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit
When the application requires level translation between
a microprocessor and multiple peripheral devices, the
ADG3308/ADG3308-1/ADG3308-2 I/O pins can be three-
stated by setting EN = 0. This feature allows the ADG3308/
ADG3308-1/ADG3308-2 to share the data buses with other
devices without causing contention issues. Figure 41 shows an
application where a 3.3 V microprocessor is connected to 1.8 V
peripheral devices using the three-state feature.
ADG3308/
ADG3308-1
/
ADG3308-2
MICROPROCESSOR/
MICROCONTROLLER/
DSP
I/O
H
1
CS
3.3V 1.8V
PERIPHERAL
DEVICE 1
PERIPHERAL
DEVICE 2
100nF 100nF
I/O
H
2
I/O
H
8
I/O
H
7
I/O
H
6
I/O
H
5
I/O
H
4
I/O
H
3
GND
1.8V
100nF 100nF
I/O
L
1
I/O
L
2
I/O
L
8
I/O
L
7
I/O
L
6
I/O
L
5
I/O
L
4
I/O
L
3
GND
GND
Y1
V
CCY
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN GND
A8
A7
A6
A5
A4
A3
A2
A1
V
CCA
ADG3308/
ADG3308-1
/
ADG3308-2
I/O
L
1
I/O
L
2
I/O
L
8
I/O
L
7
I/O
L
6
I/O
L
5
I/O
L
4
I/O
L
3
Y1
V
CCY
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN GND
A8
A7
A6
A5
A4
A3
A2
A1
V
CCA
04865-055
Figure 41. 1.8 V to 3.3 V Level Translation Circuit
Using the Three-State Feature
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board
layout is important in the overall performance of the circuit. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each VCC pin (VCCA and
VCCY) should be bypassed using low effective series resistance
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the VCCA and VCCY pins. The parasitic induc-
tance of the high speed signal track can cause significant overshoot.
This effect can be reduced by keeping the length of the tracks as
short as possible. A solid copper plane for the return path
(GND) is also recommended.
ADG3308/ADG3308-1
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARIT
Y
0.10
Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
3.75
BCS SQ
4.00
BSC SQ
COMPLIANT
TO
JEDEC STANDARDS MO-220-VGGD-1
082207-B
1
0.50
BSC
PIN 1
INDICATOR
0.75
0.60
0.50
TOP VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDI
C
ATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
2.25
2.10 SQ
1.95
20
6
16
10
11
15
5
EXPOSED
PAD
(BOTTOM VIEW)
0.60 MAX
0.60 MAX
0.25 MIN
Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ADG3308/ADG3308-1
Rev. C | Page 20 of 20
070606- A
A
1
23
4
B
C
D
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
E
2.06
2.00
1.94
2.56
2.50
2.44
A1 BALL
IDENTIFIER
0.65
0.59
0.53
0.28
0.24
0.20
0.36
0.32
0.28
0.50 BSC
PITCH
Figure 44. 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-2)
Dimensions shown in millimeters
081707-B
A
1
23
4
B
C
D
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
E
2.06
2.00
1.94
2.56
2.50
2.44
A1 BALL
IDENTIFIER
0.28
0.24
0.20
0.36
0.32
0.28
0.50 BSC
PITCH
0.042
0.040
0.037
0.645
0.585
0.525
Figure 45. Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-20-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG3308BRUZ1−40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG3308BRUZ-REEL1−40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG3308BRUZ-REEL71−40°C to +85°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG3308BCPZ-REEL1−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
ADG3308BCPZ-REEL71−40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
ADG3308BCBZ-1-RL71−40°C to +85°C 20-Ball Wafer Level Chip Scale Package [WLCSP] CB-20-2
ADG3308BCBZ-1-REEL1−40°C to +85°C 20-Ball Wafer Level Chip Scale Package [WLCSP] CB-20-2
ADG3308BCBZ-2-RL71−40°C to +85°C Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP] CB-20-3
ADG3308BCBZ-2-REEL1−40°C to +85°C Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP] CB-20-3
T
1 Z = RoHS Compliant Part.
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D04865-0-9/07(C)
TTT
