intel" 270010 1M (128K x 8) CHMOS EPROM m JEDEC Approved EPROM Pinouts m Fast Programming 32-Pin DIP, 32-Pin PLCC Quick-Pulse Programming Simple Upgrade from Lower Algorithm Densities Programming Time as Fast as 15 m Complete Upgrade Capability to Higher Seconds Densities m High-Performance m Versatile EPROM Features 120 ns, + 10% Vec CMOS and TTL Compatibility 30 mA Icc Active Two Line Control @ Surface Mount Packaging Available - Smallest 1 Mbit Footprint in SMT Intels 27C010 is a 5V only, 1,048,576-bit, Erasable Programmable Read Only Memory, organized as 129,536 words of 8 bits. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple upgrades to 8 Mbits in the future in both DIP and PLCC. The 27C010 represents state-of-the-art 1 micron CHMOS manufacturing technology while providing un- equaled performance. Its 120 ns speed (tacc) offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to telecommunications. Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP (CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the design is in full production, the plastic DIP (PDIP) one-time programmable part provides a ower cost alterna- tive that is well adapted for auto insertion. In addition to the JEDEC 32-pin DIP package, Intel also offers a 32-lead PLCC version of the 27C010. This one-time-programmable surface mount device is ideal where board space consumption is a major concern or where surface mount manufacturing technology is being implemented across an entire production line. The 27C010 is equally at home in both a TTL or CMOS environment. It programs as fast as 15 seconds using Intels industry leading Quick-Pulse Programming algorithm. OATA OUTPUTS Veo Oo Q-07 GND o_>- a , eo LETT OE efoutpuT ENABLE Pam CHIP ENABLE cE PROG LOGIC OUTPUT BUFFERS Y . pecopen [Lt Y-GATING AonAre > soNeurs I x : 1,048,576-BIT INPUTS >| DECODER | CELL MATRIX e P 290174-1 Figure 1. Block Diagram September 1990 5-113 Order Number: 290174-004el 9% 15 [16] [12] [ss] [15] [20] 02 | ono | os | 0, | Os | 06 N i ' + [4 ' i i 290174-3 27C010 Pin Names Ag-Aig | ADDRESSES cE CHIP ENABLE OE OUTPUT ENABLE Qo-O7 | OUTPUTS PEM | PROGRAM NC NO INTERNAL CONNECT 27C010 SMbit | 4Mbit | 2Mbit | 542K | 256K 256K 512K 2Mbit | 4Mbit | SMbit Aig Vpp Vpp Vpp OH 32919 Vee Voc Voo Vec Ate Ate Ae AygC42 31 Pow PGM | Aig Ais Ais Ais Ais Ais Vep. Ays45 ofc Vec Voc Aqz | An? Ai7 Anz Ay Ai Ata Ai2 Ay Os 290 Ay, Ata Aig Arq | Ata Aus Ay A; A? Ay A? a, Cs 28F ays Aas Ais Aig | Ais Ai3 As As Ag As As aC 27D As Ag Aa Ag Ag Ag As As As As As as C7 26PAs Ag Ag Ag Ag Ag Aa Ag Ag Ag Aa 4,18 23EIAy, 1 An Ar | Ans Ait Ag Ag Ag Ag Ag Aso 241 oF OE | GE/Vpp| OE GE | OE/Vpp A2 A2 Ap Ae Aa A, CJ 10 23 Ato 10 Ato Aro | Ato Aio Ay Ay Ay Ay Ay Aint 2 cE ce CE ce te Ao Ao Ag Ao Ao AoC 12 2107 O7 Q7 O7 07 07 O Oo O Oo Oo So 413 201 06 O6 Og O6 O6 O6 O71 0; 0; O71 O71 O,Cy14 199) Og Os Os Os Os Os Oz O2 O2 Oe Oo O2 C415 180, Os O4 O4 Og O4 GND | GND | GND | GND | GND GND Chis 17905 03 O3 OQ, | Og O3 290174-2 Figure 2. DIP Pin Configuration am(asexxa)| f |} f | t |} tt td tf dae N27C010 (128Kx8) | ay | Ais | Ave | Yer | Yoo | Pomp nc / 4 Wap es =|4,[ 5 } 29 Jayl > =|Ae] 6 ] 28 FAi3| ~|As] 7 } [2 ag | 4,1 8 } [2 ag | 32 LEAD PLCC _ 9 0.450" x 0.550" | 25 Ta As [>] TOP VIEW Wh =] A, ] 10 [24 oe | Jap [2s Ayo] +] A> 12 } | 22 | CEL +] 0 13 [ 21 Joy | Figure 3. PLCC Lead Configuration 5-114intel 27C010 EXTENDED TEMPERATURE vamin using Intel's standard bias configuration. iS processing meets or exceeds most industry (EXPRESS) EPROMs burn-in specifications. The EXPRESS product family The Intel EXPRESS EPROM family receives addi- _'S available in both 0C to +70C and 40C to tional processing to enhance product characteris- + 85C operating temperature range versions. Like tics. EXPRESS processing is available for several ll Intel EPROMs, the EXPRESS EPROM family is densities allowing the appropriate memory size to inspected to 0.1% electrical AQL. This allows reduc- match system requirements. EXPRESS EPROMs __ tion or elimination of incoming testing. are available with 168 +8 hour, 125C dynamic EXPRESS EPROM FAMILY OPTIONS Packaging PRODUCT DEFINITIONS Speed CERDIP Type] Operating Temperature| Burn-in 125C (hr) 150V10 QTL Q 0C to 70C 168 +8 T 40C to 85C None L 40C to 85C 168 +8 READ OPERATION DC CHARACTERISTICS Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for: TD27C010(2) Symbol Parameter LD27C010 Test Condition Min Max loc?) Voc Operating Current (mA) 30 OE = CE = Vit, Tambient = 40C Voc Operating Current 30 OE = CE = Vit at High Temperature (mA) Vpp = Voc, Tambient = 85C NOTES: 1. Maximum current is with outputs Og to O7 unloaded. 2. D refers to the CERDIP package. Ypp 1 ad 322) Yee Aye? 32 Pow AysCV3 soPNc. AO 2D Ay ays 28P ays 30 & 7 BS td, mbes ri 8 270010 aq 25 FI Ay ro _| | f | f 4,9 uDoe 4,0 to 23D Aro Adan 220 TE Yee 4 aq folfiz 21 Oy 1 O Mo 13 20 5 O% : 0) pet] 14 19 ewe Os Als : 02 1S 1a wes 0, 290174-5 GnDd] 16 17d 05 Binary Sequence from Ap to Aig, 290174-4 OE = +65V R= 1k Voo= +5V Vpp = +5V GND = OV CE = GND PGM = +5V Burn-in Bias and Timing Diagrams 5-115intel 27010 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. Operating Temperature ............. 0C to 70C(1) perating vemperatur to * WARNING: Stressing the device beyond the Absolute Temperature Under Bias........... 10C to 80C Maximum Ratings may cause permanent damage. Storage Temperature............. 65C to 125C These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. Voltage on Any Pin (except Ag, Voc and Vpp) with Respect to GND ........ 0.6V to 6.5V(2, 8) Voltage on Ag with Respect toGND ............. 0.6V to 13.0V(2) Vpp Program Voltage with Respect toGND........... 0.6V to 14V(2) Voc Supply Voltage with Respect to GND .......... 0.6V to 7.0V(2) READ OPERATION DC CHARACTERISTICS() Vcc = 5.0V + 10% Symboi Parameter Notes Min Typ Max Unit Test Condition lu Input Load Current 7 0.01 1.0 pA | Vin = OV to 5.5V lto Output Leakage Current +10 pA | Vout = OV to 5.5V Isp Voc Standby Current 1.0 mA | CE = Vin 100 pA | CE = Voc +0.2V loc Vcc Operating Current 3 30 mA | CE = Vic = 5 MHz, louT = OMA Ipp Vpp Operating Current 3 10 BA | Vpp = Voc los Output Short Circuit Current 4,6 100 mA Vit Input Low Voltage -0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5 v VoL Output Low Voltage 0.45 v lo, = 2.1 mA Vou Output High Voltage 2.4 Vv lon = 400 pA Vpp Vpp Operating Voltage 5 Voc 9.7 Voc Vv NOTES: 1. Operating temperature is for commercial product defined by this specification. Extended temperature options are available in EXPRESS versions. 2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voitage on input/output pins is Voc + 0.5V which, during transitions, may overshoot to Vcc + 2.0V for periods <20 ns. 3. Maximum active power usage is the sum Ipp + !oc. Maximum current is with outputs Op to O7 unloaded. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. Vpp may be connected directly to Voc, or may be one diode voltage drop below Voc. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 6. Sampled, not 100% tested. 7. Typical limits are at Voc = 5V, Ta = 25C. 8. Absolute Maximum Ratings apply to NC pins. 5-116intel 270010 READ OPERATION AC CHARACTERISTICS() Vcc = 5.0v +10% 27C010-150V10 | 270010-200V10 Versions(4) Voc + 10% | 27C010-120V10 P27C010-150V10 | P27C010-200V10 N27C010-150V10 | N27C010-200v10 | Units Symbol Parameter Notes Min Max Min Max Min Max tacc Address to Output Delay 120 150 200 ns tce CE to Output Delay 2 120 150 200 ns toe OE to Output Delay 2 55 60 70 ns tor OE High to Output HighZ | 39 30 50 60 ns toH Output Hold from 3 0 0 0 ns Addresses, CE or OE Change-Whichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OF may be delayed up to tce-toe after the falling edge of CE without impact on tog. 3. Sampled, not 100% tested. 4, Model Number Prefixes: No Prefix = CERDIP, P = PDIP,N = PLCC. 5-11727010 CAPACITANCE(1) 1, = 25C, f = 1MHz Symbol Parameter Typ(2) | Max | Unit | Conditions Cin Input Capacitance 4 8 pF Vin = OV Cout Output Capacitance 8 12 PF | Vout = OV Cypp Vpp Capacitance 18 25 pF Vpp 5 OV NOTES: 1. Sampled, not 100% tested. 2. Typical values are for Ta = 25C and nominal supply voltages. AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT 24 2.0 5 2.0 INPUT , TEST POINTS OUTPUT 0.45 x 0.8 it <Xu 290174-6 AC test inputs are driven at Voy (2.4V T7) for a Logic 1" and Vor (0.45V tT) for a Logic 0. Input timing begins at Vi} (2.0V TrL) and Vi (0.8V +r,). Output timing ends at Vy and Vic. Input Rise and Fait Times (10% to 90%) < 10 ns. 1.3V 1N914 RL DEVICE UNDER OUT TEST T* CL = 100 pF C_ Includes Jig Capacitance RL = 3.3 Ko 290174-7 AC WAVEFORMS vn case ~ ADDRESSES Agnes vin N , Vin cE / vn sese ed cee +J YY a vn Lone aed t tog }] tacc fon 1 f* vi me " 5 HIGH Z OUTPUTS men VALID OUTPUT te AAW 290174-8 5-118intel 27C010 DEVICE OPERATION The Mode Selection table lists 27C010 operating modes. Read Mode requires a single 5V power supply. All inputs, except Vcc and Vpp, and Ag during intgligent Identifier Mode, are TTL or CMOS. Table 1. Mode Selection Mode Notes | CE | OE | PGM | Ag Ao | Vpp | Voc | Outputs Read 1 Viv | Vit x X x Voc | Voc Dout Output Disable Vit Vin xX xX x Veco Voc High Z Standby Vin Xx X Xx x Vcc Voc High Z Program 2 Vit Vin Vit x x Vpp Vop DIN Program Verify ViL Vit Vin x xX Vpp Vep Dout Program Inhibit Vin x Xx x Vpp Vcp High Z intgligent Manufacturer 2,3 ViL Vit Vio Vit Voc Voc 89H Identifier | Device Vi | Vit Vin | Vin | Veco | Voc 35H NOTES: 1. X can be Vit or Vip. 2. See DC Programming Characteristics for Vcp, Vpp and Vip voltages. 3. Ay-Ag, Ato-Ate = VIL. Read Mode The 27C010 has two control functions: both must be enabled to obtain data at the outputs. CE is the pow- er control and device select. OE controls the output buffers to gate data to the outputs. With addresses stable, the address access time (tacc) equals the delay from CE to output (tc). Outputs display valid data tog after OEs falling edge, assuming tacc and tce times are met. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. Two Line Output Control EPROMs are often used in larger memory arrays. Intel provides two control inputs to accommodate multiple memory connections. Two-line control pro- vides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these two control inputs, an ad- dress decoder should enable CE, while OE should be connected to all memory devices and the sys- tems READ controi line. This assures that only se- lected memory devices have active outputs while deselected memory devices are in Standby Mode. Standby Mode Standby Mode substantially reduces Voc current. When CE = Vjy, the outputs are in a high imped- ance state, independent of OE. 5-119intel 27C010 Program Mode Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all EPROM bits are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Al- though only Os are programmed, the data word can contain both 1s and Os. Ultraviolet light era- sure is the only way to change Os to ''1s. Program Mode is entered when Vpp is raised to 12.75V. Data is introduced by applying an 8-bit word to the output pins. Pulsing PGM low while CE = Vi, and OE = Viy programs that data into the device. Program Verify A verify should be performed following a program operation to determine that bits have been correctly programmed. With Vcc at 6.25V, a substantial pro- gram margin is ensured. The verify is performed with E at V and PGM at Vy. Valid data is available tog after OE falls low. Program inhibit Program Inhibit Mode allows parallel programming of multiple EPROMs with different data. CE-high in- hibits programming of non-targeted devices. Except for CE, parallel EPROMs may have common inputs. inteligent identifier Mode The intgligent identifier Mode will determine an EPROMs manufacturer and device type, allowing programming equipment to automatically match a device with its proper programming algorithm. This mode is activated when a programmer forces 12V +0.5V on Ag. With CE, GE, Ay-Ag, and Aio- Aig at Vit. Ag = Vit will present the manufacturer code and Ag = Vip the device code. This mode functions in the 25C +6C ambient temperature range required during programming. UPGRADE PATH Future upgrade to 2-Mbit, 4-Mbit, and 8-Mbit densi- ties are easily accomplished due to the standardized pin configuration of the 27C010. When the 27C010 is in Read Mode, the PGM input becomes non-func- tional. The PGM and NC pins may be Vj, of Viy. This allows address lines A;7-Ajg to be routed directly to these inputs in anticipation of future density up- grades. A jumper between Vcc and Ajg allows fur- ther upgrade using the Vpp pin. Systems designed for 1-Mbit program memories today can be upgrad- ed to higher densities (2-Mbit, 4-Mbit, and 8-Mbit) in the future with no circuit board changes. SYSTEM CONSIDERATIONS EPROM power switching characteristics require careful device decoupling. System designers are in- terested in 3 supply current issues: standby current levels (Isg), active current levels (icc), and transient current peaks produced by falling and rising edges ot CE. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its Voc and GND. This high fre- quency, low inherent-inductance capacitor should be placed as close as possible to the device. Addi- tionally, for every 8 devices, a 4.7 uF electrolytic capacitor should be placed at the arrays power sup- ply connection between Vcc and GND. The bulk ca- pacitor will overcome voltage slumps caused by PC board trace inductances. ERASURE CHARACTERISTICS Erasure begins when EPROMs are exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain fluorescent lamps have wavelengths in the 3000A-4000A range. Data shows that constant ex- posure to room level fluorescent lighting can erase an EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sun- light. if the device is exposed to these lighting condi- tions for extended periods, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure is exposure to ultraviolet light of wavelength 2537A. The inte- grated dose (UV intensity x exposure time) for era- sure should be a minimum of 15 Wsec/cm2. Erasure time is approximately 15 to 20 minutes using an ul- traviolet lamp with a 12000 4 W/cm? power rating. The EPROM should be placed within 1 inch of the lamp tubes. An EPROM can be permanently dam- aged if the integrated dose exceeds 7258 Wsec/ cm2 (1 week @ 12000 pW/cmz?). 5-120intel 270010 START == ADDRESS = FIRST LOCATION Voc = 6.25 Vpp = 12.75V PROGRAM ONE 100 ys PULSE INCREMENT ADDRESS YES Voc = Vpp = 5.0 COMPARE ALL BYTES TO ORIGINAL DATA PASS FAIL DEVICE PASSED 290174-9 Figure 4. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm mine when the addressed byte has been successful- $ 9 9 9 ly programmed. The algorithm terminates if 25 at- The Quick-Pulse programming algorithm programs tempts fail to program a byte. Intels 27C010. Developed to substantially reduce programming throughput, this algorithm can program = The entire program pulse/byte verify sequence is the 27C010 as fast as 15 seconds. Actual program- performed with Vpp = 12.75V and Vcc = 6.25V. ming time depends on programmer overhead. When programming is complete, all bytes are com- pared to the original data with Voc = Vpp = 5.0V. The Quick-Pulse programming algorithm employs a 100 ys pulse followed by a byte verification to deter- 5-121intel 27 C010 DC PROGRAMMING CHARACTERISTICS T, = 26C +5C Symbol Parameter Notes Min Typ Max | Unit Test Condition Io Input Load Current 1 BA | Vin = Vicor Vin lop Vcc Program Current 1 40 mA | CE = PGM = Vi. Ipp Vpp Program Current 1 50 mA | CE = PGM = Vi, ViL Input Low Voltage ~-0.1 0.8 Vv VIH Input High Voltage 2.4 6.5 Vv VoL Output Low Voltage (Verify) 0.45 Vv lo, = 2.1 mA Vou Output High Voltage (Verify) 3.5 Vv lon = 2.5mA Vip Ag intgligent Identifier Voltage 11.5 12.0 12.5 v Vpp Vpp Program Voitage 2,3 12.5 | 12.75 | 13.0 v Vop Voc Supply Voltage (Program) 2 6.0 6.25 6.5 v AC PROGRAMMING CHARACTERISTICS(4) T, = 25C +5C Symbol Parameter Notes Min Typ Max Unit ~ tyes Vcp Setup Time 2 2 ps typs Vpp Setup Time 2 2 BS tces CE Setup Time 2 ps tas Address Setup Time 2 ps tos Data Setup Time 2 ps tpw PGM Program Pulse Width 95 100 105 pS tou Data Hold Time 2 pS toes OE Setup Time ps toe Data Valid from OE 5 150 ns torp OE High to Output High Z 5,6 130 ns taH Address Hold Time pS NOTES: 1. Maximum current is with outputs Op-O7 unloaded. 2. Vop must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming, a 0.1 yF capacitor is required across Vpp and GND to suppress spurious voltage transients which can damage the device. 4. See AC Input/Output Reference Waveform for timing measurements. 5. tog and tprp are device characteristics but must be accommodated by the programmer. 6. Sampied, not 100% tested. 5-122intel 27C010 PROGRAMMING WAVEFORMS VERIFY -w ADDRESSES a v, x ADORESS STABLE DATA 12.75V Ver 5.0v yp. 1 6.25V Voc 5.0V Vine Vin DATA IN STABLE 1 jo-'os are HIGH Z f ~ DATA OUT VALIO 2 tore ces ___,] Pam Mu tow lors . ee ff a \ / Mu 290174-10 REVISION HISTORY Number Description Revised general datasheet structure, text to.improve clarity. 04 Added PDIP package Combined TTL/NMOS and CMOS Read Operation DC Characteristics tables. Deleted 4 Meg and 8 Meg PLCC pinout references. 5-123