CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
36-Mbit QDR® II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-57832 Rev. *C Revised December 8, 2011
36-Mbit QDR® II+ SRAM 4-Word Burst A rchitecture ( 2.0 Cycle Read Latency)
Features
■Separate independent read and write data ports
❐Supports concurrent transactions
■450 MHz clock for high bandwidth
■4-word burst for reducing address bus frequency
■Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
■Available in 2.0 clock cycle latency
■Two input clocks (K and K) for precise DDR timing
❐SRAM uses rising edges only
■Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■Data valid pin (QVLD) to indicate valid data on the output
■Single multiplexed address input bus latches address inputs
for read and write ports
■Separate port selects for depth expansion
■Synchronous internally self-timed writes
■QDR® II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
■Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■Available in × 8, × 9, × 18, and × 36 configurations
■Full data coherency, providing most current data
■Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
❐Supports both 1.5 V and 1.8 V I/O supply
■HSTL inputs and variable drive HSTL output buffers
■Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■Offered in both Pb-free and non Pb-free packages
■JTAG 1149.1 compatible test access port
■Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1241KV18 – 4 M × 8
CY7C1256KV18 – 4 M × 9
CY7C1243KV18 – 2 M × 18
CY7C1245KV18 – 1 M × 36
Functional Description
The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and
CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C1241KV18), 9-bit words (CY7C1256KV18), 18-bit
words (CY7C1243KV18), or 36-bit words (CY7C1245KV18) that
burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description 450 MHz 400 MHz 375 MHz 333 MHz Unit
Maximum operating frequency 450 400 375 333 MHz
Maximum operating current × 8 710 650 620 560 mA
× 9 710 650 620 560
× 18 720 660 630 570
× 36 1020 920 870 790
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 2 of 32
Logic Block Diagram (CY7C1241KV18)
1M x 8 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
20
32
8
NWS[1:0]
VREF
Write Add. Decode
Write
Reg
16
A(19:0)
20
1M x 8 Array
1M x 8 Array
1M x 8 Array
8
CQ
CQ
DOFF
Q[7:0]
8
QVLD
8
8
8
Write
Reg
Write
Reg
Write
Reg
Logic Block Diagram (CY7C1256KV18)
Q[8:0]
9
1M x 9 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
36
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
18
A(19:0)
20
1M x 9 Array
1M x 9 Array
1M x 9 Array
9
CQ
CQ
DOFF
QVLD
9
9
9
Write
Reg
Write
Reg
Write
Reg
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 3 of 32
Logic Block Diagram (CY7C1243KV18)
512K x 18 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
72
18
BWS[1:0]
VREF
Write Add. Decode
Write
Reg
36
A(18:0)
19
512K x 18 Array
512K x 18 Array
512K x 18 Array
18
CQ
CQ
DOFF
Q[17:0]
QVLD
18
18
18
Write
Reg
Write
Reg
Write
Reg
18
Logic Block Diagram (CY7C1245KV18)
256K x 36 Array
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
18
144
36
BWS[3:0]
VREF
Write Add. Decode
Write
Reg
72
A(17:0)
18
256K x 36 Array
256K x 36 Array
256K x 36 Array
36
CQ
CQ
DOFF
Q[35:0]
QVLD
36
36
36
Write
Reg
Write
Reg
Write
Reg
36
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 4 of 32
Contents
Pin Configurations ...........................................................5
165-ball FBGA (13 × 15 × 1.4 mm) pinout ..................5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Read Operations .........................................................9
Write Operations .........................................................9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion .......................................................10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
Valid Data Indicator (QVLD) ...................................... 10
PLL ............................................................................ 10
Application Example ...................................................... 10
Truth Table ...................................................................... 11
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ......................................14
Test Access Port ....................................................... 14
Performing a TAP Reset ........................................... 14
TAP Registers ...........................................................14
TAP Instruction Set ...................................................14
TAP Controller State Diagram .......................................16
TAP Controller Block Diagram ......................................17
TAP Electrical Characteristics ......................................17
TAP AC Switching Characteristics ...............................18
TAP Timing and Test Conditions .................................. 19
Identification Register Definitions ................................ 20
Scan Register Sizes ....................................................... 20
Instruction Codes ........................................................... 20
Boundary Scan Order .................................................... 21
Power Up Sequence in QDR II+ SRAM ......................... 22
Power Up Sequence ................................................. 22
PLL Constraints ......................................................... 22
Maximum Ratings ........................................................... 23
Operating Range ............................................................. 23
Neutron Soft Error Immunity ......................................... 23
Electrical Characteristics ............................................... 23
DC Electrical Characteristics ..................................... 23
AC Electrical Characteristics ..................................... 25
Capacitance .................................................................... 25
Thermal Resistance ........................................................ 25
AC Test Loads and Waveforms ..................................... 25
Switching Characteristics .............................................. 26
Switching Waveforms .................................................... 27
Read/Write/Deselect Sequence ................................ 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagram ............................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC Solutions ......................................................... 32
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 5 of 32
Pin Configurations
The pin configurations for CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 follow. [2]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1241KV18 (4 M × 8)
12345678910 11
ACQ NC/72M A WPS NWS1KNC/144M RPS AACQ
BNC NC NC A NC/288M K NWS0ANCNCQ3
CNC NC NC VSS ANCAV
SS NC NC D3
DNC D4 NC VSS VSS VSS VSS VSS NC NC NC
ENC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2
FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
GNC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1
KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
LNC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0
MNC NC NC VSS VSS VSS VSS VSS NC NC D0
NNC D7 NC VSS AAAV
SS NC NC NC
PNC NC Q7 A A QVLD A A NC NC NC
RTDOTCKAAANCAAATMSTDI
CY7C1256KV18 (4 M × 9)
12345678910 11
ACQ NC/72M A WPS NC K NC/144M RPS AACQ
BNC NC NC A NC/288M K BWS0ANCNCQ4
CNC NC NC VSS ANCAV
SS NC NC D4
DNC D5 NC VSS VSS VSS VSS VSS NC NC NC
ENC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3
FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
GNC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2
KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
LNC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1
MNC NC NC VSS VSS VSS VSS VSS NC NC D1
NNC D8 NC VSS AAAV
SS NC NC NC
PNC NC Q8 A A QVLD A A NC D0 Q0
RTDOTCKAAANCAAATMSTDI
Note
2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 6 of 32
CY7C1243KV18 (2 M × 18)
12345678910 11
ACQ NC/144M A WPS BWS1KNC/288M RPS ANC/72MCQ
BNC Q9 D9 A NC K BWS0ANCNCQ8
CNC NC D10 VSS ANCAV
SS NC Q7 D8
DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
NNC D17 Q16 VSS AAAV
SS NC NC D1
PNC NC Q17 A A QVLD A A NC D0 Q0
RTDOTCKAAANCAAATMSTDI
CY7C1245KV18 (1 M × 36)
12345678910 11
ACQ NC/288M NC/72M WPS BWS2KBWS1RPS A NC/144M CQ
BQ27 Q18 D18 A BWS3KBWS
0AD17Q17Q8
CD27 Q28 D19 VSS ANCAV
SS D16 Q7 D8
DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
ND34 D26 Q25 VSS AAAV
SS Q10 D9 D1
PQ35 D35 Q26 A A QVLD A A Q9 D0 Q0
RTDOTCKAAANCAAATMSTDI
Pin Configurations (continued)
The pin configurations for CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 follow. [2]
165-ball FBGA (13 × 15 × 1.4 mm) pinout
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 7 of 32
Pin Definitions
Pin Name I/O Pin Description
D[x:0] Input-
synchronous
Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C1241KV18 D[7:0]
CY7C1256KV18 D[8:0]
CY7C1243KV18 D[17:0]
CY7C1245KV18 D[35:0]
WPS Input-
synchronous
Write port select active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1
Input-
synchronous
Nibble write select 0, 1 active LOW (CY7C1241KV18 only). Sampled on the rising edge of the K
and K clocks when write operations are active. Used to select which nibble is written into the device
during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
synchronous
Byte write select 0, 1, 2 and 3 active LOW. Sampled on the rising edge of the K and K clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1256KV18 BWS0 controls D[8:0]
CY7C1243KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1245KV18 BWS0 controls D[8:0], BWS1 controls D[17:9],
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A Input-
synchronous
Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 4 M × 8 (4 arrays each of 1 M × 8) for CY7C1241KV18, 4 M × 9 (4 arrays each of 1 M × 9)
for CY7C1256KV18, 2 M × 18 (4 arrays each of 512 K × 18) for CY7C1243KV18 and 1 M × 36 (4 arrays
each of 256 K × 36) for CY7C1245KV18. Therefore, only 20 address inputs are needed to access the
entire memory array of CY7C1241KV18 and CY7C1256KV18, 19 address inputs for CY7C1243KV18
and 18 address inputs for CY7C1245KV18. These inputs are ignored when the appropriate port is
deselected.
Q[x:0] Outputs-
synchronous
Data output signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tri-stated.
CY7C1241KV18 Q[7:0]
CY7C1256KV18 Q[8:0]
CY7C1243KV18 Q[17:0]
CY7C1245KV18 Q[35:0]
RPS Input-
synchronous
Read port select active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the K clock. Each read access consists of a burst of four sequential transfers.
QVLD Valid output
indicator
Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
KInput clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 26.
CQ Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 26.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 8 of 32
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF Input PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull-up through a 10 K or less pull-up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with QDR I timing.
TDO Output TDO for JTAG
TCK Input TCK pin for JTAG
TDI Input TDI pin for JTAG
TMS Input TMS pin for JTAG
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
VREF Input-
reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD Power supply Power supply inputs to the core of the device
VSS Ground Ground for the device
VDDQ Power supply Power supply inputs for the outputs of the device
Pin Definitions (continued)
Pin Name I/O Pin Description
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 9 of 32
Functional Overview
The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18,
CY7C1245KV18 are synchronous pipelined burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ completely
eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1241KV18, four 9-bit data transfers in the case of
CY7C1256KV18, four 18-bit data transfers in the case of
CY7C1243KV18, and four 36-bit data transfers in the case of
CY7C1245KV18, in two clock cycles.
These devices operate with a read latency of two cycles when
DOFF pin is tied HIGH. When DOFF pin is set LOW or connected
to VSS then device behaves in QDR I mode with a read latency
of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, NWS[x:0], BWS[x:0]) inputs
pass through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1243KV18 is described in the following sections. The
same basic descriptions apply to CY7C1241KV18,
CY7C1256KV18 and CY7C1245KV18.
Read Operations
The CY7C1243KV18 is organized internally as four arrays of
512 K × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
When the read port is deselected, the CY7C1243KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The
72 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second write request. Write
accesses can be initiated on every other rising edge of the
positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1243KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate byte write select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the byte write select input during the
data portion of a write enables the data stored in the device for
that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Concurrent Transactions
The read and write ports on the CY7C1243KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 10 of 32
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations can not be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in
alternating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C1243KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ =1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ is
referenced with respect to K. These are free-running clocks and
are synchronized to the input clock of the QDR II+. The timing
for the echo clocks is shown in the Switching Characteristics on
page 26.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time). For information refer to the application note PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1 shows two QDR II+ used in an application.
Figure 1. Application Example
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Vt
Vt
Vt
R
R
D
AK
SRAM #2
RQ = 250 ohms
ZQ
CQ/CQ
Q
K
RPS WPS BWS
D
AK
SRAM #1 CQ/CQ
Q
K
RPS WPS BWS
RPS
WPS
BWS
CLKIN1/CLKIN1
R = 50ohms, Vt = V /2
DDQ
R
RQ = 250 ohms
ZQ
R
CLKIN2/CLKIN2
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 11 of 32
Truth Table
The truth table for CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 follows. [3, 4, 5, 6, 7, 8]
Operation KRPS WPS DQ DQ DQ DQ
Write cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L–H H [9] L [10] D(A) at K(t + 1)D(A + 1) at K(t + 1)D(A + 2) at K(t + 2)D(A + 3) at K(t + 2)
Read cycle:
(2.0 cycle latency)
Load address on the rising
edge of K; wait two cycles;
read data on two
consecutive K and K rising
edges.
L–H L [10] X Q(A) at K(t + 2)Q(A + 1) at K(t + 2)Q(A + 2) at K(t + 3)Q(A + 3) at K(t + 3)
NOP: No operation L–H H H D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock stopped Stopped X X Previous state Previous state Previous state Previous state
Notes
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
4. Device powers up deselected with the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 12 of 32
Write Cycle Descriptions
The write cycle description table for CY7C1241KV18 and CY7C1243KV18 follows. [11, 12]
BWS0/
NWS0
BWS1/
NWS1
KKComments
L L L–H – During the data portion of a write sequence
CY7C1241KV18 both nibbles (D[7:0]) are written into the device.
CY7C1243KV18 both bytes (D[17:0]) are written into the device.
L L – L–H During the data portion of a write sequence
CY7C1241KV18 both nibbles (D[7:0]) are written into the device.
CY7C1243KV18 both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence
CY7C1241KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1243KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence
CY7C1241KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1243KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence
CY7C1241KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1243KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence
CY7C1241KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1243KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1256KV18 follows. [11, 13]
BWS0K K Comments
L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L – L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Notes
11. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
12. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
13. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 13 of 32
Write Cycle Descriptions
The write cycle description table for CY7C1245KV18 follows. [14, 15]
BWS0BWS1BWS2BWS3K K Comments
L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Notes
14. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
15. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 14 of 32
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power-up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 16. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 20).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 17. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The section Boundary Scan Order on page 21 shows the order
in which the bits are connected. Each bit corresponds to one of
the bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 20.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 20. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 15 of 32
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a high Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 16 of 32
TAP Controller State Diagram
The state diagram for the TAP controller follows. [16]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
Note
16. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 17 of 32
TAP Controller Block Diagram
0
012..29
3031
Boundary Scan Register
Identification Register
012..
.
.108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [17, 18, 19] Description Test Conditions Min Max Unit
VOH1 Output HIGH voltage IOH =2.0 mA 1.4 – V
VOH2 Output HIGH voltage IOH =100 A1.6–V
VOL1 Output LOW voltage IOL = 2.0 mA – 0.4 V
VOL2 Output LOW voltage IOL = 100 A–0.2V
VIH Input HIGH voltage 0.65 × VDD VDD + 0.3 V
VIL Input LOW voltage –0.3 0.35 × VDD V
IXInput and output load current GND VI VDD –5 5 A
Notes
17. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 23.
18. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
19. All voltage referenced to ground.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 18 of 32
TAP AC Switching Characteristics
Over the Operating Range
Parameter [20, 21] Description Min Max Unit
tTCYC TCK clock cycle time 50 – ns
tTF TCK clock frequency – 20 MHz
tTH TCK clock HIGH 20 – ns
tTL TCK clock LOW 20 – ns
Setup Times
tTMSS TMS set-up to TCK clock rise 5 – ns
tTDIS TDI set-up to TCK clock rise 5 – ns
tCS Capture set-up to TCK rise 5 – ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 – ns
tTDIH TDI hold after clock rise 5 – ns
tCH Capture hold after clock rise 5 – ns
Output Times
tTDOV TCK clock LOW to TDO valid – 10 ns
tTDOX TCK clock LOW to TDO invalid 0 – ns
Notes
20. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
21. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 19 of 32
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [22]
Figure 2. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Note
22. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
[+] Feedback
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
Document Number: 001-57832 Rev. *C Page 20 of 32
Identification Register Definitions
Instruction Field Value Description
CY7C1241KV18 CY7C1256KV18 CY7C1243KV18 CY7C1245KV18
Revision number
(31:29)
000 000 000 000 Version number.
Cypress device ID
(28:12)
11010010101000111 11010010101001111 11010010101010111 11010010101100111 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1)
00000110100 00000110100 00000110100 00000110100 Allows unique
identification of
SRAM vendor.
ID register
presence (0)
1 1 1 1 Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary scan 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
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Document Number: 001-57832 Rev. *C Page 21 of 32
Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N 329F 605C 882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M
9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H
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Document Number: 001-57832 Rev. *C Page 22 of 32
Power Up Sequence in QDR II+ SRAM
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐Apply VDD before VDDQ.
❐Apply VDDQ before VREF or at the same time as VREF
.
❐Drive DOFF HIGH.
■Provide stable DOFF (HIGH), power and clock (K, K) for 20 s
to lock the PLL.
PLL Constraints
■PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■The PLL functions at frequencies down to 120 MHz.
■If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 s of stable clock to
relock to the desired clock frequency.
Figure 3. Power Up Waveforms
> 20μs Stable clock
Start Normal
Operation
DOFF
Stable(< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to V
DDQ)
K
K
DDQDD
VV
/DDQDD
VV
/
Clock Start (Clock Starts after Stable)
DDQ
DD
VV
/
~
~
~
~
Unstable Clock
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Document Number: 001-57832 Rev. *C Page 23 of 32
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +2.9 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC applied to outputs in high Z ........ –0.5 V to VDDQ + 0.3 V
DC input voltage [23] ...........................–0.5 V to VDD + 0.3 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, M. 3015) ........................................> 2,001 V
Latch-up current ....................................................> 200 mA
Operating Range
Range Ambient
Temperature (TA)VDD[24] VDDQ[24]
Commercial 0 °C to +70 °C 1.8 ± 0.1 V 1.4 V to
VDD
Industrial –40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description Test
Conditions Typ Max* Unit
LSBU Logical
single-bit
upsets
25 °C 197 216 FIT/
Mb
LMBU Logical
multi-bit
upsets
25 °C 00.01 FIT/
Mb
SEL Single event
latch-up
85 °C 00.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation
of Terrestrial Failure Rates”
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [25] Description Test Conditions Min Typ Max Unit
VDD Power supply voltage 1.7 1.8 1.9 V
VDDQ I/O supply voltage 1.4 1.5 VDD V
VOH Output HIGH voltage Note 26 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V
VOL Output LOW voltage Note 27 VDDQ/2 – 0.12 – VDDQ/2 + 0.12 V
VOH(LOW) Output HIGH voltage IOH =0.1 mA, nominal impedance VDDQ – 0.2 – VDDQ V
VOL(LOW) Output LOW voltage IOL = 0.1 mA, nominal impedance VSS –0.2 V
VIH Input HIGH voltage VREF + 0.1 – VDDQ + 0.15 V
VIL Input LOW voltage –0.15 – VREF – 0.1 V
IXInput leakage current GND VI VDDQ 2 – 2 A
IOZ Output leakage current GND VI VDDQ, output disabled 2 – 2 A
VREF Input reference voltage [28] Typical value = 0.75 V 0.68 0.75 0.95 V
Notes
23. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
24. Power-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
25. All voltage referenced to ground.
26. Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 .
27. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350 .
28. VREF(min) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(max) = 0.95 V or 0.54 VDDQ, whichever is smaller.
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Document Number: 001-57832 Rev. *C Page 24 of 32
IDD [29] VDD operating supply VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
450 MHz (× 8) – – 710 mA
(× 9) – – 710
(× 18) – – 720
(× 36) – – 1020
400 MHz (× 8) –– 650 mA
(× 9) –– 650
(× 18) –– 660
(× 36) –– 920
375 MHz (× 8) – – 620 mA
(× 9) – – 620
(× 18) – – 630
(× 36) – – 870
333 MHz (× 8) –– 560 mA
(× 9) –– 560
(× 18) –– 570
(× 36) –– 790
ISB1 Automatic power-down
current
Max VDD,
both ports deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC,
inputs static
450 MHz (× 8) – – 330 mA
(× 9) – – 330
(× 18) – – 330
(× 36) – – 330
400 MHz (× 8) – – 310 mA
(× 9) – – 310
(× 18) – – 310
(× 36) – – 310
375 MHz (× 8) – – 300 mA
(× 9) – – 300
(× 18) – – 300
(× 36) – – 300
333 MHz (× 8) – – 280 mA
(× 9) – – 280
(× 18) – – 280
(× 36) – – 280
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [25] Description Test Conditions Min Typ Max Unit
Note
29. The operation current is calculated with 50% read cycle and 50% write cycle.
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Document Number: 001-57832 Rev. *C Page 25 of 32
AC Electrical Characteristics
Over the Operating Range
Parameter [30] Description Test Conditions Min Typ Max Unit
VIH Input HIGH voltage VREF + 0.2 – VDDQ + 0.24 V
VIL Input LOW voltage –0.24 – VREF – 0.2 V
Capacitance
Parameter [31] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V 4 pF
COOutput capacitance 4pF
Thermal Resistance
Parameter [31] Description Test Conditions 165-ball FBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
13.7 °C/W
JC Thermal resistance
(junction to case)
3.73 °C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
1.25 V
0.25 V
R = 50
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device RL= 50
Z0= 50
VREF = 0.75 V
VREF = 0.75 V
[32]
0.75 V
Under
Test
0.75 V
Device
Under
Te s t
OUTPUT
0.75 V
VREF
VREF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
(b)
RQ =
250
Notes
30. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
31. Tested initially and after any design or process change that may affect these parameters.
32. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 4.
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Switching Characteristics
Over the Operating Range
Parameters [33, 34]
Description
450 MHz 400 MHz 375 MHz 333 MHz
Unit
Cypress
Parameter
Consortium
Parameter Min Max Min Max Min Max Min Max
tPOWER VDD(typical) to the first access [35] 1–1–1–1–ms
tCYC tKHKH K clock cycle time 2.2 8.4 2.5 8.4 2.66 8.4 3.0 8.4 ns
tKH tKHKL Input clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – ns
tKL tKLKH Input clock (K/K) LOW 0.4 – 0.4 – 0.4 – 0.4 – ns
tKHKHtKHKHK clock rise to K clock rise (rising edge to rising
edge)
0.94 – 1.06 – 1.13 – 1.28 – ns
Setup Times
tSA tAVKH Address set-up to K clock rise 0.275 – 0.4 – 0.4 – 0.4 – ns
tSC tIVKH Control set-up to K clock rise (RPS, WPS)0.275 – 0.4 – 0.4 – 0.4 – ns
tSCDDR tIVKH DDR control set-up to clock (K/K) rise (BWS0,
BWS1, BWS2, BWS3)
0.22 – 0.28 – 0.28 – 0.28 – ns
tSD tDVKH D[X:0] set-up to clock (K/K) rise 0.22 – 0.28 – 0.28 – 0.28 – ns
Hold Times
tHA tKHAX Address hold after K clock rise 0.275 – 0.4 – 0.4 – 0.4 – ns
tHC tKHIX Control hold after K clock rise (RPS, WPS) 0.275 – 0.4 – 0.4 – 0.4 – ns
tHCDDR tKHIX DDR control hold after clock (K/K) rise (BWS0,
BWS1, BWS2, BWS3)
0.22 – 0.28 – 0.28 – 0.28 – ns
tHD tKHDX D[X:0] hold after clock (K/K) rise 0.22 – 0.28 – 0.28 – 0.28 – ns
Output Times
tCO tCHQV K/K clock rise to data valid –0.45–0.45–0.45–0.45ns
tDOH tCHQX Data output hold after output K/K clock rise
(active to active)
–0.45 – –0.45 – –0.45 – –0.45 – ns
tCCQO tCHCQV K/K clock rise to echo clock valid –0.45–0.45–0.45–0.45ns
tCQOH tCHCQX Echo clock hold after K/K clock rise –0.45 – –0.45 – –0.45 – –0.45 – ns
tCQD tCQHQV Echo clock high to data valid – 0.15 – 0.20 – 0.20 – 0.20 ns
tCQDOH tCQHQX Echo clock high to data invalid –0.15 – –0.20 – –0.20 – –0.20 – ns
tCQH tCQHCQL Output clock (CQ/CQ) HIGH [36] 0.85 – 1.0 – 1.08 – 1.25 – ns
tCQHCQHtCQHCQHCQ clock rise to CQ clock rise (rising edge to
rising edge) [36] 0.85 – 1.0 – 1.08 – 1.25 – ns
tCHZ tCHQZ Clock (K/K) rise to high Z (active to high Z) [37, 38] –0.45–0.45–0.45–0.45ns
tCLZ tCHQX1 Clock (K/K) rise to low Z [37, 38] –0.45 – –0.45 – –0.45 – –0.45 – ns
tQVLD tCQHQVLD Echo clock high to QVLD valid [39] –0.15 0.15 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns
PLL Timing
tKC Var tKC Var Clock phase jitter – 0.15 – 0.20 – 0.20 – 0.20 ns
tKC lock tKC lock PLL lock time (K) 20–20–20–20– s
tKC Reset tKC Reset K static to PLL reset [40] 30–30–30–30– ns
Notes
33. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 4 on page 25.
34. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
35. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD minimum initially before a read or write operation can be
initiated.
36. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
37. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of Figure 4 on page 25. Transition is measured ± 100 mV from steady-state voltage.
38. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
39. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
40. Hold to >VIH or <VIL.
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Document Number: 001-57832 Rev. *C Page 27 of 32
Switching Waveforms
Read/Write/Deselect Sequence
Figure 5. Waveform for 2.0 Cycle Read Latency [41, 42, 43]
tKH tKL tCYC tKHKH
NOP READ
NOP WRITE READ WRITE
123 4 5 6 78
t
t
t
tSA HA
SC HC
tHD
tSC tHC
A0 A1 A2 A3
t
t
SD
HD
tSD
D11D10 D12 D13 D30 D31 D32 D33
D
A
WPS
RPS
K
K
DON’T CARE UNDEFINED
CQ
CQ
tCQOH
CCQO
t
tCQOH
CCQO
t
tQVLD
QVLD
tQVLD
(Read Latency = 2.0 Cycles)
CLZ
t
tCO
t
DOH tCQDOH
CQD
ttCHZ
Q00 Q01 Q20
Q02 Q21
Q03 Q22 Q23
tCQH t
CQHCQH
Q
Notes
41. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
42. Outputs are disabled (high Z) one clock cycle after a NOP.
43. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.
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Document Number: 001-57832 Rev. *C Page 28 of 32
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code Package
Diagram Package Type Operating
Range
400 CY7C1243KV18-400BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Commercial
CY7C1245KV18-400BZC
CY7C1245KV18-400BZXC 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free
CY7C1245KV18-400BZXI Industrial
450 CY7C1243KV18-450BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Commercial
CY7C1245KV18-450BZC
Ordering Code Definitions
Temperature Range:
C = Commercial = 0 C to +70 C
X = Pb-free; X Absent = Leaded
Package Type:
BZ = 165-ball FBGA
Speed Grade: XXX = 450 MHz or 400 MHz
V18 = 1.8 V VDD
Process Technology 65 nm
Part Identifier: 12XX = 1243 or 1245
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CY 12XX K - XXX BZ XV18 CC7
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Document Number: 001-57832 Rev. *C Page 29 of 32
Package Diagram
Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *E
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Document Number: 001-57832 Rev. *C Page 30 of 32
Acronyms Document Conventions
Units of Measure
Acronym Description
DDR double data rate
EIA electronic industries alliance
FBGA fine-pitch ball grid array
HSTL high-speed transceiver logic
I/O input/output
JEDEC joint electron devices engineering council
JTAG joint test action group
LMBU logical multiple bit upset
LSB least significant bit
LSBU logical single bit upset
MSB most significant bit
PLL phase locked loop
QDR quad data rate
SEL single event latch-up
SRAM static random access memory
TAP test access port
TCK test clock
TDI test data-in
TDO test data-out
TMS test mode select
TQFP thin quad flat pack
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mm millimeter
ms millisecond
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
ps picosecond
Vvolt
Wwatt
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Document Number: 001-57832 Rev. *C Page 31 of 32
Document History Page
Document Title: CY7C1241KV18/CY7C1256KV18/CY7C1243KV18/CY7C1245KV18, 36-Mbit QDR® II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Document Number: 001-57832
Rev. ECN Orig. of
Change
Submission
Date Description of Change
** 2816620 VKN/AESA 11/27/2009 New Data Sheet
*A 3068457 NJY 10/21/2010 Converted from Preliminary to Final.
Added Ordering Code Definitions.
Updated Package Diagram.
Minor edits and updated in new template.
*B 3181270 SHTC 02/24/2011 Updated Ordering Information (Added MPN CY7C1245KV18-400BZXC).
*C 3439118 PRIT 12/08/2011 Updated Ordering Information (Added MPN CY7C1245KV18-400BZXI).
Updated Package Diagram.
Added Acronyms and Units of Measure.
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Document Number: 001-57832 Rev. *C Revised December 8, 2011 Page 32 of 32
QDR II+ is a registered trademark of Cypress Semiconductor Corporation. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and
Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1241KV18, CY7C1256KV18
CY7C1243KV18, CY7C1245KV18
© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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