1. General description
The PCF2119x is a low power CMOS1 LCD controller and driver, designed to drive a dot
matrix LCD display of 2-lines by 16 characters or 1-line by 32 characters with 5 8 dot
format. All necessary functions for the display are provided in a single chip, including
on-chip generation of LCD bias voltages, resulting in a minimum of ex tern al com p on e nts
and lower system current consumption. The PCF2119x interfaces to most
microcontrollers via a 4-bit or 8-bit bus or via the 2-wire I2C-bus. The chip contains a
character generator and displays alphanumeric and kana (Japanese) characters.
The letter ‘x’ in PCF2119x characterize s the built-in character set. Various character sets
can be manufactured on request. In addition 16 user defined symbols (5 8 dot format)
are available.
For a selection of NXP LCD character drivers, see Table 51 on page 78.
2. Features and benefits
Single-chip LCD controller and driver
2-line display of up to 16 characters plus 160 icons or 1-line display of up to
32 characters plus 160 icons
57 character format plus cursor; 5 8 for kana (Japanese) and user defined
symbols
Reduced current consumption while displaying icons only
Icon blink function
On-chip:
Configurable 4, 3, or 2 times voltage multiplier generating LCD supply voltage,
independent of VDD, programmable by instruction (external supply also possible)
Temperature compensation of on-chip generated VLCDOUT: 0.16 %/K to
0.24 %/K (programmable by instruction)
Generation of intermediate LCD bias voltages
Oscillator requires no external components (external clock also possible)
Display Data RAM (DDRAM): 80 characters
Character Ge ne ra to r RO M (CG R O M ): 24 0 char a cte rs (5 8)
Character Generator RAM ( CGRAM): 16 characters (5 8); 4 characters used to drive
160 icons, 8 characters used if icon blink feature is used in application
4-bit or 8-bit parallel bus and 2- wir e I 2C-bus interface
Manufactured in silicon gate CMOS process
18 row and 80 column outputs
PCF2119x
LCD controllers/drivers
Rev. 12 — 16 April 2015 Product data sheet
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
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Product data sheet Rev. 12 — 16 April 2015 2 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
Multiplex rates 1:18 (2-line display or 1-line display), 1:9 (for 1-line display of up to
16 characters and 80 icons) and 1:2 (for icon only mode)
Uses common 11 code instruction set (extended)
Logic supply voltage: VDD1 VSS1 = 1.5 V to 5.5 V (chip may be driven with two
battery cells)
LCD supply voltage: VLCDOUT VSS2 = 2.2 V to 6.5 V
VLCD generator supply voltage: VDD2 VSS2 = 2.2 V to 4 V and
VDD3 VSS2 =2.2Vto4V
Direct mode to save current consumption for icon mode and multiplex drive mode 1:9
(depending on VDD2 value and LCD liquid properties)
Very low current consumption (20 A to 200 A):
Icon mode: < 25 A
Power-down mode: < 2 A
Icon mode is used to save curr en t. When only i cons ar e displaye d, a much lower L CD
operating voltage can be use d an d th e switc hin g freque n cy of the LCD outputs is
reduced; in most applications it is possible to use VDD as LCD supply voltage
3. Applications
Telecom equipment
Portable instruments
Point-of-sale terminals
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Product data sheet Rev. 12 — 16 April 2015 3 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
4. Ordering information
4.1 Ordering options
5. Marking
Table 1. Ordering information
Type number Package
Name Description Version
PCF2119AU bare die 168 bumps PCF2119x
PCF2119DU bare die 168 bumps PCF2119x
PCF2119FU bare die 168 bumps PCF2119x
PCF2119IU bare die 168 bumps PCF2119x
PCF2119RU bare die 168 bumps PCF2119x
PCF2119SU bare die 168 bumps PCF2119x
Table 2. Ordering options
Product type number IC
revision Sales item (12NC) Delivery form
PCF2119AU/2DA/2 2 935273369033 chips in tray
PCF2119DU/2/2 2 935272743033 chips in tray
PCF2119FU/2/F2 2 935267829033 chips in tray
PCF2119IU/2 DA/2 2 935294878033 chips in tray
PCF2119RU/2/F2 2 935263699033 chips in tray
PCF2119RU/2DB/2 2 935293133033 chips in tray
PCF2119SU/2/F2 2 935263700033 chips in tray
Table 3. Marking codes
Product type number Marking code
PCF2119AU PC2119-2
PCF2119DU PC2119-2
PCF2119FU PC2119-2
PCF2119IU PC2119-2
PCF2119RU PC2119-2
PCF2119SU PC2119-2
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Product data sheet Rev. 12 — 16 April 2015 4 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
6. Block diagram
Fig 1. Block diagram of PCF2119x
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PCF21 19X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 12 — 16 April 2015 5 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
7. Pinning information
7.1 Pinning
Viewed from active side. For mechanical details, see Figure 49.
Fig 2. Pinning diagram of PCF2119x (bare die)
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PCF21 19X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 12 — 16 April 2015 6 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
7.2 Pin description
Table 4. Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol Pin Description
VDD1 1 to 6 supply voltage 1 (logic)
VDD2 7 to 14 [1] supply voltage 2 (for high voltage generator)
VDD3 15 to 18 [1] supply voltage 3 (for high voltage generator)
E19
[2] data bus clock input
•set HIGH to signa l the start of a read or write operation
•data is clocked in or out of the chip on the negative edge
of the clock
T1 and T2 20 and 21 test pins
•must be connected to VSS1
VSS1 22 to 29 [3] ground supply voltage 1
•for all circuits, except of high voltage generator
VSS2 30 to 35 [3] ground supply voltage 2
•for high voltage generator
VLCDSENSE 36 input for voltage multiplier regulation circuitry and for the bias
level generation
•if VLCD is generated internally then this pin must be
connected to VLCDOUT and VLCDIN
•if VLCD is generated externally then this pin must be
connected to VLCDIN only
VLCDOUT 37 to 43 VLCD output
•if VLCD is generated internally then this pin must be
connected to VLCDIN and to VLCDSENSE
•if VLCD is generated externally then this pin must be left
open-circuit
VLCDIN 44 to 49 input for LCD bias level generator
•if VLCD is generated internally then this pin must be
connected to VLCDOUT and to VLCDSENSE
•if VLCD is generated externally then this pin must be
connected to VLCDSENSE and to the externa l VLCD power
supply
dummy 50 -
R8 to R1,
R17,
R17DUP,
R18,
R9 to R16
51 to 58,
59,
100
141,
142 to 149
LCD row driver output
•R17 has two pins: R17 and R17DUP
•R17 and R18 drive the icons
C80 to C41,
C40 to C1 60 to 99,
101 to 140 LCD column driver output
dummy 150 -
SCL 151 and 152 [4] I2C-bus serial clock input
T3 153 test pin
•open-circuit
•not user accessible
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Product data sheet Rev. 12 — 16 April 2015 7 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
[1] Always put VDD2 =V
DD3.
[2] When the I2C-bus is used, the parallel interface pin E must be LOW.
[3] The substrate (rear side of the die) is wired to VSS but should not be electrically connected.
[4] When the parallel bus is used, the pins SCL and SDA must be connected to VSS1 or VDD1; they must not be
left open-circuit.
[5] In the I2C-bus read mode, ports DB7 to DB4 and DB2 to DB0 should be connected to VDD1 or left
open-circuit.
[6] When the 4-bit interface is used without reading out from the PCF2119x (bit R/W is set permanently to
logic 0), the unused ports DB4 to DB0 can either be set to VSS1 or VDD1 instead of leaving them
open-circuit.
POR 154 external Power-On Reset (POR) input
PD 155 power-down mode select
•for normal operation, pin PD must be LOW
SDA 156 and 157 [4] I2C-bus serial data input/output
R/W 158 read/write input
•pin R/W = HIGH selects the read operation
•pin R/W = LOW selects the write operation
•this pin has an internal pull-up resistor
RS 159 register select pin
•this pin has an internal pull-up resistor
DB0 to DB2,
DB3/SA0,
DB4 to DB7
160 to 162,
163,
164 to 167
[5][6] 8 bit bidirectional data bus (bit 0 to bit 7)
•the 8-bit bid i rect i on a l data bus (3-st a te ) tr a nsf ers data
between the microcontroller and the PCF2119x
•pin DB7 may be used as the busy flag, signalling that
internal operations are not yet completed
•4-bit operations the 4 higher order lines DB7 to DB4 are
used, DB3 to DB0 must be left open-circuit
•data bus line DB3 has an alternative function (SA0) as the
I2C-bus address pin
•each data line has its own internal pull-up resistor
OSC 168 oscillator or external clock input
•when the on-chip oscillator is used this pin must be
connected to VDD1
Table 4. Pin description …continued
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
Symbol Pin Description
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Product data sheet Rev. 12 — 16 April 2015 8 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
8. Functional description
8.1 Oscillator and timing generator
The internal logic and the LCD drive signals of the PCF2119x are timed by the frequency
fclk which equals either the built in oscillator frequency fosc or an external clock frequency
fosc(ext).
8.1.1 Timing generator
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not disturbed by operations on the data buses.
8.1.2 Internal clock
To use the on-chip oscillator, pin OSC must be connected to VDD1. The on-chip oscillator
provides the clock signal for the display system. No external components are required.
8.1.3 External clock
If an external clock will be used, the input is at pin OSC. The resulting display frame
frequency is give n by :
(1)
Remark: Only in the power-down mode the clock is allowed to be stopped (pin OSC
connected to VSS), otherwise the LCD is frozen in a DC state, which is n ot suitab le for the
liquid crystals.
8.2 Reset function and Power-On Reset (POR)
The PCF2119x must be reset externally when power is turned on. If no external reset is
performed, the chip might start-up in an unwanted state.
For the external reset, pin POR has to be active HIGH. The reset has to be active for at
least 3 oscillator periods in order for the reset to be executed. If the internal oscillator is
used, the minimum reset activity time follows from the lowest possible oscillator frequency
(fosc = 140 kHz, tosc ~7.1s, 3 tosc ~2.15s). The internal oscillator start-up time is
200 s (typ) up to 300 s (max) after power-on. In case that an external oscillator is used,
tosc is dependent fro m fosc(ext).
Afterwards the chip executes the Clear_display instruction, which requires 165 oscillator
cycles. After the reset the chip has the state shown in Table 5 and is then ready for use.
ffr fclk
3072
------------
=
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Product data sheet Rev. 12 — 16 April 2015 9 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
[1] The Busy Flag (BF) indicates the busy state (bit BF = 1) until initialization ends. The busy state lasts 2 ms. The chip may also be
initialized by software (see Table 45 and Table 46).
8.3 Power-down mode
The chip can be put into power-down mode by applying a HIGH-level to pin PD. In
power-down mode all static currents are switched off (no internal oscillator, no bias level
generation and all LCD outputs are internally connected to VSS).
During power-down, information in the RAM and the chip state are preserved. Instruction
execution during power-down is possible when pin OSC is externally clocked.
8.4 LCD supply voltage generator
The LCD supply voltage may be generated on-chip. The VLCD generator is controlled by
two internal 6-bit registers: VA and VB. Re gister VA is programmed with the voltage for
character mode and register VB with the voltage for icon mode.
The nominal LCD operating voltage at room temperature is given by Equation 2:
(2)
Where Vx is the integer value of the register VA or VB.
Table 5. State after reset
Step Function Control bit and
register state Description Reference
1 Clear_display - - Table 17
2 Entry_mode_set bit I_D = 1 incremental cursor move direction Table 19
bit S = 0 no display shift
3 Display_ctl bit D = 0 display off Table 20
bit C = 0 cursor off
bit B = 0 cursor character blink off
4 Function_set bit DL = 1 8-bit interface Table 13
bit M = 0 1-line display
bit SL = 0 1:18 multiplex drive mode
bit H = 0 normal instruction set
5 default address pointer to DDRAM[1] -- Table 23
6 Icon_ctl bit IM = 0 character mode, full display Table 26
bit IB = 0 icon blink disabled
7 Screen_conf bit L = 0 default co nfiguration Table 24
Disp_conf bit P = 0;
bitQ=0 default configurations Table 25
8 Temp_ctl bit TC1 = 0;
bit TC2 = 0 default temperature coefficient Table 29
9 VLCD_set register VA=0;
register VB=0 VLCD generator off Table 33
10 I2C-bus interface reset - - -
11 HV_gen bit S1 = 1;
bit S0 = 0 VLCD generator set to 3 internal stages
(4 voltage multipliers) Table 31
VLCD nom Vx0.08 1.82+=
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Product data sheet Rev. 12 — 16 April 2015 10 of 88
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LCD controllers/drivers
VLCD is sometimes referred as the LCD operating voltage (Voper).
8.4.1 Programming ranges
Possible values for VA and VB are betw ee n 0 to 63.
Remarks:
•Values producing more than 6.5 V at operating temperature are not allowed.
Operation above this voltage may damage the device. When progra mming the
operating voltage, the temperature coefficient of VLCDOUT must be taken into account.
•Values below 2.2 V are below the spec ified op e ra tin g ra ng e of the chip and are
therefore not allowed.
When the LCD supply volt age is generated on-chip, the VLCD pins should be decoupled to
VSS with a suitab le capacitor. The generated VLCDOUT is independent of VDD and is
temperature compensated.
In Equation 2 the internal char ge pump is not considered. However, if the supplied voltag e
to VDD2 and VDD3 is below the required VLCD, it is necessary to use the internal charge
pump. The multiplication factor indicates the number of stages used to increase the
voltage. At multiplication factor 2 one, at multiplication factor 3 two and at multiplication
Table 6. Values of VA and VB and the corresponding VLCD values
All values at Tref =27
C; allowed values are highlighted.
Integer values
of VA and VB
Corresponding
value of VLCD in V Integer values
of VA and VB
Corresponding
value of VLCD in V Integer values
of VA and VB
Corresponding
value of VLCD in V
0VLCD switched off 22 3.58 44 5.34
11.90 23 3.66 45 5.42
21.98 24 3.74 46 5.50
32.06 25 3.82 47 5.58
42.14 26 3.90 48 5.66
52.22273.98495.74
62.30284.06505.82
72.38294.14515.90
82.46304.22525.98
92.54314.30536.06
10 2.62 32 4.38 54 6.14
11 2.70 33 4.46 55 6.22
12 2.78 34 4.54 56 6.30
13 2.86 35 4.62 57 6.38
14 2.94 36 4.70 58 6.46
15 3.02 37 4.78 59 6.54
16 3.10 38 4.86 60 6.62
17 3.18 39 4.94 61 6.70
18 3.26 40 5.02 62 6.78
19 3.34 41 5.10 63 6.86
20 3.42 42 5.18
21 3.50 43 5.26
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Product data sheet Rev. 12 — 16 April 2015 11 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
factor 4, three stages are used. A multiplication factor of for example, 4 does not mean
that a volt age of 4 VDD2,3 is generated in the in ternal high-volt age generator. The charge
pump is part of a control loop. This means that the control loop a ims to regulate VLCD at
the program m ed valu e.
The ITO track resistance limit the speed by which the capacitors can be charged. The
multiplication factor exceeds the required VLCD under all circumstances (that is, at low
temperatures and along with the temper ature co mpe nsation, see Section 10.2.2.4). If still
a higher multiplication factor is chosen, VLCD will remain as set by Equation 2 but the
ripple will increase. The increase in ripple can be counteracted by increasing the external
decoupling capacitor at VLCD. A higher multiplication factor will also result in a higher
current consumption (see Section 16.6). However the current that can be delivered will be
higher, for example, for larger display are a.
When the VLCD generator and the direct mode are switched off, an external voltage may
be supplied at connected pins VLCDIN and VLCDOUT. VLCDIN and VLCDOUT may be higher or
lower than VDD2.
In direct mode (see Icon_ctl instruction, Section 10.2.3.3) the internal VLCD generator is
turned off and the VLCDOUT output voltage is directly conn ec te d to VDD2. This reduces the
current consumption depending on VDD2 value and LCD liquid properties.
The VLCD gener ator ensures that, as long as VDD2 and VDD3 are in the valid range (2.2 V
to 4 V), the required peak voltage VLCD = 6.5 V can be generated at an y time.
8.5 LCD bias voltage generator
The intermediate bias voltages for the LCD display are also generated on-chip. This
removes the need for an extern al resistive bias chain and significantly reduces the system
current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD
threshold volt age (Vth) and the number of bias levels. Using a 5-level bias scheme for the
1:18 multiplex rate allows VLCD < 5 V for most LCD liquids.
The intermedia te bias levels for th e different multip le x rat es ar e sh ow n in Table 7. These
bias levels are auto m ati ca lly set to the giv en valu es when switch in g to the co rr esp o nd in g
multiplex rate.
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 3 and the
RMS off-state voltage (Voff(RMS)) with Equation 4:
Table 7. Bias levels as a function of multiplex rate
Multiplex
rate Number of
bias levels Bias voltages
V1V2V3V4V5V6
1:18 5 VLCD VSS
1:9 5 VLCD VSS
1:2 4 VLCD VSS
3
4
---VLCD VSS
–
1
2
---VLCD VSS
–
1
2
---VLCD VSS
–
1
4
---VLCD VSS
–
3
4
---VLCD VSS
–
1
2
---VLCD VSS
–
1
2
---VLCD VSS
–
1
4
---VLCD VSS
–
2
3
---VLCD VSS
–
2
3
---VLCD VSS
–
1
3
---VLCD VSS
–
1
3
---VLCD VSS
–
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Product data sheet Rev. 12 — 16 April 2015 12 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
(3)
(4)
where the value s of a ar e
a=2 for 1⁄4 bias
a=3 for 1⁄5 bias
and the values for n are
n = 2 for 1:2 multiplex rate
n = 9 for 1:9 multiplex rate
n = 18 for 1:18 multiplex rate.
Discrimination (D) is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 5.
Discrimination is a term which is defined as the ratio of the on a nd off RMS volt age across
a segment. It can be thought of as a measurement of contrast.
(5)
8.5.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependant on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vlow) and the other at 90 % relative transmission (at Vhigh), see Figure 3.
For a good contrast performance, the following rules should be followed:
(6)
(7)
Von(RMS) and Voff(RMS) are properties of the display driver and ar e affected by the selection
of a, n (see Equation 3 to Equation 5) and the VLCD voltage.
Vlow and Vhigh are properties of the LCD liquid and can be provided by the module
manufacturer.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
Von RMS a22a n++
n1a+
2
------------------------------
VLCD
=
Voff RMS a22a–n+
n1a+
2
------------------------------
VLCD
=
DVon RMS
Voff RMS
-----------------------a1+
2n1–+
a1–
2n1–+
--------------------------------------------==
Von RMS
Vhigh
Voff RMS
Vlow
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Product data sheet Rev. 12 — 16 April 2015 13 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
8.6 LCD row and column drivers
The PCF2119x contains 18 row and 80 column drivers, which drive the appropriate LCD
bias voltages in sequence to the display in accord ance with the dat a to be di splayed. R17
and R18 drive the icon rows. Unused outputs should be left open.
The bias voltages and the timing are selected automatically when the number of lines in
the display is selected. Figure 4 to Figure 6 show typical waveforms.
The waveforms used to drive LC displays inherently produce a DC voltage acro ss the
display cell. The PCF2119x compensates for the DC voltage by inverting the waveforms
on alternate frames (called frame inversio n mode or driving scheme A).
Fig 3. Electro - op tical characteristic: relative transmission curve of the liqu id
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Product data sheet Rev. 12 — 16 April 2015 14 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
state(n) marks intersection(row(x),col(n)) of pixel(x,n)
Vstate(n)(t) = VCOL(n)(t) VROW(x)(t).
Vstate1(t) = VCOL1(t) VROW1(t).
Vstate2(t) = VCOL2(t) VROW1(t).
Fig 4. Waveforms for the 1:18 multiplex drive mode with 5 bias levels; character mode
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Product data sheet Rev. 12 — 16 April 2015 15 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
state(n) marks intersection(row(x),col(n)) of pixel(x,n)
Vstate(n)(t) = VCOL(n)(t) VROW(x)(t).
Vstate1(t) = VCOL1(t) VROW1(t).
Vstate2(t) = VCOL2(t) VROW1(t).
Fig 5. Waveforms for the 1:9 multiplex drive mode with 5 bias levels; character mode, R9 to R16 and R18 open
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PCF21 19X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 12 — 16 April 2015 16 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
state(n) marks intersection(row(x),col(n)) of pixel(x,n)
Vstate(n)(t) = VCOL(n)(t) VROW(x)(t).
Vstate1(t) = VCOL1(t) VROW17(t).
Vstate2(t) = VCOL2(t) VROW17(t).
Vstate3(t) = VCOL3(t) VROW1 to 16(t).
Fig 6. Waveforms for the 1:2 multiplex drive mode with 4 bias levels; icon mode
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PCF21 19X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 12 — 16 April 2015 17 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
9. Display data RAM and ROM
9.1 DDRAM
The Display Data RAM (DDRAM) stores up to 80 characters of display data represented
by 8-bit character codes. RAM locations which are not used for storing display data can
be used as general purpose RAM.
The basic RAM to display a ddressing scheme is shown in Figure 7, Figure 8 and Figure 9.
With no display shift the character s represented by the codes in the first 32 RAM locations
starting at address 00h are displayed in line 1.
All addresses are shown in hex.
Fig 7. DDRAM to display mapping: no shift
All addresses are shown in hex.
Fig 8. DDRAM to display mapping: right shift
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PCF21 19X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 12 — 16 April 2015 18 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
When dat a is written to or rea d from the DDRAM, wrap- around occurs from the end of one
line to the start of the next line. When the display is shifted each line wrap s around within
itself, independe ntly of the others. Thus all lines a re shif ted and wrapped a round together.
The address ranges and wrap-around operations for the various modes are shown in
Table 8.
9.2 CGROM
The Character Generator ROM (CGROM) contains 240 character patterns in a 5 8dot
format from 8-bit character codes. Figure 10 to Figure 15 show the character sets that are
currently implemented.
All addresses are shown in hex.
Fig 9. DDRAM to display mapping: left shift
Table 8. Address space and wrap-around opera tion
Mode 132 216 116
Address space 00h to 4Fh 00h to 27h;
40hto67h 00h to 27h
Read/write wrap-around
(moves to next line) 4Fhto00h 27hto40h;
67hto00h 27h to 00h
Display shift wrap-around
(stays within line) 4Fhto00h 27hto00h;
67hto40h 27h to 00h
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PCF21 19X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 12 — 16 April 2015 19 of 88
NXP Semiconductors PCF2119x
LCD controllers/drivers
The first column (0000) is the CGRAM, the other 15 columns (0001 to 1111) are the CGROM.
Fig 10. Character set ‘A’ in CGROM
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