Rev.0.10 Nov 14, 2005 Page 1 of 22
REJ03B0168-0010
PRELIMINARY
R8C/26, R8C/27 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Notice: This is not a final specification.
Some parametric limits are subject to change.
1. Overview
This MCU is built using the high-perfo rm ance silicon gate CMOS process using the R8C/Tiny Series CPU core and is
packaged in a 32-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high l evel
of instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed.
Furthermore, the data flash (1KB x 2 blocks) is embedded in the R8C/27 group.
The difference between R8C/26 and R8C/27 groups i s only the existence of the data flash. Their peripheral functions
are the same.
1.1 Applications
Electric household appliance, office equipment, audio, consumer products, etc.
REJ03B0168-0010
Rev.0.10
Nov 14, 2005
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 2 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tent ative and subject to change.
1.2 Performance Overview
Table 1.1 lists the R8C/26 Group Performance. Table 1.2 lists the R8C/27 Group Performance.
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version when using it.
Table 1.1 R8C/26 Group Performance
Item Performance
CPU Number of Basic Instructions 89 instructions
Minimum Instruction Execution
Time 50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V)
100ns (f(XIN)=10MHz, VCC=2. 7 to 5. 5V)
TBD(f(XIN)=TBD, VCC=2.2 to 5.5V)
Operating Mode Single-chip
Memory Space 1 Mbyte
Memory Capacity See Table 1.3 Product Information of R8C/26 Group
Peripheral
Function Port I/O port: 25 pins, Input port: 3 pins
LED Drive Port I/O port: 8 pins
Timer Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Circuits of input capture a nd outpu t compare)
Timer RE:
With real-time clock and compare match function
Serial Interface 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock Synchronous Serial
Interface 1 channel
I
2
C bus Interface
(1)
Clock synchronous serial I/O with chip select
LIN Module
Hardware LIN: 1 channel (Timer RA, UART0)
A/D Converter 10-bit A/D conver ter: 1 circuit, 12 channels
Watchdog Timer 15 bits × 1 channel (with prescaler)
Reset start selectable
Interrupt
Internal: 10 factors, External: 4 factors, Software: 4 factors,
Priority level: 7 levels
Clock Generation Circuit 3 circuits
• XIN clock generation circuit (Equipped with a built-in
feedback resistor)
• On-chip oscillator (High speed, low speed)
Equipped with frequency adjustment function on
high speed on-chip oscillator
• XCIN clock generation circuit (32 kHz)
Oscillation Stop Detection Function
XIN clock oscillation stop detection function
Voltage Detection Circuit Included
Power-On Reset Circuit Included
Electric
Characteristics Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz)
VCC=2.7 to 5.5V (f (XIN )=1 0 MH z)
VCC=2.2 to 5.5V (f (XIN )=T BD)
Power Consumption TBD
Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V
Program/Erase Endurance 100 times
Operating Ambient Temperature -20 to 85°C
-40 to 85°C (D Version)(2)
Package 32-pin plastic mold LQFP
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 3 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tent ative and subject to change.
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version when using it.
Table 1.2 R8C/27 Group Performance
Item Performance
CPU Number of Basic Instructions 89 instructions
Minimum Instruction Execution
Time 50ns (f(XIN)=20MHz, VCC=3.0 to 5.5V)
100ns (f(XIN)=10MHz, VCC=2. 7 to 5. 5V)
TBD (f(XIN)=TB D, VCC= 2. 2 to 5. 5V)
Operating Mode Single-chip
Memory Space 1 Mbyte
Memory Capacity See Table 1.4 Product Information of R8C/27 Group
Peripheral
Function Port I/O: 25 pins, Input: 3 pins
LED Drive Port I/O port: 8 pins
Timer Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Circuits of input capture a nd outpu t compare)
Timer RE:
With real-time clock and compare match function
Serial Interface 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock Synchronous Serial
Interface 1 channel
I
2
C bus Interface
(1)
Clock synchronous serial I/O with chip select
LIN Module
Hardware LIN: 1 channel (Timer RA, UART0)
A/D Converter 10-bit A/D conver ter: 1 circuit, 12 channels
Watchdog Timer 15 bits × 1 channel (with prescaler)
Reset start selectable
Interrupt
Internal: 10 factors, External: 4 factors, Software: 4 factors,
Priority level: 7 levels
Clock Generation Circuit 3 circuits
• XIN clock generation circuit (Equipped with a built-in
feedback resistor)
• On-chip oscillator (High speed, low speed)
Equipped with frequency adjustment function on
high speed on-chip oscillator
• XCIN clock generation circuit (32 kHz)
Oscillation Stop Detection Function
XIN clock oscillation stop detection function
Voltage Detection Circuit Included
Power-On Reset Circuit Included
Electric
Characteristics Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz)
VCC=2.7 to 5.5V (f (XIN )=1 0 MH z)
VCC=2.2 to 5.5V (f (XIN )=T BD)
Power Consumption TBD
Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V
Program/Erase Endurance 1,0000 times (Data flash)
1,000 times (Program ROM)
Operating Ambient Temperature -20 to 85°C
-40 to 85°C (D Version)(2)
Package 32-pin plastic mold LQFP
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 4 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tent ative and subject to change.
1.3 Block Diagram
Figure 1.1 shows a Block Diagram.
Figure 1.1 Block Diagra m
R8C/Tiny Series CPU Core
A/D Converter
(10 bits × 12 channels) System Clock Generator
XIN-XOUT
High- Spe e d On -C hip Os cillato r
Low- Spe e d O n-C hip O scilla tor
XCIN-XCOUT
UART or
Clock Synchronous Serial I/O
(8 bits × 2 channels)
Memory
Watchdog Timer
(15 bit s)
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O port
NOTES:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
I2C bu s Interface or Clock
synchronous serial I/O w ith chip select
(8 b its × 1 channel)
LIN Module
(1 channel)
Timer
Timer RA (8 bits )
Timer RB (8 bits )
Timer RC
(16 bits × 1 channel)
Timer RE (8 bits )
8
Port P0
8
Port P1
6
Port P3
1 3
Port P4
2
Port P5
Peripheral Function
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 5 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
1.4 Product Information
Table 1.3 lists the Product Informat ion of R8C/26 Group.
Table 1.4 lists the Product Informat ion of R8C/27 Group.
(D): Under Development
Figure 1.2 Type Number, Memory Size and Package of R8C/26 Group
Table 1.3 Product Information of R8C/26 Group As of Nov 2005
Type No. ROM Capacity RAM Capacity Package Type Remarks
R5F21262SNFP (D) 8 Kbytes 512 bytes PLQP0032GB-A N Version
R5F21264SNFP (D) 16 Kbytes 1 Kbytes PLQP0032GB-A
R5F21265SNFP (D) 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SNFP (D) 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SDFP (D) 8 Kbytes 512 bytes PLQP0032GB-A D Version
R5F21264SDFP (D) 16 Kbytes 1 Kbytes PLQP0032GB-A
R5F21265SDFP (D) 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SDFP (D) 32 Kbytes 1.5 Kbytes PLQP0032GB-A
Type No. R 5 F 21 26 6 S N FP
Package Type:
FP: PLQP0032GB-A
Grouping
N : Operating Ambient Temperature -20 °C to 85 °C
D : Operating Ambient Temperature -40 °C to 85 °C
S : Low voltage version
ROM Capacity
2 : 8KB
4 : 16KB
5 : 24KB
6 : 32KB
R8C/26 Group
R8C/Tiny Series
Memory Type
F : Flash Memory Version
Renesas MCU
Renesas Semiconductors
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 6 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
(D): Under Development
Figure 1.3 Type Number, Memory Size and Package of R8C/27 Group
Table 1.4 Product Information of R8C/27 Group As of Nov 2005
Type No. ROM Capacity RAM
Capacity Package Type Remarks
P r o g r a m R O M Data flash
R5F21272SNFP (D) 8 Kbytes 1 Kbytes × 2 512 bytes PLQP0032GB-A N Version
R5F21274SNFP (D) 16 Kbytes 1 Kbytes × 2 1 Kbytes PLQP0032GB-A
R5F21275SNFP (D) 24 Kbytes 1 Kbytes × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SNFP (D) 32 Kbytes 1 Kbytes × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SDFP (D) 8 Kbytes 1 Kbytes × 2 512 bytes PLQP0032GB-A D Version
R5F21274SDFP (D) 16 Kbytes 1 Kbytes × 2 1 Kbytes PLQP0032GB-A
R5F21275SDFP (D) 24 Kbytes 1 Kbytes × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SDFP (D) 32 Kbytes 1 Kbytes × 2 1.5 Kbytes PLQP0032GB-A
Type No. R 5 F 21 27 6 S N FP
Package Type:
FP: PLQP0032GB-A
Grouping
N : Operating Ambient Temperature -20 °C to 85 °C
D : Operating Ambient Temperature -40 °C to 85 °C
S : Low volt ag e ve rs io n
ROM Capaci ty
2 : 8KB
4 : 16KB
5 : 24KB
6 : 32KB
R8C/27 Group
R8C/Tiny Series
Memory Type
F : Flash Memory Version
Renesas MCU
Renesas Semiconductors
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 7 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
1.5 Pin Assignment
Figure 1.4 shows the Pin Assignment (top view).
Figure 1.4 Pin Assignment (top view)
NOTES:
1. P4_7 is a port for the input.
2. This can be assigned to the pin in parentheses by program.
Package: PLQP0032GB- A (32P6U-A)
Pin Assignment (top view)
R8C/26 Group
R8C/27 Group
XIN/XCIN/P4_6
XOUT/XCOUT/P4_7(1)
VSS/AVSS
RESET
VCC/AVCC
P3_7/TRAO/SSO/RXD1/(TXD1)(2)
MODE
P4_5/INT0/(RXD1)(2)
P1_7/TRAIO/INT1
P3_6/(TXD1)/(RXD1)/(INT1)(2)
P3_5/SCL/SSCK/(TRCIOD)(2)
P1_0/KI0/AN8
P1_4/TXD0
VREF/P4_2
P1_3/KI3/AN11/TRBO
P3_3/INT3/SSI/TRCCLK
P1_1/KI1/AN9/TRCIOA/TRCTRG
P1_2/KI2/AN10/TRCIOB
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7/(TXD1)(2)
P0_7/AN0
P0_6/AN1
P0_5/AN2/CLK1
P1_5/RXD0/(TRAIO)/(INT1)(2)
P1_6/CLK0/(SSI)(2)
P5_3/TRCIOC
P5_4/TRCIOD
P3_1/TRBO
P3_4/SDA/SCS/(TRCIOC)(2)
P0_4/AN3/TREO 29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
24 23 22 21 20 19 18 17
5781234 6
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 8 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
1.6 Pin Description
Table 1.5 lists the Pin Description.
I: Input O: Output I/O: Input and output
Table 1.5 Pin Description
Function Pin name I/O type Description
Power Supply Input VCC, VSS I Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog Power
Supply Input AVCC, AVSS I Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset Input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XIN Clock Input XIN I These pins are provided for the XIN clock generation circuit I/
O. Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins. To use an externally derived clock,
input it to the XIN pin and leave the XOUT pin open.
XIN Clock Output XOUT O
XCIN Clock Input XCIN I These pins are provided for the XCIN clock generation circuit I/
O. Connect a crystal oscillator between the XCIN and XCOUT
pins. To use an externally derived clock, input it to the XCIN pin
and leave the XCOUT pin open.
XCIN Clock Output XCOUT O
INT Interrupt Input INT0, INT1, INT3 IINT interrupt input pins.
Key Input Interrupt KI0 to KI3 I Key input interrupt input pins.
Timer RA TRAO O Timer RA output pin.
TRAIO I/O Timer RA I/O pin.
Timer RB TRBO O Timer RB output pin.
Timer RC TRCCLK I External clock input pin.
TRCTRG I External trigger input pin.
TRCIOA, TRCIOB,
TRCIOC, TRCIOD I/O Sharing output-compare output / input-capture input / PWM /
PWM2 output pins.
Timer RE TREO O Timer RE output pin.
Serial Interface CLK0, CLK1 I/O Clock I/O pin.
RXD0, RXD1 I Receive data input pins.
TXD0, TXD1 O Transmit data output pins.
I2C bus Interface SCL I/O Clock I/O pin.
SDA I/O Data I/O pin.
Clock Synchronous
Serial I/O with Chip
Select
SSI I/O Data I/O pin.
SCS I/O Chip-select signal I/O pin.
SSCK I/O Clock I/O pin.
SSO I/O Data I/O pin.
Reference Voltage
Input VREF I Reference voltage input pin to A/D converter.
A/D Converter AN0 to AN11 I Analog input pins to A/D converter.
I/O Port P0_0 to P0_7,
P1_0 to P1_7,
P3_1, P3_3 to P3_7,
P4_5,
P5_3, P5_4
I/O These are CMOS I/O ports. Each port contains an input/output
select direction register, allowing each pin in that port to be
directed for input or output individually.
Any port set to input can select whether to use a pull-up
resistor or not by program.
P1_0 to P1_7 also function as LED drive ports.
Input Port P4_2, P4_6, P4_7 I Ports for input-only.
R8C/26, R8C/27 Group 1. Overview
Rev.0.10 Nov 14, 2005 Page 9 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
NOTES:
1. This can be assigned to the pin in parentheses by program.
Table 1.6 Pin Name Information by Pin Number
Pin
Number Control Pin Port
I/O Pin of Peripheral Func tion
Interrupt Timer Serial Interface
Clock
Synchronous
Serial I/O with
Chip Select
I2C bus
Interface A/D
Converter
1 P3_5 (TRCIOD)(1) SSCK SCL
2 P3_7 TRAO RXD1/(TXD1)(1) SSO
3RESET
4 XOUT P4_7
5 VSS/AVSS
6 XIN P4_6
7 VCC/AVCC
8MODE
9 P4_5 INT0 (RXD1)(1)
10 P1_7 INT1 TRAIO
11 P3_6 (INT1)(1) (TXD1)/(RXD1)(1)
12 P3_1 TRBO
13 P5_4 TRCIOD
14 P5_3 TRCIOC
15 P1_6 CLK0 (SSI)(1)
16 P1_5 (INT1)(1) (TRAIO)(1) RXD0
17 P1_4 TXD0
18 P1_3 KI3 TRBO AN11
19 P1_2 KI2 TRCIOB AN10
20 VRFF P4_2
21 P1_1 KI1 TRCIOA/
TRCTRG AN9
22 P1_0 KI0 AN8
23 P3_3 INT3 TRCCLK SSI
24 P3_4 (TRCIOC)(1) SCS SDA
25 P0_7 AN0
26 P0_6 AN1
27 P0_5 CLK1 AN2
28 P0_4 TREO AN3
29 P0_3 AN4
30 P0_2 AN5
31 P0_1 AN6
32 P0_0 (TXD1)(1) AN7
R8C/26, R8C/27 Group 2. Central Processing Unit (CPU)
Rev.0.10 Nov 14, 2005 Page 10 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise
a register bank. Two sets of register banks are provided.
Figure 2.1 CPU Register
R2
b31 b15 b8b7 b0
Data Registers (1)
Address Registers (1)
R3 R0H (high -order of R0)
R2
R3
A0
A1
INTBHb15b19 b0
INTBL
FB Frame Bass Register (1)
The 4-high order bits of INTB are INTBH and
the 16-low order bits of INTB are INTBL.
Interrupt Table Register
b19 b0
USP
Program Counter
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Reg ister
PC
FLG Flag Register
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Regist er B ank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Bit
Processor Interrupt Priority Level
Reserved Bit
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTES:
1. These registers comprise a register bank. There are two register banks.
R1H (high -order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
R8C/26, R8C/27 Group 2. Central Processing Unit (CPU)
Rev.0.10 Nov 14, 2005 Page 11 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
2.1 Data Registers (R0, R1, R2 and R3)
R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be
split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same
applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0).
The same applies to R3R1 as R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and addre ss register relative addressing. They also are
used for transfer , arithmetic and logic operations. The same applies to A1 as A0. A1 can be combined with A0 to be
used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC, 20 bits wide, indicates the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is a 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debug only. Set to “0”.
2.8.3 Zero Flag (Z)
The Z flag is set to “1” when an arithmetic operation resulted in 0; otherwise, “0”.
2.8.4 Sign Flag (S)
The S flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, “0”.
2.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is “0”. The register bank 1 is selected when this flag is set to “1”.
2.8.6 Overflow Flag (O)
The O flag is set to “1” when the operation resulted in an overflow; otherwise, “0”.
R8C/26, R8C/27 Group 2. Central Processing Unit (CPU)
Rev.0.10 Nov 14, 2005 Page 12 of 22
REJ03B0168-0010
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Specications in this manual are tentative and subject to change.
2.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The I flag is
set to “0” when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt requ est is acknowled ged or the INT instructi on of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
When write to this bit, set to “0”. When read, its content is indeterminate.
R8C/26, R8C/27 Group 3. Memory
Rev.0.10 Nov 14, 2005 Page 13 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
3. Memory
3.1 R8C/26Group
Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group provides the 1-Mbyte address space from
addresses 00000h to FFFFFh.
The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 16-Kbyte internal
ROM is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal
RAM is allocated add resses 00400h t o 007FFh. The internal RAM is used not only for storing data but for calling
subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and
cannot be accessed by users.
Figure 3.1 Memory Map of R8C/26 Group
Undefined I nstruction
Overflow
BRK Instr uc t ion
Address Match
Single Step
Watchdog Timer•Oscillation Stop Detection•Voltage Monitor
(Reserved)
(Reserved)
Reset
00400h
002FFh
00000h
Internal RAM
SFR
(See 4. Special Function
Register (SFR))
0FFFFh
0FFDCh
NOTES:
1. Blank spaces are reserved. No access is allowed.
FFFFFh
0FFFFh
0YYYYh Internal ROM
(Program ROM)
Expansion Area
0XXXh
Part Numb er Interna l ROM Inter na l RA M
Size Size
R5F21262SNF P, R5F2126 2SDFP
R5F2126 4SNFP, R5F2126 4SD FP
R5F21265SNF P, R5F2126 5SDFP
R5F21266SNF P, R5F2126 6SDFP
8 Kbyte s
16 Kbytes
24 Kbytes
32 Kbytes
0E000h
0C000h
0A000h
08000h
512 bytes
1 Kbyt e s
1.5 Kbytes
1.5 Kbytes
005FFh
007FFh
009FFh
009FFh
Address 0YYYYh Address 0XXXXh
R8C/26, R8C/27 Group 3. Memory
Rev.0.10 Nov 14, 2005 Page 14 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentative and subject to change.
3.2 R8C/27 Group
Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group provides the 1-Mbyte address space from
addresses 00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM is allocated addresses 0C00 0h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal
RAM is allocated add resses 00400h t o 007FFh. The internal RAM is used not only for storing data but for calling
subroutines and stacks when interrupt request is acknowledged.
Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and
cannot be accessed by users.
Figure 3.2 Memory Map of R8C/27 Group
Undefined I nstruction
Overflow
BRK Instr uc t ion
Address Match
Single Step
Watchdog Timer•Oscillation Stop Detection•Voltage Monitor
(Reserved)
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
00400h
002FFh
00000h
Internal ROM
(Program ROM)
Expansion Area
Internal RAM
SFR
(See 4. Special Function
Register (SFR))
0FFFFh
0FFDCh
Internal ROM
(Data flash)(1)
NOTES:
1. The data flash block A (1 Kbytes) and B (1 Kbytes) are shown.
2. Blank spaces are reserved. No access is allo wed.
0XXXXh
02400h
02BFFh
Part Number Internal ROM Internal RAM
Size Address 0YYYYh Size Address 0XXXXh
R5F21272SNFP, R5F21272SDFP
R5F21274SNFP, R5F21274SDFP
R5F21275SNFP, R5F21275SDFP
R5F21276SNFP, R5F21276SDFP
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
0E000h
0C000h
0A000h
08000h
512 bytes
1 Kbyt e s
1.5 Kbytes
1.5 Kbytes
005FFh
007FFh
009FFh
009FFh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 15 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
4. Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR
information.
Table 4.1 SFR Information(1)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Software reset, the watchdog timer reset, the voltage moni tor 1 or the voltage monitor 2 reset does not aff ect this regist er.
3. Owing to Hardware reset.
4. Owing to Power-on rese t or the voltage monitor 0 reset.
5. Software reset, the watchdog timer reset, the voltage monitor 1 or the voltage monitor 2 reset does not affect b2 and b3.
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation Stop Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 000XXXXXb
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0030h
0031h Voltage Detection Register 1 (2) VCA1 00001000b
0032h Voltage Detection Register 2 (2) VCA2 00h (3)
01000000b (4)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register (5) VW1C 00001000b
0037h Voltage Monitor 2 Circuit Control Register (5) VW2C 00h
0038h Voltage Monitor 0 Circuit Control Register (2) VW0C 00001000b (3)
01001001b (4)
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 16 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
Table 4.2 SFR Information(2)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Selected by the IICSEL bit in the PMR register.
Address Register Symbol After reset
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register TRCIC XXXXX000b
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh SSU / IIC Interrupt Control Register (2) SSUIC / IICIC XXXXX000b
0050h
0051h UART0 Transmit Interrupt Cont rol Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 17 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
Table 4.3 SFR Information(3)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. Selected by the IICSEL bit in the PMR register.
Address Register Symbol After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Ra te Register U0BRG XXh
00A2h UART0 Transmit Buf fer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00 001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00 000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Ra te Register U1BRG XXh
00AAh UART1 Transmit Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(2) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(2) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Regist er(2) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(2) SSER / ICIER 00h
00BCh SS Status Register / IIC bus Status Register(2) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register (2) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(2) SSRDR / ICDRR FFh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 18 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
Table 4.4 SFR Information(4)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address Register Symbol After reset
00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 00h
00D5h
00D6h A/D Control Register 0 ADCON0 00h
00D7h A/D Control Register 1 ADCON1 00h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 XXh
00E1h Port P1 Register P1 XXh
00E2h Port P0 Dir ection Regi ster PD0 00h
00E3h Port P1 Dir ection Regi ster PD1 00h
00E4h
00E5h Port P3 Register P3 XXh
00E6h
00E7h Port P3 Dir ection Regi ster PD3 00h
00E8h Port P4 Register P4 XXh
00E9h Port P5 Register P5 XXh
00EAh Port P4 Direction Register PD4 00h
00EBh Port P5 Direction Register PD5 00h
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h Pin Sel ect Registe r 1 PINSR1 0 0h
00F6h Pin Sel ect Registe r 2 PINSR2 0 0h
00F7h Pin Sel ect Registe r 3 PINSR3 0 0h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 XX000000b
00FEh Port P1 Drive Capacity Control Register DRR 00h
00FFh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 19 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
Table 4.5 SFR Information(5)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address Register Symbol After reset
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h
0119h Timer RE Minute Data Register / Compare Register TREMIN 00h
011Ah Timer RE Time Data Register TREHR 00h
011Bh Timer RE Day Data Register TREWK 00h
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Clock Source Select Register TRECSR 00001000b
011Fh
0120h Time r RC Mode Register TRCMR 01 001000b
0121h Timer RC Control Register 1 TRCCR1 00h
0122h Time r RC Interrupt Enable Register TRCIER 01110000b
0123h Timer RC Status Register TRCSR 01110000b
0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b
0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b
0126h Timer RC Counter TRC 00h
0127h 00h
0128h Timer RC General Register A TRCGRA FFh
0129h FFh
012Ah Timer RC General Register B TRCGRB FFh
012Bh FFh
012Ch Timer RC General Register C TRCGRC FFh
012Dh FFh
012Eh Timer RC General Register D TRCGRD FFh
012Fh FFh
0130h Timer RC Control Register 2 TRCCR2 00011111b
0131h Timer RC Digital Filter Function Select Register TRCDF 00h
0132h Timer RC Output Master Enable Register TRCOER 01111111b
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 20 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
Table 4.6 SFR Information(6)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
Address Register Symbol After reset
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
R8C/26, R8C/27 Group 4. Special Function Register (SFR)
Rev.0.10 Nov 14, 2005 Page 21 of 22
REJ03B0168-0010
Under development Preliminary specification
Specications in this manual are tentat ive and subject to change.
Table 4.7 SFR Information(7)(1)
X: Undefined
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. The OFS register cannot be changed by program. Use a flash programmer to write to it.
Address Register Symbol After reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh Option Function Select Register OFS (Note 2)
Rev.0.10 Nov 14, 2005 Page 22 of 22
REJ03B0168-0010
R8C/26, R8C/27 Group Package Dimensions
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
Package Dimensions
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
*3
F
32
25
24 17
16
9
81
*1
*2
x
b
p
e
H
E
E
D
H
D
Z
D
Z
E
Detail F
L
1
L
A
c
A
2
A
1
Previous CodeJEITA Package Code RENESAS Code
PLQP0032GB-A 32P6U-A
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
1.0
0.125
0.35
0.7
0.7
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9
D
7.17.06.9
E
1.4
A
2
9.29.08.8
9.29.08.8
1.7
A
0.20.1
0
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
b
1
c
1
bp
c
A - 1
REVISION HISTORY R8C/26, R8C/27 Group Shortsheet
Rev. Date Description
Page Summary
0.10 Nov 14, 2005 −First Edition issued
REVISION HISTORY R8C/26, R8C/27 Group Shortsheet
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