IRLR7807ZTRPBF - INTERNATIONAL RECTIFIER

www.irf.com 1

12/8/04

IRLR7807ZPbF

IRLU7807ZPbF

HEXFET® Power MOSFET

Notes  through  are on page 11

Applications

Benefits

lVery Low RDS(on) at 4.5V VGS

lUltra-Low Gate Impedance

lFully Characterized Avalanche Voltage

and Current

lHigh Frequency Synchronous Buck

Converters for Computer Processor Power

lLead-Free

D-Pak

IRLR7807Z I-Pak

IRLU7807Z

PD - 95777A

VDSS RDS(on) max Qg (typ

30V 13.8m

:

7.0nC

Absolute Maximum Ratings

Parameter Units

VDS Dr ain-to- Source Voltage V

VGS Gat e- to-Source Voltage

ID @ TC = 25 °C Co nti n uo us D rain C ur rent, VGS @ 10V

ID @ TC = 10 0°C

Co nti n uo us D rain C ur rent, V

@ 10V

IDM

Pulsed D r ain Current

PD @TC = 25°C

Maximum Power D issi pation

PD @TC = 100°C

Maximum Power D issi pation

Linear Derating Factor W/°C

TJ Operatin g Junction and °C

TSTG Stor ag e Te m per ature Ra ng e

Soldering Temperature, for 10 seconds

Thermal Resist ance

Parameter Typ. Max. Units

RθJC Junction-to-Case ––– 3.75

RθJA

Junc ti o n- to- A mbien t (P CB Mo unt )

g

––– 50 °C/W

RθJA Junction-to-Ambient ––– 110

Max.

170

± 20

0.27

300 ( 1.6m m f r o m ca se)

-55 to + 17 5

IRLR/U7807ZPbF

2www.irf.com

Static @ TJ = 25°C (unles s otherwise s pec ified)

Parameter Min. Typ. Max. Units

DSS Drain-to-Sou rce Breakdown Voltage 30 ––– ––– V

∆Β

DSS

∆

J B reak dow n Vo l tag e Tem p. Coeffi c i e nt ––– 23 ––– m V/°C

DS(on) Static Drai n-t o- Source O n- Resist ance ––– 11 13.8

Ω

––– 14.5 18.2

GS(th) Gate Thr eshold Volt age 1.35 1.8 2.25 V

∆

GS(th)

∆

JGat e Threshol d Voltage C oeffici ent ––– -4. 5 ––– mV/°C

DSS Drain- to-Source Leakage Curren t ––– ––– 1.0 µA

––– ––– 150

GSS Gate-to-Source Forward Leakage ––– ––– 100 nA

Gate-t o- Source Reve rse Leaka ge ––– ––– -1 00

gf s F orw a r d Tr a ns c ond uctan ce 51 – –– – –– S

gTotal Gate Charge ––– 7.0 11

gs1 Pre-Vth Gate-to-Source Charge ––– 1.8 –––

gs2 Post-Vth Gate-to-Source Charge ––– 0.7 ––– nC

gd Ga t e - to- Dr ain C ha r ge ––– 2.7 –––

godr Gate Char g e O v er dri v e ––– 1.8 ––– Se e Fi g. 16

Switch Charge (Q

gs2

+ Q

)

––– 3.4 –––

oss Output Charge ––– 4.0 ––– nC

d(on) T urn-On Delay Tim e ––– 7. 1 –––

rRise Time –––28–––

d(off) Turn-Off Delay Time ––– 9.8 ––– ns

fFall Time ––– 3.5 –––

iss Input Capaci tance ––– 780 –– –

oss Output Capacitance ––– 180 ––– pF

rss R everse Tra nsfer Cap acitance ––– 100 –––

Avalanche Characteristics

Parameter Units

Single Pul s e Avala nche Energy

Avalanche Current

c

Re petit i ve Ava l a nc he Ener g y

Diode Characteristics

Paramet e r Min . Typ. Ma x. Un its

SCo ntinuous S o ur c e Cu r rent ––– –––

(Body Diode) A

SM Pulsed Source Current ––– ––– 170

(Body Diode)

c

SD Diode Forward Voltage ––– ––– 1.0 V

rr Reve r se Reco ver y Ti me ––– 23 35 ns

rr Reverse R ecovery Cha r ge ––– 14 2 1 nC

on Forward Turn-On Time

VDS = VGS, ID = 250µ A

VDS = 24V , V GS = 0V

VDS = 24V , V GS = 0V , TJ = 12 5°C

Conditions

4.0

Max.

ƒ = 1. 0M H z

ID = 12A

VDS = 15V

Conditions

VGS = 0V, ID = 25 0µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 15A

VGS = 4.5V , ID = 12A

VGS = 20V

VGS = -20V

VDS = 15V , I D = 12A

VDS = 15V , V GS = 0V

VDD = 15V, V GS = 4.5V

Cla m ped I n du ctive Lo ad

TJ = 25°C, IF = 12 A, V DD = 15V

di /dt = 100A/µs

TJ = 25°C, IS = 12A, VGS = 0V

showing t he

integra l revers e

p-n ju nctio n diode.

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

MOSFET symbol

–––

VGS = 4.5V

Typ.

–––

ID = 12A

VGS = 0V

VDS = 15V

IRLR/U7807ZPbF

www.irf.com 3

Fig 4. Normalized On-Resistance

vs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

0.1 110

VDS, Drain-to-Source Volt age (V)

0.1

100

1000

ID, Drain-to-Source Current (A)

2.5V

20µs PU LSE WIDT H

Tj = 175°C

VGS

TOP 10V

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

BOTTOM 2.25V

2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0

VGS, G ate-to-Source Voltage (V )

0.1

1.0

10.0

100.0

1000.0

ID, Drain-to-Source Current (Α)

TJ = 25° C

TJ = 175° C

VDS = 10V

20µs PU LSE WIDT H

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction T em perature ( °C)

0.5

1.0

1.5

2.0

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 30A

VGS = 10V

0.1 110

VDS, Dr ain-to-Sour ce Vol tage (V)

0.001

0.01

0.1

100

1000

ID, Drain-to-Source Current (A)

2.5V

20µs PU LSE WIDT H

Tj = 25°C

VGS

TOP 10V

5.0V

4.5V

3.5V

3.0V

2.7V

2.5V

BOTTOM 2.25V

IRLR/U7807ZPbF

4www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Dr ain-to-Source Voltage ( V)

100

1000

10000

C, Capacitance (pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, C ds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0 4 8 12 16

QG Tot al Gate Char ge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 24V

VDS= 15V

ID= 12A

0.0 0.5 1.0 1.5 2.0

VSD, Source-t oDrain Volt age (V )

0.1

1.0

10.0

100.0

1000.0

ISD, Reverse Drain Current (A)

TJ = 25° C

TJ = 175° C

VGS = 0V

0.1 1.0 10.0 100.0 1000.0

VDS , Dr ain-toS ource Voltage (V )

0.1

100

1000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY RDS(on)

100µsec

IRLR/U7807ZPbF

www.irf.com 5

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.

Case Temperature Fig 10. Threshold Voltage vs. Temperature

25 50 75 100 125 150 175

TC , C ase Temper ature (°C)

ID , Drain Current (A)

LIMITED BY PACKAGE

-75 -50 -25 025 50 75 100 125 150 175

TJ , T em perat ure ( °C )

1.0

1.5

2.0

2.5

VGS(th) Gate threshold Voltage (V)

ID = 250µA

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangul ar P ulse Duration ( sec)

0.001

0.01

0.1

Thermal Response ( Z thJC )

0.20

0.10

D = 0. 50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zt hjc + Tc

Ri (°C/W) τi (sec)

1.796 0.000267

1.112 0.000607

0.842 0.004249

τJ

τ1

τ1τ2

τ2τ3

τ3

R1R2

R2R3

Ci= i/Ri

Ci= τi/Ri

IRLR/U7807ZPbF

6www.irf.com

D.U.T. V

3mA

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

Fig 13. Gate Charge Test Circuit

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

25 50 75 100 125 150 175

Starting TJ, Juncti on Temperatur e (°C)

100

120

EAS, Single Pulse Avalanche Energy (mJ)

TOP 3.0A

1.4A

BOTTOM 12A

Fig 14a. Switching Time Test Circuit

Fig 14b. Switching Time Waveforms

VGS

VDS

10%

td(on) td(off)

trtf

VGS

Pulse Width < 1µs

Duty Factor < 0.1%

VDD

VDS

D.U.T

IRLR/U7807ZPbF

www.irf.com 7

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

e-Applied

oltage

Reverse

Recovery

Current Body Diode Forward

Current

=10V

Driver Gate Drive

D.U.T. I

Waveform

D.U.T. V

Waveform

Inductor Curent

D = P.W.

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



Fig 16. Gate Charge Waveform

Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

IRLR/U7807ZPbF

8www.irf.com

Control FET

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the Rds(on) of the

MOSFET, but these conduction losses are only about

one half of the total losses.

Power losses in the control switch Q1 are given

by;

Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput

This can be expanded and approximated by;

loss =Irms 2×Rds(on )

()

+I×Qgd

×Vin ×f

⎛

⎝

⎜ ⎞

⎠

⎟ +I×Qgs2

×Vin ×

⎛

⎝

⎜ ⎞

⎠

⎟

+Qg×Vg×f

()

+Qoss

2×Vin ×f

⎛

⎝ ⎞

⎠

This simplified loss equation includes the terms Qgs2

and Qoss which are new to Power MOSFET data sheets.

Qgs2 is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Qgs1 and Qgs2, can be seen from

Fig 16.

Qgs2 indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to Idmax at which time the drain voltage be-

gins to change. Minimizing Qgs2 is a critical factor in

reducing switching losses in Q1.

Qoss is the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Qoss is formed by the

parallel combination of the voltage dependant (non-

linear) capacitances Cds and Cdg when multiplied by

the power supply input buss voltage.

Synchronous FET

The power loss equation for Q2 is approximated

by;

loss =P

conduction +P

drive +P

output

loss =Irms

2×Rds(on)()

+Qg×Vg×f

()

+Qoss

2×Vin ×f

⎛

⎝

⎜ ⎞

⎠ +Qrr ×Vin ×

(

)

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, Rds(on) is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Qoss and re-

verse recovery charge Qrr both generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and Vin. As Q1 turns on and of f there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Qgd/Qgs1 must be minimized to reduce the

potential for Cdv/dt turn on.

Power MOSFET Selection for Non-Isolated DC/DC Converters

Figure A: Qoss Characteristic

IRLR/U7807ZPbF

www.irf.com 9

D-Pak (TO-252AA) Part Marking Information

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

IN THE ASSEMBLY LINE "A"

ASSEMBLED ON WW 16, 1999

EXAMPLE: WIT H ASSE MBLY

THIS IS AN IRFR120

LOT CODE 12 34 YEAR 9 = 199

DA TE CODE

WEEK 16

PART NUMBER

LOGO

INTERNATIONAL

RECTIFIER

AS S EMBLY

LOT CODE

916A

IRFU120

YEAR 9 = 1999

DATE CODE

P = DESIGNATES LEAD-FREE

PRODUCT (OPTIONAL)

Note: "P" in assembly line position

indicate s "Lead-F ree"

12 34

WEEK 16

A = AS S E MB L Y S IT E CODE

PART NUMBER

IRFU120

LINE A

LOGO

LOT CODE

AS S E MB L Y

INTERNATIONAL

RECTIFIER

IRLR/U7807ZPbF

10 www.irf.com

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

AS S EMBLY

EXAMPLE: WIT H AS SEMBLY

THIS IS AN IRFU120

YEAR 9 = 199

DATE C O DE

LI NE A

WEEK 19

IN THE ASSEM BLY LINE "A"

ASSEMBLED O N WW 19, 1999

LOT CODE 5678

PART NUMBER

IRFU120

INTERNATIONAL

LOGO

RECTIFIER

LOT CODE

919A

Note: "P" in asse mb ly line

pos ition indicates "Lead-F ree"

56 78

AS S E MB LY

LOT CODE

RECTIFIER

LOGO

INTERNATIONAL

IRFU120

PART NUMBER

WEEK 19

DATE CODE

YEAR 9 = 1999

A = ASSEMBLY SITE CODE

P = D E SI GNATES LEAD- FREE

PRODUCT (OPTIONAL)

IRLR/U7807ZPbF

www.irf.com 11

 Repetitive rating; pulse width limited by

max. junction temperature.

 Starting TJ = 25°C, L = 0.39mH, RG = 25Ω,

IAS = 12A.

 Pulse width ≤ 400µs; duty cycle ≤ 2%.

Notes:

 Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 30A.

 When mounted on 1" square PCB (FR-4 or G-10 Material).

For recommended footprint and soldering techniques refer to

application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.12/04

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)

16.3 ( .641 )

15.7 ( .619 )

8.1 ( .318 )

7.9 ( .312 )

12.1 ( .476 )

11.9 ( .469 ) FEED DIRECTION FEED DIRE CTION

16.3 ( .641

)

15.7 ( .619

)

TRR TRL

OTES :

. CONTROLLING DIMENSION : MILLIMETE R.

. ALL D IMENSIONS ARE SH OWN IN MIL L IMETERS ( IN C H ES ).

. OUTLINE CONFORMS TO EIA-481 & EIA-541.

NOTES :

1. OUTLINE CONFORMS TO EIA-481.

16 mm

13 INCH

Note: For the most current drawings please refer to the IR website at:

http://www.irf.com/package/