MF0UL1101DUD,005 - NXP Semiconductors

MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Rev. 3.3 — 9 April 2019 Product data sheet

234533 COMPANY PUBLIC

1 General description

NXP Semiconductors developed the MIFARE Ultralight EV1 MF0ULx1 for use in a

contactless smart ticket, smart card or token in combination with a Proximity Coupling

Device (PCD). The MF0ULx1 is designed to work in an ISO/IEC 14443 Type A compliant

environment (see [1]). The target applications include single trip or limited use tickets in

public transportation networks, loyalty cards or day passes for events. The MF0ULx1

serves as a replacement for conventional ticketing solutions such as paper tickets,

magnetic stripe tickets or coins. It is also a perfect ticketing counterpart to contactless

card families such as MIFARE DESFire or MIFARE Plus.

The MIFARE Ultralight EV1 is succeeding the MIFARE Ultralight ticketing IC and is fully

functional backwards compatible. Its enhanced feature and command set enable more

efficient implementations and offer more flexibility in system designs.

The mechanical and electrical specifications of MIFARE Ultralight EV1 are tailored to

meet the requirements of inlay and paper ticket manufacturers.

In this document the term „MIFARE Ultralight card“ refers to a MIFARE Ultralight IC-

based contactless card.

1.1 Contactless energy and data transfer

In a contactless system, the MF0ULx1 is connected to a coil with a few turns. The

MF0ULx1 fits the TFC.0 (Edmondson) and TFC.1 (ISO) ticket formats as defined in Ref.

The MF0ULx1 chip, which is available with 17 pF or 50 pF on-chip resonance capacitor,

supports both TFC.1 and TFC.0 ticket formats.

1.2 Anticollision

An intelligent anticollision function allows more than one card to operate in the field

simultaneously. The anticollision algorithm selects each card individually. It ensures

that the execution of a transaction with a selected card is performed correctly without

interference from another card in the field.

aaa-006271

energy

data

ISO/IEC 14443 A

PCD

Figure 1. Contactless system

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 2 / 45

1.3 Simple integration and user convenience

The MF0ULx1 is designed for simple integration and user convenience which allows

complete ticketing transactions to be handled in less than 35 ms.

1.4 Security

•Manufacturer programmed 7-byte UID for each device

•32-bit user definable One-Time Programmable (OTP) area

•3 independent 24-bit true one-way counters

•Field programmable read-only locking function per page (per 2 pages for the extended

memory section)

•ECC based originality signature

•32-bit password protection to prevent unintended memory operations

1.5 Naming conventions

Table 1. Naming conventions

MF0ULHx101Dyy Description

MF MIFARE product family

0 MIFARE Ultralight product family

UL Product: MIFARE Ultralight

H If present, defining high input capacitance

H... 50 pF input capacitance

x One character identifier defining the memory size

1... 640 bit total memory, 384 bit free user memory

2... 1312 bit total memory, 1024 bit free user memory

Dyy yy defining the delivery type

UF... bare die, 75 μm thickness, Au bumps, e-map file

UD... bare die, 120 μm thickness, Au bumps, e-map file

A8... MOA8 contactless module

2 Features and benefits

•Contactless transmission of data and supply

energy

•Operating distance up to 100 mm

depending on antenna geometry and reader

configuration

•Operating frequency of 13.56 MHz •Data transfer of 106 kbit/s

•Data integrity of 16-bit CRC, parity, bit coding,

bit counting

•True anticollision

•7 byte serial number (cascade level 2

according to ISO/IEC 14443-3)

•Typical ticketing transaction: < 35 ms

•Fast counter transaction: < 10 ms

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 3 / 45

2.1 EEPROM

•640-bit or 1312-bit, organized in 20 or 41

pages with 4 bytes per page

•First 512 bits compatible to MF0ICU1

•Field programmable read-only locking

function per page for the first 512 bits

•Field programmable read-only locking

function per 2 pages above page 15

•32-bit user definable One-Time

Programmable (OTP) area

•384-bit or 1024-bit freely available user Read/

Write area (12 or 32 pages)

•3 independent, true one-way 24-bit counters

on top of the user area

•Anti-tearing support for counters, OTP area

and lock bits

•Configurable password protection with

optional limit of unsuccessful attempts

•ECC based originality signature

•Data retention time of 10 years •Write endurance 100.000 cycles

•Write endurance for one-way counters

1.000.000 cycles

3 Applications

•Public transportation

•Event ticketing

•Loyalty

4 Quick reference data

Table 2. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

Ciinput capacitance MF0ULx1 [1] - 17.0 - pF

Ciinput capacitance MF0ULHx1 [1] - 50.0 - pF

fiinput frequency - 13.56 - MHz

EEPROM characteristics

tret retention time Tamb = 22 °C 10 - - year

Nendu(W) write endurance Tamb = 22 °C 100000 - - cycle

Nendu(W) write endurance counters Tamb = 22 °C 100000 1000000 - cycle

[1] Tamb = 22 °C, f = 13.56 MHz, VLaLb = 1.5 V RMS

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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5 Ordering information

Table 3. Ordering information

PackageType number

Name Description Version

MF0UL1101DUF FFC Bump 8 inch wafer, 75 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

384 bit user memory, 17 pF input capacitance

MF0UL1101DUD FFC Bump 8 inch wafer, 120 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

384 bit user memory, 17 pF input capacitance

MF0UL1101DUD2 FFC Bump 12 inch wafer, 120 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

384 bit user memory, 17 pF input capacitance

MF0ULH1101DUF FFC Bump 8 inch wafer, 75 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

384 bit user memory, 50 pF input capacitance

MF0ULH1101DUD FFC Bump 8 inch wafer, 120 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

384 bit user memory, 50 pF input capacitance

MF0UL2101DUF FFC Bump 8 inch wafer, 75 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

1024 bit user memory, 17 pF input capacitance

MF0UL2101DUD FFC Bump 8 inch wafer, 120 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

1024 bit user memory, 17 pF input capacitance

MF0UL2101DUD2 FFC Bump 12 inch wafer, 120 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

1024 bit user memory, 17 pF input capacitance

MF0ULH2101DUF FFC Bump 8 inch wafer, 75 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

1024 bit user memory, 50 pF input capacitance

MF0ULH2101DUD FFC Bump 8 inch wafer, 120 μm thickness, on film frame carrier, electronic fail die

marking according to SECS-II format), Au bumps,

1024 bit user memory, 50 pF input capacitance

MF0UL2101DA8 MOA8 plastic lead less module carrier package; 35 mm wide tape,

1024 bit user memory, 17 pF input capacitance

SOT500-4

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 5 / 45

6 Block diagram

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antenna RF-INTERFACE

DIGITAL CONTROL UNIT

EEPROM

ANTICOLLISION

COMMAND

INTERPRETER

EEPROM

INTERFACE

Figure 2. Block diagram of MF0ULx1

7 Pinning information

7.1 Pinning

The pinning for the MF0ULx1DAx is shown Figure 3 for a contactless MOA8 module.

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LA LBtop view

Figure 3. Pin configuration for SOT500-4 (MOA8)

Table 4. Pin allocation table

Pin Symbol

LA LA antenna coil connection LA

LB LB antenna coil connection LB

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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8 Functional description

8.1 Block description

The MF0ULx1 chip consists of a 640-bit or a 1312-bit EEPROM, RF interface and Digital

Control Unit (DCU). Energy and data are transferred via an antenna consisting of a

coil with a few turns which is directly connected to the MF0ULx1. No further external

components are necessary. Refer to Ref. 2 for details on antenna design.

•RF interface:

–modulator/demodulator

–rectifier

–clock regenerator

–Power-On Reset (POR)

–voltage regulator

•Anticollision: multiple cards may be selected and managed in sequence

•Command interpreter: processes memory access commands that the MF0ICU1

supports

•EEPROM interface

•EEPROM: 640 bit, organized in 20 pages of 4 byte per page.

–208 bit reserved for manufacturer and configuration data

–16 bit used for the read-only locking mechanism

–32 bit available as OTP area

–384 bit user programmable read/write memory

•EEPROM: 1312 bit, organized in 41 pages of 4 byte per page.

–208 bit reserved for manufacturer and configuration data

–31 bit used for the read-only locking mechanism

–32 bit available as OTP area

–1024 bit user programmable read/write memory

8.2 RF interface

The RF-interface is based on the ISO/IEC 14443 Type A standard for contactless smart

cards.

During operation, the reader generates an RF field. This RF field must always be present

(with short pauses for data communication), as it is used for the power supply of the card.

For both directions of data communication, there is one start bit at the beginning of each

frame. Each byte is transmitted with an odd parity bit at the end. The LSB of the byte with

the lowest address of the selected block is transmitted first. The maximum length of a

PCD to PICC frame is 208 bits (21 data bytes + 2 CRC bytes = 20×9 + 2×9 + 1 start bit).

The maximum length for a fixed size PICC to PCD frame is 307 bits (32 data bytes + 2

CRC bytes = 32×9 + 2×9 + 1 start bit). The FAST_READ response has a variable frame

length depending on the start and end address parameters. When issuing this command,

take into account the maximum frame length that the PCD supports.

For a multi-byte parameter, the least significant byte is always transmitted first. As an

example, take reading from the memory using the READ command. Byte 0 from the

addressed block is transmitted first after which, byte 1 to byte 3 are transmitted. The

same sequence continues for the next block and all subsequent blocks.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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8.3 Data integrity

Following mechanisms are implemented in the contactless communication link between

reader and card to ensure very reliable data transmission:

•16 bits CRC per block

•parity bits for each byte

•bit count checking

•bit coding to distinguish between "1", "0" and "no information"

•channel monitoring (protocol sequence and bit stream analysis)

8.4 Communication principle

The reader initiates the commands and the Digital Control Unit of the MF0ULx1 controls

them. The command response is depending on the state of the IC and for memory

operations also on the access conditions valid for the corresponding page.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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(

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Remark: In all states, the command interpreter returns to the idle state on receipt of an

unexpected command. If the IC was previously in the HALT state, it returns to that state

Remark: The VCSL command is only allowed in the ACTIVE state

Figure 4. State diagram

8.4.1 IDLE state

After a power-on reset (POR), the MF0ULx1 switches to the IDLE state. It only exits this

state when a REQA or a WUPA command is received from the PCD. Any other data

received while in this state is interpreted as an error and the MF0ULx1 remains in the

IDLE state.

Refer to Ref. 4 for implementation hints for a card polling algorithm that respects relevant

timing specifications from ISO/IEC 14443 Type A.

After a correctly executed HLTA command, for example out of the ACTIVE or

AUTHENTICATED state, the default waiting state changes from IDLE to HALT. This

state can then be exited with a WUPA command only.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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8.4.2 READY1 state

In this state, the PCD resolves the first part of the UID (3 bytes) using the

ANTICOLLISION or SELECT commands in cascade level 1. This state is exited correctly

after execution of either of the following commands:

•SELECT command from cascade level 1: the PCD switches the MF0ULx1 into

READY2 state where the second part of the UID is resolved.

•READ command (from address 0): all anticollision mechanisms are bypassed and the

MF0ULx1 switches directly to the ACTIVE state.

Remark: If more than one MF0ULx1 is in the PCD field, a READ command from

address 0 selects all MF0ULx1 devices. In this case, a collision occurs due to the

different serial numbers. Any other data received in the READY1 state is interpreted as

an error. Depending on its previous state, the MF0ULx1 returns to either the IDLE state

or HALT state.

8.4.3 READY2 state

In this state, the MF0ULx1 supports the PCD in resolving the second part of its UID (4

bytes) with the cascade level 2 ANTICOLLISION command. This state is usually exited

using the cascade level 2 SELECT command.

Alternatively, READY2 state can be skipped using a READ command (from address 0)

as described for the READY1 state.

Remark: The response of the MF0ULx1 to the cascade level 2 SELECT command is the

select acknowledge (SAK) byte. In accordance with ISO/IEC 14443, this byte indicates

if the anticollision cascade procedure has finished. It also defines the type of device

selected for the MIFARE product architecture platform. The MF0ULx1 is now uniquely

selected and only this device communicates with the PCD even when other contactless

devices are present in the PCD field. If more than one MF0ULx1 is in the PCD field, a

READ command from address 0 selects all MF0ULx1 devices. In this case, a collision

occurs due to the different serial numbers. Any other data received when the device is in

this state is interpreted as an error. Depending on its previous state the MF0ULx1 returns

to either the IDLE state or HALT state.

8.4.4 ACTIVE state

All memory operations and other functions like the originality signature read-out are

operated in the ACTIVE state.

The ACTIVE state is gratefully exited with the HLTA command and upon reception the

MF0ULx1 transits to the HALT state. Any other data received when the device is in this

state is interpreted as an error. Depending on its previous state the MF0ULx1 returns to

either the IDLE state or HALT state.

The MF0ULx1 transits to the AUTHENTICATED state after successful password

verification using the PWD_AUTH command.

8.4.5 AUTHENTICATED state

In this state, all operations on memory pages, which are configured as password

verification protected, can be accessed.

The AUTHENTICATED state is gratefully exited with the HLTA command and upon

reception the MF0ULx1 transits to the HALT state. Any other data received when the

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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device is in this state is interpreted as an error. Depending on its previous state the

MF0ULx1 returns to either the IDLE state or HALT state.

8.4.6 HALT state

The HALT and IDLE states constitute the two wait states implemented in the MF0ULx1.

An already processed MF0ULx1 can be set into the HALT state using the HLTA

command. In the anticollision phase, this state helps the PCD to distinguish between

processed cards and cards yet to be selected. The MF0ULx1 can only exit this state on

execution of the WUPA command. Any other data received when the device is in this

state is interpreted as an error and the MF0ULx1 state remains unchanged. Refer to Ref.

4 for correct implementation of an anticollision procedure based on the IDLE and HALT

states and the REQA and WUPA commands.

8.5 Memory organization

The EEPROM memory is organized in pages with 4 bytes per page. The MF0UL11

variant has 20d pages and the MF0UL21 variant has 41d pages in total. The memory

organization can be seen in Figure 5 and Figure 6, the functionality of the different

memory sections is described in the following sections.

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1. counter pages are only accessible with READ_CNT and INCR_CNT commands

Figure 5. Memory organization MF0UL11

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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a p

l n

r me

r d

a a

Tim

r me

)

r p

1. counter pages are only accessible with READ_CNT and INCR_CNT commands

Figure 6. Memory organization MF0UL21

8.5.1 UID/serial number

The unique 7-byte serial number (UID) and its two check bytes are programmed into

the first 9 bytes of memory covering page addresses 00h, 01h and the first byte of page

02h. The second byte of page address 02h is reserved for internal data. These bytes are

programmed and write protected in the production test.

001aai001

MSB LSB

page 0

byte

check byte 0

serial number

part 1

serial number

part 2

manufacturer ID for NXP Semiconductors (04h)0 0 0 0 0 1 0 0

0 1 2 3

page 1

0 1 2 3

page 2

0 1 2 3

internal

check byte 1

lock bytes

Figure 7. UID/serial number

In accordance with ISO/IEC 14443-3 check byte 0 (BCC0) is defined as CT ⊕ SN0 ⊕

SN1 ⊕ SN2. Check byte 1 (BCC1) is defined as SN3 ⊕ SN4 ⊕ SN5 ⊕ SN6.

SN0 holds the Manufacturer ID for NXP Semiconductors (04h) in accordance with ISO/

IEC 14443-3 and ISO/IEC 7816-6 AMD.1

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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8.5.2 Lock byte 0 and byte 1

The bits of byte 2 and byte 3 of page 02h represent the field programmable read-only

locking mechanism. Each page from 03h (OTP) to 0Fh can be individually locked by

setting the corresponding locking bit Lx to logic 1 to prevent further write access. After

locking, the corresponding page becomes read-only memory.

The three least significant bits of lock byte 0 are the block-locking bits. Bit 2 deals

with pages 0Ah to 0Fh, bit 1 deals with pages 04h to 09h and bit 0 deals with page

03h (OTP). Once the block-locking bits are set, the locking configuration for the

corresponding memory area is frozen.

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OTP

15-10

9-4

OTP

MSB

page 2

Lx locks page x to read-only

BLx blocks further locking for the memory area x

lock byte 0

lock byte 1

1 2 3

LSB

MSB LSB

Figure 8. Lock bytes 0 and 1

For example if BL15-10 is set to logic 1, then bits L15 to L10 (lock byte 1, bit[7:2]) can

no longer be changed. A WRITE command or COMPATIBILITY_WRITE command to

page 02h, sets the locking and block-locking bits. Byte 2 and byte 3 of the WRITE or

COMPATIBILITY_WRITE command, and the contents of the lock bytes are bit-wise

OR’ed and the result then becomes the new content of the lock bytes. This process is

irreversible. If a bit is set to logic 1, it cannot be changed back to logic 0.

The contents of bytes 0 and 1 of page 02h are unaffected by the corresponding data

bytes of the WRITE or COMPATIBILITY_WRITE command.

The default value of the static lock bytes is 00 00h.

Any write operation to the lock bytes 0 and 1, features anti-tearing support.

Remark: Setting a lock bit to 1 immediately prevents write access to the respective page

8.5.3 Lock byte 2 to byte 4

To lock the pages of the MF0UL21 starting at page address 10h onwards, the lock bytes

2-4 located in page 24h are used. Those three lock bytes cover the memory area of 80

data bytes. The granularity is 2 pages, compared to a single page for the first 512 bits as

shown in Figure 9.

Remark: Set all bits marked with RFUI to 0, when writing to the lock bytes.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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lock

byte 2

lock byte 3

(

)

F U

lock byte 4

Figure 9. Lock bytes 2-4

The default value of lock bytes 2-4 is 00 00 00h. The value of byte 3 on page 36 (see

Figure 9) is always BDh when read.

Any write operation to the lock bytes 2-4, features anti-tearing support.

Remark: Setting a lock bit to 1 immediately prevents write access to the respective

pages

8.5.4 OTP bytes

Page 03h is the OTP page and it is preset so that all bits are set to logic 0

after production. These bytes can be bit-wise modified using the WRITE or

COMPATIBILITY_WRITE command.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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001aak571

byte 12 13 14 15

page 3 example

OTP bytes

default value

00000000 00000000 00000000 00000000

1st write command to page 3

11111111 11111100 00000101 00000111

result in page 3

11111111 11111100 00000101 00000111

2nd write command to page 3

11111111 00000000 00111001 10000000

result in page 3

11111111 11111100 00111101 10000111

This memory area can be used as a 32 tick one-time counter.

Figure 10. OTP bytes

The parameter bytes of the WRITE command and the current contents of the OTP bytes

are bit-wise OR’ed. The result is the new OTP byte contents. This process is irreversible

and once a bit is set to logic 1, it cannot be changed back to logic 0.

The default value of the OTP bytes is 00 00 00 00h.

Any write operation to the OTP bytes features anti-tearing support.

8.5.5 Data pages

Pages 04h to 0Fh for the MF0UL11 and 04h to 23h for the MF0UL21 are the user

memory read/write area.

The access to a part of the user memory area can be restricted using a password

verification. See Section 8.6 for further details.

Remark: The default content of the data blocks at delivery is not defined.

8.5.6 Configuration pages

Pages 10h-13h for the MF0UL11 and pages 25h-28h for the MF0UL21 variant, are

used to configure the memory access restriction of the MF0ULx1. They are also used to

configure the response to a VCSL command. The memory content of the configuration

pages is detailed in Table 5, Table 7 and Table 8.

Table 5. Configuration Pages

Page Address Byte number

Dec Hex 0 1 2 3

16/37 10h/25h MOD RFUI RFUI AUTH0

17/38 11h/26h ACCESS VCTID RFUI RFUI

18/39 12h/27h PWD

19/40 13h/28h PACK RFUI RFUI

1. page address for MF0UL11/MF0UL21

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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Table 6. MOD configuration byte

Bit number

7 6 6 4 3 2 1 0

RFUI STRG_MOD_EN RFUI

Table 7. ACCESS configuration byte

Bit number

76643210

PROT CFGLCK RFUI AUTHLIM

Table 8. Configuration parameter descriptions

Field Bit Default

Value

Description

STRG_

MOD_EN

1 0b/1b[1] STRG MOD_EN defines the modulation mode

0b ... strong modulation mode disabled

1b ... strong modulation mode enabled

AUTH0 8 FFh

AUTH0 defines the page address from which the password verification

is required. Valid address range for byte AUTH0 is 00h to FFh.

If AUTH0 is set to a page address which is higher than the last user

configuration page, the password protection is effectively disabled.

PROT 1 0b

One bit inside the ACCESS byte defining the memory protection

0b ... write access is protected by the password verification

1b ... read and write access is protected by the password verification

CFGLCK 1 0b

Write locking bit for the user configuration

0b ... user configuration open to write access

1b ... user configuration permanently locked against write access

AUTHLIM 3 000b

Limitation of negative password verification attempts

000b... limiting of negative password verification attempts disabled

001b-111b ... maximum number of negative password verification

attempts

VCTID 8 05h

Virtual Card Type Identifier which represents the response to a VCSL

command. To ensure infrastructure compatibility, it is recommended

not to change the default value of 05h.

PWD 32 FFFF

FFFFh

32-bit password used for memory access protection

PACK 16 0000h 16-bit password acknowledge used during password verification

RFUI - all 0b Reserved for future use - implemented. Write all bits and bytes

denoted as RFUI as 0b.

[1] Values for MF0ULx1/MF0ULHx1. The STRG_MOD_EN feature is only available on the high capacitance variants

MF0ULHx1 types. For the MF0ULx1 types, this bit is set to 0b and only the strong modulator is available.

Remark: The CFGLCK bit activates the permanent write protection of the first two

configuration pages. The write lock is only activated after a power cycle of the MF0ULx1.

If write protection is enabled, each write attempt leads to a NAK response.

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MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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8.6 Password verification protection

The memory write or read/write access to a configurable part of the memory can be

constrained to a positive password verification. The 32-bit secret password (PWD)

and the 16-bit password acknowledge (PACK) are typically programmed into the

configuration pages at ticket issuing or personalization. The use of a chip individual

password acknowledge response raises the trust level on the PCD side into the PICC.

The AUTHLIM parameter specified in Section 8.5.6 can be used to limit the negative

verification attempts.

In the initial state of the MF0ULx1, an AUTH0 value of FFh disables password protection.

PWD and PACK are freely writable in this state. Access to the configuration pages and

any part of the user memory, can be restricted by setting AUTH0 a page address within

the available memory space. The page address is the first one protected.

Remark: Note that the password verification method available in then MF0ULx1 does not

offer a high security protection. It is an easy and convenient way to prevent unauthorized

memory access. If a higher level of protection is required, cryptographic methods on

application layer can be used to increase overall system security.

8.6.1 Programming of PWD and PACK

Program the 32-bit PWD and the 16-bit PACK into the configuration pages, see Section

8.5.6. The password as well as the password acknowledge, are written LSByte first. This

byte order is the same as the byte order used during the PWD_AUTH command and its

response.

The PWD and PACK bytes can never be read out of the memory. Instead of transmitting

the real value on any valid READ or FAST_READ command, only 00h bytes are replied.

If the password verification does not protect the configuration pages, PWD and PACK

can be written with normal WRITE and COMPATIBILITY_WRITE commands.

If the password verification protects the configuration pages, PWD and PACK can only

be written after a successful PWD_AUTH command.

The PWD and PACK are writable even if the CFGLCK bit is set to 1b. Therefore it is

strongly recommended to set AUTH0 to the page where the PWD is located after the

password has been written. This page is 12h for the MF0UL11 and 27h for the MF0UL21.

Remark: To improve the overall system security, it is strongly recommended to diversify

the password and the password acknowledge using a die individual parameter, that is,

the 7-byte UID available on the MF0ULx1.

8.6.2 Limiting negative verification attempts

To prevent brute-force attacks on the password, the maximum allowed number of

negative password verification attempts can be set using AUTHLIM. This mechanism

is disabled by setting AUTHLIM to a value of 000b which is also the initial state of the

MF0ULx1.

If AUTHLIM is not equal to 000b, each negative authentication verification is internally

counted. The count operation features anti-tearing support. As soon as this internal

counter reaches the number specified in AUTHLIM, any further negative password

verification leads to a permanent locking of the protected part of the memory for the

specified access modes. Independent, whether the provided password is correct or not,

each subsequent PWD_AUTH fails.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 17 / 45

Any successful password verification, before reaching the limit of negative password

verification attempts, resets the internal counter to zero.

8.6.3 Protection of special memory segments

The configuration pages can be protected by the password authentication as well. The

protection level is defined with the PROT bit.

The protection is enabled by setting the AUTH0 byte to a value that is within the

addressable memory space.

All counters can always be incremented and read without prior password verification.

8.7 Counter functionality

The MF0ULx1 features three independent 24-bit one-way counters. These counters are

located in a separate part of the NVM which is not directly addressable using READ,

FAST_READ, WRITE or COMPATIBILITY_WRITE commands. The actual value can

be retrieved by using the READ_CNT command, the counters can be incremented

with the INCR_CNT command. The INCR_CNT command features anti-tearing

support, thus no undefined values originating from interrupted programing cycles are

possible. Either the value is unchanged or the correct, incremented value is correctly

programmed into the counter. The occurrence of a tearing event can be checked using

the CHECK_TEARING_EVENT command.

In the initial state, the counter values are set to 000000h.

The counters can be incremented by an arbitrary value. The incremented value is

valid immediately and does not require a RF reset or re-activation. Once counter value

reaches FFFFFFh and an increment is performed via a valid INCR_CNT command, the

MF0ULx1 replies a NAK. If the sum of the addressed counter value and the increment

value in the INCR_CNT command is higher than FFFFFFh, the MF0ULx1 replies a NAK

and does not update the respective counter.

An increment by zero (000000h) is always possible, but does not have any impact on the

counter value.

8.8 Originality function

The MF0ULx1 features a cryptographically supported originality check. With this

feature, it is possible to verify with a certain probability, that the ticket is using an NXP

Semiconductors manufactured silicon. This check can also be performed on personalized

tickets.

Each MF0ULx1 holds a 32-byte cryptographic signature based on elliptic curve

cryptography. This signature can be retrieved using the READ_SIG command and can

be verified using the corresponding ECC public key in the PCD.

8.9 Virtual Card Architecture Support

The MF0ULx1 supports the virtual card architecture by replying to a Virtual Card Select

Last (VCSL) command with a virtual card type identifier. The VCTID that is replied can be

programmed in the configuration pages. It enables infrastructure supporting this feature

to process MIFARE product-based cards across different MIFARE families in a common

way.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 18 / 45

For example, a contactless system is enabled to select a specific virtual MIFARE

product-based card inside a mobile phone. It can use the same card identification

principle to detect that the MF0ULx1 belongs to the system.

9 Command overview

The MIFARE Ultralight card activation follows the ISO/IEC 14443 Type A. After the

MIFARE Ultralight card has been selected, it can either be deactivated using the ISO/

IEC 14443 HLTA command, or the MIFARE Ultralight commands can be performed. For

more details about the card activation, refer to Ref. 1.

9.1 MIFARE Ultralight EV1 command overview

All available commands for the MIFARE Ultralight are shown in Table 9.

Table 9. Command overview

Command[1] ISO/IEC 14443 Command code

(hexadecimal)

Request REQA 26h (7 bit)

Wake-up WUPA 52h (7 bit)

Anticollision CL1 Anticollision CL1 93h 20h

Select CL1 Select CL1 93h 70h

Anticollision CL2 Anticollision CL2 95h 20h

Select CL2 Select CL2 95h 70h

Halt HLTA 50h 00h

GET_VERSION[2] - 60h

READ - 30h

FAST_READ[2] - 3Ah

WRITE - A2h

COMP_WRITE - A0h

READ_CNT[2] - 39h

INCR_CNT[2] - A5h

PWD_AUTH[2] - 1Bh

READ_SIG[2] - 3Ch

CHECK_TEARING_EVENT[2] - 3Eh

VCSL[2] - 4Bh

[1] Unless otherwise specified, all commands use the coding and framing as described in Ref. 1.

[2] this command is new in MIFARE Ultralight EV1 compared to MIFARE Ultralight

9.2 Timing

The command and response timings shown in this document are not to scale and values

are rounded to 1 μs.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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All given command and response transmission times refer to the data frames including

start of communication and end of communication. A PCD data frame, contains the start

of communication (1 "start bit") and the end of communication (one logic 0 + 1 bit length

of unmodulated carrier). A PICC data frame, contains the start of communication (1 "start

bit") and the end of communication (1 bit length of no subcarrier).

The minimum command response time is specified according to Ref. 1 as an integer

n which specifies the PCD to PICC frame delay time. The frame delay time from PICC

to PCD has a minimum n of 9. The maximum command response time is specified as

a time-out value. Depending on the command, the TACK value specified for command

responses defines the PCD to PICC frame delay time. It does it for either the 4-bit ACK

value specified in Section 9.3 or for a data frame.

All command timings are according to ISO/IEC 14443-3 frame specification as shown for

the Frame Delay Time in Figure 11. For more details, refer to Ref. 1.

aaa-006279

last data bit transmitted by the PCD

FDT = (n* 128 + 84)/fc

first modulation of the PICC

FDT = (n* 128 + 20)/fc

128/fc

logic „1“

128/fc

logic „0“

256/fc

end of communication (E)

256/fc

end of communication (E)

128/fc

start of

communication (S)

128/fc

start of

communication (S)

Figure 11. Frame Delay Time (from PCD to PICC)

Remark: Due to the coding of commands, the measured timings usually excludes (a part

of) the end of communication. Consider this factor when comparing the specified times

with the measured times.

9.3 MIFARE Ultralight ACK and NAK

The MIFARE Ultralight uses a 4-bit ACK / NAK as shown in Table 10.

Table 10. ACK and NAK values

Code (4-bit) ACK/NAK

Ah Acknowledge (ACK)

0h NAK for invalid argument (i.e. invalid page address)

1h NAK for parity or CRC error

4h NAK for counter overflow

5h, 7h NAK for EEPROM write error

6h, 9h NAK, other error

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

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9.4 ATQA and SAK responses

For details on the type identification procedure, refer to Ref. 3.

The MF0ULx1 replies to a REQA or WUPA command with the ATQA value shown in

Table 11. It replies to a Select CL2 command with the SAK value shown in Table 12. The

2-byte ATQA value is transmitted with the least significant byte first (44h).

Table 11. ATQA response of the MF0ULx1

Bit number

Sales type Hex value 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

MF0ULx1 00 44h 0000000001000100

Table 12. SAK response of the MF0ULx1

Bit number

Sales type Hex value 8 7 6 5 4 3 2 1

MF0ULx1 00h 0 0 0 0 0 0 0 0

Remark: The ATQA coding in bits 7 and 8 indicate the UID size according to ISO/IEC

14443 independent from the settings of the UID usage.

Remark: The bit numbering in the ISO/IEC 14443 starts with LSB = bit 1 and not with

LSB = bit 0. So 1 byte counts bit 1 to bit 8 instead of bit 0 to 7.

10 MIFARE Ultralight EV1 commands

10.1 GET_VERSION

The GET_VERSION command is used to retrieve information on the MIFARE family,

product version, storage size and other product data required to identify the MF0ULx1.

This command is available on other MIFARE products to have a common way of

identifying products across platforms and evolution steps.

The GET_VERSION command has no arguments and replies the version information for

the specific MF0ULx1 type. The command structure is shown in Figure 12 and Table 13.

Table 14 shows the required timing.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 21 / 45

aaa-006280

CRC

PCD Cmd

Data

PICC ,,ACK''

283 µs 868 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

Figure 12. GET_VERSION command

Table 13. GET_VERSION command

Name Code Description Length

Cmd 60h Get product version 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - Product version information 8 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 14. GET_VERSION timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

GET_VERSION n=9 TTimeOut n=9 TTimeOut 5 ms

Table 15. GET_VERSION response for MF0UL11 and MF0UL21

Byte no. Description MF0UL11/

MF0ULH11

MF0UL21/

MF0ULH21

Interpretation

0 fixed header 00h 00h

1 vendor ID 04h 04h NXP Semiconductors

2 product type 03h 03h MIFARE Ultralight

3 product subtype 01h/02h 01h/02h 17 pF / 50pF

4 major product version 01h 01h EV1

5 minor product version 00h 00h V0

6 storage size 0Bh 0Eh see following explanation

7 protocol type 03h 03h ISO/IEC 14443-3 compliant

The most significant 7 bits of the storage size byte are interpreted as an unsigned integer

value n. As a result, it codes the total available user memory size as 2n. If the least

significant bit is 0b, the user memory size is exactly 2n. If the least significant bit is 1b, the

user memory size is between 2n and 2n+1.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

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The user memory for the MF0UL11 is 48 bytes. This memory size is between 32d bytes

and 64d bytes. Therefore, the most significant 7 bits of the value 0Bh, are interpreted as

5d and the least significant bit is 1b.

The user memory for the MF0UL21 is 128 bytes. This memory size is exactly 128d.

Therefore, the most significant 7 bits of the value 0Eh, are interpreted as 7d and the least

significant bit is 0b.

10.2 READ

The READ command requires a start page address, and returns the 16 bytes of four

MIFARE Ultralight pages. For example if address (Addr) is 03h then pages 03h, 04h,

05h, 06h are returned. A rollover mechanism is implemented if the READ command

address is near the end of the accessible memory area. This rollover mechanism is also

used when at least part of the addressed pages is within a password protected area. For

details on those cases see the description below. The command structure is shown in

Figure 13 and Table 16.

Table 17 shows the required timing.

aaa-006284

CRC

AddrPCD Cmd

Data

PICC ,,ACK''

368 µs 1548 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

Figure 13. READ command

Table 16. READ command

Name Code Description Length

Cmd 30h read four pages 1 byte

Addr - start page address 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - Data content of the addressed pages 16 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 17. READ timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

READ n=9 TTimeOut n=9 TTimeOut 5 ms

NXP Semiconductors MF0ULX1

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In the initial state of the MF0ULx1, all memory pages are allowed as Addr parameter to

the READ command.

•page address 00h to 13h for the MF0UL11

•page address 00h to 28h for the MF0UL21

Addressing a memory page beyond the limits above results in a NAK response from the

MF0ULx1.

A roll-over mechanism is implemented to continue reading from page 00h once the

end of the accessible memory is reached. For example, reading from address 11h on a

MF0UL11 results in pages 11h, 12h, 13h and 00h being returned.

The following conditions apply if part of the memory is password protected for read

access:

•if the MF0ULx1 is in the ACTIVE state

–addressing a page which is equal or higher than AUTH0 results in a NAK response

–addressing a page lower than AUTH0 results in data being returned with the roll-over

mechanism occurring just before the AUTH0 defined page

•if the MF0ULx1 is in the AUTHENTICATED state

–the READ command behaves like on a MF0ULx1 without access protection

Remark: PWD and PACK values can never be read out of the memory. When reading

from the pages holding those two values, all 00h bytes are replied to the PCD instead.

10.3 FAST_READ

The FAST_READ command requires a start page address and an end page address and

returns the all n*4 bytes of the addressed pages. For example if the start address is 03h

and the end address is 07h then pages 03h, 04h, 05h, 06h and 07h are returned. If the

addressed page is outside of accessible area, the MF0ULx1 replies a NAK. For details

on those cases and the command structure, refer to Figure 14 and Table 18.

Table 19 shows the required timing.

aaa-006285

CRC

StartAddrPCD Cmd

Data

PICC ,,ACK''

453 µs depending on nr of read pages

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

EndAddr

Figure 14. FAST_READ command

Table 18. FAST_READ command

Name Code Description Length

Cmd 3Ah read multiple pages 1 byte

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

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Name Code Description Length

StartAddr - start page address 1 byte

EndAddr - end page address 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - data content of the addressed pages n*4 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 19. FAST_READ timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

FAST_READ n=9 TTimeOut n=9 TTimeOut 5 ms

In the initial state of the MF0ULx1, all memory pages are allowed as StartAddr parameter

to the FAST_READ command.

•page address 00h to 13h for the MF0UL11

•page address 00h to 28h for the MF0UL21

Addressing a memory page beyond the limits above results in a NAK response from the

MF0ULx1.

The EndAddr parameter must be equal to or higher than the StartAddr.

The following conditions apply if part of the memory is password protected for read

access:

•if the MF0ULx1 is in the ACTIVE state

–if any requested page address is equal or higher than AUTH0 a NAK is replied

•if the MF0ULx1 is in the AUTHENTICATED state

–the FAST_READ command behaves like on a MF0ULx1 without access protection

Remark: PWD and PACK values can never be read out of the memory. When reading

from the pages holding those two values, all 00h bytes are replied to the PCD instead.

Remark: The FAST_READ command is able to read out the whole memory with one

command. Nevertheless, receive buffer of the PCD must be able to handle the requested

amount of data as there is no chaining possibility.

10.4 WRITE

The WRITE command requires a block address, and writes 4 bytes of data into the

addressed MIFARE Ultralight EV1 page. The WRITE command is shown in Figure 15

and Table 20.

Table 21 shows the required timing.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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aaa-006286

CRCAddrPCD Cmd

PICC ,,ACK''

708 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

ACK

57 µs

Data

Figure 15. WRITE command

Table 20. WRITE command

Name Code Description Length

Cmd A2h write one page 1 byte

Addr - page address 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - data 4 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 21. WRITE timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

WRITE n=9 TTimeOut n=9 TTimeOut 5 ms

In the initial state of the MF0ULx1, the following memory pages are valid Addr

parameters to the WRITE command.

•page address 02h to 13h for the MF0UL11

•page address 02h to 28h for the MF0UL21

Addressing a memory page beyond the limits above results in a NAK response from the

MF0ULx1.

Pages which are locked against writing cannot be reprogrammed using any write

command. The locking mechanisms include lock bits as well as the locking of the

configuration pages.

The following conditions apply if part of the memory is password protected for write

access:

•if the MF0ULx1 is in the ACTIVE state

–writing to a page which address is equal or higher than AUTH0 results in a NAK

response

•if the MF0ULx1 is in the AUTHENTICATED state

–the WRITE command behaves like on a MF0ULx1 without access protection

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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The MF0ULx1 features tearing protected write operations to specific memory content.

The following pages are protected against tearing events during a WRITE operation:

•page 2 containing lock bits

•page 3 containing OTP bits

•page 36d containing the additional lock bits for the MF0UL21

10.5 COMPATIBILITY_WRITE

The COMPATIBILITY_WRITE command is implemented to accommodate the

established MIFARE Classic PCD infrastructure. Even though 16 bytes are transferred

to the MF0ULx1, only the least significant 4 bytes (bytes 0 to 3) are written to

the specified address. Set all the remaining bytes, 04h to 0Fh, to logic 00h. The

COMPATIBILITY_WRITE command is shown in Figure 16 and Table 20.

Table 23 shows the required timing.

001aan015

CRCAddrPCD Cmd

PICC ,,ACK''

368 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

59 µs

ACK

59 µs

Figure 16. COMPATIBILITY_WRITE command part 1

001aan016

CRCPCD Data

PICC ,,ACK''

1558 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

59 µs

ACK

59 µs

Figure 17. COMPATIBILITY_WRITE command part 2

Table 22. COMPATIBILITY_WRITE command

Name Code Description Length

Cmd A0h compatibility write 1 byte

NXP Semiconductors MF0ULX1

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Product data sheet Rev. 3.3 — 9 April 2019

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Name Code Description Length

Addr - page address 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - 16-byte Data, only least significant 4

bytes are written

16 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 23. COMPATIBILITY_WRITE timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

COMPATIBILITY_WRITE part 1 n=9 TTimeOut n=9 TTimeOut 5 ms

COMPATIBILITY_WRITE part 2 n=9 TTimeOut n=9 TTimeOut 10 ms

In the initial state of the MF0ULx1, the following memory pages are valid Addr

parameters to the COMPATIBILITY_WRITE command.

•page address 02h to 13h for the MF0UL11

•page address 02h to 28h for the MF0UL21

Addressing a memory page beyond the limits above results in a NAK response from the

MF0ULx1.

Pages which are locked against writing cannot be reprogrammed using any write

command. The locking mechanisms include lock bits as well as the locking of the

configuration pages.

The following conditions apply if part of the memory is password protected for write

access:

•if the MF0ULx1 is in the ACTIVE state

–writing to a page which address is equal or higher than AUTH0 results in a NAK

response

•if the MF0ULx1 is in the AUTHENTICATED state

–the COMPATIBILITY_WRITE command behaves the same as on a MF0ULx1 without

access protection

The MF0ULx1 features tearing protected write operations to specific memory

content. The following pages are protected against tearing events during a

COMPATIBILITY_WRITE operation:

•page 2 containing lock bits

•page 3 containing OTP bits

•page 36d containing the additional lock bits for the MF0UL21

10.6 READ_CNT

The READ_CNT command is used to read out the current value of one of the 3 one-way

counters of the MF0ULx1. The command has a single argument specifying the counter

number and returns the 24-bit counter value of the corresponding counter. The counters

are always readable, independent on the password protection settings. The command

structure is shown in Figure 18 and Table 24.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

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Table 25 shows the required timing.

aaa-006287

CRC

AddrPCD Cmd

Data

PICC ,,ACK''

368 µs 444 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

Figure 18. READ_CNT command

Table 24. READ_CNT command

Name Code Description Length

Cmd 39h read counter 1 byte

Addr - counter number from 00h to 02h 1 byte

CRC - CRC according to Ref. 1 2 bytes

Data - counter value 3 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 25. READ_CNT timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

READ_CNT n=9 TTimeOut n=9 TTimeOut 5 ms

10.7 INCR_CNT

The INCR_CNT command is used to increment one of the 3 one-way counters of the

MF0ULx1. The two arguments are the counter number and the increment value. The

INCR_CNT command is shown in Figure 19 and Table 26.

Table 27 shows the required timing.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

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aaa-006288

CRCAddrPCD Cmd

PICC ,,ACK''

708 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

ACK

57 µs

IncrValue

Figure 19. INCR_CNT command

Table 26. INCR_CNT command

Name Code Description Length

Cmd A5h increment counter 1 byte

Addr - counter number from 00h to 02h 1 byte

IncrValue - increment value, only the 3 least

significant bytes are relevant

4 byte

CRC - CRC according to Ref. 1 2 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 27. INCR_CNT timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

INCR_CNT n=9 TTimeOut n=9 TTimeOut 5 ms

The IncrValue argument is a 4-byte field to support the same command structure as

the WRITE command. As the counter width is only 3 byte, the last transmitted, most

significant byte is ignored.

Any increment value is allowed. Nevertheless, the final counter value is FFFFFFh. No

further increment is possible after the final value is reached. Also, trying to increment the

current value by a number which would exceed the final value leads to a NAK response

and the counter remains unchanged. An increment by 0 is allowed but leaves the counter

unchanged.

The order of bytes in the increment argument follows the same order that the bytes

are sent via the communication interface. This means from the LSbyte (IncrValue0) to

MSbyte (IncValue3), where the last valid byte is actually IncrValue2. It is in line with

the arguments consisting of multiple bytes for other commands. As an example, an

increment of the counter 00h by 01h, is formulated as INCR CNT 00 01 00 00 00.

The INCR_CNT command features anti-tearing support.

NXP Semiconductors MF0ULX1

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10.8 PWD_AUTH

A protected memory area can be accessed only after a successful password verification

using the PWD_AUTH command. The AUTH0 configuration byte defines the protected

area. It specifies the first page that the password mechanism protects. The level of

protection can be configured using the PROT bit either for write protection or read/

write protection. The PWD_AUTH command takes the password as parameter and, if

successful, returns the password authentication acknowledge, PACK. By setting the

AUTHLIM configuration bits to a value larger than 000b, the number of unsuccessful

password verifications can be limited. Each unsuccessful authentication is then counted

in a counter featuring anti-tearing support. After reaching the limit of unsuccessful

attempts, the memory access specified in PROT, is no longer possible. The PWD_AUTH

command is shown in Figure 20 and Table 28.

Table 29 shows the required timing.

aaa-006289

CRCPCD Cmd

PICC ,,ACK''

623 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

PACK

359 µs

Pwd

CRC

Figure 20. PWD_AUTH command

Table 28. PWD_AUTH command

Name Code Description Length

Cmd 1Bh password authentication 1 byte

Pwd - password 4 bytes

CRC - CRC according to Ref. 1 2 bytes

PACK - password authentication acknowledge 2 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 29. PWD_AUTH timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

PWD_AUTH n=9 TTimeOut n=9 TTimeOut 5 ms

Remark: It is strongly recommended to change the password from its delivery state at

ticket issuing and set the AUTH0 value to the PWD page.

NXP Semiconductors MF0ULX1

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10.9 READ_SIG

The READ_SIG command returns an IC-specific, 32-byte ECC signature, to verify NXP

Semiconductors as the silicon vendor. The signature is programmed at chip production

and cannot be changed afterwards. The command structure is shown in Figure 21 and

Table 30.

Table 31 shows the required timing.

aaa-006290

CRC

AddrPCD Cmd

Sign

PICC ,,ACK''

368 µs 2907 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

Figure 21. READ_SIG command

Table 30. READ_SIG command

Name Code Description Length

Cmd 3Ch read ECC signature 1 byte

Addr 00h RFU, is set to 00h 1 byte

CRC - CRC according to Ref. 1 2 bytes

Sign - ECC signature 32 bytes

NAK see Table 10 see Section 9.3 4-bit

Table 31. READ_SIG timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

READ_SIG n=9 TTimeOut n=9 TTimeOut 5 ms

Ref. 7 describes the signature verification procedure.

10.10 CHECK_TEARING_EVENT

The CHECK_TEARING_EVENT command enables the application to identify if a tearing

event happened on a specified counter element. It takes the counter number as single

argument and returns a specified valid flag for this counter. If the returned valid flag is

not equal to the predefined value, a tearing event happened. Note, although a tearing

event might have happened on the counter, a valid value corresponding to the last valid

counter status is still available using the READ_CNT command. The command structure

is shown in Figure 22 and Table 32.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

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Table 33 shows the required timing.

aaa-006291

CRC

AddrPCD Cmd

Valid

PICC ,,ACK''

368 µs 274 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

Figure 22. CHECK_TEARING_EVENT command

Table 32. CHECK_TEARING_EVENT command

Name Code Description Length

Cmd 3Eh check tearing event 1 byte

Addr - counter number from 00h to 02h 1 byte

CRC - CRC according to Ref. 1 2 bytes

Valid - valid flag 1 byte

NAK see Table 10 see Section 9.3 4-bit

Table 33. CHECK_TEARING_EVENT timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

CHECK_TEARING_EVENT n=9 TTimeOut n=9 TTimeOut 5 ms

The valid flag for normal operation is BDh. If any other value than BDh is replied on the

CHECK_TEARING_EVENT command, a tearing event has happened on the addressed

counter.

The application can use this information to base business logic decisions on.

10.11 VCSL

The VCSL command is used to enable a unique identification and selection process

across different MIFARE product-based cards and card implementations on mobile

devices. The command requires a 16-byte installation identifier IID and a 4-byte PCD

capability value as parameters. The parameters are present to support compatibility to

other MIFARE product-based devices but are not used or checked inside the MF0ULx1.

Nevertheless, the number of bytes is checked for correctness. The answer to the VCSL

command is the virtual card type identifier VCTID. This identifier indicates the type of

card or ticket. Using this information, the reader can decide whether the ticket belongs to

the installation or not. The command structure is shown in Figure 23 and Table 34.

Table 35 shows the required timing.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 33 / 45

aaa-006292

CRCIID PCDCAPSPCD Cmd

PICC ,,ACK''

1982 µs

PICC ,,NAK'' NAK

Time out TTimeOut

TNAK

TACK

57 µs

VCTID

274 µs

CRC

Figure 23. VCSL command

Table 34. VCSL command

Name Code Description Length

Cmd 4B read four pages 1 byte

IID - installation identifier 16 bytes

PCDCAPS - PCD capabilities 4 bytes

CRC - CRC according to Ref. 1 2 bytes

VCTID - virtual Card Type Identifier 1 byte

NAK see Table 10 see Section 9.3 4-bit

Table 35. VCSL timing

These times exclude the end of communication of the PCD.

TACK min TACK max TNAK min TNAK max TTimeOut

VCSL n=9 TTimeOut n=9 TTimeOut 5 ms

11 Limiting values

Stresses exceeding one or more of the limiting values, can cause permanent damage to

the device. Exposure to limiting values for extended periods can affect device reliability.

Table 36. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Min Max Unit

IIinput current - 40 mA

Ptot/pack total power dissipation per package - 120 mW

Tstg storage temperature -55 125 °C

Tamb ambient temperature -25 70 °C

VESD electrostatic discharge voltage on LA/LB [1] 2 - kV

[1] ANSI/ESDA/JEDEC JS-001; Human body model: C = 100 pF, R = 1.5 kΩ

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 34 / 45

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe

precautions for handling electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,

JESD625-A or equivalent standards.

12 Characteristics

Table 37. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Ciinput capacitance MF0ULx1 [1] - 17.0 - pF

Ciinput capacitance

MF0ULHx1

[1] - 50.0 - pF

fiinput frequency - 13.56 - MHz

EEPROM characteristics

tret retention time Tamb = 22 °C 10 - - year

Nendu(W) write endurance Tamb = 22 °C 100000 - - cycle

Nendu(W) write endurance counters Tamb = 22 °C 100000 1000000 - cycle

[1] Tamb = 22 °C, f = 13.56 MHz, VLaLb = 1.5 V RMS

13 Wafer specification

Table 38. Wafer specifications MF0ULx1

Wafer

diameter 200 mm typical (8 inches)

300 mm typical (12inches)

maximum diameter after foil expansion 210 mm (8 inches)

not applicable (12inches)

die separation process laser dicing (8 inches)

blade dicing (12 inches)

thickness MF0ULx101DUD 120 μm ± 15 μm

MF0ULx101DUF 75 μm ± 10 μm

flatness not applicable

Potential Good Dies per Wafer (PGDW) MF0ULx1 103682 (8 inches)

219126 (12 inches)

MF0ULHx1 86470 (8 inches)

Wafer backside

material Si

treatment ground and stress relieve

Ra max = 0.5 μmroughness

Rt max = 5 μm

Chip dimensions

NXP Semiconductors MF0ULX1

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Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 35 / 45

x = 505 μm (8 inches)

x = 505 μm (12 inches)

step size[1] MF0ULx1

y = 590 μm (8 inches)

y = 590 μm (12 inches)

x = 505 μmstep size[1] MF0ULHx1

y = 720 μm

typical = 20 μmgap between chips[1]

minimum = 5 μm

not applicable (12 inches)

Passivation

type sandwich structure

material PSG / nitride

thickness 500 nm / 600 nm

Au bump (substrate connected to VSS)

material > 99.9 % pure Au

hardness 35 to 80 HV 0.005

shear strength > 70 MPa

height 18 μm

within a die = ±2 μm

within a wafer = ±3 μm

height uniformity

wafer to wafer = ±4 μm

flatness minimum = ±1.5 μm

size LA, LB, GND, TP[2] = 60 μm × 60 μm

size variation ±5 μm

under bump metallization sputtered TiW

[1] The step size and the gap between chips may vary due to changing foil expansion

[2] Pads GND and TP are disconnected when wafer is sawn

13.1 Fail die identification

Electronic wafer mapping covers the electrical test results and the results of mechanical/

visual inspection. No ink dots are applied.

14 Package outline

For more details on the contactless MOA8 module, refer to Ref. 5.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 36 / 45

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT500-4 - - -

- - -

sot500-4_po

11-02-18

Unit

max

nom

min

0.26 35.05

35.00

34.95

A(1)

Dimensions

Note

1. Total package thickness, exclusive punching burr.

PLLMC: plastic leadless module carrier package; 35 mm wide tape SOT500-4

For unspecified dimensions see PLLMC-drawing given in the subpackage code.

0 10 20 mm

scale

detail X

Figure 24. Package outline SOT500-4

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 37 / 45

15 Bare die outline

For more details on the wafer delivery forms, see Ref. 6.

aaa-006293

)

43,

(

)

n. 5

(

)

[

]

[

, L

p (8 inches)

(

)

(

e ai

p a

ep s

(

ons

µm, p

(

)

p (12 inches)

Figure 25. Bare die outline MF0ULx1

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 38 / 45

aaa-008074

x [ m] y [ m]

Chip Step

Bump size

LA, LB, GND, TP

505(1)

720(1)

(1) the air gap and thus the step size may vary due to varying foil expansion

(2) all dimensions in µm, pad locations measured from metal ring edge (see detail)

typ. 505,0(1)

typ. 720,0(1)

43,0

423,0

638,0

typ. 20,0(1)

GND

LA TP

43,0

min. 5,0

. 2

)

min. 5

Figure 26. Bare die outline MF0ULHx1

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 39 / 45

16 Abbreviations

Table 39. Abbreviations and symbols

Acronym Description

ACK Acknowledge

ATQA Answer to request: Type A

CRC Cyclic Redundancy Check

CT Cascade Tag (value 88h) as defined in ISO/IEC 14443-3 Type A

ECC Elliptic Curve Cryptography

EEPROM Electrically Erasable Programmable Read-Only Memory

FDT Frame Delay Time

FFC Film Frame Carrier

IC Integrated Circuit

IID Installation Identifier

LCR L = inductance, Capacitance, Resistance (LCR meter)

LSB Least Significant Bit

LSByte Least Significant Byte

MSByte Most Significant Byte

NAK Not acknowledge

NV Non-Volatile memory

OTP One Time Programmable

PCD Proximity Coupling Device (contactless reader)

PCDCAPS PCD Capability bytes

PICC Proximity Integrated Circuit Card (contactless card)

REQA Request command: Type A

RF Radio Frequency

RFUI Reserver for Future Use - Implemented

RMS Root Mean Square

SAK Select acknowledge: Type A

SECS-II SEMI Equipment Communications Standard part 2

TiW Titanium Tungsten

UID Unique identifier

VCTID Virtual Card Type Identifier

WUPA Wake-Up Protocol: Type A

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 40 / 45

17 References

[1]

ISO/IEC 14443

International Organization for Standardization

[2]

MIFARE (Card) Coil Design Guide

Application note, BU-ID Document number 0117** 1

[3]

MIFARE Type Identification Procedure

Application note, BU-ID Document number 0184**1

[4]

MIFARE ISO/IEC 14443 PICC Selection

Application note, BU-ID Document number 1308**1

[5]

Contactless smart card module specification MOA8

Delivery Type Description, BU-ID Document number 1636**1

[6]

General specification for 8" wafer on UV-tape; delivery types

Delivery Type Description, BU-ID Document number 1005**1

[7]

AN073121 MIFARE Ultralight Features and Hints

Application note, BU-ID Document number 0731**

[8]

ISO/IEC 15457-1 Identification cards

Thin flexible cards

1** ... document version number

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 41 / 45

18 Revision history

Table 40. Revision history

Document ID Release date Data sheet status Change notice Supersedes

MF0ULx1 v.3.3 20180409 Product data sheet - MF0ULx1 v.3.2

Modifications: •Editorial updates

MF0ULx1 v.3.2 20171127 Product data sheet - MF0ULx1 v.3.1

Modifications: •12 inch FFC delivery forms added

MF0ULx1 v.3.1 20130724 Product data sheet - MF0ULx1 v.3.0

Modifications: •Editorial changes

•Added 50 pF delivery types

MF0ULx1 v.3.0 20130219 Product data sheet - 234521

Modifications: •Editorial changes

•Security status changed into "COMPANY PUBLIC"

•Added default values for configuration elements in Table 8

•Corrected response timing in Figure 18

•Corrected PCDCAPS length in Table 34

•Changed EEPROM reliability parameters for counters

234521 20120928 Preliminary data sheet - 234520

Modifications: •Editorial changes

•Changed EEPROM reliability parameters

234520 20120525 Objective data sheet - -

•Initial version

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 42 / 45

19 Legal information

19.1 Data sheet status

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product

development.

Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

19.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 43 / 45

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor

tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of non-

automotive qualified products in automotive equipment or applications. In

the event that customer uses the product for design-in and use in automotive

applications to automotive specifications and standards, customer (a) shall

use the product without NXP Semiconductors’ warranty of the product for

such automotive applications, use and specifications, and (b) whenever

customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own

risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,

damages or failed product claims resulting from customer design and use

of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

19.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

MIFARE — is a trademark of NXP B.V.

DESFire — is a trademark of NXP B.V.

MIFARE Plus — is a trademark of NXP B.V.

MIFARE Ultralight — is a trademark of NXP B.V.

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Product data sheet Rev. 3.3 — 9 April 2019

COMPANY PUBLIC 234533 44 / 45

Tables

Tab. 1. Naming conventions ..........................................2

Tab. 2. Quick reference data .........................................3

Tab. 3. Ordering information ..........................................4

Tab. 4. Pin allocation table ............................................5

Tab. 5. Configuration Pages ........................................14

Tab. 6. MOD configuration byte .................................. 15

Tab. 7. ACCESS configuration byte ............................ 15

Tab. 8. Configuration parameter descriptions ..............15

Tab. 9. Command overview .........................................18

Tab. 10. ACK and NAK values ......................................19

Tab. 11. ATQA response of the MF0ULx1 .................... 20

Tab. 12. SAK response of the MF0ULx1 .......................20

Tab. 13. GET_VERSION command .............................. 21

Tab. 14. GET_VERSION timing .................................... 21

Tab. 15. GET_VERSION response for MF0UL11 and

MF0UL21 .........................................................21

Tab. 16. READ command ............................................. 22

Tab. 17. READ timing ....................................................22

Tab. 18. FAST_READ command .................................. 23

Tab. 19. FAST_READ timing .........................................24

Tab. 20. WRITE command ............................................ 25

Tab. 21. WRITE timing .................................................. 25

Tab. 22. COMPATIBILITY_WRITE command ............... 26

Tab. 23. COMPATIBILITY_WRITE timing ..................... 27

Tab. 24. READ_CNT command .................................... 28

Tab. 25. READ_CNT timing .......................................... 28

Tab. 26. INCR_CNT command ..................................... 29

Tab. 27. INCR_CNT timing ............................................29

Tab. 28. PWD_AUTH command ................................... 30

Tab. 29. PWD_AUTH timing ..........................................30

Tab. 30. READ_SIG command ..................................... 31

Tab. 31. READ_SIG timing ............................................31

Tab. 32. CHECK_TEARING_EVENT command ........... 32

Tab. 33. CHECK_TEARING_EVENT timing ................. 32

Tab. 34. VCSL command .............................................. 33

Tab. 35. VCSL timing .................................................... 33

Tab. 36. Limiting values ................................................ 33

Tab. 37. Characteristics .................................................34

Tab. 38. Wafer specifications MF0ULx1 ........................34

Tab. 39. Abbreviations and symbols ............................. 39

Tab. 40. Revision history ............................................... 41

Figures

Fig. 1. Contactless system ........................................... 1

Fig. 2. Block diagram of MF0ULx1 ...............................5

Fig. 3. Pin configuration for SOT500-4 (MOA8) ........... 5

Fig. 4. State diagram ....................................................8

Fig. 5. Memory organization MF0UL11 ...................... 10

Fig. 6. Memory organization MF0UL21 ...................... 11

Fig. 7. UID/serial number ........................................... 11

Fig. 8. Lock bytes 0 and 1 ......................................... 12

Fig. 9. Lock bytes 2-4 ................................................ 13

Fig. 10. OTP bytes ....................................................... 14

Fig. 11. Frame Delay Time (from PCD to PICC) .......... 19

Fig. 12. GET_VERSION command .............................. 21

Fig. 13. READ command ............................................. 22

Fig. 14. FAST_READ command .................................. 23

Fig. 15. WRITE command ............................................ 25

Fig. 16. COMPATIBILITY_WRITE command part 1 .....26

Fig. 17. COMPATIBILITY_WRITE command part 2 .....26

Fig. 18. READ_CNT command .................................... 28

Fig. 19. INCR_CNT command ..................................... 29

Fig. 20. PWD_AUTH command ................................... 30

Fig. 21. READ_SIG command ..................................... 31

Fig. 22. CHECK_TEARING_EVENT command ........... 32

Fig. 23. VCSL command .............................................. 33

Fig. 24. Package outline SOT500-4 ............................. 36

Fig. 25. Bare die outline MF0ULx1 .............................. 37

Fig. 26. Bare die outline MF0ULHx1 ............................ 38

NXP Semiconductors MF0ULX1

MIFARE Ultralight EV1 - Contactless ticket IC

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 9 April 2019

Document identifier: MF0ULX1

Document number: 234533

Contents

1 General description ............................................ 1

1.1 Contactless energy and data transfer ................1

1.2 Anticollision ........................................................ 1

1.3 Simple integration and user convenience .......... 2

1.4 Security .............................................................. 2

1.5 Naming conventions .......................................... 2

2 Features and benefits .........................................2

2.1 EEPROM ........................................................... 3

3 Applications .........................................................3

4 Quick reference data .......................................... 3

5 Ordering information .......................................... 4

6 Block diagram ..................................................... 5

7 Pinning information ............................................ 5

7.1 Pinning ............................................................... 5

8 Functional description ........................................6

8.1 Block description ............................................... 6

8.2 RF interface ....................................................... 6

8.3 Data integrity ..................................................... 7

8.4 Communication principle ................................... 7

8.4.1 IDLE state ..........................................................8

8.4.2 READY1 state ................................................... 9

8.4.3 READY2 state ................................................... 9

8.4.4 ACTIVE state .....................................................9

8.4.5 AUTHENTICATED state ....................................9

8.4.6 HALT state .......................................................10

8.5 Memory organization ....................................... 10

8.5.1 UID/serial number ............................................11

8.5.2 Lock byte 0 and byte 1 ....................................12

8.5.3 Lock byte 2 to byte 4 .......................................12

8.5.4 OTP bytes ........................................................13

8.5.5 Data pages ...................................................... 14

8.5.6 Configuration pages .........................................14

8.6 Password verification protection ...................... 16

8.6.1 Programming of PWD and PACK .................... 16

8.6.2 Limiting negative verification attempts ............. 16

8.6.3 Protection of special memory segments .......... 17

8.7 Counter functionality ........................................ 17

8.8 Originality function ........................................... 17

8.9 Virtual Card Architecture Support .................... 17

9 Command overview .......................................... 18

9.1 MIFARE Ultralight EV1 command overview .....18

9.2 Timing .............................................................. 18

9.3 MIFARE Ultralight ACK and NAK .................... 19

9.4 ATQA and SAK responses ..............................20

10 MIFARE Ultralight EV1 commands .................. 20

10.1 GET_VERSION ............................................... 20

10.2 READ ............................................................... 22

10.3 FAST_READ ....................................................23

10.4 WRITE ............................................................. 24

10.5 COMPATIBILITY_WRITE ................................ 26

10.6 READ_CNT ......................................................27

10.7 INCR_CNT .......................................................28

10.8 PWD_AUTH .....................................................30

10.9 READ_SIG .......................................................31

10.10 CHECK_TEARING_EVENT .............................31

10.11 VCSL ................................................................32

11 Limiting values .................................................. 33

12 Characteristics .................................................. 34

13 Wafer specification ........................................... 34

13.1 Fail die identification ........................................ 35

14 Package outline .................................................35

15 Bare die outline .................................................37

16 Abbreviations .................................................... 39

17 References ......................................................... 40

18 Revision history ................................................ 41

19 Legal information .............................................. 42