73S8010C
Smart Card Interface
Simplifying System Integration™ DATA SHEET
April 2009
Rev. 1.5 © 2009 Teridian Semiconductor Corporation 1
DESCRIPTION
The Teridian 73S8010C is a single smart card
interface IC. It provides full electrical compliance
with ISO-7816-3 and EMV 4.0 specifications.
Interfacing with the host is done through the two-wire
I2C bus. Data exchange with the card is managed
from the system controller using the I/O line (and
eventually the auxiliary I/O lines).
An on-chip oscillator using an external crystal, or
connection to a clock signal coming from the
system controller can generate the card clock
signal.
The 73S8010C IC incorporates an ISO-7816-3
activation/deactivation sequencer that controls the
card signals. Level shifters drive the card signals
with the selected card voltage (3 V or 5 V), coming
from an internal DC-DC converter.
With its high-efficiency DC-DC converter, the
Teridian 73S8010C is a cost-effective solution for
any smart card reader application to be powered
from a single 2.7 V to 3.6 V power supply.
Hardware support for auxiliary I/O lines, C4 / C8
contacts, is provided.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the
protection circuitry. The fault can be a VDD (digital
power supply), a VCC (card power supply), a card
over-current, or an over-heating fault.
ADVANTAGES
Single smart card interface
The inductor-based DC-DC converter provides
higher current and efficiency than the usual
charge-pump capacitor-based converters
Ideal for battery-powered applications
Suitable for high current cards and
SAMs: (100 mA max)
Power down mode: 2 A typical
Small Format (5x5mm) 32-QFN package option
FEATURES
Card Interface:
Complies with ISO-7816-3 and EMV 4.0
A DC-DC Converter provides 3V / 5V to the
card from an external power supply input
High-efficiency converter: > 80% @ VDD= 3.3 V,
VCC = 5 V and ICC = 65 mA
Up to 100 mA supplied to the card
ISO-7816-3 Activation / Deactivation sequencer
with emergency automated deactivation on
card removal or fault detected by the protection
circuitry
Protection include 2 voltage supervisors that
detect voltage drops on card VCC and VDD
power supplies
The VDD voltage supervisor threshold value
can be externally adjusted
True over-current detection (150 mA max.)
1 card detection input
Auxiliary I/O lines, for C4 / C8 contact signals
Host Interface:
Fast mode, 400 kbps I2C slave bus
8 possible devices in parallel
One control register and one status register
Interrupt output to the host for fault
detection
Crystal oscillator or host clock, up to 27 MHz
Power Supply:
V
DD: 2.7 V to 3.6 V
6 kV ESD Protection on the card interface
Package: SO28 or 32QFN
APPLICATIONS
Set-Top-Boxes, DVD / HDD Recorders:
Conditional Access and Pay-per-View slots
Point of Sales and Transaction Terminals
EMV slots in cell phones and PDAs
73S8010C Data Sheet DS_8010C_024
2 Rev. 1.5
FUNCTIONAL DIAGRAM
Figure 1: 73S8010C Bloc k Diagram
Pin number reference to SO28 Package
[Pin number] reference to 32QFN Package
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 3
Table of Contents
1Pin Description .................................................................................................................................... 5
1.1Card Interface ............................................................................................................................... 5
1.2Miscellaneous Inputs and Outputs ................................................................................................ 5
1.3Power Supply and Ground ............................................................................................................ 5
1.4Microcontroller Interface ............................................................................................................... 6
2Host Interface (I2C Bus) ...................................................................................................................... 7
2.1Host Interface Control ................................................................................................................... 7
2.2Host Interface Status .................................................................................................................... 8
2.3I2C-bus Timing .............................................................................................................................. 9
3Oscillator ............................................................................................................................................ 10
4DC-DC Converter – Card Power Supply ......................................................................................... 10
5Voltage Supervision ......................................................................................................................... 11
6Power Down ....................................................................................................................................... 11
7Over-temperature M onitor ................................................................................................................ 12
8Activation Sequence ......................................................................................................................... 12
9Deactivation Sequence ..................................................................................................................... 13
10Interrupt ............................................................................................................................................. 13
11Warm Reset ....................................................................................................................................... 14
12I/O Timing ........................................................................................................................................... 14
13Typical Application Schematic ........................................................................................................ 15
14Electrical Specification ..................................................................................................................... 16
14.1Absolute Maximum Ratings ........................................................................................................ 16
14.2Recommended Operating Conditions......................................................................................... 16
14.3DC Characteristics: Card Interface ............................................................................................. 17
14.4DC Characteristics: Digital Signals ............................................................................................. 20
14.5DC Characteristics: Supply ......................................................................................................... 20
14.6DC Characteristics: I2C Interface ................................................................................................ 21
14.7Voltage / Temperature Fault Detection Circuits .......................................................................... 21
15Mechanical Drawings ....................................................................................................................... 22
15.132-pin QFN ................................................................................................................................. 22
15.228-pin SO .................................................................................................................................... 23
16Package Pin Designation ................................................................................................................. 24
16.132-pin QFN ................................................................................................................................. 24
16.228-pin SO .................................................................................................................................... 25
17Ordering Information ........................................................................................................................ 26
18Related Documentation .................................................................................................................... 26
19Contact Information .......................................................................................................................... 26
Revision History ........................................................................................................................................ 27
73S8010C Data Sheet DS_8010C_024
4 Rev. 1.5
Figures
Figure 1: 73S8010C Block Diagram ............................................................................................................. 2
Figure 2: I2C Bus Write Protocol ................................................................................................................... 8
Figure 3: I2C Bus Read Protocol ................................................................................................................... 9
Figure 4: I2C Bus Timing Diagram ................................................................................................................ 9
Figure 5: Power Down Mode Operation ...................................................................................................... 12
Figure 6: Activation Sequence .................................................................................................................... 12
Figure 7: Deactivation Sequence ................................................................................................................ 13
Figure 8: FAULT Functions, INT operation ................................................................................................. 13
Figure 9: Warm Reset operation ................................................................................................................. 14
Figure 10: I/O Timing .................................................................................................................................. 14
Figure 11: 73S8010C – Typical Application Schematic .............................................................................. 15
Figure 12: DC – DC Converter Efficiency (VCC = 5 V) ................................................................................ 18
Figure 13: DC – DC Converter Efficiency (VCC = 3 V) ................................................................................ 18
Figure 14: 32-pin QFN Package Drawing ................................................................................................... 22
Figure 15: 28-pin SO Package Drawing ..................................................................................................... 23
Tables
Table 1: Device Address Selections ............................................................................................................. 7
Table 2: Host Control Register ...................................................................................................................... 7
Table 3: Host Status Register ....................................................................................................................... 8
Table 4: Choice of Vcc Capacitor ............................................................................................................... 10
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 5
1 Pin Description
1.1 Card Interface
Name Pin
(SO) PIN
(QFN) Description
I/O 11 9 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC.
AUX1 13 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
AUX2 12 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
RST 16 14 Card reset: provides reset (RST) signal to card.
CLK 15 13
Card clock: provides clock (CLK) signal to card. The rate of this clock is
determined by the crystal oscillator frequency and CLKSEL bits in the
control register.
PRES 10 7 Card Presence switch: active high indicates card is present. Includes a
pull-down resistor.
VCC 17 15
Card power supply: logically controlled by sequencer, output of DC-DC
converter. Requires an external filter capacitor to the card GND.
GND 14 12 Card ground.
1.2 Miscellaneous Inputs and Outputs
Name PIN
(SO) PIN
(QFN) Description
XTALIN 24 23
Crystal oscillator input: can either be connected to a crystal or driven
as a source for the card clock.
XTALOUT 25 24
Crystal oscillator output: connected to crystal. Left open if XTALIN is
being used as an external clock input.
VDDF_ADJ 18 17
VDD threshold adjustment input: this pin can be used to overwrite a
higher VDDF value (that controls deactivation of the card). Must be
left open if unused.
NC 7, 9
4, 6, 8,
16, 25,
32
Non-connected pin.
1.3 Power Supply and Ground
Name PIN
(SO) Pin
(QFN) Description
VDD 6, 21 3, 20 System controller interface supply voltage: supply voltage for internal
circuitry and DC-DC converter power supply source.
GND 4 1 DC-DC converter ground.
GND 14 12 Smart Card I/O ground.
GND 22 21 Digital ground.
LIN 5 2
External inductor: Connect external inductor from pin 5 to VDD. Keep the
inductor close to pin 5.
73S8010C Data Sheet DS_8010C_024
6 Rev. 1.5
1.4 Microcontroller Interface
Name PIN
(SO) PIN
(QFN) Description
INT 23 22
Interrupt output (negative assertion): Interrupt output signal to the
processor. A 20 kΩ pull up to VDD is provided internally.
PWRDN 8 5
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8010C
in its lowest power consumption mode. Must be tied to ground when the
power down function is not used.
SAD0
SAD1
SAD2
1
2
3
29
30
31
Serial device address bits: Digital inputs for address selection that allow
the connection of up to 8 devices in parallel. Address selections as follows:
SAD2 SAD1 SAD0 I2C Address (7 bits)
0 0 0 0x40
0 0 1 0x42
0 1 0 0x44
0 1 1 0x46
1 0 0 0x48
1 0 1 0x4A
1 1 0 0x4C
1 1 1 0x4E
Pins SAD0 and SAD1 are internally pulled-down and SAD2 is
internally pulled-up.
The default address when left unconnected is 48h.
SCL 19 18 I2C clock signal input.
SDA 20 19 I2C bi-directional serial data signal.
I/OUC 26 26
System controller data I/O to/from the card. Includes internal pull-up
resistor to VDD.
AUX1UC 27 27 System controller auxiliary data I/O to/from the card. Includes internal pull-
up resistor to VDD.
AUX2UC 28 28 System controller auxiliary data I/O to/from the card. Includes internal pull-
up resistor to VDD.
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 7
2 Host Interface (I2C Bus)
A fast-mode 400 kHz I2C bus slave interface is used for controlling the device and reading the status of
the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1,
and SAD2. This allows up to 8 devices to be connected in parallel.
Table 1: Device Address Selections
SAD2 SAD1 SAD0 I2C Address (7 bits)
0 0 0 0x40
0 0 1 0x42
0 1 0 0x44
0 1 1 0x46
1 0 0 0x48
1 0 1 0x4A
1 1 0 0x4C
1 1 1 0x4E
Bit 0 of the I2C address is the R/W bit. Refer to Figure 2 and Figure 3 for usage.
2.1 Host Interface Control
Table 2 describes the Host Interface Control Register bits (power-on Reset = 0x00).
Table 2: Host Control Register
Name Bit Description
Start/Stop 0
When set, initiates an activation and a cold reset procedure; when reset, initiates
a deactivation sequence.
Warm reset 1 When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
5 V and 3 V 2 When set, VCC = 3 V; when reset, VCC = 5 V.
Clock Stop 3 When set, card clock is stopped. Bit 4 determines the card clock stop level.
Clock Stop
Level
4 When set, card clock stops high; when reset card clock stops low.
Clksel1 5
Bits 5 and 6 determine the clock rate to the card according to the following table.
CLKDIV1 CLKDIV2 Clock Rate
0 0 XTALIN/8
0 1 XTALIN/4
1 1 XTALIN/2
1 0 XTALIN
Clksel2 6
I/O enable 7 When set, data is transferred between I/O (AUX1, AUX2) and I/OUC (AUX1UC,
AUX2UC); when reset, I/O (AUX1, AUX2) and I/OUC (AUX1UC, AUX2UC) are
high impedance.
I2C-bus Write to the Control Register
The I2C-bus Write command to the control register follows the format shown in Figure 2.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The master now starts
sending the 8 bits of data to the control register during the DATA bits time. After the DATA bits, the ‘zero’
73S8010C Data Sheet DS_8010C_024
8 Rev. 1.5
ACK bit is sent to the master by the device. The master should send the STOP condition after receiving
the ACK bit.
Figure 2: I2C Bus Write Protocol
2.2 Host Interface Status
Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04).
Table 3: Host Status Register
Name Bit Description
PRES 0 Set when the card is present; reset when the card is not present.
PRESL 1
Set when the PRES pin changes state (rising/falling edge); reset when the status
register is read. Generates an interrupt when set
I/O 2 Set when I/O is high; reset when I/O is low.
SUPL 3
Set when a voltage fault is detected; reset when the status register is read.
Generates an interrupt when set.
PROT 4
Set when an over-current or over-heating fault has occurred during a card session;
reset when the status register is read. Generates an interrupt when set.
MUTE 5
Set during ATR when the card has not answered during the ISO 7816-3 time
window (40000 card clock cycles); reset when the next session begins or this
register is read.
EARLY 6
Set during ATR when the card has answered before 400 card clock cycles; reset
when the next session begins or this register is read.
ACTIVE 7 Set when the card is active (VCC is on); reset when the card is inactive.
I2C-bus Read from the Status Register:
The I2C-bus Read Command from the Status Register follows the format shown in Figure 3.
After the START condition, the master sends a slave address. This address is seven bits long followed
by an eighth bit, which is the opcode bit (R/W). A ‘one’ indicates the master will read data from the status
register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device. The device now starts
sending the 8-bit status register data to the control register during the DATA bits time. After the DATA
bits, the ‘one’ ACK bit is sent to the device by the master. The master should send the STOP condition
after receiving the ACK bit.
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 9
Figure 3: I2C Bus Read Protocol
2.3 I2C-bus Timing
Symbol Parameter Conditions Min. Typ. Max. UNIT
Fsclk Clock frequency 400 kHz
Tlow Clock low 1.3
s
Thi Clock high 0.6
s
Thdsta Hold time START condition 0.6 s
Tsudat Data set up time 100 ns
Thddat Data hold time 5 900 ns
Tsusto Set up time STOP condition 0.6 s
Tbuf Bus free time between a STOP and
START condition
1.3
s
Figure 4: I2C Bus Timing Diagram
SCL
SDA
Thdsta Tsudat Thddat Tsusto
Tbuf
Tlow
Thi
73S8010C Data Sheet DS_8010C_024
10 Rev. 1.5
3 Oscillator
The Teridian 73S8010C device has an on-chip oscillator that can generate the smart card clock using an
external crystal, connected between the XTALIN and XTALOUT pins, to set the oscillator frequency.
When the card clock signal is available from another source, it can be connected to the pin XTALIN, and
the pin XTALOUT should be left unconnected.
4 DC-DC Converter – Card Power Supply
An internal DC-DC converter provides the card power supply. This converter is able to provide either a
3 V or 5 V card voltage from the power supply applied on the VDD pin. The digital ISO-7816-3 sequencer
controls the converter. Bit 2 of the Control register selects the card voltage.
The circuit is an inductive step-up converter/regulator. The external components required are 2 filter
capacitors on the power-supply input VDD (100 nF + 10 F, next to the LIN pin), an inductor, and an output
filter capacitor on the card power supply VCC. The circuit performs regulation by activating the step-up
operation when VCC is below a set point of 5.0 or 3.0 volts minus a comparator hysteresis voltage and the
input supply VDD is less than the set point for VCC. When VDD is greater than the set point for VCC (VDD =
3.6 V, VCC = 3 V) the circuit operates as a linear regulator. Depending on the inductor values, the voltage
converter can provide current on VCC as high as 100 mA.
The circuit provides over-current protection and limits ICC to 150 mA. When an over-current condition is
sensed, the circuit initiates a deactivation sequence from the control logic and reports back to the host
controller a fault on the interrupt output INT.
Choice of the Inductor
The nominal inductor value is 10 H, rated for 400 mA. The inductor is connected between pin LIN (pin 5
in the SO package, pin 2 in the QFN package) and the VDD voltage. The value of the inductor can be
optimized to meet a particular configuration (ICC_MAX). The inductor should be located on the PCB as
close as possible to the LIN pin of the IC.
Choice of the VCC Capacitor
Depending on the applications, the requirements in terms of both VCC minimum voltage and transient
currents that the interface must be able to provide to the card vary. Table 4 shows the recommended
capacitors for each VCC power supply configuration and applicable specification.
Table 4: Choice of Vcc Capacitor
Specification Requirement Application
Specification Min VCC Voltage
Allowed During
Transient Current
Max Transient
Current Charge Capacitor Type Capacitor Value
EMV 4.0 4.6V 30nA.s X5R/X7R w/
ESR < 100 m
3.3 F
ISO-7816-3 4.5V 20nA.s 1 F
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 11
5 Voltage Supervision
Two voltage supervisors constantly check the level of the VDD and VCC voltages. A card deactivation
sequence is forced when a fault occurs for any of these voltage supervisors.
The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage
range to interface with the system controller. The VDD voltage supervisor is also used to initialize the
ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or when a fault occurs. The
voltage threshold of the VDD voltage supervisor is internally set by default to 2.3 V nominal. However, it
may be desirable in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the
SO package, pin 17 in the QFN package) is used to connect an external resistor REXT1 to ground to raise
the VDD fault voltage to another value, VDDF (refer to Figure 11). The resistor value is defined as follows:
REXT = 180 kΩ / (VDDF - 2.33)
An alternative (more accurate) method of adjusting the VDD fault voltage is to use a resistive network of
R3 from the pin to supply and R4 from the pin to ground (see Figure 11). In order to set the new
threshold voltage, the equivalent resistance must be determined. This resistance value will be
designated Kx. Kx is defined as R4/(R4+R5). Kx is calculated as:
Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.
To determine the values of R4 and R5, use the following formulas.
R5 = 72000 / Kx R4 = R5*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7 V is desired, solving for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0.377.
Solving for R5 gives: R5 = 72000 / 0.377 = 191 k.
Solving for R4 gives: R4 = 191000 *(0.377 / (1 – 0.377)) = 115.6 k.
Using standard 1% resistor values gives R5 = 191 kand R4 = 115 kThese values give an equivalent
resistance of Kx = 0.376, a 0.3% error.
If the 2.3 V default threshold is used, the VDDF_ADJ pin must be left unconnected.
6 Power Down
A power down function is provided via the PWRDN pin (active high). When activated, the Power Down
(PD) mode disables all the internal analog functions, including the card analog interface, the oscillators
and the DC-DC converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only
allowed in the deactivated condition (out of a card session, when the Start/Stop bit is set to 0 from the I2C
host controller).
The host controller invokes the power down state when it is desirable to save power. The signal PRES
remains functional in PD mode such that a card insertion sets INT high. The micro-controller must then
set PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to
setting the Start/Stop bit to 1).
Resumption of the normal mode occurs approximately 10 ms (stabilization of the internal oscillators +
reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10 ms
time period. If a card is present, INT can be used as an indication that the circuit has completed its
recovery from power down state. INT will go high at the end of the stabilization period. Should the
Start/Stop be set to 1 during PWRDN = 1, or within the 10 ms internal stabilization / reset time, it will not
be taken into account and the card interface will remain inactive. Since Start/Stop is taken into account
on its edges, it should be toggled low and high again after the 10 ms to activate a card.
Figure 5 illustrates the sequencing of the PD and Normal modes. PWRDN must be connected to GND if
the power down function is not used.
73S8010C Data Sheet DS_8010C_024
12 Rev. 1.5
Figure 5: Power Down Mode Operation
7 Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs (most likely
resulting from a heavily loaded card interface, including short circuits), a card deactivation sequence is
initiated, and a fault condition is reported to the system controller (bit 4 of the status register is set and
generates an interrupt).
8 Activation Sequence
After Power on Reset, the INT signal is low until VDD is stable. When VDD has been stable for
approximately 10 ms and the INT signal is high, the system controller may read the status register to see
if the card is present. If all the status bits are satisfactory, the system controller can initiate the activation
sequence by writing a ‘1’ to the Start/Stop bit (bit 0 of the Control register).
The following steps and Figure 6 show the activation sequence and the timing of the card control signals
when the system controller initiates the Start/Stop bit (bit 0) of the control register:
1. Voltage VCC to the card should be valid by the end of t1. If VCC is not valid for any reason, then the
session is aborted.
2. Turn I/O to reception mode at the end of t1.
3. CLK is applied to the card at the end of t2.
4. RST (to the card) is set high at the end of t3.
Figure 6: Activation Sequence
PRES
INT
PWRDN
Internal RC OSC
Start/Stop bit
OFF follows PRES regardless of PWRDN
PWRDN during a card
session has no effect
After setting PWRDN = 0,
the controller must wait at
least 10ms before setting
Start/Stop = 1
EMV / ISO deactivation
time ~= 100 uS
~10ms
PWRDN has effect when
the cardi s deactivated
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator), I/O in reception mode
t2 ≥ 0.5 μs, CLK starts
t3 ≥ 42000 card clock cycles, RST set high
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 13
9 Deactivation Sequence
Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the
event of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VCC fault, and
card extraction during the session.
The following steps and Figure 7 show the deactivation sequence and the timing of the card control
signals when the system controller clears the Start/Stop bit:
1. RST goes low at the end of t1.
2. CLK goes low at the end of t2.
3. I/O goes low at the end of t3. Out of reception mode.
4. Shut down VCC at the end of time t4.
Figure 7: Deactivation Sequence
10 Interrupt
The interrupt is an active low interrupt. It is set low if either a VCC fault or a VDD fault is detected. It is also
set low if one of the following status bit conditions is detected:
Early ATR
Mute ATR
Card insert or card extract
Protection status from Over-current or Over-heating
If the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
Figure 8: FAULT Functions, INT operation
t1 ≥ 0.5 μs t3 ≥ 0.5 μs
t2 ≥ 7.5 μs t4 ≥ 0.5 μs
INT
ANY FAULT
STATUS BITS
READ STATUS DONE
73S8010C Data Sheet DS_8010C_024
14 Rev. 1.5
A power-on-reset (POR) event will reset all of the control and status registers to their default states. A VDD fault
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that
creates interval “t1,” will not clear the interrupt until VDD is valid for at least the t1 time. The VDD fault can be
considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of the VDD fault, POR will be asserted.
11 Warm Reset
The 73S8010C automatically asserts a warm reset to the card when instructed through bit 1 of the I2C Control
register (Warm Reset bit). The warm reset length is automatically defined as 42,000 card clock cycles. The bit
Warm Reset is automatically reset when the card starts answering or when the card is declared mute.
Figure 9: Warm Reset operation
12 I/O Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are high when the
activation sequencer turns on the I/O reception state. See Section 8 Activation Sequence for more
details on when the I/O reception is enabled.
The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. When the control I/O enable
bit (bit 7 of the Control register) is set, the first I/O line on which a falling edge is detected becomes the
input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected
then both I/O lines return to their neutral state. The delay between the I/O signals is shown in Figure 10.
Figure 10: I/O Timing
Warm Reset
(bit 1)
RST
t1t2t3
IO
t1> 1.5 µs, Warm Reset Starts
t2= 42000 card clock cycles, End of Warm Reset
t3= Resets Warm Reset bit 1 when detected ATR or Mute
Delay from I/O to I/OUC: tIO_HL = 100 ns tIO_LH = 25 ns
Delay from I/OUC to I/O: tI/OUC_HL = 100 ns tI/OUC_LH = 25 ns
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 15
C2
22pF
C3
22pF
SDA_f rom_uC
SCL_f rom_uC
C6
100nF
SAD2
AUX1UC_to.f rom_uC
AUX2UC_to/f rom_uC
External_clock_f rom uC
VDD R1
20K
C1
ISO7816=1uF, EMV=3.3uF
L1 10uH
R4
Rext1
SAD1
SAD0
R2 2K
R3 2K
INT_interrupt_to_uC
VDD
See NOTE 1
See
note 6
- OR -
See NOTE 5
SO28
Card detection
switch is normally
closed.
CLK track should be routed
far from RST, I/O, C4 and
C8.
See NOTE 3
NOTES:
1) VDD supply should be = 2.7V to 3.6V DC.
2) Hardwire to define address of device
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Pin can not float. Must be driven or connected to GND
if power down function is not used.
6) Rext1 and Rext2 are external resistors to ground and
VDD to modify the VDD fault voltage. Can be left open
7) Keep L1 close to pin 5
See NOTE 4
See NOTE 5
Low E SR (< 1 0 0 mohms) C1
should be placed near the SC
connecter contact
IOUC_to/f rom_uC
See note 7
PWRDN_f rom_uC
Y1
CRYSTAL
Note 2
Smart Card Connector
VCC 1
RST 2
CLK 3
C4 4
GND 5
VPP 6
I/O 7
C8 8
SW-1 9
SW-2 10
73S8010C
SAD0
1
SAD1
2
SAD2
3
GND
4
GND
5
VPC
6
NC
7
AUX2
12
NC
8
NC
9
PRES
10
I/O
11
AUX1
13
GND
14 CLK 15
RST 16
VCC 17
VDD_ADJ 18
SCL 19
SDA 20
VDD 21
GND 22
INT_ 23
AUX2UC 28
AUX1UC 27
XTAL O U T 25
XTA LI N 24
I/OUC 26
R5
Rext2
C4
100nF
C5
10uF
13 Typical Application Schematic
Figure 11: 73S8010C – Typical Application Schematic
73S8010C Data Sheet DS_8010C_024
16 Rev. 1.5
14 Electrical Specification
14.1 Absolute Maximum Ratings
Operation outside these rating limits may cause permanent damage to the device.
Parameter Rating
Supply Voltage VDD -0.5 to 4.0 VDC
Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC
Storage Temperature -60 °C to 150 °C
Pin Voltage (except LIN and card interface) -0.3 to (VDD +0.5) VDC
Pin Voltage (LIN) -0.3 to 6.0 VDC
Pin Voltage (card interface) -0.3 to (VCC + 0.5) VDC
ESD Tolerance – Card interface pins +/- 6 kV
ESD Tolerance – Other pins +/- 2 kV
ESD testing on Card pins uses the HBM condition, 3 pulses, each polarity referenced to ground.
14.2 Recommended Operating Conditions
Parameter Rating
Supply Voltage VDD 2.7 to 3.6 VDC
Ambient Operating Temperature -40 °C to +85 °C
Input Voltage for Digital Inputs 0 V to VDD + 0.3 V
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 17
14.3 DC Characteristics: Card Interface
Symbol Parameter Condition Min. Typ. Max. Unit
Card Power Supply (VCC) DC-DC Converter
General conditions, -40 C < T < 85 C, 2.7 V < VDD < 3.6 V
VCC
Card supply voltage
including ripple and noise
Inactive mode -0.1 0.1 V
Inactive mode
ICC = 1 mA -0.1 0.4 V
Active mode
ICC < 65 mA; 5 V 4.75 5.25 V
Active mode
ICC < 65 mA; 3 V 2.8 3.2 V
Active mode
single pulse of 100 mA
for 2 s; 5 V,
fixed load = 25 mA
4.6 5.25 V
Active mode
single pulse of 100 mA
for 2 s; 3 V,
fixed load = 25 mA
2.76 3.2 V
Active mode
current pulses of 40 nAs
with peak |ICC | < 200 mA,
t < 400 ns; 5 V
4.6 5.25 V
Active mode
current pulses of 40 nAs
with peak |ICC | < 200 mA,
t < 400 ns; 3 V
2.76 3.2 V
ICCmax Maximum supply current to
the card
Static load current,
VCC > 4.6 or 2.7 V as
selected, L=10 H
100 mA
ICCF I
CC fault current Short circuit, VCC to ground 100 125 180 mA
VSR VCC slew rate - Rise rate on
activate CF on VCC = 1 µF 0.05 0.15 0.25 V/s
VSF VCC slew rate - Fall rate on
deactivate CF on VCC = 1 µF 0.1 0.3 0.5 V/s
CF External filter capacitor
(VCC to GND) 0.47 1 3.3
F
L Inductor (LIN to VDD) 10
H
Limax Imax in inductor VCC = 5 V, ICC = 65 mA,
VDD = 2.7 V 400 mA
Efficiency VCC = 5 V, ICC = 65 mA,
VDD = 3.3 V 87 %
73S8010C Data Sheet DS_8010C_024
18 Rev. 1.5
1011B01 Converter efficiency (VCC 5V)
50
55
60
65
70
75
80
85
90
95
100
0 20406080100
Icc [mA]
Efficiency [%]
2.7V
3.0V
3.3V
3.6V
Figure 12: DC – DC Converter Efficiency (V CC = 5 V)
Output current on Vcc at 5 V. Input voltage on VDD at 2.7, 3.0, 3.3 and 3.6 volts.
1011B01 Converter efficiency (VCC 3V)
50
55
60
65
70
75
80
85
90
95
100
0 20 40 60 80 100
Icc [mA]
Efficiency [%]
2.7V
3.0V
3.3V (Linear)
3.6V (Linear)
Figure 13: DC – DC Converter Efficiency (V CC = 3 V)
Output current on VCC at 3 V. Input voltage on VDD at 2.7, 3.0, 3.3 and 3.6 volts.
Converter Efficiency (VCC 5 V)
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 19
Symbol Parameter Condition Min. Typ. Max. Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. IIL
requirements only pertain to I//OUC, AUX1UC, and AUX2UC.
VOH Output level, high (I/O, AUX1,
AUX2)
IOH = 0 0.9 VCC V
CC+ 0.1 V
IOH = -40 A 0.75 VCC V
CC + 0.1 V
VOH Output level, high (I/OUC,
AUX1UC, AUX2UC)
IOH = 0 0.9 VDD V
DD+ 0.1 V
IOH = -40 A 0.75 VDD V
DD + 0.1 V
VOL Output level, low IOL=1 mA 0.3 V
VIH Input level, high (I/O, AUX1,
AUX2) 1.8 VCC + 0.30 V
VIH Input level, high (I/OUC,
AUX1UC, AUX2UC) 1.8 VDD + 0.30 V
VIL Input level, low -0.3 0.8 V
VINACT Output voltage when outside
of session
IOL = 0 0.1 V
IOL = 1 mA 0.3 V
ILEAK Input leakage VIH = VCC 10
A
IIL Input current, low VIL = 0, CS = 1 0.65 mA
VIL = 0, CS = 0 5 μA
ISHORTL Short circuit output current For output low, shorted
to VCC through 33 15 mA
ISHORTH Short circuit output current For output high, shorted
to ground through 33 15 mA
tR, tF Output rise time, fall times
For I/O, AUX1, AUX2,
CL = 80 pF, 10% to 90%
For I/OUC, AUX1UC,
AUX2UC,
CL=50 pF, 10% to 90%
100 ns
tIR, tIF Input rise, fall times 1
s
RPU Internal pull-up resistor Output stable for >200 ns 8 11 14 k
FDMAX Maximum data rate 1 MHz
TFDIO Delay, I/O to I/OUC,
I/OUC to I/O 20 ns
CIN Input capacitance 10 pF
73S8010C Data Sheet DS_8010C_024
20 Rev. 1.5
Symbol Parameter Condition Min. Typ. Max. Unit
Reset and Clock for c ard interface, RST, CLK
VOH Output level, high IOH = -200 A 0.9 VCC V
CC V
VOL Output level, low IOL = 200 A 0 0.3 V
VINACT Output voltage when outside of
a session
IOL = 0 0.1 V
IOL = 1 mA 0.3 V
IRST_LIM Output current limit, RST 30 mA
ICLK_LIM Output current limit, CLK 70 mA
tR, tF Output rise time, fall time
CL = 35 pF for CLK,
10% to 90% 8 ns
CL = 200 pF for RST,
10% to 90% 100 ns
Duty cycle for CLK,
except for f=fXTAL
CL =35 pF,
FCLK 20 MHz 45 55 %
14.4 DC Characteristics: Digital Signals
Symbol Parameter Condition Min. Typ. Max. Unit
Digital I/O except for OSC I/O
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 1.8 VDD + 0.3 V
VOL Output Low Voltage IOL = 2 mA 0.45 V
VOH Output High Voltage IOH = -1 mA VDD - 0.45 V
ROUT Pull-up resistor, INT 20
k
|IIL1| Input Leakage Current GND < VIN < VDD -5 5 μA
Oscillator (XTALIN) I/O Parameters
VILXTAL Input Low Voltage - XTALIN -0.3 0.3 VDD V
VIHXTAL Input High Voltage - XTALIN 0.7 VDD V
DD+0.3 V
IILXTAL Input Current - XTALIN GND < VIN < VDD -30 30 μA
fMAX Max freq. Osc or external clock 27 MHz
in External input duty cycle limit tR/F < 10% fIN,
45% < CLK < 55% 48 52 %
14.5 DC Characteristics: Supply
Symbol Parameter Condition Min. Typ. Max. Unit
IDD Supply Current on VDD
Linear mode, ICC=0
I/O, AUX1, AUX2=high 4.9 mA
Step up mode, ICC=0
I/O, AUX1, AUX2=high 4.7 mA
IDD_PD Supply Current on VDD
in Power Down mode
PWRDN=1, Start/stop bit = 0
All digital inputs driven with a
true logical 0 or 1
0.11 2.5
A
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 21
14.6 DC Characteristics: I2C Interface
Symbol Parameter Condition Min. Typ. Max. Unit
SDA, SCL
VIL Input Low Voltage -0.3 0.3* VDD V
VIH Input High Voltage 0.7*VDD V
DD + 0.3 V
VOL Output Low Voltage IOL = 3 mA 0.40 V
CIN Pin capacitance 10 pF
IIN Output High Voltage IOH = -1 mA VDD - 0.45 V
TF Output fall time CL = 0 to 400 pF 20 + 0.1*CL 250 ns
TSP Pulse width of spikes
that are suppressed
Transition from valid logic
level to opposite level 50 ns
14.7 Voltage / Temperature Fault Detection Circuits
Symbol Parameter Condition Min. Typ. Max. Unit
VDDF VDD fault – VDD Voltage
supervisor threshold
No external resistor on
VDDF_ADJ pin 2.15 2.4 V
VCCF VCC fault – VCC Voltage
supervisor threshold
VCC = 5 V 4.20 4.6 V
VCC= 3 V 2.5 2.7 V
TF Die over temperature fault 115 145 C
73S8010C Data Sheet DS_8010C_024
22 Rev. 1.5
15 Mechanical Drawings
15.1 32-pin QFN
Figure 14: 32-pin QFN Package Drawing
0.85 NOM./ 0.9MAX.
0.00 / 0.005
0.20 REF.
SEATING
PLANE
SIDE VIEW
0.2 MIN.
0.35 / 0.45
1.5 / 1.875
3.0 / 3.75
0.18 / 0.3
BOTTOM VIEW
1
2
3
0.25
0.5
0.5
0.25
3.0 / 3.75
1.5 / 1.875
0.35 / 0.45
CHAMFERED
0.30
2.5
5
2.5
5
TOP VIE W
1
2
3
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 23
15.2 28-pin SO
Figure 15: 28-pin SO Package Drawing
73S8010C Data Sheet DS_8010C_024
24 Rev. 1.5
16 Package Pin Designation
Use handling procedures necessary for a static sensitive component.
16.1 32-pin QFN
Figure 13: 73S8010C 32-pin QFN Pin Out
(Top View)
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
GND
LIN
VDD
NC
PRDWN
PRES
I/O
XTALOUT
XTALIN
INT
GND
VDD
SDA
SCL
VDDF_ADJNC
AUX2
AUX1
GND
CLK
RST
VCC
NC
TERIDIAN
73S8010C
NC
NC
SAD2
SAD1
SAD0
AUX2UC
AUX1UC
I/OUC
NC
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 25
16.2 28-pin SO
Figure 15: 73S8010C 28-pin SO Pin Out
(Top View)
73S8010C
1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
19
20
28
27
26
25
24
23
22
21
SAD0
SAD1
SAD2
GND
VDD
NC
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALIN
XTALOUT
INT
VDD
SDA
SCL
VCC
RST
CLK
NC
LIN
PWRDN
VDDF_ADJ
GND
73S8010C Data Sheet DS_8010C_024
26 Rev. 1.5
17 Ordering Information
Part Description Order Number Packaging Mark
73S8010C-SO 28-pin Lead-Free SO 73S8010C-IL/F 73S8010C-IL
73S8010C-SO 28-pin Lead-Free SO Tape / Reel 73S8010C-ILR/F 73S8010C-IL
73S8010C-QFN 32-pin Lead-Free QFN 73S8010C-IM/F 73S8010C
73S8010C-QFN 32-pin Lead-Free QFN Tape / Reel 73S8010C-IMR/F 73S8010C
18 Related Documentation
The following 73S8010C documents are available from Teridian Semiconductor Corporation:
73S8010C Data Sheet (this document)
73S8010C 28SO Dem o Board User’s Guide
73S8010C QFN Demo Board User’s Guide
19 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the
73S8010C, contact us at:
6440 Oak Canyon Road
Suite 100
Irvine, CA 92618-5201
Telephone: (714) 508-8800
FAX: (714) 508-8878
Email: scr.support@teridian.com
For a complete list of worldwide sales offices, go to http://www.teridian.com.
DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 27
Revision History
Revision Date Description
1.0 6/13/2005 First publication.
1.2 9/21/2005 Changed SDATA hold time.
1.3 12/5/2007
Added ISO and ENV logo, remove leaded package options, replace 32QFN punched
with SAWN, update 28SO dimension.
1.4 1/17/2008 Changed dimension of bottom exposed pad on 32QFN mechanical package
figure.
1.5 4/3/2009 Removed all references to VPC as VPC must be tied to VDD.
© 2009 Teridian Semiconductor Corporation. All rights reserved.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation.
Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.
All other trademarks are the property of their respective owners.
Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly
contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms
and Conditions. The company assumes no responsibility for any errors which may appear in this
document, reserves the right to change devices or specifications detailed herein at any time without
notice and does not make any commitment to update the information contained herein. Accordingly, the
reader is cautioned to verify that this document is current by comparing it to the latest version on
http://www.teridian.com or by checking with your sales representative.
Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com
