CY62126ESL MoBL®Automotive
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-66522 Rev. ** Revised January 17, 2011
Features
■Very high speed: 45 ns
■Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■Ultra low standby power
❐Typical standby current: 1 A
❐Maximum standby current: 4 A
■Ultra low active power
❐Typical active current: 1.3 mA at f = 1 MHz
■Easy memory expansion with CE, and OE features
■Automatic power down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 44-Pin thin small outline package (TSOP) II
package
Functional Description
The CY62126ESL is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The input and
output pins (I/O0 through I/O15) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write
operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A15). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A15).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the Truth Table on page 11 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
64K x 16
RAM Array I/O0–I/O7
ROW DECODER
A8
A7
A6
A5
A2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A4
A3I/O8–I/O15
CE
WE
BHE
A0
A1
A9
A10
BLE
Logic Block Diagram
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Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 5
Thermal Resistance ..........................................................5
Data Retention Characteristics ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ......................................................8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagram ............................................................ 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC Solutions ......................................................... 16
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Document #: 001-66522 Rev. ** Page 3 of 16
Pin Configuration
44-Pin TSOP II (Top View) [1]
Product Portfolio
Product Range VCC Range (V) [2] Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(A)
f = 1MHz f = fmax
Typ [3] Max Typ [3] Max Typ [3] Max
CY62126ESL Auto-A 2.2 V–3.6 V and 4.5 V–5.5 V 45 1.3 2 11 16 1 4
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
NC
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ............................................. 55 °C to +125 °C
Supply voltage to ground
potential ..........................................................–0.5 V to 6.0 V
DC voltage applied to outputs
in High Z state [4, 5] ..........................................–0.5 V to 6.0 V
DC input voltage [4, 5] .......................................–0.5 V to 6.0 V
Output current into outputs (low) ................................. 20 mA
Static discharge voltage.......................................... > 2001 V
(MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Device Range Ambient
Temperature VCC[6]
CY62126ESL Automotive-A –40 °C to +85 °C 2.2 V–3.6 V,
and
4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
45 ns
UnitMin Typ [7] Max
VOH Output high voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 – – V
2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 – –
4.5 < VCC < 5.5 IOH = –1.0 mA 2.4 – –
VOL Output low voltage 2.2 < VCC < 2.7 IOL = 0.1 mA – – 0.4 V
2.7 < VCC < 3.6 IOL = 2.1mA – – 0.4
4.5 < VCC < 5.5 IOL = 2.1mA – – 0.4
VIH Input high voltage 2.2 < VCC < 2.7 1.8 – VCC + 0.3 V
2.7 < VCC < 3.6 2.2 – VCC + 0.3
4.5 < VCC < 5.5 2.2 – VCC + 0.5
VIL Input low voltage 2.2 < VCC < 2.7 –0.3 – 0.6 V
2.7 < VCC < 3.6 –0.3 – 0.8
4.5 < VCC < 5.5 –0.5 – 0.8
IIX Input leakage current GND < VI < VCC –1 – +1 A
IOZ Output leakage current GND < VO < VCC, Output disabled –1 – +1 A
ICC VCC operating supply
current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA, CMOS levels
–11 16mA
f = 1 MHz – 1.3 2.0
ISB1 Automatic CE
power-down current —
CMOS Inputs
CE > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only), f = 0 (OE and WE),
VCC = VCC(max)
–1 4 A
ISB2[8] Automatic CE
power-down current —
CMOS inputs
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–1 4 A
Notes
4. VIL(min) = –2.0 V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
8. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
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Capacitance
Parameter[9] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter[9] Description Test Conditions TSOP II Unit
JA Thermal resistance
(Junction to ambient)
Still air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
28.2 C/W
JC Thermal resistance
(Junction to case)
3.4 C/W
Figure 1. AC Test Loads and Waveforms
Parameters 2.50 V 3.0 V 5.0 V Unit
R1 16600 1103 1800
R2 15400 1554 990
RTH 8000 645 639
VTH 1.2 1.75 1.77 V
Note
9. Tested initially and after any design or process changes that may affect these parameters
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
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Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 1.5 – – V
ICCDR[11] Data retention current CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
VCC = 1.5 V – – 3 A
tCDR [12] Chip deselect to data
retention time
0––ns
tR [13] Operation recovery time 45 – – ns
Figure 2. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.5 V
DATA RETENTION MODE
tR
VCC
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
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Switching Characteristics
Over the Operating Range
Parameter[14] Description 45 ns Unit
Min Max
Read Cycle
tRC Read cycle time 45 – ns
tAA Address to data valid – 45 ns
tOHA Data hold from address change 10 – ns
tACE CE LOW to data valid – 45 ns
tDOE OE LOW to data valid – 22 ns
tLZOE OE LOW to Low Z [15] 5– ns
tHZOE OE HIGH to High Z [15, 16] –18 ns
tLZCE CE LOW to Low Z [15] 10 – ns
tHZCE CE HIGH to High Z [15, 16] –18 ns
tPU CE LOW to power up 0 – ns
tPD CE HIGH to power up – 45 ns
tDBE BHE / BLE LOW to data valid –22 ns
tLZBE BHE / BLE LOW to Low Z [15] 5–ns
tHZBE BHE / BLE HIGH to High Z [15, 16] –18 ns
Write Cycle [17]
tWC Write cycle time 45 – ns
tSCE CE LOW to write end 35 – ns
tAW Address setup to write end 35 – ns
tHA Address Hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 – ns
tBW BHE / BLE pulse width 35 –ns
tSD Data setup to write end 25 – ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to High Z [15, 16] –18 ns
tLZWE WE HIGH to Low Z [15]10 – ns
Notes
14. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input
pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5.
15. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enter a high impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [18, 19]
Figure 4. Read Cycle No. 2 (OE Controlled) [19, 20]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
LZBE
t
LZCE
t
PU
HIGH IMPEDANCE
I
CC
t
HZOE
t
HZCE
t
PD
t
HZBE
t
LZOE
t
DBE
t
DOE
IMPEDANCE
HIGH
I
SB
DATA OUT
OE
CE
V
CC
SUPPLY
CURRENT
BHE/BLE
ADDRESS
Notes
18. Device is continuously selected. OE, CE = VIL.
19. WE is high for read cycles.
20. Address valid before or similar to CE transition low.
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Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [21, 22]
Figure 6. Write Cycle No. 2 (CE Controlled) [21, 22]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
tHZOE
DATAIN
NOTE 23
tBW
tSCE
DATA I/O
ADDRESS
CE
WE
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
DATAIN
tBW
tSA
CE
ADDRESS
WE
DATA I/O
OE
BHE/BLE
NOTE 23
Notes
21. Data I/O is high impedance if OE = VIH.
22. If CE goes high simultaneously with WE high, the output remains in high impedance state.
23. During this period, the I/Os are in output state. Do not apply input signals.
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Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) [24]
Figure 8. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [24]
Switching Waveforms (continued)
DATAIN
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 25
CE
ADDRESS
WE
DATA I/O
BHE/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
DATA
IN
t
BW
tSCE
t
PWE
tHZWE
tLZWE
NOTE 25
DATA I/O
ADDRESS
CE
WE
BHE/BLE
Notes
24. If CE goes high simultaneously with WE high, the output remains in high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
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Truth Table
CE[26] WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect or power-down Standby (ISB)
L X X H H High Z Output disabled Active (ICC)
L H L L L Data out (I/O0–I/O15) Read Active (ICC)
L H L H L Data out (I/O0–I/O7);
I/O8–I/O15 in High Z
Read Active (ICC)
L H L L H Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read Active (ICC)
L H H L L High Z Output disabled Active (ICC)
L H H H L High Z Output disabled Active (ICC)
L H H L H High Z Output disabled Active (ICC)
L L X L L Data in (I/O0–I/O15) Write Active (ICC)
L L X H L Data in (I/O0–I/O7);
I/O8–I/O15 in High Z
Write Active (ICC)
L L X L H Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write Active (ICC)
Note
26. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
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Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
45 CY62126ESL-45ZSXA 51-85087 44-Pin TSOP II (Pb-free) Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Temperature Grade: A= Automotive-A
Package Type: ZSX= TSOP II (Pb-free)
Speed Grade
SL = Wide Voltage Range (3 V and 5 V)
E = Process Technology 90 nm
Buswidth = × 16
Density = 1-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY 45 ZSX
621 26ESL A
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Package Diagram
Figure 9. 44-Pin Thin Small Outline Package Type II, 51-85087
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087-*C
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Acronyms Document Conventions
Units of Measure
Acronym Description
BHE byte high enable
BLE byte low enable
CMOS complementary metal oxide semiconductor
CE chip enable
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
WE write enable
Symbol Unit of Measure
°C degree Celcius
µA micro Amperes
mA milli Amperes
MHz Mega Hertz
mV milli Volts
ns nano seconds
pF pico Farad
VVolts
Ohms
WWatts
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Document History Page
Document Title: CY62126ESL MoBL® Automotive 1-Mbit (64K x 16) Static RAM
Document Number: 001-66522
Revision ECN Submission
Date
Orig. of
Change
Description of Change
** 3144223 01/17/2011 RAME New datasheet for Automotive parts
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Document #: 001-66522 Rev. ** Revised January 17, 2011 Page 16 of 16
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
CY62126ESL MoBL® Automotive
© Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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