AM29DL324GT120WDEN - Advanced Micro Devices

3XEOLFDWLRQ1XPEHU 



 5HYLVLRQ 

$PHQGPHQW 



 ,VVXH'DWH 

$SULO

-XO\

7KHIROORZLQJGRFXPHQWVSHFLILHV6SDQVLRQPHPRU\SURGXFWVWKDWDUHQRZRIIHUHGE\ERWK$GYDQFHG

0LFUR'HYLFHVDQG)XMLWVX$OWKRXJKWKHGRFXPHQWLVPDUNHGZLWKWKHQDPHRIWKHFRPSDQ\WKDWRULJ

LQDOO\GHYHORSHGWKHVSHFLILFDWLRQWKHVHSURGXFWVZLOO EHRIIHUHG WR FXVWRPHUVRIERWK$0' DQG

)XMLWVX

Continuity of Specifications

7KHUHLVQRFKDQJHWRWKLVGDWDVKHHWDVDUHVXOWRIRIIHULQJWKHGHYLFHDVD6SDQVLRQSURGXFW$Q\

FKDQJHVWKDWKDYHEHHQPDGHDUHWKHUHVXOWRIQRUPDOGDWDVKHHWLPSURYHPHQWDQGDUHQRWHGLQWKH

GRFXPHQWUHYLVLRQVXPPDU\ZKHUHVXSSRUWHG)XWXUHURXWLQHUHYLVLRQVZLOORFFXUZKHQDSSURSULDWH

DQGFKDQJHVZLOOEHQRWHGLQDUHYLVLRQVXPPDU\

Continuity of Ordering Part Numbers

$0'DQG)XMLWVXFRQWLQXHWRVXSSRUWH[LVWLQJSDUWQXPEHUVEHJLQQLQJZLWK$PDQG0%07RRUGHU

WKHVHSURGXFWVSOHDVHXVHRQO\WKH2UGHULQJ3DUW1XPEHUVOLVWHGLQWKLVGRFXPHQW

For More Information

3OHDVHFRQWDFW\RXUORFDO$0'RU)XMLWVXVDOHVRIILFHIRUDGGLWLRQDOLQIRUPDWLRQDERXW6SDQVLRQ

PHPRU\VROXWLRQV

Am29DL32xG

Data Sheet

ADVANCE INFORMATION

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to h elp you evaluate t his product. AMD re serves the righ t to change or discontinu e work on this pr oposed

product without notice.

Publication# 25686 Rev: B Amendment/3

Issue Date: April 21, 2003

Refer to AMD’s We bsite (www.amd.com) fo r the latest information.

Am29DL32xG

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■Multiple bank architectures

— Three devic es available with dif ferent bank sizes

(refer to Table 3)

■256-byte SecSi (Secured Silicon) Sector

—Fact ory locked a nd identi fiable: 16 bytes av ailable f or

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—Customer lockable: One time programmable. Once

locked, data cannot be changed.

■Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■Package options

— 63-ball FBG A

— 48-ball FBG A

— 48-pin TSOP

— 64-ball Forti fie d BGA

■Top or bottom boot block

■Manufactured on 0.17 µm process technology

■Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

■High performance

— Access time as fast 70 ns

— Program time : 4 µs/word typ ic al util iz ing Accel era te

function

■Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■Minimum 1 million erase cycles guaranteed per

sector

■20 year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■Data Management Software (DMS)

— AMD-su pplied softw are man ages data programming ,

enabling EEPROM emulation

— Eases historical sector erase flash limitations

■Supports Common Flash Memory Interface (CFI)

■Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■Data# Polling and Toggle Bits

— Provi des a softw are metho d of dete cting the status o f

program or erase cycles

■Unlock Bypas s Pro gram com man d

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■Any combination of sectors can be erased

■Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

■WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect

status

— Acceleration (ACC) function accelerates program

timing

■Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

2 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

GENERAL DESCRIPTION

The Am29DL32x G family consists of 32 megabit, 3.0

volt-only flash memory devices, organized as

2,097,152 wor ds o f 1 6 b its e ac h o r 4,1 94,3 04 by tes o f

8 b its each. Word mo de data appears on DQ15–DQ0;

byte mode data appears on DQ7–DQ0. The device is

designed to be programmed in-system with th e stan-

dard 3.0 volt VCC supply, and can also be programmed

in standard EPROM programmers.

The device s are available with an acc ess time of 70,

90, or 120 ns. The devices are offered in 48-pin TSOP,

48-ball or 63-ball FBGA, and 64-ball Fortified BGA

packages. Standard control pins—chip enable (CE#),

write enable (WE#), and output enable (OE#)—control

norma l read an d writ e ope rations , and av oid bu s con-

tention issues.

The devices requires only a single 3.0 volt power

supply for both read and write functions. Internally

generate d and reg ulated voltages are prov ided for the

program and erase operations.

Simultaneous Rea d/Write Ope rations with

Zero Latency

The Simultaneous Read/Write architecture pro vides

simultaneous operation by dividing the memory

space into two banks. The device can improve overall

system perfor m anc e b y a llowi ng a hos t sy ste m to pr o-

gram or er ase in one bank , then imme diately and si-

multaneously read from the other bank, with zero

latency. This releases the system from waiting for the

completion of program or erase operations.

The Am29DL32xG device family uses multiple bank

architectures to provide flexibility for different applica-

tions. Three devices are available with the following

bank sizes:

Am29DL 32 xG Feature s

The SecSiTM (Sec ured Si lic on) S ecto r i s an extra sector

capable of being permanently locked by AMD or cus-

tome rs. The SecSi Indicator Bit (DQ7) is perma-

nently set to a 1 if the part is factory locked, and set

to a 0 if customer lockable. Th is wa y, cu stome r lo ck-

able parts can never be used to replace a factory

locked part. Current version of device has 256

bytes, which differs from previous versions of this

device.

Factory locked parts provide several options. The

SecSi Sector may store a se cure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both.

DMS (Data Management Software) allows systems

to easi ly take ad vantag e of the ad vance d arch itectur e

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it wi ll perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifica tions. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user onl y needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written softwar e must kee p track of the ol d data

location, status, logical to physical translation of the

data onto the F lash memory de vice (or memor y de-

vices), and more. Using DMS, user-written software

does not need to interfac e with the Flash memory di-

rectly. Ins te ad, t he u se r's s oftw ar e acc es ses t he Fl as h

memory by calling one of only s ix functio ns. AMD pr o-

vides this s oftwar e to s implify system de sign and so ft-

ware integrati on efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

Reading data out of the device is similar to reading

from other Flash or EP ROM devi c es .

The host system can detect whether a program or

erase operat ion is complete by usi ng the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The sector erase architecture allows memory sec-

tors to be eras ed and reprogr ammed wit hout affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures i nclude a low

VCC detector that automatically inhibits write opera-

tions during power transiti ons. The hard ware sect or

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipm ent.

The device offers two power -saving features. Whe n

addres ses have been sta ble f or a spe cified amoun t of

time, the device enter s the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

Device Bank 1 Bank 2

DL322 4 28

DL323 8 24

DL324 16 16

April 21, 2003 Am29DL32xG 3

ADVANCE INFORMATION

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations ...........................................................10

Word/Byte Configuration ..............................................................10

Requirements for Reading Array Data .........................................10

Writing Commands/Command Sequences ..................................11

Accelerated Program Operation ...................................................11

Autoselect Functions ....................................................................11

Simultaneous Read/Write Operations

with Zero Latency .........................................................................11

Standby Mode ..............................................................................11

Automatic Sleep Mode .................................................................11

RESET#: Hardware Reset Pin .....................................................12

Output Disable Mode ...................................................................12

Table 2. Device Bank Divisions .............................................................12

Table 3. Top Boot Sector Addresses ...................................................13

Table 4. Top Boot SecSiTM Sector Addresses..................................... 14

Table 5. Bottom Boot SecSiTM Sector Addresses................................ 14

Autoselect Mode ..........................................................................15

Table 6. Autoselect Codes, (High Voltage Method) .............................15

Sector/Sector Block Protection and Unprotection ........................16

Table 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................16

Table 8. Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................16

Write Protect (WP#) .....................................................................17

Temporary Sector Unprotect ........................................................17

Figure 1. Temporary Sector Unprotect Operation................................. 17

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms ............................................................ 18

SecSiTM (Secured Silicon) Sector

Flash Memory Region ..................................................................19

Factory Locked: SecSi Sector Programmed and Protected At the

Factory .........................................................................................19

Customer Lockable: SecSi Sector NOT Programmed or Protected At

the Factory ...................................................................................19

Hardware Data Protection ............................................................19

Low VCC Write Inhibit ..................................................................20

Write Pulse “Glitch” Protection .....................................................20

Logical Inhibit ...............................................................................20

Power-Up Write Inhibit .................................................................20

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 9. CFI Query Identification String................................................ 20

Table 10. System Interface String......................................................... 21

Table 11. Device Geometry Definition .................................................. 21

Table 12. Primary Vendor-Specific Extended Query ............................ 22

Command Definitions . . . . . . . . . . . . . . . . . . . . . .22

Reading Array Data ......................................................................22

Reset Command ..........................................................................23

Autoselect Command Sequence ..................................................23

Enter SecSiTM Sector/Exit SecSi Sector

Command Sequence ...................................................................23

Byte/Word Program Command Sequence ...................................23

Unlock Bypass Command Sequence ...........................................24

Figure 3. Program Operation................................................................ 24

Chip Erase Command Sequence .................................................24

Sector Erase Command Sequence ..............................................25

Erase Suspend/Erase Resume Commands ................................25

Figure 4. Erase Operation .................................................................... 26

Table 13 . Command Definitions ...................................... ..................... 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling ......................................................................28

Figure 5. Data# Polling Algorithm......................................................... 28

RY/BY#: Ready/Busy# ................................................................. 29

DQ6: Toggle Bit I ..........................................................................29

Figure 6. Toggle Bi t Algorithm.............................................................. 29

DQ2: Toggle Bit II .........................................................................30

Reading Toggle Bits DQ6/DQ2 ....................................................30

DQ5: Exceeded Timing Limits ......................................................30

DQ3: Sector Erase Timer .............................................................30

Table 14 . Write Operation Status .........................................................31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform. ............................ 32

Figure 8. Maximum Positive Overshoot Waveform .............................. 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. ICC1 Current vs. Time (Showing Active and

Automatic Sleep Currents).................................................................... 34

Figure 10. Typical ICC1 vs. Frequency................................................... 34

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup.......................................................................... 35

Figure 12. Input Waveforms and Measurement Levels........................ 35

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Read Operation Timings...................................................... 36

Figure 14. Reset Timing s........ ....... ....... ...... ....... ....... ....... ...... ....... ....... . 37

Word/Byte Configuration (BYTE#) ...............................................38

Figure 15. BYTE# Timings for Read Operations.................................. 38

Figure 16. BYTE# Timings for Write Operations .................................. 38

Erase and Program Operations ...................................................39

Figure 17. Progr am Opera tion Timing s ............. ....... ....... ...... .............. . 40

Figure 18. Acce lerated Pro gra m Timing Dia gra m ................. ....... ....... . 40

Figure 19. Chip/Sector Erase Operation Timings................................. 41

Figure 20. Back-to- back R ead/ Write Cycle Timing s........ ...... ....... ....... . 42

Figure 21. Data# Po lling Timings (D urin g Embedde d Algorithms)....... 42

Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............ 43

Figure 23. DQ2 vs. DQ6....................................................................... 43

Temporary Sector Unprotect ........................................................44

Figure 24. Temporary Sector Unprotect Timing Diagram..................... 44

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diag ram 45

Alternate CE# Controlled Erase and Program Operations ...........46

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings ................................................................................ 47

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 48

TSOP Pin and Fine-Pitch BGA Capacitance. . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm .49

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm .........................50

TS 048—Thin Small Outline Package ..........................................51

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53

Revision A (November 7, 2001) ...................................................53

4 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

PRODUCT SELEC TOR GUIDE

BLOCK DIAGRAM

Part Number Am29DL32xG

Speed Rating Standard Voltage Range: VCC = 2.7–3.6 V 70 90 120

Max Access Time (ns) 70 90 120

CE# Access (ns) 70 90 120

OE# Access (ns) 30 40 40

VCC

VSS

Upper Bank Address

A20–A0

RESET#

WE#

CE#

BYTE#

DQ15–DQ0

WP#/ACC

STATE

CONTROL

COMMAND

RY/BY#

Upper Bank

X-Decoder

Y-Decoder

Latches and Control Logic

OE# BYTE#

DQ15–DQ0

Lower Bank

Y-Decoder

X-Decoder

Latches and

Control Logic

Lower Bank Address

OE# BYTE#

Status

Control

A20–A0

A20–A0A20–A0

DQ15–DQ0 DQ15–DQ0

April 21, 2003 Am29DL32xG 5

ADVANCE INFORMATION

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

48-Pin Standard TSOP

C2 D2 E2 F2 G2 H2 J2 K2

C3 D3 E3 F3 G3 H3 J3 K3

C4 D4 E4 F4 G4 H4 J4 K4

C5 D5 E5 F5 G5 H5 J5 K5

C6 D6 E6 F6 G6 H6 J6 K6

C7 D7A7 B7

A8 B8

A1 B1

E7 F7 G7 H7 J7 K7 L7

NC* NC*NC*

NC* NC* NC* NC*

NC* NC*

NC* NC*NC NC

NC NC DQ15/A-1 V

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# V

CE#A0A1A2A4A3

* Balls are shorted together via the substrate but not connected to the die.

63-Ball Fine-pitch BGA (8 x 14 mm)

Top View, Balls Facing Down

6 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

CONNECTION DIAGRAMS

Special Package Handling Instructions

Special handling is required for Flash Memory prod-

ucts in molded packages (TSOP, BGA, PLCC, SSOP).

The packag e and/or data inte grity may be compromi sed

if the package body is exposed to temperatures above

150°C for prolonge d pe ri o ds of t im e.

C2 D2 E2 F2 G2 H2 J2 K2

C3 D3 E3 F3 G3 H3 J3 K3

C4 D4 E4 F4 G4 H4 J4 K4

C5 D5 E5 F5 G5 H5 J5 K5

C6 D6 E6 F6 G6 H6 J6 K6

C7 D7 E7 F7 G7 H7 J7 K7

DQ15/A-1 VSSBYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSSCE#A0A1A2A4A3

48-Ball Fine-pitch BGA (6 x 12 mm)

Top View, Balls Facing Down

B3 C3 D3 E3 F3 G3 H3

B4 C4 D4 E4 F4 G4 H4

B5 C5 D5 E5 F5 G5 H5

B6 C6 D6 E6 F6 G6 H6

B7 C7 D7 E7 F7 G7 H7

B8 C8 D8 E8 F8 G8 H8

NCNCNCV

CCQ

NCNC

DQ15BYTE#A16A15A14A12

DQ6

DQ13DQ14DQ7A11A10A8

DQ4V

DQ12DQ5A19NCRESET#

DQ3DQ11DQ10DQ2A20A18WP#/ACC

DQ1DQ9DQ8DQ0A5A6A17

A13

WE#

RY/BY#

B2 C2 D2 E2 F2 G2 H2

OE#CE#A0A1A2A4

B1 C1 D1 E1 F1 G1 H1

NCNCV

CCQ

NCNCNCNC

64-Ball Fortified BGA (11 x 13 mm)

Top View, Balls Facing Down

April 21, 2003 Am29DL32xG 7

ADVANCE INFORMATION

PIN DESCRIPTION

A20–A0 = 21 Address es

DQ14–DQ0 = 15 Data Inputs/Outpu ts

DQ15/A-1 = DQ15 (Data Input/Output, word

mode), A-1 (LSB Addres s Input, byte

mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RESET# = Hardware Reset Pin, Active Low

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy Output

VCC = 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply toler-

ances)

VSS = Device Ground

NC = Pin Not Connected Internally

LOGIC SYMBOL

21 16 or 8

DQ15–DQ0

(A-1)

A20–A0

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

WP#/ACC

8 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29DL32xG T 70 E I OPTIONAL PROCESSING

Blank = Standar d Pr oce ssing

N = 16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48- Pi n Th in Sm all Ou tline P ack age

(TSOP) Standard Pinou t (TS 04 8)

WD = 63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pi t ch, 8 x 14 mm pack age (FBD06 3)

WM = 48-Ba ll Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pi t ch, 6 x 12 mm pack age (FBD04 8)

PC = 64-Ball Fortified Pitch Ball Grid Array (FBGA)

1.00 mm pit ch, 11 x 13 mm package (LAA0 64)

SPEED OPTION

See Produc t Se le ct or Gui de and Valid Combination s

BOOT CODE SECTOR ARCHITECTURE

T = Top se ctor

B = Bottom sect or

DEVICE NUMBER/DESCRIPTION

Am29DL32xG

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combina tions for TSOP Packages

AM29DL322GT70,

AM29DL322GB70

EI, EIN,

EE, EEN

AM29DL323GT70

AM29DL323GB70

AM29DL324GT70,

AM29DL324GB70

AM29DL322GT90,

AM29DL322GB90

AM29DL323GT90,

AM29DL323GB90

AM29DL324GT90,

AM29DL324GB90

AM29DL322GT120,

AM29DL322GB120

AM29DL323GT120,

AM29DL323GB120

AM29DL324GT120,

AM29DL324GB120

Va lid Combinations for FBGA Packages

Orde r N um ber Package Ma rking

AM29DL322GT70,

AM29DL322GB70

WMI,

WMIN

D322GT70U,

D322GB70U

AM29DL323GT70,

AM29DL323GB70 D323GT70U,

D323GB70U

AM29DL324GT70,

AM29DL324GB70 D324GT70U,

D324GB70U

AM29DL322GT90,

AM29DL322GB90 D322GT90U,

D322GB90U

AM29DL323GT90,

AM29DL323GB90 D323GT90U,

D323GB90U

AM29DL324GT90,

AM29DL324GB90 D324GT90U,

D324GB90U

AM29DL322GT120,

AM29DL322GB120 D322GT12U,

D322GB12U

AM29DL323GT120,

AM29DL323GB120 D323GT12U,

D323GB12U

AM29DL324GT120,

AM29DL324GB120 D324GT12U,

D324GB12U

April 21, 2003 Am29DL32xG 9

ADVANCE INFORMATION

Valid Combinations

V alid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Valid Combina tions for FBGA Packages

Orde r Nu m ber Packa ge Marking

AM29DL322GT70,

AM29DL322GB70

WDI,

WDIN,

D322GT70V,

D322GB70V

AM29DL323GT70,

AM29DL323GB70 D323GT70V,

D323GB70V

AM29DL324GT70,

AM29DL324GB70 D324GT70V,

D324GB70V

AM29DL322GT90,

AM29DL322GB90 D322GT90V,

D322GB90V

AM29DL323GT90,

AM29DL323GB90 D323GT90V,

D323GB90V

AM29DL324GT90,

AM29DL324GB90 D324GT90V,

D324GB90V

AM29DL322GT120,

AM29DL322GB120 D322GT12V,

D322GB12V

AM29DL323GT120,

AM29DL323GB120 D323GT12V,

D323GB12V

AM29DL324GT120,

AM29DL324GB120 D324GT12V,

D324GB12V

Valid Comb in ations for Fortified B G A Packages

Orde r Nu m ber Packa ge Marking

AM29DL322GT70,

AM29DL322GB70

PCI

D322GT70P,

D322GB70P

AM29DL323GT70,

AM29DL323GB70 D323GT70P,

D323GB70P

AM29DL324GT70,

AM29DL324GB70 D324GT70P,

D324GB70P

AM29DL322GT90,

AM29DL322GB90 D322GT90P

D322GB90P

AM29DL323GT90,

AM29DL323GB90 D323GT90P,

D323GB90P

AM29DL324GT90,

AM29DL324GB90 D324GT90P,

D324GB90P

AM29DL322GT120,

AM29DL322GB120 D322GT12P,

D322GB12P

AM29DL323GT120,

AM29DL323GB120 D323GT12P,

D323GB12P

AM29DL324GT120,

AM29DL324GB120 D324GT12P,

D324GB12P

10 Am29DL32xG April 21, 2003
 ADVANCE INFORMATION
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the in ternal co mmand r egiste r.  The comma nd regi ster
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed  to  exec ute  the  comm and.  Th e c onten ts o f th e
register serve as inputs to the internal state machine.
The state m achine outputs dic tate the function  of the
devic e. Table 1 list s the devic e bus operat ions, the  in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Tab le 1. Device Bus Operations
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, 
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector 
Block Protection and Unprotection” section.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector 
protecti on d epe nds  on  wh eth er the y we re la st p rotec te d or un pro t ected using the m eth od d es cribed  in “Se cto r/Sec tor Bl oc k 
Protection and Unprotection”. If WP#/ ACC = VHH, all sectors will be unprotected.
Word/Byte Configuration
The BY TE# pin contr ols whethe r the devic e data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE#  pi n is set a t logic ‘0 ’, the dev ic e is  in byt e
config uration, and only  data I/O pi ns DQ7–DQ0 are
active an d controlle d by CE# and OE#. T he data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and O E# pins to VIL. CE# is the power
contro l and sel ects the devi ce. OE # is the outp ut con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon dev ice power -up,  or after  a hardwa re res et. Th is
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessar y in this mode to obtai n array dat a.
Stand ard micropr ocessor  read cycles  that assert va lid
address es on  the devi ce add ress  inputs  prod uce va lid
Operation CE# OE# WE# RESET# WP#/ACC Addresses
(N ote 2)
DQ15–DQ8
DQ7–
DQ0
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H L/H AIN DOUT DQ8–DQ14 = 
High-Z,  DQ 15 = A- 1 DOUT
Write L H L H (Note 3) AIN DIN DIN
Standby VCC ± 
0.3 V XXVCC ± 
0.3 V H X High-Z High-Z High-Z
Output Disable L H H H L/H X High-Z High-Z High-Z
Reset X X X L L/H X High-Z High-Z High-Z
Sector Protect (Note 2) L H L VID L/H SA, A6 = L, 
A1 = H, A0 = L XXD
IN
Sector Un pr ot ect (Note 2) L H L VID (Note 3) SA, A6 = H, 
A1 = H, A0 = L XXD
IN
Temporary Sect or  
Unprotect XXX V
ID (Note 3) AIN DIN High-Z DIN

April 21, 2003 Am29DL32xG 11
 ADVANCE INFORMATION
data o n the device  dat a outputs.  Each ba nk remains
enabled for read ac cess until the co mmand register
contents are altered.
See “Requirements for Reading Array Data” for more
informa tion. Refe r to the AC  Read-Onl y Operatio ns
table for timing specifications and to Figure 13 for the
timing diagram. ICC1 in the DC Char acteristics tabl e
represents the active current specification for reading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes progra mming data to the dev ice and erasin g
sectors  of memor y), the system  must dr ive WE# an d
CE# to VIL, and OE# to VIH.
For pro gram operati ons, the BY TE#  pin determi nes
whether the d evice ac cepts prog ram data in  bytes or
words. Refer to “Word/Byte Configuration” for more in-
formation. 
The devic e fe atures  a n Unlock  Bypas s mode to facil-
itate  faster prog rammi ng. Once a ba nk enters  the Un-
lock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on pro-
gramming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector , multiple sec-
tors, or the entire devic e. Tables 3–5 indicate the ad-
dress space that each sector occupies. The device
address space is divided into two banks: Bank 1 con-
tains the boot /par am ete r sect or s, an d Ban k 2 co ntai ns
the larger, code sectors of uniform size. A “bank ad-
dress” i s th e ad dr es s b its r equ ir ed t o uni qu ely  s ele ct  a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
ICC2 in  the DC  Charact eristic s table  repres ents the ac -
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program O peration
The device offers accelerated program operations
through  the  A CC fu nc tio n.  This  i s on e o f two functi ons
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory. 
If the system asserts VHH on this  pin, the devi ce auto-
maticall y enters the  aforemention ed Unlock B ypass
mode, temporarily unprotects any protected sectors,
and use s the h igher vo ltage on  the pi n to re duce th e
time required for program operations. The system
would use a two-cycle program command sequence
as require d by the Unlock  Bypass mode. R emoving
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not
be at VHH for operations other than accelerated pro-
gramming, or de vice damage  may result. In ad dition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result.
Autoselect Fun ctions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system  can then read  autoselec t codes  from the inter -
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings app ly in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
Simultaneous Read/Write Operations 
with Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of  memo ry. An er as e op er ation may also be  su s-
pended to rea d from or program to an other location
within the same bank (except the sector being
erase d). Figu re 20  shows  how re ad and  write  cycl es
may be initiated for simultaneous operation with zero
late ncy. ICC6 and ICC7 in the DC Char acterist ics table
represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input. 
The devic e ente rs the CM OS stan dby m ode whe n the
CE# and RE SET# pins ar e both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the s tandby  curren t will be gr eater. The devi ce re-
quires standard access time (tCE) for read access
when the devic e is in eithe r of these standby  modes,
before it is ready to read data.
If the device is  deselecte d during eras ure or progra m-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy co nsumption. The  dev ice automatica lly enables
this mo de when addresses remain stable for tACC +
30 ns. T he automatic s leep mode i s independe nt of
the CE#, WE# , and OE#  control s ignals. St and ard ad-
dress access timings provide new data when ad-

12 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

dresses are changed. While in sleep mode, output

data i s latche d and a lways av ailable t o the s ystem.

ICC5 in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Rese t Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. T he device also resets the i nternal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. Wh en RESE T# is held at VSS± 0.3 V, the devic e

draws CMOS standby current (ICC4). If RES ET# is held

at VIL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine

whether t he res et ope ration i s co mplete . If RES ET# is

asserted when a program or erase operation is not ex-

ecuting (RY/BY# pin is “1”), the reset operation is com-

pleted within a time of tREADY (not during Embedded

Algorithms). T he system can read data tRH after the

RESET# pin returns to VIH.

ICC4 in the DC Characteristics table represents the

reset current. Also refer to AC Characteristics tables

for RESE T# tim ing parameters and to Figure 14 for

the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Table 2. Device Bank Divisions

Device

Part Number

Bank 1 Bank 2

Megabits Sector Sizes Megabits Sector Sizes

Am29DL322G 4 Mbit Eight 8 Kbyte/4 Kword,

seven 64 Kbyt e/3 2 Kword 28 Mbit Fifty-six

64 Kbyte/32 Kword

Am29DL323G 8 Mbit Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword 24 Mbit Forty-eight

64 Kbyte/32 Kword

Am29DL 324 G 16 Mbit Eight 8 Kbyte/4 Kword,

thrity-one 64 Kbyte/32 Kword 16 Mbit Thirty-two

64 Kbyte/32 Kword

April 21, 2003 Am29DL32xG 13

ADVANCE INFORMATION

Table 3. Top Boot Sector Addresses

Am29DL324GT

Am29DL323GT

Am29DL322GT

Sector Sector Address

A20–A12 Sector Si ze

(Kbytes/Kwords) (x8)

Address Range (x16)

Address Range

Bank 2

SA0 000000xxx 64/32 000000h–00FFFFh 000000h–07FFFh

SA1 000001xxx 64/32 010000h–01FFFFh 008000h–0FFFFh

SA2 000010xxx 64/32 020000h–02FFFFh 010000h–17FFFh

SA3 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh

SA4 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh

SA5 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh

SA6 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh

SA7 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh

SA8 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh

SA9 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh

SA10 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh

SA11 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh

SA12 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh

SA13 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh

SA14 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh

SA15 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh

SA16 010000xxx 64/32 100000h–10FFFFh 080000h–087FFFh

SA17 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh

SA18 010010xxx 64/32 120000h–12FFFFh 090000h–097FFFh

SA19 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh

SA20 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh

SA21 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh

SA22 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh

SA23 010111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh

SA24 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh

SA25 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh

SA26 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh

SA27 011011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh

SA28 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh

SA29 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh

SA30 011110xxx 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh

SA31 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh

Bank 1

SA32 100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh

SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh

SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh

SA35 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh

SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh

SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh

SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh

SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh

SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh

SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh

SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh

SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh

SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh

SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

14 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits are A20–A18 for

Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324.

Table 4. Top Boot SecSiTM Sector Addresses

Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH). The bank address bits

are A20–A18 for Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324.

Table 5. Bottom Boot SecSiTM Sector Addresses

Bank 1

Bank 2

SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh

SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh

SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh

SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh

SA52 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh

SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

Bank 1

SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh

SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh

SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh

SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh

SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh

SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh

SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh

SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh

SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh

SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh

SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh

Table 3. Top Boot Sector Addresses (Continued)

Am29DL324GT

Am29DL323GT

Am29DL322GT

Sector Sector Address

A20–A12 Sector Si ze

(Kbytes/Kwords) (x8)

Address Range (x16)

Address Range

Device Sector Address

A20–A12 Sector Size

(Bytes/Words) (x8)

Address Range (x16)

Address Range

Am29DL32xGT 111111xxx 256/128 3FE000h–3FE0FFh 1FF000h–1FF07Fh

Device Sector Address

A20–A12 Sector Size

(Bytes/Words) (x8)

Address Range (x16)

Address Range

Am29DL32xGB 000000xxx 256/128 000000h–0000FFh 00000h–00007Fh

April 21, 2003 Am29DL32xG 15

ADVANCE INFORMATION

Autoselect Mode

The autos elect mode provid es manufacture r and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algor ithm. Ho wever, the autose lect co des can al so be

accessed in-system through the command register.

When using programming equipment, the autoselect

mode requires VID (8.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 6. In addition, when verifying s ector protection,

the sector address must appear on the appropriate

highest order address bits (see Tables 3–5). Table 6

shows the remaining address bits that are don’t care.

When all ne cessary bits ha ve been set as requ ired,

the prog rammin g equipment may then r ead the corr e-

sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command re gis te r, as shown in Ta ble 13. T his method

does not require VID. Refer to the Autoselect Com-

mand Sequence section for more information.

Table 6. Autoselect Codes, (High Voltage Method)

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, B A = Bank Addres s, SA = Sector Address, X

= Don’t care.

Description CE# OE# WE#

A20

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8 to DQ15 DQ7

DQ0

BYTE#

= VIH

BYTE#

= VIL

Manufacturer ID: AMD L L H BA X VID XLXLL X X 01h

Device ID: Am29DL322G L L H BA X VID X L X L H 22h X 55h (T ), 56h (B)

Device ID: Am29DL323G L L H BA X VID X L X L H 22h X 50h (T ), 53h (B)

Device ID: Am29DL324G L L H BA X VID X L X L H 22h X 5Ch (T), 5Fh (B)

Sector Protection

Verification LLHSAX

VID XLXHL X X 01h (protected),

00h (unprotected)

SecSi Indicator Bit

(DQ7) LLHBAX

VID XLXHH X X 82h (factory locked),

02h (not factory

locked)

16 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

Sector/S ec tor Block Protecti on and

Unprotection

(Note: For the foll owing discussi on, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protecte d or unpr otected at the same tim e (see Tables

7 and 8).

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotec tion can be imple-

mented via two methods.

T able 7. T op Boot Sector/Sector Block Addresses

for Protection/Unprotection

Table 8. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotec tion

Sect or pr otec tion/u npr ot ect ion re qui res VID on the RE-

SET# pi n only, and can be implemen ted eith er in-s ys-

tem or via programming equipment. Figure 2 shows

the algorithms and Figure 25 shows the timing dia-

gram. Thi s me thod us es standard mi cro pr oces so r bus

cycle timing. For sector unprotect, all unprotected sec-

tors must first be protected prior to the first sector un-

protect write cy cle.

The secto r unprotect alg orithm unprotects all sectors

in paral le l. A l l pr evi ous ly protected sec tors must be i n-

dividuall y re-protected. To change data in protecte d

sectors efficiently, the temporary sector unprotect

function is available. See “Temporary Sector Unpro-

tect”.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Sector A20–A12 Sector/

Sector Block Size

SA0 000000XXX 64 Kbytes

SA1-SA3 000001XXX,

000010XXX

000011XXX 192 (3x64) Kbytes

SA4-SA7 0001XXXXX 256 (4x64) Kbytes

SA8-SA11 0010XXXXX 256 (4x64) Kbytes

SA12-SA15 0011XXXXX 256 (4x64) Kbytes

SA16-SA19 0100XXXXX 256 (4x64) Kbytes

SA20-SA23 0101XXXXX 256 (4x64) Kbytes

SA24-SA27 0110XXXXX 256 (4x64) Kbytes

SA28-SA31 0111XXXXX 256 (4x64) Kbytes

SA32-SA35 1000XXXXX 256 (4x64) Kbytes

SA36-SA39 1001XXXXX 256 (4x64) Kbytes

SA40-SA43 1010XXXXX 256 (4x64) Kbytes

SA44-SA47 1011XXXXX 256 (4x64) Kbytes

SA48-SA51 1100XXXXX 256 (4x64) Kbytes

SA52-SA55 1101XXXXX 256 (4x64) Kbytes

SA56-SA59 1110XXXXX 256 (4x64) Kbytes

SA60-SA62 111100XXX,

111101XXX,

111110XXX 192 (3x64) Kbytes

SA63 111111000 8 Kbytes

SA64 111111001 8 Kbytes

SA65 111111010 8 Kbytes

SA66 111111011 8 Kbytes

SA67 111111100 8 Kbytes

SA68 111111101 8 Kbytes

SA69 111111110 8 Kbytes

SA70 111111111 8 Kbytes

Sector A20–A12 Sector/Sector Block

Size

SA70 111111XXX 64 Kbytes

SA69-SA67 111110XXX,

111101XXX,

111100XXX 192 (3x64) Kbytes

SA66-SA63 1110XXXXX 256 (4x64) Kbytes

SA62-SA59 1101XXXXX 256 (4x64) Kbytes

SA58-SA55 1100XXXXX 256 (4x64) Kbytes

SA54-SA51 1011XXXXX 256 (4x64) Kbytes

SA50-SA47 1010XXXXX 256 (4x64) Kbytes

SA46-SA43 1001XXXXX 256 (4x64) Kbytes

SA42-SA39 1000XXXXX 256 (4x64) Kbytes

SA38-SA35 0111XXXXX 256 (4x64) Kbytes

SA34-SA31 0110XXXXX 256 (4x64) Kbytes

SA30-SA27 0101XXXXX 256 (4x64) Kbytes

SA26-SA23 0100XXXXX 256 (4x64) Kbytes

SA22–SA19 0011XXXXX 256 (4x64) Kbytes

SA18-SA15 0010XXXXX 256 (4x64) Kbytes

SA14-SA11 0001XXXXX 256 (4x64) Kbytes

SA10-SA8 000011XXX,

000010XXX,

000001XXX 192 (3x64) Kbytes

SA7 000000111 8 Kbyt es

SA6 000000110 8 Kbytes

SA5 000000101 8 Kbyte s

SA4 000000100 8 Kbyte s

SA3 000000011 8 Kbytes

SA2 000000010 8 Kbyte s

SA1 000000001 8 Kbyte s

SA0 000000000 8 Kbyte s

April 21, 2003 Am29DL32xG 17

ADVANCE INFORMATION

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode sec-

tion for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using VID. This function is one of two provided by the

WP#/ACC pin.

If the system asserts VIL on the WP #/ACC pi n, the d e-

vice disable s program and erase func tions in the two

“outermost” 8 Kbyt e boot sectors independently of

whether those sectors were protected or unprotec ted

using the method described in “Sector/S ector Block

Protection and Unprotection”. The two outermost 8

Kbyte boot sectors are the two sectors containing the

lowest addresses in a bottom-boot-configured device,

or the two s ec tor s con t ain in g the hi ghe st ad dr es se s i n

a top-boot-configured device.

If the system a sser ts VIH on the WP#/ACC pin, the de-

vice reverts to whether the two outermost 8K Byte

boot sectors were last set to be protected or unpro-

tected. That i s, sector protection or unprotection for

these two sectors depends on whether they were last

protected or unprotected using the method described

in “Sector/Sector Block Protection and Unprotection”.

Note that the WP#/ACC pin must not be left floating or

unconne cted; inc onsistent be havior of the de vice may

result.

Temporary Sector Unprotect

(Note: For the foll owing discussion, the ter m “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protecte d or unpr ote cted at the same time (see Tables

7 and 8).

This feature allows temporary unp rotection of previ-

ously protected sectors to change data in-system. The

Sect or Unpro tect m ode is ac tiva ted by setting t he RE-

SET# pin to VID (8.5 V – 12.5 V). During this mode, for-

merly protected sectors can be programmed or erased

by selecting the sector addresses. Once VID is re-

moved from the RESET# pin, all the pr eviously pro-

tected sectors are protected again. Figure 1 shows the

algorithm, and Figure 24 shows t he timing di agrams,

for this feature.

Figure 1. Temporary Sector Unprotect Operation

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protect ed sec to r s unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

2. All previous ly protected sect o rs ar e prote cte d once

again.

18 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to any

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

April 21, 2003 Am29DL32xG 19

ADVANCE INFORMATION

SecSiTM (Secured Silicon) Sector

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a

256-byte Flash memory region that enables perm a-

nent part identification through an Electronic Serial

Number (ESN). The SecSi Sector uses a SecSi Sector

Indicator Bit (DQ7) to indicate whether or not the

SecSi S ector is lo cked wh en shippe d from th e factory.

This bit is permanently set at the factory and cannot

be changed, which prevents cloning of a factory

locked part. This ensures the security of the ESN once

the product is shipped to the field.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory -locke d vers ion is always prot ected wh en sh ippe d

from the factory, and has the SecSi (Secured Silicon)

Sector Indic ator Bit per manen tly set to a “1.” Th e cus-

tomer-l ockable ve rsion is shi pped with the S ecSi Sec-

tor unprotected, allowing customers to utiliz e the that

sector in any manner they choose. The customer-lock-

able version has the SecSi (Secured Silicon) Sector

Indicato r Bit permanently set to a “0.” Thus, the SecSi

Sector Indicato r Bi t prevents c ustomer-loc kable de-

vices fr om being used to replace de vices tha t are fac-

tory locked.

The system accesses the SecSi Sector through a

comm and sequ ence (s ee “Ente r Sec SiTM Sector/Exit

SecSi Se cto r Comman d Seq uence”) . After the system

has written the Enter SecSi Sector command se-

quence, it may r ead th e S ecS i Sec tor by usin g the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the devic e. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the boot sectors.

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The S ecSi S ector c annot be m odified in a ny wa y. The

device is available pr eprogrammed with one of the fol -

lowing:

■A random, secure ESN only

■Customer code through the ExpressFlash service

■Both a random, secure ESN and customer code

through the ExpressFlash service.

In devices that have an ESN, a Bottom Boot devic e

will have the 16-byte ESN at addresses

000000h–000007h in word mode (or

000000h– 00000Fh in byte mode). In th e Top Boot de-

vice the ESN will be at addresses

1FF000h–1FF007Fh in word mode (or addresses

3FE000h–3FE0FFh in byte mode).

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional 256-byte Flash mem-

ory space, expanding the size of the available Flash

array. Additionally, note the difference in the loca-

tion of the ESN compared to previous Am29DL32x

top boot factory locked devices. The SecSi Se ctor

is one-time programmable, may not be erased, and

can be locked only once. Note that the accelerated

programming (ACC) and unlock bypass functions are

not available when programming the SecSi Sector.

The SecSi Sector area can be protected using one of

the following procedures:

■Write the three-cycle Enter SecSi Sector Region

command sequ enc e, and the n fol low the in- s yste m

sector protect algorithm as shown in Figure 2, ex-

cept that RES ET# may be at either VIH or VID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector

■Write the three-cycle Enter SecSi Sector Region

command sequence, and then use the alternate

method of sector protection described in the “Sec-

tor/Sector Block Protection and Unprote ction” sec-

tion.

The SecSi Sector is one-time programmable. Once

the SecSi Sector is locked and verified, the system

must write the Exit SecSi Sector Region command se-

quence to return to reading and writing the remainder

of the array.

The SecSi Sector protection must be used with cau-

tion since, once protected, there is no procedure avail-

able for unprotecting the SecSi Sector area and none

of the bits in the SecSi Sector memory space can be

modified in any way.

Hardware Data Protection

The comm and seq uenc e requirement of unlock cycl es

for programming or erasing provides data protection

against inadver tent writes (refer to Table 13 for co m-

mand definitions). In a ddition, the following hardware

data protection measures pr event accidental erasure

or progr ammi ng, whic h might ot herwi se be caus ed by

spurious system level signals during VCC power-up

and power-down transitions, or from system noise.

20 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

Low VCC Write Inhibit

When VCC is less than VLKO, th e device does not ac-

cept any write cycles. This pr otects data during VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subs equent

writes are ignored until VCC is greater than VLKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when VCC is

greater than VLKO.

Write Pulse “Glitch ” Prot ec tio n

Noise pulses o f less than 5 ns (typical) on OE#, CE #

or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE # = VIH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL an d OE# = VIH d uring powe r up,

the device does not accept com mands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE

(CFI)

The Commo n Flash Interf ace (CFI) s pecification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algor ithms to be used for entir e families of

devices. Software support can then be device-inde-

pendent , JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

This devi c e en ter s the CF I Q ue ry m ode w hen the sys-

tem writes the CFI Qu ery command , 98h, to ad dress

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 9–12. To te rminate readi ng CFI data,

the sys tem must write th e reset command . The CFI

Query mode is not acc essible when the device is exe-

cuting an Embedd ed Progr am or Emb edde d Erase al-

gorithm.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at th e addresses g iven in Tables 9– 12. The

system must write the reset command to return the de-

vice to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the

World Wide Web at http://www.amd.com/flash/cfi. Al-

ternatively, contact an AMD representative for copies

of these documents.

Table 9. CFI Query Identification String

Addresses

(Word Mod e) Addresses

(Byte Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h Primary OEM Command Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended Table

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 32h

34h 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

April 21, 2003 Am29DL32xG 21

ADVANCE INFORMATION

Table 10. System Interface String

Table 11. Device Geometry Definition

Addresses

(Word Mod e) Addresses

(Byte Mode) Data Description

1Bh 36h 0027h VCC Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typical tim eou t for Min. si ze buffer write 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Addresses

(Word Mod e) Addresses

(Byte Mode) Data Description

27h 4Eh 0016h Device Size = 2N byte

28h

29h 50h

52h 0002h

0000h Flash Device Interface descri pti on (refe r to CFI publ ica tio n 100)

2Ah

2Bh 54h

56h 0000h

0000h Max. number of bytes in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

22 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

Table 12. Primary Vendor-Specific Ex tended Query

Note:

The number of sectors in Bank 2 is device dependent.

Am29DL322 = 38h, Am29DL323 = 30h, Am29DL324 = 20h

COM MAND DEFINITI ONS

Writing speci fic address and data commands or s e-

quences into the command register initiates device op-

erati ons. Ta ble 13 defi nes the val id reg ister c ommand

sequences. Writ ing inco rrect addr ess and data v alues

or writing them in the improper sequence may place

the device in an unknown state. A reset command is

then required to return t he device to reading array

data.

All addresses are latched on the falling e dge of WE#

or CE#, whichever happens later . All data is latched on

the rising edge of WE# or CE#, whichever happens

first. R efer to th e AC Ch arac teristics sectio n for timing

diagrams.

Reading Array Data

The de vice i s automa tically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase alg orith m.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. After completing a programming operation

in the Erase Suspend mode, the system may once

Addresses

(Word Mod e) Addresses

(Byte Mode) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h Query-unique ASCII string “PRI”

43h 86h 0031h Major version number, ASCII

44h 88h 0033h Minor version number, ASCII

45h 8Ah 0004h Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

Silicon Revision Number (Bits 7-2)

46h 8Ch 0002h Erase Suspend

0 = Not Supported, 1 = To R ead Only, 2 = To Read & Write

47h 8Eh 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0004h Sector Protect/Unprotect scheme

04 = 29 LV800 mode

4Ah 94h 00XXh

(See Note) Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank 2 (Uniform Bank)

4Bh 96h 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0000h Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag

02h = Bottom B oot Device, 03h = Top Boot Device

April 21, 2003 Am29DL32xG 23
 ADVANCE INFORMATION
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands sec-
tion for more information.
The syste m must issue the reset comm and to return  a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active  program or erase opera-
tion, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cy cl es in an er as e co mm and s equ ence before
erasin g begin s. This  rese ts the b ank to w hich t he sys-
tem was writing to the read mode. Once erasure be-
gins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
whic h the sy stem was  writi ng to the r ead m ode. If  the
program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-sus-
pend-read mode. Once programming begins, how-
ever, the device ignores reset commands until  the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be  written  to retu rn to the  read  mode. If  a bank
entered the au toselect mode whi le in the Erase Sus-
pend mode, writing the rese t command returns tha t
bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writin g the res et comma nd return s the bank s to th e
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The auto select command s equence allows  the host
system  to acce ss the  manufac turer an d devi ce cod es,
and determine whether or not a sector is protected.
Table 13 shows the address and data requirements.
This m eth od  is  an  al ternative to that sh own  in  Tabl e 6 ,
which is intended for PROM programmers and re-
quires VID on address pin A9. The autoselect com-
mand sequ enc e m ay  be writ ten to an addres s  with in  a
bank that is either  in the read or erase-s uspend-read
mode. The  autoselect comm and may not be  written
while th e devic e is activ ely prog rammi ng or eras ing in
the other bank.
The au tosele ct c omman d seq uence  is  initi ated b y fir st
writing two unlock cycles. This is followed by a third
write cy cle t hat c on tain s t he ba nk  add re ss  an d the  au-
toselect command. The bank then enters the autose-
lect mode. The system may read at any address within
the same bank any  number of times without i nitiating
another autoselect command sequence:
■A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code. 
■A read c ycle to an a ddress co ntaining a  sector  ad-
dress ( SA) within the  same bank , and the  address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Ta-
bles 3–5 for valid sector addresses).
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Enter SecSiTM Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing a random, sixteen-byte electronic serial
number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector  command s equence. T he device c ontinues  to
access the SecSi Sector region until the system is-
sues th e four-cycle Exit  SecSi Sec tor command se-
quence. The Exit Sec Si Sector command sequence
returns the device to normal operation. The SecSi
Sector is not accessible when the device is executing
an Embedded Program or Embedded Erase algo-
ri thm.  Ta ble 13 shows the add ress  and data require-
ments for both command sequences. See also
“SecSiTM (Secured Silicon) Sector Flash
Memory Region” for further information. 
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is  a f our-bus -cyc le op eration.  The  progr am co m-
mand sequ ence is initi ated by writ ing two unloc k write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to  provide further  controls or
timings. The device automatically provides internally
generated program pulses and verifies the pro-

24 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

grammed cell margin. Table 13 shows the address

and data requirements for the byte program command

sequence.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresse s are no l onger l atched . The syst em can de ter-

mine the status of the program operation by usin g

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

Any commands written to the device during the Em-

bedded Progr am Algorithm are ignor ed. Note that a

hardware reset immed iately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

Programming is allowed in any sequenc e and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a

“0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is follo wed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all tha t is r eq uir e d to pr og ra m in th is mode. The fir s t

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed i n the same ma nner. This mode dispenses

with the initial two unl ock cycl es required in the s tan-

dard program command sequence, resulting in faster

total programming time. Table 13 shows the require-

ments for the command sequence.

During the unlo ck byp ass mode, only t he Unloc k By-

pass Program and Unlock Bypass Reset commands

are valid . To exit the unloc k bypass mod e, the sys tem

must issue the two-cycle unlock bypass reset com-

mand sequ enc e. The fi r st cy cle m us t co nta in t he b ank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

The device offers accelerated program operations

through the WP#/ACC pin . When the sy stem asse rts

VHH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two -cycle Unlock By pass prog ram comm and

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at VHH any operation

other than accelerated program ming, or dev ice dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; i nconsistent behavior

of the device may result.

Figure 3 illus tr ates the al gor it hm for the pr og ra m oper-

ation. Refer to the Erase and Program Operations

table in the AC Cha r act eris tic s sec ti on for par am eters ,

and Figure 17 for timing diagrams.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command seq uence is initiated by writi ng two unlock

cycles, fo llowed by a set- up comm and. Two additi onal

unlock write cycles are then followed by the chip erase

command , whi ch in tur n in vo kes t he E mb edded Eras e

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for a n all zero data pattern prior to electrical

eras e. The sy stem is no t requi red to pro vide a ny con-

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table 13 for program command sequence.

April 21, 2003 Am29DL32xG 25
 ADVANCE INFORMATION
trols or timings during these operations. Table 13
shows the ad dres s and data r equir ement s for the chi p
erase command sequence.
When the Embedded Erase algorithm is complete,
that ban k retu rn s t o the  re ad m ode a nd a ddr es s es ar e
no lo nger lat ched.  The sy stem  can det ermin e the st a-
tus of the  erase oper ation by us ing DQ7, DQ 6, DQ2,
or RY/BY# . Refer to the Write  Operation  Status s ec-
tion for information on these status bits.
Any commands written during the chip erase operation
are ignored . However, note tha t a hard ware res et im-
mediately terminates the erase operation. If that oc-
curs , the chi p erase  command  sequen ce should  be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles  in the AC Ch aracte risti cs secti on for pa rame ters,
and Figure 19 section for timing diagrams.
Sector Erase Command Sequence
Sector eras e is a s ix bus cy cle opera tion. The  sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector  to be erased, and
the sector  erase command. Tabl e 13 shows the ad-
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to  er ase. The Emb edded Eras e algorithm  auto-
matically programs and verifies the entire memory for
an all  zero data  pattern  prior to el ectrical  erase. T he
system is  not required to pr ovide any controls o r tim-
ings during these operations. 
After the command sequence is written, a sector erase
time-out  of 50  µs occu rs. During the ti me-out peri od,
additional sector addresses and sector erase com-
mands (for sectors within the same bank) may be writ-
ten. Loading the sector erase buffer may be done in
any sequence, and the number of sectors may be from
one sector to all sectors. The time between these ad-
ditional  cycl es mu st be  less  than  50 µs, oth erwis e er a-
sure may begin. Any sector erase address and
command following the exceeded time-out may or
may no t be acce pted. It i s reco mmende d that pro ces-
sor interrupts be disabled during this time to ensure all
comma nds a re  ac ce pte d. T he  in ter rupts  c an  be  re -e n-
abled after the last Sector Erase command is written.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets that
bank to the read mode. The system  must rewr ite the
command sequence and any additional addresses
and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer .). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the  Emb edde d Eras e al gor it hm is  com pl ete,  the
bank r eturns  to read ing arr ay data an d add resses a re
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from  the non-eras ing bank.  The system c an de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank.
Refer to th e Writ e Oper ation Statu s section for  infor-
mation on these status bits.
Once the sec tor erase operation has  begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. Howev er, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
Figure 4 illus trates the algorithm for  the erase opera-
tion. Refer to the Erase and Program Operations ta-
bles  in the AC Ch arac teris tics se ction fo r para meter s,
and Figure 19 section for timing diagrams.
Erase Suspend/Erase Resume 
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data f rom,  or  p ro gram  data to, a ny  sec tor  n ot  se le cte d
for  eras ur e. Th e bank  add re ss is re qui red  when  writ ing
this command. This command is valid only during the
sector erase oper ation, including the 50 µs time-out
period during the sector erase comman d sequence.
The Erase Suspend command is ignored if written dur-
ing the chi p erase operation  or Embedded Pro gram
algorithm. 
When the Erase S uspend command i s written during
the sector erase operation, the device requires a max-
imum of  20 µs to susp end the eras e operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately term inates th e time- out peri od and su spend s th e
erase operation. 
After the erase operation has been suspended, the
bank ent ers the erase-suspend -read mode . Th e sys-
tem can  read d ata from  or prog ram d ata to  any sec tor
not selected for erasure. (The device “erase sus-
pends” all sec tors selected fo r erasure .) Reading at
any address within erase-suspended sectors pro-
duces status information on DQ7–DQ0. The system
can use DQ7 , or  DQ6 an d DQ 2 to geth er, to determ ine
if a sector is actively erasing or is erase-suspended.

26 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

Refer to the Wr ite Op eration Statu s secti on for infor-

mation on these sta tus bits.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to th e Write Operatio n Status sec tion for more

information.

In the e rase -sus pe nd- read mode, the sys tem ca n al s o

issue t he a utos elec t c om man d s equ enc e. Refer t o th e

Autoselect Mode and Autoselect Command Sequence

sections for details.

To resume the sector erase operation, the system

must write the Erase Resume command. The bank

address of the erase-suspended bank is required

when writing this command. Further writes of the Re-

sume command are ignored. Another Erase Suspend

command can be written after the chip has resumed

erasing.

Figure 4. Erase Operation

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

Notes:

1. See Table 13 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

April 21, 2003 Am29DL32xG 27
 ADVANCE INFORMATION
Table 13. Command Definitions
Legend:
X = Don’t care
RA = Address of th e me mo r y loc at ion  to  be rea d.  
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses 
latch on  th e fallin g e dg e of th e WE#  or CE # pulse , wh ichev er ha pp en s 
later.
PD = Data to be programmed at location PA. Data latches on the rising 
edge of WE# or CE# pulse, whichever happens first.
SA = Addr e ss of  the  sec tor  to  be  ver if ied  (in au t os elect mode ) or  
erased. Address bits A20–A12 uniquely select any sector .
BA = Addr e ss of  th e b an k th at  is  being  s wi tch ed  to  au tos el ect  mo de , is 
in bypass mode, or is being erased.
Notes:
1. See Table 1 for descriptio n of bus operations .
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences, 
except for RD and PD.
5. Unless otherwise noted, address bits A20–A11 are don’t cares.
6. No unlock or command cycles required when bank is reading 
array data.
7. The Reset command is required to return to the read mode (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when a bank is in the autoselect mode, or if DQ5 goes high (while 
the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read 
cycle. The system must provide the bank address to obtain the 
manufacturer ID, device ID, or SecSi Sector factory protect 
information. Data bits DQ15–DQ8 are don’t care. See the 
Autoselect Command Sequence section for more information.
9. The data is 82h for factory locked and 02h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h 
for a protected sector/sector block. 
11. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to the 
read mode when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase 
Suspend mode, and requires the bank address.
15. Command is valid when device is rea dy to read array data  or  when 
device is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufacturer ID Word 4555 AA 2AA 55 (BA)555 90 (BA)X00 01
Byte AAA 555 (BA)AAA
Device ID  Word 4555 AA 2AA 55 (BA)555 90 (BA)X01 (see 
Table 6)
Byte AAA 555 (BA)AAA (BA)X02
SecSi Sector Factory 
Protect (Note 9) Word 4555 AA 2AA 55 (BA)555 90 (BA)X03 82/02
Byte AAA 555 (BA)AAA (BA)X06
Sector/Sector Block 
Protect Ver i fy 
(Note 10)
Word 4555 AA 2AA 55 (BA)555 90 (SA)X02 00/01
Byte AAA 555 (BA)AAA (SA)X04
Enter SecSi Sector Region Word 3555 AA 2AA 55 555 88
Byte AAA 555 AAA
Exit SecSi Sector Region Word 4555 AA 2AA 55 555 90 XXX 00
Byte AAA 555 AAA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2BA 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 BA B0
Erase Resume (Note 14) 1 BA 30
CFI Query (Note 15) Word 155 98
Byte AA

28 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

WRITE OPERATION STATUS

The device provides several bits to determine the status of

a program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 14 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method

for determining whether a program or erase operation is

complete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum progr ammed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, th e de vi ce o utputs the dat um prog ra mmed to

DQ7. The sy s tem mu s t prov i de the prog r am add r ess to

read valid status information on DQ7. If a program address

falls wit hin a prot ected sect or, Data# Polling on D Q7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The syste m mu st pr ov ide an a ddr ess within an y of th e

sectors selected for erasure to read valid status infor-

mation on DQ7.

After an erase command sequence is written, if all

sect ors s el ec ted for e rasi ng ar e p rotec ted, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then

the bank r eturns to the read mode. If not all s elected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lect ed sect ors tha t are pr otecte d. Howe ver, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Just p rior to the com pleti on of an E mbed ded P rogram

or Eras e op erati on, D Q7 m ay c hang e a syn chro nously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid da ta, the da ta output s on DQ0–D Q6 may be s till

invalid. Val id data on DQ7–DQ0 will appear on suc-

cessive read cycles.

Table 14 shows the outpu ts for Data # Poll ing on DQ7.

Figure 5 sh ows the Data # Polli ng algo rithm . Figure 21

in the AC Characteristics section shows the Data#

Polling timing diagram.

Figure 5. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

April 21, 2003 Am29DL32xG 29

ADVANCE INFORMATION

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

which in dicate s w he ther an E mbe dded Al gor ithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since R Y/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to VCC.

If the output is low (Busy), the device is actively eras-

ing or programmin g. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the devic e is in the read mode, the sta ndby

mode, or one of the banks is in the erase-sus-

pend-read mode.

Table 14 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

To ggle Bit I on DQ6 indi cates whethe r an Emb edded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be r ead at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

During an Embedd ed Progra m or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

After an erase command seq uence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice en ter s th e E ras e S usp e nd mo de, DQ 6 st o ps t o ggling.

However, the system mus t also u se DQ2 to deter mine

which se cto rs ar e e ra sing or eras e- suspe nded. Alterna -

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

If a program address falls within a p rotected sector,

DQ6 toggles for approximately 1 µs after the program

command s equenc e is wri tten, then returns to readin g

array data.

DQ6 also toggles during the era se-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 14 shows the outputs for Toggle Bit I on DQ6.

Figure 6 shows the toggle bit algorithm. Figure 22 in

the “AC Character istics” section sh ows the toggle bit

timing diagrams. Figure 23 shows the differences be-

tween DQ 2 and DQ6 in gr aphical form. See also th e

subsection on DQ2: Toggle Bit II.

Figure 6. Toggle Bit Algorithm

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Note: The system should rec heck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

30 Am29DL32xG April 21, 2003
 ADVANCE INFORMATION
DQ2: Toggle Bit II
The “Tog gle  Bit  II”  on  DQ2,  whe n u se d wi th  DQ6,  ind i-
cates  whether a particula r sector is a ctively erasin g
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within tho se secto rs that have been selecte d for era-
sure. ( The  s ys tem  ma y  us e e ith er  OE # o r  CE#  to  co n-
trol the read cycles.) But DQ2 cannot distinguish
wheth er the  sector  is act ively er asing  or is e rase- sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode infor mation. R efer to Tabl e 14 to com pare out-
puts for DQ2 and DQ6. 
Figure 6 shows the toggle bit algorit hm in flowchart
form, an d the  se ction  “DQ2:  Toggl e Bit I I” ex plai ns the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 22 shows the toggle bit timing diagram. Figure
23 shows the differences between DQ2 and  DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure  6 for the following  discussion. W hen-
ever the system initially begins reading toggle bit sta-
tus, it must  read DQ7–DQ0 at le ast twice in a row  to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system  would comp are th e new va lue of th e toggl e bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system  can read ar ray data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it i s, the system should
then determine again whether the toggle bit is tog-
gling, since the  toggle bit may  have stopp ed toggling
just as DQ5 went high . If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not  complet ed the oper ation su ccessf ully, an d
the sys tem mus t writ e the rese t comma nd to ret urn to
reading array data. 
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The  system may conti nue to monitor
the toggle bit and DQ 5 through successive read c y-
cles , determ ining  the st atus as de scrib ed in  the prev i-
ous para graph . Al ter nat iv ely, it may choos e to pe rf orm
other system tasks. In this case, the system must start
at the begin nin g of the alg or ithm when it returns to de-
termine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully  completed.
The device may output a “1” on DQ5 if the system tries
to program a “ 1” to a location  that was previ ously pro-
grammed to “0.” Only an erase operation can
change a “0 ” b ack  to a “1.”  Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a  bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After wri ting a sect or erase comm and sequen ce, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase tim er does not
apply to the chip erase command.) If additional
sectors are s elected for erasure, the entire time- out
also applies after each additional sector erase com-
mand. When the  time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the s ector era se comman d is writte n, the syste m
should  re ad th e st atu s o f DQ7  (D ata#  Poll ing)  or  DQ 6
(Toggle B it I) to ensure that  the dev ice has acce pted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Em bedded  Erase alg orithm has  begun; al l fur-
ther c ommands  (except  Erase  Suspend)  are ig nored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the  status of DQ3 prior  to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 14 show s the sta tus of DQ 3 relativ e to the ot her
status bits.

April 21, 2003 Am29DL32xG 31

ADVANCE INFORMATION

Table 14. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write ope ration statu s bits, the s ystem must al ways provid e the bank addres s where the Embedded Algorith m

is in progress. The device outputs array data if the system addresses a non-busy bank.

Status DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase A lgorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1 No t oggle 0 N/A To ggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

32 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

ABSOLUTE MAXIMUM RATINGS

Storage Tempe ra tur e

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot VSS to –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is VCC +0.5 V.

See Figure 7. D u ring vo lta ge transitions, input or I /O pins

may overs hoot to VCC + 2.0 V for peri ods up to 20 ns. Se e

Figure 8.

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. Duri ng voltage transitions, A9,

OE#, WP# /ACC, and RES ET# may overshoot VSS to

–2.0 V for per iods o f up to 20 ns . See Fi gure 7. Maxi mum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14 .0 V for period s up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to t he device. This

is a stres s rating only; fu nctiona l operati on of the dev ice at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Figure 7. Maximum Negative

Overshoot Waveform

Figure 8. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for standard voltage range . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

April 21, 2003 Am29DL32xG 33
 ADVANCE INFORMATION
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. T ypical sleep mode current is 
200 nA.
5. Not 100% tested.
Parameter 
Symbol Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC ma x ; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1,  2)
CE# = VIL, OE# = VIH, 
Byte Mode 5 MHz 10 16 
mA
1 MHz 2 4
CE# = VIL, OE# = VIH, 
Word Mode 5 MHz 10 1 6 
1 MHz 2 4
ICC2 VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 15 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA
ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 0.2 5 µA
ICC6 VCC Active Read-While-Program 
Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA
Word 21 45
ICC7 VCC Active Read-While-Erase 
Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA
Word 21 45
ICC8
VCC Active 
Program-While-Erase-Suspended 
Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VHH
Voltage for WP#/ACC Sector 
Protect/Unprotect and Program 
Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min  0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

34 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

DC CHARACTERISTICS

Zero-Power Flash

Note: Addresses are switching at 1 MHz

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

1 2345

Frequency in MHz

Supply Current in mA

Note: T = 25 °CFigure 10. Typical ICC1 vs. Frequency

2.7 V

3.6 V

April 21, 2003 Am29DL32xG 35

ADVANCE INFORMATION

TEST CONDITIONS Table 15. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

Test Condition 70 90, 120 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

Figure 12. Input Waveforms and Measurement Levels

36 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

AC CHARACTERISTICS

Read-Only Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 15 for test specifications.

Parameter

Description Test Setup

Speed Options

JEDEC Std. 70 90 120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 ns

tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 70 90 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 40 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns

tAXQX tOH Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First Min 0 ns

tOEH Output Enable Hold T ime

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tOH

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tRH

tOE

tRH

0 V

RY/BY#

RESET#

tDF

Figure 13. Read Operation Timings

April 21, 2003 Am29DL32xG 37

ADVANCE INFORMATION

AC CHARACTERISTICS

Hardware Reset (RESET# )

Note: Not 100% tested.

Parameter

Description All Speed Options UnitJEDEC Std

tReady RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

tReady RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH Reset High Time Before Read (See Note) Min 50 ns

tRPD RESET# Low to Standby Mode Min 20 µs

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

Figure 14. Reset Timings

38 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter Speed Options

JEDEC Std Description 70 90 120 Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 16 ns

tFHQV BYTE# Switching High to Output Active Min 70 90 120 ns

DQ15

Output

Data Output

(DQ7–DQ0)

CE#

OE#

BYTE#

tELFL

DQ14–DQ0 Data Output

(DQ14–DQ0)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ7–DQ0)

BYTE#

tELFH

DQ14–DQ0 Data Output

(DQ14–DQ0)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

April 21, 2003 Am29DL32xG 39

ADVANCE INFORMATION

AC CHARACTERISTICS

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And P rogramming Perf ormance” section for more information.

Parameter Speed Options

JEDEC Std Description 70 90 120 Unit

tAVAV tWC Wr ite Cyc le Time (Note 1) Min 70 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tASO Addr ess Setup Time to OE# low during t oggle bit polling Min 15 15 ns

tWLAX tAH Address Hold Time Min 45 45 50 ns

tAHT Address Hold Time From CE# or OE# high

during toggle bit polling Min 0 ns

tDVWH tDS Data Setup Time Min 35 45 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOEPH Output Enable High during toggle bit polling Min 20 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Wr ite Puls e Wid th Min 30 35 50 ns

tWHDL tWPH Write Pulse Width High Min 30 ns

tSR/W Latency Between Read and Write Operations Min 0 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs

Word Typ 7

tWHWH1 tWHWH1 Accelerat ed Progra mmin g Oper ati on,

Word or Byte (Note 2) Typ 4 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Wr ite Reco ve ry Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

40 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

RY/BY#

tBUSY

otes:

. PA = program address, PD = program data, DOUT is the true data at the program address.

. I llustration shows device in word mode.

Figure 17. Program Operation Timings

WP#/ACC tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Figure 18. Accelerated Program Timing Diagram

April 21, 2003 Am29DL32xG 41

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

42 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Data Valid

In Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

Figure 20. Back-to-back Read/Write Cycle Timings

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycl e.

Figure 21. Data# Polling Timings (During Embedded Algorithms)

April 21, 2003 Am29DL32xG 43

ADVANCE INFORMATION

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status Valid

Status

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycl e, and array data read cycl e

Figure 22. Toggle Bit Timings (During Embedde d Algorithms)

Note: DQ2 tog gles on ly when read at an address w ithin an eras e-suspen ded sector . Th e system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 23. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

44 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time (See Note) Min 500 ns

tVHH VHH Rise and Fall Time (See Note) Min 250 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

tRRB RESET# Hold Time from RY/BY# High for

Temporary Sec tor Un prot ect Min 4 µs

RESET#

tVIDR

VID

VSS, VIL,

or VIH

VID

VSS, VIL,

or VIH

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

tRRB

Figure 24. Temporary Sector Unprotect Timing Diagram

April 21, 2003 Am29DL32xG 45

ADVANCE INFORMATION

AC CHARACTERISTICS

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector/Sector Block Protect or Unprotect Verify

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

46 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And P rogramming Perf ormance” section for more information.

Parameter Speed Options

JEDEC Std Description 70 90 120 Unit

tAVAV tWC Write Cycle Time (Not e 1) Min 70 90 120 ns

tAVWL tAS A ddress Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 50 ns

tDVEH tDS Data Setup Time Min 35 45 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 30 35 50 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation

(Note 2) Byte Typ 5 µs

Word Typ 7

tWHWH1 tWHWH1 Accelerated Programming Operation,

Word or Byte (Note 2) Typ 4 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

April 21, 2003 Am29DL32xG 47

ADVANCE INFORMATION

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

48 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,00 0,0 00 cy cl es. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for regulated devices), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

13 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Note: Inclu des all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP PIN AND FINE-PITCH BGA CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditio ns TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.4 5 sec Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 28 sec

Byte Program Time 5 150 µs

Excl ude s sy stem level

overhead (Note 5)

Accelerated Byte/Word Program Time 4 120 µs

Word Program Time 7 210 µs

Chip P rogram Time

(Note 3) Byte Mode 21 63 sec

W ord Mo de 14 42

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE#, and RESET#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capa cit anc e VIN = 0 TSOP 6 7.5 pF

Fine-pitch BGA 4.2 5.0 pF

COUT Output Capacitance VOUT = 0 TSOP 8.5 12 pF

Fine-pitch BGA 5.4 6.5 pF

CIN2 Control Pin Capa cit anc e VIN = 0 TSOP 7.5 9 pF

Fine-pitch BGA 3.9 4.7 pF

Parameter Description Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C10Years

125°C20Years

April 21, 2003 Am29DL32xG 49

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm

Dwg rev AF; 10/99

50 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm

Dwg rev AG; 7/2000

FBD!048

6.00!mm!x!12.00!mm

PACKAGE

1.20

0.20

0.84 0.94

12.00!BSC

6.00!BSC

5.60!BSC

4.00!BSC

0.25 0.30 0.35

0.80!BSC

0.40!BSC

April 21, 2003 Am29DL32xG 51

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

TS 048—Thin Small Outline Package

Dwg rev AA; 10/99

52 Am29DL32xG April 21, 2003

ADVANCE INFORMATION

PHYSICAL DIMENSIONS

LAA064—64-ball Fortified Ball Grid Array (FBGA)

11 x 13 mm package

April 21, 2003 Am29DL32xG 53

ADVANCE INFORMATION

REVISION SUMMARY

Revision A (November 7, 2001)

Global

Initial release. This device replaces the AM29DL32xD.

Revision B (July 31, 2002)

Global

Added LAA064 package.

Ordering Information

Corrected pac ka ge mar k ing for FBGA.

AC Characteristics

Added 7 0 ns speed grad e to Te st Speci fications and

Read-Only Oper ations

Revision B + 1 (August 27, 2002)

Distinctive Characteristics

Changed write cycles guaranteed per sector to erase

cycles guaranteed per sector.

Connection Diagrams, Special Handling

Instructions for FBGA Package

Changed text to reflect revised handling instructions.

Ordering Information

Added 120 ns to Valid Combinations for TSOP Pack -

ages.

Table 7, Autoselect Codes, (High Voltage Method)

Changed SecSiTM Indicator Bit (DQ7 to DQ0) from

81h to 82h (factory locked); 01h to 02h (not factory

locked).

Sector/Sector Block Protection and Unprotec tion

Removed paragraph referring to programming equip-

ment.

Common Flash Memory Interface (CFI)

Corrected thir d paragraph text to indicate that res et

command will return device to reading array data.

Changed CFI URL to current link.

Command Definitions

Corrected first paragraph text regarding incorrect ad-

dress and data values.

Table 14, Command Definitions

Changed Sector/Sector Block Protect V erify fourth bus

cycle from 81/01 to 82/02.

DC Characterist ics, CMOS Compatible

Removed IACC from table.

AC Characteristics, Alternate CE# Controlled

Erase and Program Operations

Change tBHEL from 0b to 0.

TSOP and SO Pi n Capacitance

Added Fine-Pitch BGA capacitance to table.

Revision B + 2 (November 6, 2002)

Global

Removed 6 0 ns sp eed opti on and re ferenc es to 80 ns

speed option.

Removed reverse 48-pin TSOP package option.

Connection Diagrams, 64-Ball Fortified BGA

Changed RFU to NC.

Package Capacitance

Removed references to SO package.

Revision B + 3 (April 21, 2003)

Connection Diagrams

Upda t ed 64 - B al l Fo rt if i ed FBA ( 11 x 13 mm); ch an g ed

C5 from A21 to NC.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advan ced Micro Devices , Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.