
2002 May 28 13
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7.12 L3 interface
The UDA1345TS has a microcontroller input mode. In the
microcontroller mode, all of the digital sound process i ng
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:
•System clock frequency
•Data input format
•Power control
•DC filtering
•De-emphasis
•Volume
•Mute.
The exchange of data and control information between the
microcontroller and the UDA1345TS is accomplished
through a serial hardware interface comprising the
following pins:
•L3DATA: microcontroller interface data line
•L3MODE: microcontroller interface mode line
•L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is LSB first,
and is organized in accordance with the so called ‘L3’
format, in which two different modes of operation can b e
distinguished; address mode and data transfer mode
(see Figs 4 and 5).
The address mode is required to select a device
communicatin g via the L3-bus and to define the
destination register set for the data transfe r mode. Data
transfer for the UDA134 5TS can only be in one direction:
for the UDA134 5TS, data can only be written to the device.
Important: since the UDA1345TS does not have a
Power-up reset circuit, after power up the L3 interface
registers MUST be initialized.
7.12.1 ADDRESS MODE
The address mode is used to selec t a device for
subsequent data transf er and to define the destination
register set (DATA or STATUS) . The ad dr ess mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 data bits.
The fundamental timing is shown in Fig.4. Data
bits 0 a nd 1 indicate the type of subsequen t data transfer
as given in Table 12.
Table 12 Selection of data transfer
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The addr ess of the
UDA1345TS is 000101 (bit 7 to bit 2). In the event that the
UDA1345TS receiv es a different address, it will d eselect
its microcontroller interface logic.
7.12.2 DATA TRANSFER MODE
The selection prefo rmed in the address mode remains
active during subsequent data transfers, until the
UDA1345TS rece ives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4. The
maximum input cloc k and data rate is 128fs. All transfers
are byte wise, i.e. they are based on groups of 8 bits. Data
will be stored in the UDA1345TS after the eighth bit of a
byte has been received. A multibyte transfer is illustrated
in Fig.6.
7.12.2.1 Programming the sound processing and other
features
The feature values are stored in independent registers.
The first selection of the registers is achieved by the choice
of data type that is transferred, being DATA or STATUS.
This is performed in the address mode, bit 1 and bit 0
(see Table 12). The second selection is performed by the
2 MSBs of the data byte (bi t 7 and bit 6). The other b its in
the data byte (bit 5 to bit 0) are the values that are placed
in the selected registers.
When the data transfer of type DATA is select ed, the
features Volume, De-emphasis, Mute and Power con tr ol
can be controlled. When the data transfer of type STATUS
is selected, the featu res system clock frequency, data
input format and DC filter can be controlled.
BIT 1 BIT 0 TRANSFER
0 0 DATA (volume, de-emphasis, mute,
and power contr o l)
0 1 not used
1 0 STATUS (system clock frequenc y , dat a
input format and DC filter)
1 1 not used