1©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
General Description
The 843441 is a low jitter, high performance clock generator. The
843441 is designed for use in applications using the SAS and SATA
interconnect. The 843441 uses an external, 25MHz, parallel
resonant crystal to generate four selectable output frequencies:
75MHz, 100MHz, 150MHz, and 300MHz. This silicon based
approach provides excellent frequency stability and reliability. The
843441 features down and center spread spectrum (SSC) clocking
techniques.
Additional Ordering Information
Features
•Designed for use in SAS, SAS-2, and SATA systems
•Center (±0.33%) Spread Spectrum Clocking (SSC)
•Down (-0.30% or -0.60%) SSC
•Better frequency stability than SAW oscillators
•One differential 3.3V LVPECL output
•Crystal oscillator interface designed for 25MHz
(CL = 18pF) frequency
•External fundamental crystal frequency ensures high reliability
and low aging
•Selectable output frequencies: 75MHz, 100MHz, 150MHz,
300MHz
•Output frequency is tunable with external capacitors
•RMS phase jitter: 1.33ps (typical)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Industrial temperature available upon request
•Available in lead-free (RoHS 6) package
•843441-150 Functional replacement part use 8T49N242i
Part/Order Number Package Output Frequency
(MHz)
843441AG 16 TSSOP 75, 100, 150, 300
843441AM-75 8 SOIC 75
843441AM-100 8 SOIC 100
843441AM-150 8 SOIC 150
843441AM-300 8 SOIC 300
Block Diagrams
FemtoClock
PLL
OSC
nPLL_SEL
1
0
25MHz
XTAL
XTAL_IN
XTAL_OUT
00 = 7 5MHz
01 = 100 MHz
10 = 150MHz (default)
11 = 300MHz
Q
nQ
SSC_SEL(1:0)
F_SEL(1:0)
SSC Output
Control Logic 16- Lead TSSOP
FemtoClock
PLL
OSC
25MHz
XTAL
XTAL_IN
XTAL_OUT
Q
nQ
SSC_SEL(1:0) SSC Output
Control Logic 8-Lead SOIC
Pulldown
Pullup:Pulldown
Pulldown:Pulldown
Pulldown:Pulldown
Pin Assignments
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
SSC_SEL0
XTAL_IN
XTAL_OUT
VEE F_SEL1
nPLL_SEL
nQ
Q
VCC
F_SEL0
V
CC
SSC_SEL1
VEE
nc
nc
843441
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
843441
8-Lead SOIC, 150 Mil
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
843441-150 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
843441
Data Sheet
FemtoClock® SAS/SATA Clock
Generator
2©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Table 1A. Pin Descriptions (SOIC Package)
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 1B. Pin Descriptions (TSSOP Package)
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1,
2
XTAL_OUT,
XTAL_IN Input Pullup Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
3,
4
SSC_SEL0,
SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
5V
CC Power Power supply pin.
6, 7 Q, nQ Output Differential clock outputs. LVPECL interface levels.
8V
EE Power Negative supply pin.
Number Name Type Description
1, 15 VEE Power Negative supply pins.
2,
3
XTAL_OUT,
XTAL_IN Input Pullup Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
4,
8
SSC_SEL0,
SSC_SEL1 Input Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
5, 6, 7 nc Unused No connect pins.
9, 11 VCC Power Power supply pins.
10 F_SEL0 Input Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
12, 13 Q, nQ Output Differential clock outputs. LVPECL interface levels.
14 nPLL_SEL Input Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels.
16 F_SEL1 Input Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4pF
RPULLDOWN Input Pulldown Resistor 51 k
RPULLUP Input Pullup Resistor 51 k
3©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Table 3B. F_SEL[1:0] Function Table
Table 3B applicable only for 16 Lead TSSOP package.
Inputs
ModeSSC_SEL1 SSC_SEL0
0 (default) 0 (default) SSC Off
0 1 0.60% Down-spread
1 0 0.30% Down-spread
1 1 0.33% Center-spread
Inputs
Output Frequency (MHz)F_SEL1 F_SEL0
00 75
01 100
1 (default) 0 (default) 150
11 300
4©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE 1: Output termination with 50 to VCC – 2V.
Item Rating
Supply Voltage, VCC 4.6V
Inputs, VI, (LVCMOS)
XTAL_IN
Other Inputs
0V to VCC
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
16 Lead TSSOP
8 Lead SOIC
81.2°C/W (0 mps)
96.0°C/W (0 lfpm)
Storage Temperature, TSTG -65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 66 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 0.8 V
IIH
Input
High Current
F_SEL1 VCC = VIN = 3.465V 5 µA
SSC_SEL[0:1],
F_SEL0, nPLL_SEL VCC = VIN = 3.465V 150 µA
IIL
Input
Low Current
F_SEL1 VCC = 3.465V, VIN = 0V -150 µA
SSC_SEL[0:1],
F_SEL0, nPLL_SEL VCC = 3.465V, VIN = 0V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V
VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V
VSWING Peak-to-Peak Output Voltage Swing 0.6 0.9 V
5©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C
NOTE: Using a 25MHz, 18pF quartz crystal.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise plots.
NOTE 2: Refer to Application Section for peak-to-peak jitter calculations.
NOTE 3: Tested per JEDEC 65B.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency
F_SEL(1:0) = 00 75 MHz
F_SEL(1:0) = 01 100 MHz
F_SEL(1:0) = 10 150 MHz
F_SEL(1:0) = 11 300 MHz
tjit(Ø) RMS Phase Jitter
(Random); NOTE 1
75MHz,
Integration Range: 12kHz – 20 MHz 1.33 ps
100MHz,
Integration Range: 12kHz – 20MHz 1.39 ps
150MHz,
Integration Range: 12kHz – 20MHz 1.36 ps
300MHz,
Integration Range: 12kHz – 20MHz 1.37 ps
tjit(per) Period Jitter, RMS;
NOTE 2, 3
75MHz, SSC Off 4.15 ps
100MHz, SSC Off 4.05 ps
150MHz, SSC Off 4.15 ps
300MHz, SSC Off 4.25 ps
tjit(cc) Cycle-to-Cycle Jitter:
NOTE 3
75MHz, SSC Off 31 ps
100MHz, SSC Off 31 ps
150MHz, SSC Off 31 ps
300MHz, SSC Off 31 ps
tR / tFOutput Rise/Fall Time 20% to 80% 200 700 ps
odc Output Duty Cycle 45 55 %
6©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Typical Phase Noise at 100MHz
NOTE: Measured on Aeroflex PN9000
Noise Power dBc
Hz
Offset Frequency (Hz)
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.39ps (typical)
7©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
Output Rise/Fall Time
Cycle-to-Cycle Jitter
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
RMS Period Jitter, Peak-to-Peak
SCOPE
Qx
nQx
VEE
VCC
2V
-1.3V ± 0.165V
nQ
Q
tcycle n tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
nQ
Q
nQ
Q
VOH
VREF
VOL
Mean Period
(First edge after trigger)
10,000 cycles
Reference Point
(Trigger Edge)
Histogram
t jit (pk-pk)
8©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have int ernal pullu ps an d pul ldown s; a dditi onal
resistance is not required but can be added for additional protection.
A 1k resistor can be us ed.
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC XTAL_OUT
XTAL_IN
R1
100
R2
100
Z o = 50 ohmsRs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTAL_OUT
XTAL_IN
Z o = 50 ohms C2
.1uf
LV P ECL Driver
Z o = 50 ohms
R1
50 R2
50
R3
50
9©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
Termination for 3.3V LVPECL Outputs
The clock layout t opology sh own below is a typical ter minatio n for
LVPECL outpu ts. T he t wo di ffere nt lay outs menti oned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination
10©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Schematic Example
Figure 3 shows an exa mple of 8434 41 a pplic atio n sch emati c. In this
example, the dev ice is oper ated at V CC = 3.3V. An 18pF para llel
resonant 25 MHz cr ystal is used. The load capaci tance C1 = 27p F
and C2 = 27pF are recomm ended for frequency accuracy.
Depending on the parasitics of the printed circuit board layout, these
values might req uire a slig ht adjust ment to opti mize the frequ ency
accuracy. Crystals with other load capacitance specifications can be
used. This will required adjusting C1 and C2.
As with any high spe ed analog ci rcuitry , the power su pply pins are
vulnerable to random nois e. To achiev e optimum ji tter perf ormance,
power suppl y iso lati on is requ ired . The 8434 41 prov ides sepa rate
power supplies to isolate noise from co upling in to the inte rnal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply fil ter recomme ndation s ar e a g enera l gu ideli ne t o be
used for re du cin g ex ter na l noi se f ro m c oup li ng i nto t he d ev ice s. The
filter perf orman ce i s des igned for wide r ange of n oise frequ enci es.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise c omponent is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required , additi onal filt ering be ad ded.
Additionall y, g ood g enera l de sign pract ices f or po wer p lane volt age
stability suggests adding bulk capacitances in the local area of all
devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 3. 843441 Schematic Example
Optional
Y-Termination
S et Logic
Input to
'1'
C5
10uF
C2
27pF
R6
50
Z o = 50 Ohm
Logi c Control Input Exam ples
+
-
SSC_SEL1
U1
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
VEE
XTAL_OUT
XTAL_IN
SSC_SEL0
nc
nc
nc
SSC_SEL1 VCC
F_SEL0
VCC
Q
nQ
nPLL_SEL
VEE
F_SEL1
XTAL_IN
BLM18BB221SN1
F errit e Bead
1 2
RU1
1K
3.3V
XTAL_OUT
VCC
LV PECL Term inat ion
F_SEL0
RD2
1K
nPLL_SEL R2
133
Q
C3
0.1uF
To Lo gic
Input
pins
SSC_SEL0
R5
50
nQ
C1
27pF
R4
82.5
F_SEL1
RD1
Not Install R7
50
R3
82.5
RU2
Not Install
+
-
S et Logi c
Input to
'0'
C4
0.1uF
18pF
VCC
Z o = 50 Ohm
3.3V
R1
133
X1
25MHz
To Logic
Input
pins
C6
0.1uF
Z o = 50 Ohm
Z o = 50 Ohm
VCC
11©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Peak-to-Peak Jitter Calculations
A standard dev iation of a sta tistica l populat ion or data set is the
square root of its va ri anc e. A standar d dev ia ti on is used to cal cu la te
the probability of an anomaly or to predict a failure. Many times, the
term "root mean s quare " (RM S) is used syno nymou sly f or s tanda rd
deviation. Thi s is accurat e when refe rring to th e square roo t of the
mean squared devi ation of a si gnal from a gi ven baseli ne and the
data set co ntain s a Gaussi an d istri bution with no deter minis tic
components. A low standard de viation indicate s that the da ta set
tends to be clos e to the mean with littl e var iatio n. A larg e stan dard
deviation indi cates tha t the data set is spread out and has a lar ge
variation f rom t he me an.
A standa rd devia tion is r equired when calculat ing peak -to-peak jitter.
Since true peak- to-pe ak ji tter is rando m and unbo unded , it is
importan t to always associate a bit erro r ratio ( BER) when sp ecifyin g
a peak-to-peak jitter lim it. Withou t it, the sp ecifica tion is
meaningless. Given that a BER is applica tion specifi c, many
frequency timi ng devices specify ji tter as an RMS. T his allows the
peak-to-peak jitter to be calculat ed for the sp ecific appli cation an d
BER requ iremen t. B ecause a sta ndard dev iatio n is the variat ion
from the m ean of t he da ta se t, i t i s imp ort an t to al way s c al cul ate the
peak-to-peak jitter using the typical RMS value.
The table s hows the B ER wi th it s ap propr iate RMS Mu ltipli er. O nce
the BER is chosen, t he peak to pea k jitter ca n be calcula ted by
simply multiplying the RMS multiplier with the typical RMS datasheet
specification. For example, if a 10-12 BER is required, multi ply
14.260 time s the typ ical jitt er s pecif ication .
Jitter (pea k-to- peak) = R MS Mul tipli er x RMS ( typic al)
This calculati on is not spe cific to on e type of Jit ter classi ficati on. It
can be used to calcu late BE R on vario us t ypes of RMS j itte r. I t is
important that the user understands their jitter requirement to ensure
they are ca lcula ting the corr ect B ER fo r their jit ter requi remen t.
BER RMS Multiplier
10-3 6.582
10-4 7.782
10-5 8.834
10-6 9.784
10-7 10.654
10-8 11.462
10-9 12.218
10-10 12.934
10-11 13.614
10-12 14.260
10-13 14.882
10-14 15.478
10-15 16.028
12©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 843441.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843441 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 66mA = 228.69mW
• Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 228.69mW + 30mW = 258.69mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 96°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.259W * 96°C/W = 94.864°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
Table 6B. Thermal Resistance JA for 8 Lead SOIC, Forced Convection
JA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W
JA vs. Air Flow
Linear Feet per Second 0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
13©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 4.
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
VOUT
VCC
VCC - 2V
Q1
RL
50Ω
14©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Reliability Information
Table 7A. JA vs. Air Flow Table for a 16 Lead TSSOP
Table 7B. JA vs. Air Flow Table for a 8 Lead SOIC
Transistor Count
The transistor count for 843441 is: 6303
JA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 81.2°C/W 73.9°C/W 70.2°C/W
JA vs. Air Flow
Linear Feet per Second 0200500
Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 87°C/W 82°C/W
15©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Table 8A. Package Dimensions for 16 Lead TSSOP
Reference Document: JEDEC Publication 95, MO-153
Package Outline - M Suffix for 8 Lead SOIC
Table 8B. Package Dimensions for 8 Lead SOIC
Reference Document: JEDEC Publication 95, MS-012
All Dimensions in Millimeters
Symbol Minimum Maximum
N16
A1.20
A1 0.05 0.15
A2 0.80 1.05
b0.19 0.30
c0.09 0.20
D4.90 5.10
E6.40 Basic
E1 4.30 4.50
e0.65 Basic
L0.45 0.75
0° 8°
aaa 0.10
All Dimensions in Millimeters
Symbol Minimum Maximum
N8
A1.35 1.75
A1 0.10 0.25
B0.33 0.51
C0.19 0.25
D4.80 5.00
E3.80 4.00
e1.27 Basic
H5.80 6.20
h0.25 0.50
L0.40 1.27
0° 8°
16©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number Marking Package Shipping Packaging Temperature
843441AGLF 843441AL 16 Lead “Lead-Free” TSSOP Tube 0C to 70C
843441AGLFT 843441AL 16 Lead “Lead-Free” TSSOP Tape & Reel 0C to 70C
843441AM-75LF 3441A75L 8 Lead “Lead-Free” SOIC Tube 0C to 70C
843441AM-75LFT 3441A75L 8 Lead “Lead-Free” SOIC Tape & Reel 0C to 70C
843441AM-100LF 441A100L 8 Lead “Lead-Free” SOIC Tube 0C to 70C
843441AM-100LFT 441A100L 8 Lead “Lead-Free” SOIC Tape & Reel 0C to 70C
843441AM-150LF 441A150L 8 Lead “Lead-Free” SOIC Tube 0C to 70C
843441AM-150LFT 441A150L 8 Lead “Lead-Free” SOIC Tape & Reel 0C to 70C
843441AM-300LF 441A300L 8 Lead “Lead-Free” SOIC Tube 0C to 70C
843441AM-300LFT 441A300L 8 Lead “Lead-Free” SOIC Tape & Reel 0C to 70C
17©2016 Integra ted Device Technolo gy, Inc June 30, 2 016
843441 Data Sheet
Revision History Sheet
Rev Table Page Description of Change Date
A T3A 3 SSC_SEL Function Table - updated Mode column. 5/18/11
A
T9 16 Ordering Information - Removed quantity in tape and reel. Deleted LF note below table.
Removed ICS from part number where needed.
Product Discontinuation Notice - Last time buy expires May 6, 2017.
PDN CQ-16-01
Updated header and footer
6/30/16
DISCLAIMER Integrated Device Technology , Inc. (IDT) res erves the right to modify the products and/or s pecifications des cribed herein at any time, with out notice, at IDT's sole discretion. Perfor mance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
Tech Support
www.idt.com/go/support
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
843441 Data Sheet
18©2016 Integra ted Device Technolo gy, Inc June 30, 2 016