K6L1016V3B, K6L1016U3B Family CMOS SRAM Document Title 64K x16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Design target July 24, 1995 Advance 0.1 Initial draft August 12, 1995 Preliminary 1.0 Finalize April 13, 1996 - One datasheet for commercial and industrial part and 3.0, 3.3V product. Final 2.0 Revised - Change datasheet format. - Remove Icc write current value. - Remove low power product from TSOP package - Remove 100ns part from KM616V1000B Family - Remove Extended product Errata correction Final 2.01 February 25, 1998 August 13, 1998 The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM 64K x16 bit Low Power and Low Voltage CMOS Static RAM FEATURES GENERAL DESCRIPTION * Process Technology: Poly Load * Organization: 64K x16 * Data Byte Control: LB=I/O1~8, UB=I/O9~16 * Power Supply Voltage: K6L1016V3B family: 3.0~3.6V K6L1016U3B family: 2.7~3.3V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type :44-TSOP2-400F/R The K6L1016V3B and K6L1016U3B families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and have small package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed Standby Operating (Icc2, Max) (ISB1, Max) K6L1016V3B-B K6L1016U3B-B Commercial(0~70C) 3.0~3.6V 2.7~3.3V 70 1)ns 100ns 15A 15A Industrial(-40~85C) 3.0~3.6V 2.7~3.3V 1) 20A 20A K6L1016V3B-F K6L1016U3B-F 85 ns 100ns 65mA PKG Type 44-TSOP2 Forward/Reverse 1. The parameter is measured with 30pF test load. PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 FUNCTIONAL BLOCK DIAGRAM A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 N.C A8 A9 A10 A11 N.C A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 N.C A8 A9 A10 A11 N.C 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-TSOP2 Reverse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 N.C Clk gen. Precharge circuit. A0 Vcc Vss A1 A2 A3 A4 Row select A5 Memory array 1024 rows 64x16 columns A6 A7 A8 A15 I/O1~I/O8 I/O 9~I/O16 Data cont I/O Circuit Column select Data cont Data cont Name Function Name Function CS Chip Select Input Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input I/O1~16 Data Inputs/Outputs LB Lower Byte (I/O1~8) A0~A15 Address Inputs UB Upper Byte(I/O9~16) A9 A10 A11 A12 A13 A14 WE OE N.C UB Control logic LB No Connection CS SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM PRODUCT LIST Commercial Temperature Products(0~70C) Part Name Industrial Temperature Products(-40~85C) Function Part Name Function K6L1016V3B-TB70 44-TSOP-2F, 3.3V, 70ns, LL K6L1016V3B-TF85 44-TSOP-2F, 3.3V, 85ns, LL K6L1016U3B-TB10 44-TSOP-2F, 3.0V, 100ns, LL K6L1016U3B-TF10 44-TSOP-2F, 3.0V, 100ns, LL K6L1016V3B-RB70 44-TSOP-2R, 3.3V, 70ns, LL K6L1016V3B-RF85 44-TSOP-2R, 3.3V, 85ns, LL K6L1016U3B-RB10 44-TSOP-2R, 3.0V, 100ns, LL K6L1016U3B-RF10 44-TSOP-2R, 3.0V, 100ns, LL FUNCTIONAL DESCRIPTION CS OE H X L H WE 1) LB UB I/O1~8 I/O9~16 1) 1) Mode Power X X X High-Z High-Z Deselected Standby H X1) X1) High-Z High-Z Output Disabled Active 1) L X X H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active X 1) L L H Din High-Z Lower Byte Write Active L X 1) L H L High-Z Din Upper Byte Write Active L X1) L L L Din Din Word Write Active L 1) 1) 1. X means dont care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol Ratings Unit Remark VIN,VOUT -0.5 to Vcc+0.5 V - VCC -0.5 to 4.6 V - PD 1.0 W - TSTG -65 to 150 C - 0 to 70 C K6L1016V3B-B K6L1016U3B-B -40 to 85 C K6L1016V3B-F K6L1016U3B-F 260C, 10sec (Lead Only) - - TA TSOLDER 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Product Min Typ Max Unit Supply voltage Vcc K6L1016V3B Family K6L1016U3B Family 3.0 2.7 3.3 3.0 3.6 3.3 V Ground Vss All Family 0 0 0 Input high voltage VIH K6L1016V3B, K6L1016U3B Family 2.2 - Input low voltage VIL K6L1016V3B, K6L1016U3B Family -0.3 VCC+0.3 - 3) V V 2) 0.4 V Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : V CC+3.0V in case of pulse width 30ns 3. Undershoot : -3.0V in case of pulse width 30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1) (f=1MHz, TA=25C) Symbol Test Condition Min Max Unit Input capacitance Item CIN VIN=0V - 6 pF Input/Output capacitance CIO VIO=0V - 8 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Min Typ Max Unit ILI VIN=VSS to VCC -1 - 1 A Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=VSS to VCC -1 - 1 A Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 10 mA ICC11) Cycle time=1s, 100% duty, I IO=0mA CS0.2V, VIN0.2V or VINVcc-0.2V Read - - 15 Write - - 40 Input leakage current Average operating current Symbol Test Conditions mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL , VIN=VIL or VIH - - 65 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.2 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 0.5 mA Standby current(CMOS) ISB1 CSVCC-0.2V, Other inputs=0VCC - - 152) A 1. Industrial Product : ICC1(Read/Write)=20mA/45mA 2. Industrial Product=20A 4 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CL=30pF+1TTL CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (K6L1016V3B-C Family : Vcc=3.0~3.6V, K6L1016U3B-I Family : Vcc=2.7~3.3V Commercial product : TA=0 to70C, Industrial product :TA=-40 to 85C) Speed Bins Parameter List Symbol Units 100ns Min Max Min Max Min Max 70 - 85 - 100 - ns Address access time tAA - 70 - 85 - 100 ns Chip select to output tCO - 70 - 85 - 100 ns Output enable to valid output tOE - 35 - 40 - 50 ns UB,LB Access Time tBA - 35 - 40 - 50 ns Chip select to low-Z output tLZ 10 - 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - 5 - ns UB,LB enable to low-Z output tBLZ 5 - 5 - 5 - ns Chip disable to high-Z output Write 85ns tRC Read cycle time Read 70ns tHZ 0 25 0 25 0 30 ns Output disable to high-Z output tOHZ 0 25 0 25 0 30 ns UB,LB disable to high-Z output tBHZ 0 25 0 25 0 30 ns Output hold from address change tOH 10 - 10 - 15 - ns Write cycle time tWC 70 - 85 - 100 - ns Chip select to end of write tCW 60 - 70 - 80 - ns Address set-up time tAS 0 - 0 - 0 - ns Address valid to end of write tAW 60 - 70 - 80 - ns Write pulse width tWP 50 - 60 - 70 - ns UB, LB valid to end of write tBW 60 - 70 - 80 - ns Write recovery time tWR 0 - 0 - 0 - ns Write to output high-Z tWHZ 0 30 0 30 0 35 ns Data to write time overlap tDW 30 - 35 - 40 - ns Data hold from write time tDH 0 - 0 - 0 - ns End write to output low-Z tOW 5 - 5 - 5 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition VCC for data retention VDR CSVcc-0.2V VCC=3.0V, CSVcc-0.2V Data retention current IDR Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 2.0 - 3.6 V 1) - - 15 0 - - 5 - - A ms 1. Industrial product=20A 5 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out High-Z tOHZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 3.0/2.7V1) 2.2V VDR CSVCC - 0.2V CS GND 1. 3.0V for K6L1016V3B family, 2.7V K6L1016U3B family 8 Revision 2.01 February 1998 K6L1016V3B, K6L1016U3B Family CMOS SRAM PACKAGE DIMENSIONS Unit: millimeter(inch) 0~8 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) #44 ( 0.25 ) 0.010 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 ( 0.50 ) 0.020 #1 #22 1.000.10 0.0390.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 0. 0.10 0.004 MAX 0.05 MIN. 0.002 18.81 MAX. 0.741 18.410.10 0.7250.004 0 + 0.1 5 - 0.0 04 + 0.0 02 .0 006 - 0 0.15 0~8 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) ( #1 0.25 ) 0.010 #22 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 ( 0.50 ) 0.020 #44 #23 1.000.10 0.0390.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.05 MIN. 0.002 18.81 MAX. 0.741 18.410.10 0.7250.004 0.80 0.0315 9 0 + 0.1 5 - 0.0 04 + 0 .0 02 .006 - 0.0 0.15 0 0.10 MAX 0.004 Revision 2.01 February 1998