2-109
Product Description
Ordering In formation
Typical Applications
Features
Functional Block Diagram
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
Optimum Technology Matching® Applied
Si BJT GaAs MESFETGaAs HBT
Si Bi-CMOS SiGe HBT Si CMOS
InGaP/HBT GaN HEMT SiGe Bi-CMOS
BIAS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
NC
RF IN
GND
GND
GND
GND
PC
GND
RF OU
T
RF OU
T
GND
GND
RF OU
T
RF OU
T
GND
RF2132
LINEAR POWER AMPLIFIER
• 4.8V AMPS Cellular Handsets
• 4.8V CDMA/AMPS Handsets
• 4.8V JCDMA/TACS Handsets
• Dri ver Amplifier in Cellular Base Stations
• Porta ble Battery-Powered Equipment
The RF2132 is a hig h power, high efficien cy linear ampli-
fier IC. The device is manufact ured on an advanced Gal-
lium Arsenide Heterojunction Bipolar Transistor (HBT)
process, and has been designed for use as the final RF
amplifier in dual-mode 4-cell CDMA/AMPS handheld digi-
tal cellular equipment, spread-spectrum systems, and
other applications in the 800 MHz to 950 MHz band. The
device is self-contained with 50Ω input and the output
can be easily matched to obtain optimum power, effi-
ciency, and linearity characteristics over varying supply
and control voltages.
• Single 4.2V to 5.0V Supply
• Up to 29 dBm Linear Output Power
• 29dB Gain With Analog Gain Control
• 45% Linear Efficiency
• On-board Power Down Mode
• 800MHz to 950MHz Operation
RF2132 Linear Power Amplifier
RF2132PCBA-41X Fully Assembled Evaluati on Board
0
Rev B10 060908
0.035
0.016 0.010
0.008
8° MAX
0° MIN
0.021
0.014
0.392
0.386
0.158
0.150
0.244
0.230
0.069
0.064 0.050
0.060
0.054
-A-
0.009
0.004
Package Style: Standard Batwing
9
RoHS Compliant & Pb-Free Product
2-110
RF2132
Rev B10 060908
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage (No RF) -0.5 to +8.0 VDC
Supply Voltage (POUT<32dBm) -0.5 to +5.0 VDC
Power Control Voltage (VPC) -0.5 to +5.0 or VCC V
DC Supply Current 800 mA
Input RF Power +12 dBm
Output Load VSWR 10:1
Storage Temperature -40 to +150 °C
Junction Temperature 200 °C
Parameter Specification Unit Condition
Min. Typ. Max.
Overall T=25°C, VCC=4.8V, VPC=4.0V,
Freq=824MHz to 849MHz
Usable Frequency Range 800 824 to 849 950 MHz
Linear Gain 27 29 31 dB
Total Linear Efficiency 40 45 %
Efficiency at Max Output 50 55 %
OFF Isolation 23 27 dB VPC=0V,PIN=+6dBm
Second Harmonic -30 dBc Including Second Harmonic Trap
Maximum Linear Output Power 28.5 29 IS-95A CDMA Modulation
Adjacent Channel Power Rejec-
tion @ 885 kHz -46 -44 dBc Pout = 28 dBm
ACPR can be improved by trad ing off effi-
ciency.
Adjacent Channel Power Rejec-
tion @ 1.98 MHz -58 -56 dBc Pout = 28 dBm
Maximum CW Output Power 31.5 32 dBm
Operating Case Temperature -30 110 °C Pout = 31 dBm, Efficiency = 55%
Ambient Operating Temperature -30 100 °C
Junction to Case Thermal Resis-
tance 85 °C/W
Input VSWR <2:1
Output Load VSWR 10:1 No oscillations
Power Down
Turn On/Off Time 100 ns
Total Current 10 μA “OFF” State
VPC “OFF” Voltage 0.2 0.5 V
VPC “ON” Voltage 3.6 4.0 Vcc V
Power Supply
Power Supply Voltage 4.2 4.8 5.0 V Operating voltage
Idle Current 40 100 mA VPC=4.0V
Current into VPC pin1520mA“ON” State
Caution! ESD sensitive device.
RF Micro De v ices believes the furnished inf ormation is correc t and accu rate
at the time of th is printing. RoHS marking based on EUDirectiv e2002/95/EC
(at time of this printing). However, RF Mi cro Devi ces reserves the right to
make changes to its product s without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
2-111
RF2132
Rev B10 060908
Pin Function Description Interface Schematic
1VCC1
Power supply for the driver stage, and interstage matching. Shunt
inductance is required on this pin, which can be achieved by an induc-
tor to VCC, with a decoupling capacitor on the VCC side. The val ue of
the inductor is frequency dependent; 3.3nH is required for 830MHz,
and 1.2nH for 950MHz. Instead of an inductor, a high impedance
microstrip line can be used.
2NC
Not Connected.
3RF IN
RF input. This is a 50Ω input, but the actual input impedance depends
on the interstage matching network connected to pin 1. An external DC
blocking capacitor is required if this port is connected to a DC path to
ground or a DC voltage.
See pin 1.
4GND
Ground connection. Keep traces physically short and connect immedi-
ately to the ground plane for best performance.
5GND
Same as pin 4.
6GND
Ground for stage 1. Keep traces physically short and connect immedi-
ately to ground plane for best performance. This ground should be iso-
lated from the batwing and other ground contacts. See evaluation
board layout.
7GND
Same as pin 6.
8PC
Power Control. When this pin is "low", all circuits are shut off. A "low" is
typically 0.5V or less at room temperature. During normal operation
this pin is the power control. Control range varies from about 2V for
0dBm to VCC for +31dBm RF output power. The maximum power that
can be achieved depends on the actual output matching. PC should
never exceed 5.0V or VCC, whichever is the lowest.
9GND
Same as pin 4.
10 RF OUT RF Output and power supply for the output stage. The four output pins
are combined, and bias voltage for the final stage is provided through
these pins. The external path must be kept symmetric until combined to
ensure stability. An external matching network is required to provide the
optimum load impedance; see the application schematics for details.
11 RF OUT Same as pin 10. See pin 10.
12 GND Same as pin 4.
13 GND Same as pin 4.
14 RF OUT Same as pin 10. See pin 10.
15 RF OUT Same as pin 10. See pin 10.
16 GND Same as pin 4.
RF IN
VCC
From Bias
Stages
PC
To RF
Transistors
RF OUT
From Bias
Stages
2-112
RF2132
Rev B10 060908
Application Schematic
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BIAS
1.8 nH
100 pF
18 k
Ω
100 pF
RF IN
V
PC
1 nF
1 nF
100 pF
6.8 nH
3 pF
V
CC
12 pF
3.3 nH
4.3 pF
100 pF RF OU
T
Vcc = 4.8 V
Vpc = 4.0 V
BIAS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
L1
1.8 nH
C6
100 pF
R1
18 k
Ω
C14
100 pF
C13
1 nF
C12
3.3
μ
F
P1-3
C8
33 pF
J1
L3
3.3 nH
C11
4.3 pF
C9
100 pF J2
C7
3 pF
L2
6.8 nH
C4
1 nF
C1
100 nF C2
11
μ
FC3
1
μ
F
C10
12 pF
P1-1
C5
100 pF
RF IN
RF OUT
P1-1
P1-3
P1
PC
GND
VCC
1
2
3
Vcc = 4.8 V
Vpc = 4.0 V
Power supply filtering/bypassing for V
cc
Power supply filtering/bypassing for V
PC
Adds bias to the first
amplifier stage for
improved linearity
Bias inductor for the
amplifier output stage
Harmonic trap: C7 series resonat
e
internal bondwires of pins 14 and 1
2f
0
to effectively short out 2nd harm
for optimum gain and efficiency
Matching network for
optimum load impedance
Interstage tuning (L1) for
centering output frequency
2-113
RF2132
Rev B10 060908
Evaluation Board Layout
2” x 2”
2-114
RF2132
Rev B10 060908
RF2132 Evaluation Board
Vcc = 4. 8 V, Vpc = 4. 0 V, Frequency = 836 MHz, IS- 95A CDMA
0
10
20
30
40
50
60
70
80
90
28 26 24 22 20 18 16 14 12 10
Pout (dBm)
ACPR (-dBc), Efficiency (%
)
0
50
100
150
200
250
300
350
Current (mA)
A CP R 885 k Hz
A CP R 1.98 M Hz
Current
Total E ffici e n cy
