REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADG726/ADG732
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
16-/32-Channel, 4
+1.8 V to +5.5 V, 2.5 V Analog Multiplexers
FEATURES
1.8 V to 5.5 V Single Supply
2.5 V Dual-Supply Operation
4 On Resistance
0.5 On Resistance Flatness
48-Lead TQFP or 48-Lead 7 mm 7 mm CSP Packages
Rail-to-Rail Operation
30 ns Switching Times
Single 32-to-1 Channel Multiplexer
Dual/Differential 16-to-1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent Devices with Serial Interface
See ADG725/ADG731
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
Medical Instrumentation
Automatic Test Equipment
FUNCTIONAL BLOCK DIAGRAMS
ADG732
EN
S1
S32
WR
CS
A4A3A2A1A0
D
1-OF-32
DECODER
S1A
S16A
DA
ADG726
EN
WR
A3A2A1A0
S1B
S16B
DB
1-OF-16
DECODER
CSA
CSB
PRODUCT HIGHLIGHTS
1. +1.8 V to +5.5 V single- or ±2.5 V dual-supply operation.
These parts are specified and guaranteed with +5 V ± 10%,
+3 V ± 10% single-supply, and ±2.5 V ± 10% dual-
supply rails.
2. On resistance of 4 Ω
3. Guaranteed break-before-make switching action
4. 7 mm × 7 mm 48-lead chip scale package (CSP)
or 48-lead TQFP package
GENERAL DESCRIPTION
The ADG726/ADG732 are monolithic CMOS 32-channel/dual
16-channel analog multiplexers. The ADG732 switches one of
32 inputs (S1-S32) to a common output, D, as determined by
the 5-bit binary address lines A0, A1, A2, A3, and A4. The
ADG726 switches one of 16 inputs as determined by the 4-bit
binary address lines A0, A1, A2, and A3.
On-chip latches facilitate microprocessor interfacing. The
ADG726 device may also be configured for differential opera-
tion by tying CSA and CSB together. An EN input is used to
enable or disable the devices. When disabled, all channels are
switched OFF.
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high
switching speed, very low on resistance, and leakage currents.
They operate from a single supply of +1.8 V to +5.5 V and a ±2.5 V
dual supply, making them ideally suited to a variety of applications.
On resistance is in the region of a few ohms and is closely
matched between switches and very flat over the full signal
range. These parts can operate equally well as either multiplexers
or demultiplexers and have an input signal range that extends to
the supplies. In the OFF condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
They are available in either 48-lead CSP or TQFP packages.
REV. 0
–2–
ADG726/ADG732–SPECIFICATIONS
1
(VDD = 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
–40C
Parameter +25Cto +85CUnit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
)4 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA;
5.5 6 Ω max Test Circuit 1
On Resistance Match Between 0.3 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (∆R
ON
)0.8 Ω max
On Resistance Flatness (R
FLAT(ON)
)0.5 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
1Ω max
LEAKAGE CURRENTS V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
±0.25 ±1nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.05 nA typ V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
ADG726 ±0.5 ±2.5 nA max Test Circuit 3
ADG732 ±1±5nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.05 nA typ V
D
= V
S
= 1 V, or 4.5 V;
ADG726 ±0.5 ±2.5 nA max Test Circuit 4
ADG732 ±1±5nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.4 V min
Input Low Voltage, V
INL
0.8 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.5 µA max
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
23 ns typ R
L
= 300 Ω, C
L
= 35 pF, Test Circuit 5
34 40 ns max V
S1
= 3 V/0 V, V
S32
= 0 V/3 V
Break-Before-Make Time Delay, t
D
18 ns typ R
L
= 300 Ω, C
L
= 35 pF;
1ns min V
S
= 3 V; Test Circuit 6
t
ON
(CS, WR)18ns typ V
S
= 3 V; Test Circuit 7
25 32 ns max R
L
= 300 Ω, C
L
= 35 pF;
t
OFF
(CS, WR)17ns typ V
S
= 3 V; Test Circuit 7
23 29 ns max R
L
= 300 Ω, C
L
= 35 pF;
t
ON
(EN)24ns typ R
L
= 300 Ω, C
L
= 35 pF;
32 40 ns max V
S
= 3 V; Test Circuit 8
t
OFF
(EN)16ns typ R
L
= 300 Ω, C
L
= 35 pF;
22 25 ns max V
S
= 3 V; Test Circuit 8
Charge Injection 5 pC typ V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 9
OFF Isolation –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 10
Channel-to-Channel Crosstalk –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 11
–3 dB Bandwidth R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 12
ADG726 34 MHz typ
ADG732 18 MHz typ
C
S
(OFF) 13 pF typ f = 1 MHz
C
D
(OFF)
ADG726 170 pF typ f = 1 MHz
ADG732 340 pF typ f = 1 MHz
C
D
, C
S
(ON)
ADG726 175 pF typ f = 1 MHz
ADG732 350 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 5.5 V
I
DD
10 µA typ Digital Inputs = 0 V or 5.5 V
20 µA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
REV. 0 –3–
ADG726/ADG732
B Version
–40C
Parameter +25Cto +85CUnit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to V
DD
V
On Resistance (R
ON
)7 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA;
11 12 Ω max Test Circuit 1
On Resistance Match Between 0.35 Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (∆R
ON
)1Ω max
On Resistance Flatness (R
FLAT(ON)
)3Ω typ V
S
= 0 V to V
DD
, I
DS
= 10 mA
LEAKAGE CURRENTS V
DD
= 3.3 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= 3 V/1 V, V
D
= 1 V/3 V;
±0.25 ±1nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.05 nA max V
S
= 1 V/3 V, V
D
= 3 V/1 V;
ADG726 ±0.5 ±2.5 nA max Test Circuit 3
ADG732 ±1±5nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.05 nA typ V
S
= V
D
= 1 V or 3 V;
ADG726 ±0.5 ±2.5 nA max Test Circuit 4
ADG732 ±1±5nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0 V min
Input Low Voltage, V
INL
0.7 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.5 µA max
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
34 ns typ R
L
= 300 Ω, C
L
= 35 pF; Test Circuit 5
52 62 ns max V
S1
= 2 V/0 V, V
S32
= 0 V/2 V
Break-Before-Make Time Delay, t
D
26 ns typ R
L
= 300 Ω, C
L
= 35 pF;
1ns min V
S
= 2 V; Test Circuit 6
t
ON
(WR, CS)29ns typ V
S
= 2 V; Test Circuit 7
43 52 ns max R
L
= 300 Ω, C
L
= 35 pF;
t
OFF
(WR, CS)26ns typ V
S
= 2 V; Test Circuit 7
38 42 ns max R
L
= 300 Ω, C
L
= 35 pF;
t
ON
(EN, WR)33ns typ R
L
= 300 Ω, C
L
= 35 pF;
48 55 ns max V
S
= 3 V; Test Circuit 8
t
OFF
(EN)19ns typ R
L
= 300 Ω, C
L
= 35 pF;
25 28 ns max V
S
= 2 V; Test Circuit 8
Charge Injection 1 pC typ V
S
= 1.5 V, R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 9
Off Isolation –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 10
Channel-to-Channel Crosstalk –72 dB typ R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
Test Circuit 11
–3 dB Bandwidth R
L
= 50 Ω, C
L
= 5 pF; Test Circuit 12
ADG726 34 MHz typ
ADG732 18 MHz typ
C
S
(OFF) 13 pF typ f = 1 MHz
C
D
(OFF)
ADG726 170 pF typ f = 1 MHz
ADG732 340 pF typ f = 1 MHz
C
D
, C
S
(ON)
ADG726 175 pF typ f = 1 MHz
ADG732 350 pF typ f = 1 MHz
POWER REQUIREMENTS V
DD
= 3.3 V
I
DD
5µA typ Digital Inputs = 0 V or 3.3 V
10 µA max
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
SPECIFICATIONS
1
(VDD = 3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
REV. 0
B Version
–40ⴗC
Parameter +25ⴗC to +85ⴗC Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range V
SS
to V
DD
V
On Resistance (R
ON
)4 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA;
5.5 6 Ω max Test Circuit 1
On Resistance Match Between 0.3 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
Channels (∆R
ON
) 0.8 Ω max
On Resistance Flatness (R
FLAT(ON)
) 0.5 Ω typ V
S
= V
SS
to V
DD
, I
DS
= 10 mA
1Ω max
LEAKAGE CURRENTS V
DD
= +2.75 V, V
SS
= –2.75 V
Source OFF Leakage I
S
(OFF) ±0.01 nA typ V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V;
±0.25 ±0.5 nA max Test Circuit 2
Drain OFF Leakage I
D
(OFF) ±0.05 nA max V
S
= +2.25 V/–1.25 V, V
D
= –1.25 V/+2.25 V;
ADG726 ±0.5 ±2.5 nA max Test Circuit 3
ADG732 ±1±5 nA max
Channel ON Leakage I
D
, I
S
(ON) ±0.05 nA typ V
S
= V
D
= +2.25 V/–1.25 V;
ADG726 ±0.5 ±2.5 nA max Test Circuit 4
ADG732 ±1±5 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
1.7 V min
Input Low Voltage, V
INL
0.7 V max
Input Current
I
INL
or I
INH
0.005 µA typ V
IN
= V
INL
or V
INH
±0.5 µA max
C
IN
, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
33 ns typ R
L
= 300 ⍀, C
L
= 35 pF; Test Circuit 5
45 51 ns max V
S1
= 1.5 V/0 V, V
S32
= 0 V/1.5 V
Break-Before-Make Time Delay, t
D
15 ns typ R
L
= 300 ⍀, C
L
= 35 pF;
1 ns min V
S
= 1.5 V; Test Circuit 6
t
ON
(CS, WR) 21 ns typ V
S
= 1.5 V; Test Circuit 7
30 37 ns max R
L
= 300 ⍀, C
L
= 35 pF;
t
OFF
(CS, WR) 20 ns typ V
S
= 1.5 V; Test Circuit 7
29 35 ns max R
L
= 300 ⍀, C
L
= 35 pF;
t
ON
(EN, WR) 26 ns typ R
L
= 300 ⍀, C
L
= 35 pF;
37 ns max V
S
= 1.5 V; Test Circuit 8
t
OFF
(EN) 18 ns typ R
L
= 300 ⍀, C
L
= 35 pF;
26 29 ns max V
S
= 1.5 V; Test Circuit 8
Charge Injection 1 pC typ V
S
= 0 V, R
S
= 0 ⍀, C
L
= 1 nF;
Test Circuit 9
OFF Isolation –72 dB typ R
L
= 50 ⍀, C
L
= 5 pF, f = 1 MHz;
Test Circuit 10
Channel-to-Channel Crosstalk –72 dB typ R
L
= 50 ⍀, C
L
= 5 pF, f = 1 MHz;
Test Circuit 11
–3 dB Bandwidth R
L
= 50 ⍀, C
L
= 5 pF; Test Circuit 12
ADG726 34 MHz typ
ADG732 18 MHz typ
C
S
(OFF) 13 pF typ
C
D
(OFF)
ADG726 137 pF typ f = 1 MHz
ADG732 275 pF typ f = 1 MHz
C
D
, C
S
(ON)
ADG726 150 pF typ f = 1 MHz
ADG732 300 pF typ f = 1 MHz
POWER REQUIREMENTS
I
DD
10 µA typ V
DD
= +2.75 V
20 µA max Digital Inputs = 0 V or +2.75 V
I
SS
10 µA typ V
SS
= –2.75 V
20 µA max Digital Inputs = 0 V or +2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
–4–
ADG726/ADG732 SPECIFICATIONS
1
(V
DD
= +2.5 V ⴞ 10%, V
SS
= –2.5 V ⴞ 10%, GND = 0 V, unless otherwise noted.)
DUAL SUPPLY
REV. 0 –5–
ADG726/ADG732
TIMING CHARACTERISTICS
1, 2, 3
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
t
1
0ns min CS to WR Setup Time
t
2
0ns min CS to WR Hold Time
t
3
10 ns min WR Pulsewidth
t
4
10 ns min Time between WR
Cycles
t
5
5ns min Address, Enable Setup Time
t
6
2ns min Address, Enable Hold Time
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
).
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
t1t2
t3t4
t5t6
CS
WR
A0, A1, A2, A3, (A4)
EN
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to changing the address and enable the inputs.
Input data is latched on the rising edge of WR. The ADG726
has two CS inputs. This enables the part to be used either as a
dual 16-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie CSA and
CSB together.
REV. 0
–6–
ADG726/ADG732
PIN CONFIGURATIONS
LFCSP and TQFP
PIN 1
INDICATOR
TOP VIEW
ADG732
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
NC = NO CONNECT
V
DD
13
V
DD
14
A0 15
A1 16
A2 17
A3 18
A4 19
CS 20
WR 21
EN 22
GND 23
V
SS
24
36 S28
35 S27
34 S26
33 S25
32 S24
31 S23
30 S22
29 S21
28 S20
27 S19
26 S18
25 S17
48 S13
47 S14
46 S15
45 S16
44 NC
43 D
42 NC
41 NC
40 S32
39 S31
38 S30
37 S29
1
2
3
4
5
6
7
8
9
10
11
12
PIN 1
INDICATOR
TOP VIEW
ADG726
1
S12A
2
S11A
3
S10A
4
S9A
5
S8A
6
S7A
7
S6A
8
S5A
9
S4A
10
S3A
11
S2A
12
S1A
NC = NO CONNECT
V
DD
13
V
DD
14
A0 15
A1 16
A2 17
A3 18
CSA 19
CSB 20
WR 21
EN 22
GND 23
V
SS
24
36 S12B
35 S11B
34 S10B
33 S9B
32 S8B
31 S7B
30 S6B
29 S5B
28 S4B
27 S3B
26 S2B
25 S1B
48 S13A
47 S14A
46 S15A
45 S16A
44 NC
43 DA
42 NC
41 DB
40 S16B
39 S15B
38 S14B
37 S13B
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
Analog Inputs
2
. . . . . . . . . . . . . . V
SS
– 0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs
2
. . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Thermal Impedence (Four-layer board)
48-Lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 25⬚C/W
48-Lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6⬚C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, WR, CS, S, or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG726BCP –40°C to +85°CChip Scale Package (LPCSP) CP-48
ADG726BSU –40°C to +85°CThin Quad Flatpack (TQFP) SU-48
ADG732BCP –40°C to +85°CChip Scale Package (LPCSP) CP-48
ADG732BSU –40°C to +85°CThin Quad Flatpack (TQFP) SU-48
REV. 0 –7–
ADG726/ADG732
Table II. ADG732 Truth Table
A4 A3 A2 A1 A0 EN CS WR Switch Condition
XXXX XX 1 L->H Retains Previous Switch Condition
XXXX XX 1XNo Change in Switch Condition
XXXX X 100 NONE
00000000 1
00001000 2
00010000 3
00011000 4
00100000 5
00101000 6
00110000 7
00111000 8
01000000 9
01001000 10
01010000 11
01011000 12
01100000 13
01101000 14
01110000 15
01111000 16
10000000 17
10001000 18
10010000 19
10011000 20
10100000 21
10101000 22
10110000 23
10111000 24
11000000 25
11001000 26
11010000 27
11011000 28
11100000 29
11101000 30
11110000 31
11111000 32
X = Don’t Care
Table I. ADG726 Truth Table
A3 A2 A1 A0 EN CSA CSB WR ON Switch
XXXX X 11L->H Retains Previous Switch Condition
XXXX X 11XNo Change in Switch Condition
XXXX 1 000 NONE
00000000 S1A–DA, S1B–DB
00010000 S2A–DA, S2B–DB
00100000 S3A–DA, S3B–DB
00110000 S4A–DA, S4B–DB
01000000 S5A–DA, S5B–DB
01010000 S6A–DA, S6B–DB
01100000 S7A–DA, S7B–DB
01110000 S8A–DA, S8B–DB
10000000 S9A–DA, S9B–DB
1001 0 000 S10A–DA, S10B–DB
1010 0 000 S11A–DA, S11B–DB
1011 0 000 S12A–DA, S12B–DB
1100 0 000 S13A–DA, S13B–DB
1101 0 000 S14A–DA, S14B–DB
1110 0 000 S15A–DA, S15B–DB
1111 0 000 S16A–DA, S16B–DB
X = Don’t Care
REV. 0
–8–
ADG726/ADG732
TERMINOLOGY
V
DD
Most Positive Power Supply Potential
V
SS
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND.
I
DD
Positive Supply Current
I
SS
Negative Supply Current
GND Ground (0 V) Reference
SSource Terminal. May be an input or output.
DDrain Terminal. May be an input or output.
IN Logic Control Input
V
D
(V
S
)Analog Voltage on Terminals D and S
R
ON
Ohmic Resistance between D and S
∆R
ON
On Resistance Match between any two channels, i.e., R
ON
max – R
ON
min
R
FLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
I
S
(OFF) Source Leakage Current with the Switch OFF
I
D
(OFF) Drain Leakage Current with the Switch OFF
I
D
, I
S
(ON) Channel Leakage Current with the Switch ON
V
INL
Maximum Input Voltage for Logic “0”
V
INH
Minimum Input Voltage for Logic “1”
I
INL
(I
INH
)Input Current of the Digital Input
C
S
(OFF) OFF Switch Source Capacitance. Measured with reference to ground.
C
D
(OFF) OFF Switch Drain Capacitance. Measured with reference to ground.
C
D
,C
S
(ON) ON Switch Capacitance. Measured with reference to ground.
C
IN
Digital Input Capacitance
t
TRANSITION
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch ON Condition
when Switching from One Address State to Another
t
ON
(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch ON Condition
t
OFF
(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch OFF Condition
t
OPEN
OFF Time Measured between the 80% Points of Both Switches when Switching from One Address State to Another
Charge A Measure of the Glitch Impulse Transferred from the Digital Input to the Analog Output During Switching
Injection
OFF Isolation A Measure of Unwanted Signal Coupling through an OFF Switch
Crosstalk A Measure of Unwanted Signal Coupling from One Channel to Another as a Result of Parasitic Capacitance
ON Response The Frequency Response of the ON Switch
Insertion The Loss Due to the On Resistance of the Switch
Loss
REV. 0 –9–
V
D
, V
S
– V
8
0 5.5
05.04.54.03.53.02.52.01.51.00.5
1
2
3
4
5
6
7
V
DD
= 2.7V
V
DD
= 3.0V
V
DD
= 4.5V
RESISTANCE –
V
DD
= 3.3V
V
DD
= 5V
V
DD
= 5.5V
T
A
= +25C
V
SS
= 0V
TPC 1. On Resistance vs. V
D
(V
S
),
Single Supply
V
D
, V
S
– V
8
0
0
1
2
3
4
5
6
7
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
+85C
–40C
RESISTANCE –
+25C
V
SS
= 0V
TPC 4. On Resistance vs. V
D
(V
S
),
Single Supply
V
D
, V
S
– V
Q
INJ
– pC
25
–15–3 –2 5
–1 01234
20
5
0
–5
–10
15
10
T
A
= +25C
TPC 7. ADG732 Charge Injection
vs. Source Voltage
V
D
, V
S
– V
8
–2.75
0
1
2
3
4
5
6
7
–1.75 –0.75 0.25 1.25 2.25
V
DD
= +2.25V
V
SS
= –2.25V
T
A
= +25C
V
DD
= +2.5V
V
SS
= –2.5V
V
DD
= +2.75V
V
SS
= –2.75V
RESISTANCE –
TPC 2. On Resistance vs. V
D
(V
S
),
Dual Supply
V
D
, V
S
– V
8
–2.5
0
1
2
3
4
5
6
7
–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
+85C
–40C
+25C
RESISTANCE –
TPC 5. On Resistance vs. V
D
(V
S
),
Dual Supply
TEMPERATURE – C
–40 –20 80
0204060
TIME – ns
45
40
0
20
15
10
5
35
25
30
V
SS
= 0V
t
ON
t
OFF
V
DD
= 3V
V
DD
= 5V
V
DD
= 5V
V
DD
= 3V
TPC 8. t
ON
/t
OFF
Times vs. Temperature
V
D
, V
S
– V
8
0
0
1
2
3
4
5
6
7
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
+85C
–40C
V
SS
= 0V
RESISTANCE –
+25C
TPC 3. On Resistance vs. V
D
(V
S
)
for Different Temperatures,
Single Supply
TEMPERATURE – C
0.5
5
–0.5 15 8525 35 45 55 65 75
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
V
DD
= 5V
V
SS
= 0V
CURRENT – nA
TPC 6. Leakage Currents vs.
Temperature
V
DD
– V
01 62345
LOGIC THRESHOLD VOLTAGE – V
1.8
1.6
0
0.8
0.6
0.4
0.2
1.4
1.0
1.2
T
A
= 25C
FA L L ING
RISING
TPC 9. Logic Threshold Voltage
vs. Supply Voltage
Typical Performance Characteristics—
ADG726/ADG732
REV. 0
ADG726/ADG732
–10–
FREQUENCY – MHz
0
–100
–70
–60
–50
–40
–30
–20
–10
0.03 0.1 1 10 100
–80
–90
V
DD
= 5V
T
A
= 25C
ATTENUATION – dB
TPC 10. OFF Isolation vs. Frequency
FREQUENCY – MHz
ATTENUATION – dB
0.03 0.1 100110
0
–10
–100
–20
–30
–40
–50
–60
–70
–80
–90
VDD = 3V, 5V
TA = 25C
TPC 11. Crosstalk vs. Frequency
FREQUENCY – MHz
0
–14
–12
–10
–8
–6
–4
–2
0.03 0.1 1 10 100
VDD = 5V
TA = 25C
ADG732
ADG726
ATTENUATION – dB
TPC 12. ON Response vs. Frequency
IDS
V1
SD
VS
RON = V1/IDS
Test Circuit 1. On Resistance
S1
D
V
S
GND
A
V
S
S2
S32
EN LOGIC “1”
V
DD
V
SS
V
DD
V
SS
I
S
(OFF)
V
D
Test Circuit 2. I
S
(OFF)
S1
D
V
S
GND
A
V
D
S2
S32
EN
LOGIC “1”
V
DD
V
SS
V
DD
V
SS
I
D
(OFF)
Test Circuit 3. I
D
(OFF)
D
V
S
GND
A
V
D
S1
S32
EN
V
DD
V
SS
V
DD
V
SS
I
D
(ON)
LOGIC “ 0”
Test Circuit 4. I
D
(ON)
Test Circuits
ADDRESS
DRIVE (VIN)
0V
3V
VOUT
VS1
VS32
tTRANSITION tTRANSITION
50%
90%
50%
90%
VSS
VSS
VDD
VDD
50
VIN
A4
A0
ADG732*
S2 THRU S31
S1
S32
D
EN
VS1
VOUT
RL
300
CL
35pF
CS GND WR
*SIMILAR CONNECTION FOR ADG726
VS32
Test Circuit 5. Switching Time of Multiplexer, t
TRANSITION
3V
ADDRESS
DRIVE (VIN)
0V
VS
VOUT
tOPEN
80%80%
VSS
VSS
VDD
VDD
50
VIN
A4
A0
ADG732*
S2 THRU S31
S1
S32
D
EN
VS
VOUT
RL
300
CL
35pF
CS GND WR
*SIMILAR CONNECTION FOR ADG726
Test Circuit 6. Break-Before-Make Delay, t
OPEN
REV. 0 –11–
ADG726/ADG732
tON
(WR)
tOFF
(WR)
20%
20%
50%
3V
0V
WR
SWITCH
OUTPUT
V
O
0V
V
S
V
SS
V
SS
V
DD
V
DD
V
CS
A4
A0
ADG732*
S2 THRU S32
S1
D
EN
V
OUT
R
L
300
C
L
35pF
GND
*SIMILAR CONNECTION FOR ADG726
CS
WR
V
WR
Test Circuit 7. Write Turn-ON and Turn-OFF Time, t
ON
,
t
OFF
(
WR
)
3V
0V
EN
SWITCH
OUTPUT
V
O
0V
50% 50%
10%
90%
t
ON
(EN)
t
OFF
(EN)
V
S
V
SS
V
SS
V
DD
V
DD
V
EN
A4
A0
ADG732*
S2 THRU S32
S1
D
CS
V
OUT
R
L
300
C
L
35pF
GND
*SIMILAR CONNECTION FOR ADG726
EN
WR
Test Circuit 8. Enable Delay, t
ON
(
EN
), t
OFF
(
EN
)
0V
3V
VOUT VOUT
QINJ = CL  VOUT
LOGIC
INPUT (VIN)
VSS
VSS
VDD
VDD
VIN
A4
A0
ADG732*
D
CS
VOUT
CL
1nF
GND
*SIMILAR CONNECTION FOR ADG726
EN
WR
RS
VS
S
Test Circuit 9. Charge Injection
A4
A0
ADG732*
D
GND
SIMILAR CONNECTION FOR ADG726
EN
50
V
OUT
R
L
50
V
S
NETWORK
ANALYZER
V
DD
V
SS
0.1F 0.1F
50
S
OFF ISOLATION = 20 LOG V
OUT
V
S
V
DD
V
SS
LOGIC “ 1”
*
Test Circuit 10. OFF Isolation
REV. 0
–12–
C02765–0–7/02(0)
PRINTED IN U.S.A.
ADG726/ADG732
VSS
VSS
VDD
VDD
A4
A0
ADG732*
D
EN GND
*SIMILAR CONNECTION FOR ADG726
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10 (VOUT/VS)
WR
S2
S32
50
VOUT
RL
50
VS
NETWORK
ANALYZER
CS
S1 50
Test Circuit 11. Channel-to-Channel Crosstalk
A4
A0
ADG732*
D
GND
*SIMILAR CONNECTION FOR ADG726
EN
50
VOUT
RL
50
VS
NETWORK
ANALYZER
VDD VSS
0.1F 0.1F
S
VDD VSS
INSERTION LOSS = 20 LOG VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Test Circuit 12. Bandwidth
OUTLINE DIMENSIONS
48-Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
BOTTOM
VIEW
5.25
4.70
2.25
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12MAX
0.25
REF
0.70 MAX
0.65 NOM
1.00
0.90
0.80
5.50
REF
SEATING
PLANE
0.05 MAX
0.02 NOM
COPLANARITY
0.60 MAX
0.60 MAX PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
48-Lead Thin Plastic Quad Flatpack [TQFP]
(SU-48)
Dimensions shown in millimeters
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.5
BSC
7.00
BSC
SQ
0.27
0.22
0.17
9.00 BSC SQ
SEATING
PLANE
7
0
1.05
1.00
0.95
1.20 MAX
0.75
0.60
0.45
0.20
0.09
0
MIN
0.15
0.05
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MS-026BBC