LC2MOS
5 Ω RON SPST Switches
ADG451/ADG452/ADG453
Rev. C
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Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Low on resistance (4 Ω)
On resistance flatness (0.2 Ω)
44 V supply maximum ratings
±15 V analog signal range
Fully specified at ±5 V, 12 V, ±15 V
Ultralow power dissipation (18 μW)
ESD 2 kV
Continuous current (100 mA)
Fast switching times
tON 70 ns
tOFF 60 ns
TTL-/CMOS-compatible
Pin-compatible upgrade for ADG411/ADG412/ADG413
and ADG431/ADG432/ADG433
APPLICATIONS
Relay replacement
Audio and video switching
Automatic test equipment
Precision data acquisition
Battery-powered systems
Sample-and-hold systems
Communication systems
PBX, PABX systems
Avionics
GENERAL DESCRIPTION
The ADG451/ADG452/ADG453 are monolithic CMOS
devices comprising four independently selectable switches.
They are designed on an enhanced LC2MOS process that
provides low power dissipation yet gives high switching
speed and low on resistance.
The on resistance profile is very flat over the full analog input
range, ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed, coupled with high
signal bandwidth, makes the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion, making the parts ideally suited for portable and battery-
powered instruments.
The ADG451/ADG452/ADG453 contain four independent,
single-pole/single-throw (SPST) switches. The ADG451 and
ADG452 differ only in that the digital control logic is inverted. The
ADG451 switches are turned on with a logic low on the appropriate
control input, while a logic high is required for the ADG452.
FUNCTIONAL BLOCK DIAGRAMS
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
ADG451
S
WITCHES SHOWN FOR A LOGIC 1 INPUT.
05239-001
Figure 1. ADG451
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
ADG452
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
05239-101
Figure 2. ADG452
IN1
S1
D1
IN2
S2
D2
IN3
S3
D3
IN4
S4
D4
ADG453
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
05239-102
Figure 3. ADG453
The ADG453 has two switches with digital control logic similar
to that of the ADG451, while the logic is inverted on the other
two switches.
Each switch conducts equally well in both directions when on,
and each has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
The ADG453 exhibits break-before-make switching action for
use in multiplexer applications. Inherent in the design is low
charge injection for minimum transients when switching the
digital inputs.
ADG451/ADG452/ADG453
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
15 V Dual Supply.......................................................................... 4
12 V Single Supply........................................................................ 5
5 V Dual Supply............................................................................ 6
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ..............................................9
Terminology .................................................................................... 11
Applications..................................................................................... 12
Test Circuits..................................................................................... 13
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
10/06—Rev. B to Rev. C
Changes to Table 4............................................................................ 9
Changes to Ordering Guide .......................................................... 18
12/04—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Specifications Section.................................................. 3
Changes to Absolute Maximum Ratings Section......................... 8
Changes to Pin Configuration and Function
Descriptions Section ........................................................................ 9
Updated Outline Dimensions....................................................... 16
Changes to Ordering Guide .......................................................... 17
2/98—Rev. 0 to Rev. A
10/97—Revision 0: Initial Version
ADG451/ADG452/ADG453
Rev. C | Page 3 of 16
PRODUCT HIGHLIGHTS
1. Low RON (5 Ω maximum).
2. Ultralow Power Dissipation.
3. Extended Signal Range.
The ADG451/ADG452/ADG453 are fabricated on an enhanced
LC2MOS process, giving an increased signal range that fully
extends to the supply rails.
4. Break-Before-Make Switching.
This prevents channel shorting when the switches are
configured as a multiplexer (ADG453 only.)
5. Single-Supply Operation.
For applications in which the analog signal is unipolar, the
ADG451/ADG452/ADG453 can be operated from a single
rail power supply. The parts are fully specified with a single
12 V power supply and remain functional with single supplies
as low as 5.0 V.
6. Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG451/ADG452/ADG453 can be operated from a dual
power supply ranging from ±4.5 V to ±20 V.
ADG451/ADG452/ADG453
Rev. C | Page 4 of 16
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V, VSS = −15 V, VL = 5 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version1
Parameter 25°C TMIN to TMAX Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance (RON) 4 Ω typ VD = −10 V to +10 V, IS = −10 mA
5 7 Ω max
On Resistance Match Between Channels (ΔRON) 0.1 Ω typ VD = ±10 V, IS = −10 mA
0.5 0.5 Ω max
On Resistance Flatness (RFLAT(ON)) 0.2 Ω typ VD = −5 V, 0 V, +5 V, IS = −10 mA
0.5 0.5 Ω max
LEAKAGE CURRENTS2
Source Off Leakage, IS (OFF) ±0.02 nA typ VD = ±10 V, VS = ±10 V; see Figure 17
±0.5 ±2.5 nA max
Drain Off Leakage, ID (OFF) ±0.02 nA typ VD = ±10 V, VS = ±10 V; see Figure 17
±0.5 ±2.5 nA max
Channel On Leakage, ID, IS (ON) ±0.04 nA typ VD = VS = ±10 V; see Figure 18
±1 ±5 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH; all others = 2.4 V or 0.8 V, respectively
±0.5 μA max
DYNAMIC CHARACTERISTICS3
tON 70 ns typ RL = 300 Ω, CL = 35 pF, VS = ±10 V; see Figure 19
180 220 ns max
tOFF 60 ns typ RL = 300 Ω, CL = 35 pF, VS = ±10 V; see Figure 19
140 180 ns max
Break-Before-Make Time Delay, tD (ADG453 Only) 15 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = +10 V; see Figure 20
5 5 ns min
Charge Injection 20 pC typ VS = 0 V, RS = 0 Ω, CL = 1.0 nF; see Figure 21
30 pC max
Off Isolation 65 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 22
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
CS (OFF) 37 pF typ f = 1 MHz
CD (OFF) 37 pF typ f = 1 MHz
CD, CS (ON) 140 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 16.5 V, VSS = −16.5 V; digital inputs = 0 V or 5 V
IDD 0.0001 μA typ
0.5 5 μA max
ISS 0.0001 μA typ
0.5 5 μA max
IL 0.0001 μA typ
0.5 5 μA max
IGND30.0001 μA typ
0.5 5 μA max
1 Temperature range for B version is −40°C to +85°C.
2 TMAX = 70°C.
3 Guaranteed by design, not subject to production test.
ADG451/ADG452/ADG453
Rev. C | Page 5 of 16
12 V SINGLE SUPPLY
VDD = 12 V, VSS = 0 V, VL = 5 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version1
Parameter 25°C TMIN to TMAX Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 6 Ω typ VD = 0 V to +10 V, IS = −10 mA
8 10 Ω max
On Resistance Match Between Channels (ΔRON) 0.1 Ω typ VD = 10 V, IS = −10 mA
0.5 0.5 Ω max
On Resistance Flatness (RFLAT(ON)) 1.0 1.0 Ω typ VD = 0 V, 5 V, IS = −10 mA
LEAKAGE CURRENTS2, 3
Source Off Leakage, IS (OFF) ±0.02 nA typ VD = 0 V, 10 V, VS = 0 V, 10 V; see Figure 17
±0.5 ±2.5 nA max
Drain Off Leakage, ID (OFF) ±0.02 nA typ VD = 0 V, 10 V, VS = 0 V, 10 V; see Figure 17
±0.5 ±2.5 nA max
Channel On Leakage, ID, IS (ON) ±0.04 nA typ VD = VS = 0 V, 10 V; see Figure 18
±1 ±5 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.5 μA max
DYNAMIC CHARACTERISTICS4
tON 100 ns typ RL = 300 Ω, CL = 35 pF, VS = 8 V; see Figure 19
220 260 ns max
tOFF 80 ns typ RL = 300 Ω, CL = 35 pF, VS = 8 V; see Figure 19
160 200 ns max
Break-Before-Make Time Delay, tD (ADG453 Only) 15 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 8 V;
see Figure 20
10 10 ns min
Charge Injection 10 pC typ VS = 6 V, RS = 0 Ω, CL = 1.0 nF; see Figure 21
Channel-to-Channel Crosstalk −90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
CS (OFF) 60 pF typ f = 1 MHz
CD (OFF) 60 pF typ f = 1 MHz
CD, CS (ON) 100 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V; digital inputs = 0 V or 5 V
IDD 0.0001 μA typ
0.5 5 μA max
IL 0.0001 μA typ
0.5 5 μA max VL = 5.5 V
IGND40.0001 μA typ
0.5 5 μA max VL = 5.5 V
1 Temperature range for B version is −40°C to +85°C.
2 TMAX = 70°C.
3 Tested with dual supplies.
4 Guaranteed by design, not subject to production test.
ADG451/ADG452/ADG453
Rev. C | Page 6 of 16
5 V DUAL SUPPLY
VDD = +5 V, VSS = −5 V, VL = +5 V, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version1
Parameter 25°C TMIN to TMAX Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V
On Resistance (RON) 7 Ω typ VD = −3.5 V to +3.5 V, IS = −10 mA
12 15 Ω max
On Resistance Match Between Channels (ΔRON) 0.3 Ω typ VD = 3.5 V, IS = −10 mA
0.5 0.5 Ω max
LEAKAGE CURRENTS2, 3
Source Off Leakage, IS (OFF) ±0.02 nA typ VD = ±4.5, VS = ±4.5; see Figure 17
±0.5 ±2.5 nA max
Drain Off Leakage, ID (OFF) ±0.02 nA typ VD = 0 V, 5 V, VS = 0 V, 5 V; see Figure 17
±0.5 ±2.5 nA max
Channel On Leakage, ID, IS (ON) ±0.04 nA typ VD = VS = 0 V, 5 V; see Figure 18
±1 ±5 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.5 μA max
DYNAMIC CHARACTERISTICS4
tON 160 ns typ RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 19
220 300 ns max
tOFF 60 ns typ RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 19
140 180 ns max
Break-Before-Make Time Delay, tD (ADG453 Only) 50 ns typ RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 20
5 5 ns min
Charge Injection 10 pC typ VS = 0 V, RS = 0 Ω, CL = 1.0 nF; see Figure 21
Off Isolation 65 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 22
Channel-to-Channel Crosstalk −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 23
CS (OFF) 48 pF typ f = 1 MHz
CD (OFF) 48 pF typ f = 1 MHz
CD, CS (ON) 148 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V; digital inputs = 0 V or 5 V
IDD 0.0001 μA typ
0.5 5 μA max
ISS 0.0001 μA typ
0.5 5 μA max
IL 0.0001 μA typ
0.5 5 μA max VL = 5.5 V
IGND40.0001 μA typ
0.5 5 μA max VL = 5.5 V
1 Temperature range for B version is −40°C to +85°C.
2 TMAX = 70°C.
3 Tested with dual supplies.
4 Guaranteed by design, not subject to production test.
ADG451/ADG452/ADG453
Rev. C | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameters Ratings
VDD to VSS 44 V
VDD to GND −0.3 V to +32 V
VSS to GND +0.3 V to −32 V
VL to GND −0.3 V to VDD + 0.3 V
Analog, Digital Inputs1VSS − 2 V to VDD + 2 V or 30 mA,
whichever occurs first
Continuous Current, S or D 100 mA
Peak Current, S or D (pulsed at
1 ms, 10% duty cycle maximum)
300 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Plastic DIP Package,
Power Dissipation
470 mW
θJA Thermal Impedance 117°C/W
Lead Temperature, Soldering
(10 sec)
260°C
SOIC Package, Power Dissipation 600 mW
θJA Thermal Impedance 77°C/W
TSSOP Package, Power Dissipation 450 mW
θJA Thermal Impedance 115°C/W
θJC Thermal Impedance 35°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
ESD 2 kV
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any one
time.
ESD CAUTION
ADG451/ADG452/ADG453
Rev. C | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1
1
D1
2
S1
3
V
SS 4
IN2
16
D2
15
S2
14
V
DD
13
GND
5
V
L
12
S4
6
S3
11
D4
7
D3
10
IN4
8
IN3
9
ADG451/
ADG452/
ADG453
TOP VIEW
(Not to Scale)
05239-002
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 IN1 Logic Control Input.
2 D1 Drain Terminal. Can be an input or an output.
3 S1 Source Terminal. Can be an input or an output.
4 VSS Most Negative Power Supply Potential in Dual Supplies. In single-supply applications,
it can be connected to GND.
5 GND Ground (0 V) Reference.
6 S4 Source Terminal. Can be an input or an output.
7 D4 Drain Terminal. Can be an input or an output.
8 IN4 Logic Control Input.
9 IN3 Logic Control Input.
10 D3 Drain Terminal. Can be an input or an output.
11 S3 Source Terminal. Can be an input or an output.
12 VL Logic Power Supply (5 V).
13 VDD Most Positive Power Supply Potential.
14 S2 Source Terminal. Can be an input or an output.
15 D2 Drain Terminal. Can be an input or an output.
16 IN2 Logic Control Input.
Table 6. Truth Table (ADG451/ADG452)
ADG451 In ADG452 In Switch Condition
0 1 On
1 0 Off
Table 7. Truth Table (ADG453)
Logic Switch 1, Switch 4 Switch 2, Switch 3
0 Off On
1 On Off
ADG451/ADG452/ADG453
Rev. C | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
05239-003
VD OR VSDRAIN OR SOURCE VOLTAGE (V)
16.5
–16.5
–13.5
–10.5
–7.5
–4.5
–1.5
1.5
4.5
7.5
10.5
13.5
RON (Ω)
9
8
7
6
5
4
3
0
2
1
TA= 25°C
VL=5V
VDD =+13.5V
VSS = –13.5V
VDD =+16.5V
VSS = –16.5V
VDD =+15V
VSS = –15V
VDD =+5V
VSS = –5V
Figure 5. On Resistance as a Function of VD (VS) for Various
Dual Supplies
05239-004
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE (V)
15–15 –10 –5 0 105
R
ON
(Ω)
7
4
5
6
3
1
2
0
+85°C
V
DD
= +15V
V
SS
= –15V
V
L
=+5V
+25°C
–40°C
Figure 6. On Resistance as a Function of VD (VS) for Different
Temperatures with Dual Supplies
05239-005
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE (V)
1803691215
R
ON
(Ω)
16
14
12
10
8
6
4
2
0
T
A
=25°C
V
L
=5V
V
DD
=5V
V
SS
=0V
V
DD
= 13.5V
V
SS
=0V
V
DD
=15V
V
SS
=0V
V
DD
= 16.5V
V
SS
=0V
Figure 7. On Resistance as a Function of VD (VS) for Various
Single Supplies
05239-006
TEMPERATURE (°C)
8525 35 45 55 7565
LEAKAGE CURRENT (nA)
10
1
0.1
0.01
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
V
DD
= +15V
V
SS
= –15V
V
L
=+5V
V
D
= +15V
V
S
= –15V
Figure 8. Leakage Currents as a Function of Temperature
05239-007
FREQUENCY (Hz)
10M10 100 1k 10k 100k 1M
I
SUPPLY
(µA)
100k
10k
100
1
1k
10
0.1
0.01
I
L
1SW
I
+
,I
+
4SW
V
DD
=+15V
V
SS
= –15V
V
L
=+5V
Figure 9. Supply Current vs. Input Switching Frequency
05239-008
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE (V)
1602468101214
R
ON
(Ω)
12
9
10
11
6
7
8
1
2
3
4
5
0
–40°C
+25°C
+85°C
V
DD
= 15V
V
SS
=0V
V
L
=5V
Figure 10. On Resistance as a Function of VD (VS) for Different
Temperatures with Single Supplies
ADG451/ADG452/ADG453
Rev. C | Page 10 of 16
05239-009
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE (V)
15–15 –12 –9 –6 –3 0 3 6 9 12
LEAKAGE CURRENT (nA)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
I
D
(ON)
I
D
(OFF)
I
S
(OFF)
V
DD
= +15V
V
SS
= –15V
T
A
=+25°C
V
L
=+5V
Figure 11. Leakage Currents as a Function of VD (VS)
05239-010
FREQUENCY (MHz)
100110
OFF ISOLATION (dB)
70
60
50
40
30
0
20
10
V
DD
= +15V
V
SS
=–15V
V
L
=+5V
Figure 12. Off Isolation vs. Frequency
05239-011
FREQUENCY (Hz)
100M100 1k 10k 100k 10M1M
CROSSTALK (dB)
120
100
80
60
40
20
0
V
DD
= +15V
V
SS
=–15V
V
L
=+5V
R
LOAD
=50Ω
Figure 13. Crosstalk vs. Frequency
05239-012
FREQUENCY (MHz)
2001 10 100
LOSS (dB)
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
DD
= +15V
V
SS
= –15V
V
L
=+5V
Figure 14. Frequency Response with Switch On
ADG451/ADG452/ADG453
Rev. C | Page 11 of 16
TERMINOLOGY
RON
Ohmic resistance between D and S.
ΔRON
On resistance match between any two channels, that is, RON
maximum minus RON minimum.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (OFF)
Source leakage current with the switch off.
ID (OFF)
Drain leakage current with the switch off.
ID, IS (ON)
Channel leakage current with the switch on.
VD (VS)
Analog voltage on Terminal D and Terminal S.
CS (OFF)
Off switch source capacitance.
CD (OFF)
Off switch drain capacitance.
CD (ON), CS (ON)
On switch capacitance.
tON
Delay between applying the digital control input and the output
switching on. See Figure 19.
tOFF
Delay between applying the digital control input and the output
switching off.
tD
Off time or on time measured between the 90% points of both
switches, when switching from one address state to another. See
Figure 20.
Crosstalk
A measure of unwanted signal coupled through from one
channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ADG451/ADG452/ADG453
Rev. C | Page 12 of 16
APPLICATIONS
Figure 15 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer, and the output operational
amplifier is an AD711. During track mode, SW1 is closed, and
the output, VOUT, follows the input signal, VIN. In hold mode,
SW1 is opened, and the signal is held by the hold capacitor, CH.
SD V
OUT
SD
–15V
+15V +5V
C
C
1000pF
2200pF
R
C
75Ω
1213
45
SW1
ADG451/
ADG452/
ADG453
–15V
+15V
V
IN
AD845 –15V
+15V
AD711
SW2
CH
2200pF
05239-013
Figure 15. Fast, Accurate Sample-and-Hold Circuit
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG451/ADG452/ADG453
minimize this droop due to their low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Because both
switches are at the same potential, they have a differential effect
on the op amp, AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network, RC and CC. This compensation network reduces the
hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.
ADG451/ADG452/ADG453
Rev. C | Page 13 of 16
TEST CIRCUITS
SD
R
ON
=V
1
/I
DS
V
S
V
1
I
DS
05239-014
Figure 16. On Resistance
SD
V
S
V
D
AA
I
S
(OFF) I
D
(OFF)
05239-015
Figure 17. Off Leakage
SD
V
S
V
D
A
I
D
(ON)
05239-016
Figure 18. On Leakage
SD
V
S
V
IN
V
OUT
IN
V
SS
GND
V
L
V
DD
–15V
+15
V
+5
V
C
L
35pF
R
L
300Ω
3V
50%
50% 50%
90%
90%
50%
ADG451
ADG452
V
IN
V
IN
V
OUT
3V
t
ON
t
OFF
05239-017
0.1µF
0.1µF 0.1µF
Figure 19. Switching Times
05239-018
S1 D1
V
S1
V
OUT1
IN1, IN2
V
SS
GND
V
L
V
DD
–15V
+15
V
+5
V
C
L1
35pF
R
L1
300Ω
0.1µF
0.1µF 0.1µF
S2 D2
V
S2
V
IN
V
OUT2
C
L2
35pF
R
L2
300Ω
ADG453 50%
90%
V
IN
V
OUT1
V
OUT2
50%
90%
90% 90%
t
D
t
D
3V
0V
0V
0V
Figure 20. Break-Before-Make Time Delay
SD
V
S
V
OUT
IN
R
S
V
DD
GND
V
L
V
–15V
+15
V
+5
V
C
L
10nF
3V
V
IN
V
OUT
V
IN
=C
L
×ΔV
OUT
ΔV
OUT
05239-019
Figure 21. Charge Injection
ADG451/ADG452/ADG453
Rev. C | Page 14 of 16
SD
V
S
V
OUT
IN
V
SS
GND
V
L
V
DD
–15V
+15
V
+5
V
R
L
50Ω
0.1µF
0.1µF 0.1µF
V
IN
05239-020
Figure 22. Off Isolation
SD
SD
V
S
NC
V
SS
GND
V
L
V
DD
–15V
+15
V
+5
V
50Ω
0.1µF
0.1µF 0.1µF
V
IN1
V
IN2
V
OUT
05239-021
R
L
50Ω
CHANNEL-TO-CHANNEL CROSSTALK = 20 × log |V
S
/V
OUT
|
Figure 23. Channel-to-Channel Crosstalk
ADG451/ADG452/ADG453
Rev. C | Page 15 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AC
16 9
8
1
4.00 (0.1575)
3.80 (0.1496)
10.00 (0.3937)
9.80 (0.3858)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2283)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8°
0°
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
× 45°
Figure 24. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
PIN 1
0.210
(5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 26. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
ADG451/ADG452/ADG453
Rev. C | Page 16 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG451BN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG451BNZ1−40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG451BR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG451BR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG451BR-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG451BRZ1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG451BRZ-REEL1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG451BRZ-REEL71−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG451BRUZ1−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG451BRUZ- REEL1−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG451BRUZ- REEL71−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG451BCHIPS DIE
ADG452BN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG452BNZ1−40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG452BR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG452BR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG452BR-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG452BRZ1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG452BRZ-REEL1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG452BRZ-REEL71−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG452BRUZ1−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG452BRUZ-REEL1−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG452BRUZ-REEL71−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG453BN −40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG453BNZ1−40°C to +85°C 16-Lead Plastic Dual In-Line Package [PDIP] N-16
ADG453BR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG453BR-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG453BR-REEL7 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG453BRZ1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG453BRZ-REEL1−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG453BRZ-REEL71−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADG453BRUZ1−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG453BRUZ-REEL1−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG453BRUZ-REEL71−40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C05239-0-10/06(C)
