Original Creation Date: 08/24/95
Last Update Date: 09/18/95
Last Major Revision Date: 08/24/95
MNADC0802L-X REV 0A0 MILITARY DATA SHEET
8-BIT uP COMPATIBLE A/D CONVERTER
General Description
The ADC0802, is a CMOS 8-bit successive approximation A/D converter that uses a
differential potentiometric ladder-similar to the 256R products. This converter is
designed to allow operation with the NSC800 and INS8080A derivative control but with
TRI-STATE(R) output latches directly driving the data bus. This A/D appears like memory
locations or I/O ports to the microprocessor and to interfacing logic is needed.
Differential analog voltage inputs allow increasing the common-mode rejection and
offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
NS Part Numbers
ADC0802LJ/883
Industry Part Number
ADC0802L
Prime Die
LC0001D
Controlling Document
5962-9096601MRA REV A
Processing
MIL-STD-883, Method 5004
Quality Conformance Inspection
MIL-STD-883, Method 5005
Subgrp Description Temp ( C)
o
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
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MILITARY DATA SHEET
MNADC0802L-X REV 0A0
Features
- Compatible with 8080uP derivatives-no interfacing logic needed - access time - 135nS
- Easy interface to all microporcessors, or operates "stand alone"
- Differential analog voltage inputs
- Logic inputs and outputs meet both MOS and TTL voltage level specifications
- Works with 2.5V (LM136) voltage reference
- On-chip clock generator
- 0V to 5V analog input voltage range with single 5V supply
- No zero adjust required
- Operates ratiometrically or with 5Vdc, 2.5Vdc, or analog span adjusted voltage reference
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MILITARY DATA SHEET
MNADC0802L-X REV 0A0
(Absolute Maximum Ratings)
(Note 1, 2)
Supply Voltage (Vcc)
(Note 3) 6.5V
Voltage -0.3V to +18VLogic Control Inputs -0.3V to (Vcc+0.3V)At Other Input and Outputs
Lead Temperature (Soldering, 10 seconds) 300 C
Maximum Junction Temperature 150 C
Storage Temperature Range -65 C to +150 C
Package Dissipation at TA = 25 C 875mW
Thermal Resistance
ThetaJA TBD (Still Air) TBD (500LF/Min Air flow)
TBDThetaJC
ESD Susceptibility
(Note 4) 800V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
DC and AC electrical specifications do not apply when operating the device beyond its
specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The
seperate A Gnd point should always be wired to the D Gnd.
Note 3: A zener diode exists, internally, from Vcc to Gnd and has a typical breakdown voltage
of 7Vdc.
Note 4: Human body model, 100pF discharged through a 1.5K Ohm resistor.
Recommended Operating Conditions
(Note 1, 2)
Temperature Range Tmin < TA < Tmax
-55 C < TA < +125 C
Range of Vcc 4.5Vdc to 6.3Vdc
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
DC and AC electrical specifications do not apply when operating the device beyond its
specified operating conditions.
Note 2: All voltages are measured with respect to Gnd, unless otherwise specified. The
seperate A Gnd point should always be wired to the D Gnd.
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MNADC0802L-X REV 0A0 MILITARY DATA SHEET
Electrical Characteristics
DC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vcc = 5V, fCLK = 640KHz.
SYMBOL PARAMETER CONDITIONS NOTES PIN-
NAME MIN MAX UNIT SUB-
GROUPS
Linearity Error Vref/2 = 2.5V -1/2 1/2 LSB 1, 2,
3
Vref/2 Input
Resistance (Pin
9)
2 2.5 30 KOhm 1, 2,
3
Analog Input
Voltage Range 1, 3 -0.05 5.05 v 1, 2,
3
DC Common-Mode
Error Over Analog Input Voltage Range -1/8 1/8 LSB 1, 2,
3
Power Supply
Sensitivity Vcc = 5 +10%, Over Allowed, Vin(+)
Voltage Range 3 -1/8 1/8 LSB 1, 2,
3
Logical "1" Input
Voltage (except
pin 4 CLK in)
Vcc = 5.25V 1 2 15 V 1, 2,
3
Logical "0" Input
Voltage (except
pin 4 CLK in)
Vcc = 4.75V 1 0.8 V 1, 2,
3
Iin(1) Logical "1" Input
Current Vin = 5V 4 1 uA 1, 2,
3
Iin(0) Logical "0" Input
Current Vin = 0V 4 -1.0 uA 1, 2,
3
Vt+ CLK In (pin 4)
Positive Going
Threshold Voltage
1 2.7 3.5 V 1, 2,
3
Vt- CLK In (pin 4)
Negative Going
Threshold Voltage
1 1.5 2.1 V 1, 2,
3
Vh CLK In (pin 4)
Hystersis Vh = (Vh+) - (Vt-) 1 0.6 2.0 V 1, 2,
3
Logic "0" CLK R
Output Voltage Vcc = 4.75V, Io = 360uA 0.4 V 1, 2,
3
Logic "1" CLK R
Output Voltage Vcc = 4.75V, Io = -360uA 2.4 V 1, 2,
3
Logic "0" Output
Voltage: Data
Outputs
Vcc = 4.75V, Iout = 1.6mA 5 0.4 V 1, 2,
3
Logic "0" Output
Voltage:
Intr Output
Vcc = 4.75V, Iout = 1mA 5 0.4 V 1, 2,
3
Logic "1" Output
Voltage: Data
Outputs
Vcc = 4.75V, Iout = -360uA 5 2.4 V 1, 2,
3
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MNADC0802L-X REV 0A0 MILITARY DATA SHEET
Electrical Characteristics
DC PARAMETERS(Continued)
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC: Vcc = 5V, fCLK = 640KHz.
SYMBOL PARAMETER CONDITIONS NOTES PIN-
NAME MIN MAX UNIT SUB-
GROUPS
Logic "1" Output
Voltage:
Intr Output
Vcc = 4.75V, Iout = -360uA 5 2.4 V 1, 2,
3
Logic "1" Output
Voltage: Data
Outputs
Vcc = 4.75V, Iout = -10uA 5 4.5 V 1, 2,
3
Logic "1" Output
Voltage:
Intr Outputs
Vcc = 4.75V, Iout = -10uA 5 4.5 V 1, 2,
3
Tri-State:
Disabled Output
Leakage
Vout = 0V 5 -3.0 uA 1, 2,
3
Tri-State: (All
Data Buffers) Vout = 5V 5 3.0 uA 1, 2,
3
ISOURCE: Data
Output Vout = 0V 5 -30 -4.5 mA 1, 2,
3
ISOURCE:
Intr Output Vout = 0V 5 -30 -4.5 mA 1, 2,
3
ISINK: Data
Outputs Vout = 5V 5 9 50 mA 1, 2,
3
ISINK:
Intr Output Vout = 5V 5 9 50 mA 1, 2,
3
Supply Current
(Includes Ladder
Current)
CS = WR = RD = 5V, Vref/2 = NC, 640KHz 1.8 mA 1, 2,
3
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MNADC0802L-X REV 0A0 MILITARY DATA SHEET
Electrical Characteristics
AC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.)
AC: Vcc = 5V, fCLK = 640KHz.
SYMBOL PARAMETER CONDITIONS NOTES PIN-
NAME MIN MAX UNIT SUB-
GROUPS
Tc Conversion Time
at fCLK = 640KHz fCLK = 640KHz 7 103 114 uS 9
7 95 122 uS 10, 11
Tc Conversion Time (640KHZ) (CNVTIM in seconds) 6, 7 66 73 1/
fCLK 9
6, 7 61781/
fCLK 10, 11
fCLK Clock Frequency 1, 6 1460 KHz 4
1, 6 100 KHz 4
fCLK Clock Duty Cycle 1, 6 40 % 4
1, 6 60 % 4
Conversion Rate
in Free-Running
Mode
INTR tied to WR with CS = 0V,
fCLK = 640KHZ 8770 9708 Conv/
S9
TW(WR)L Width of WR Input
(Start pulse
width)
CS = 0V 1, 8 100 nS 9
tACC Access Time
(Delay from
falling Edge of
RD to Output Data
Vaild)
CL = 100pF 1 0 200 nS 9
TRI-STATE
Control(Delay
from Rising Edge
of RD to HI-Z
State)
RL = 2K Ohms, CL = 100pF 1 0 200 nS 9
Delay from
Falling Edge of
WR or RD to Reset
of INTR
1 450 nS 9
Note 1: Functional test (go-no-go)
Note 2: The Vref/2 pin is the center point of a two resistor divider connected from Vcc to
Gnd, each resistor is 16K. Total ladder input resistance is the sum of these two
equal resistors.
Note 3: For Vin(-) > Vin(+) the digital output code will be 0000,0000. Two on-chip diodes are
tied to each analog input which will forward conduct for analog input voltage one
diode drop below Gnd or one diode drop greater than the Vcc supply. Be careful during
testing at low Vcc levels (4.5V), as high level analog inputs "5V" can cause this
input diode to conduct, especially at elevated temperatures, and cause errors for
analog inputs near full scale. The spec allows 50mV forward bias of either diode.
This means that as long as the analog Vin does not exceed the supply voltage by more
than 50mV, the output code will be correct. To achieve an absolute 0 to 5 Vdc input
voltage range will therefore require a minimum supply voltage of 4.95Vdc over
temperature variations, initial tolerance and loading.
Note 4: Iin(1) and Iin(0) are tested at four pins: CS, RD, WR, CLK.
Note 5: BXVO, BXV1L, BXV1H, BXTRIL, BXTRIH, BXSRC, BXSNK test from bits 0 to 7 (X = 0 to 7).
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MNADC0802L-X REV 0A0 MILITARY DATA SHEET
(Continued)
Note 6: Accuracy is Guaranteed at fCLK= 640KHz. At higher frequencies accuracy can degrade.
For lower clock frequencies,the duty cycle limits can be extended so long as the
minimum clock high time interval minimum clock low time interval is no less than
275nS.
Note 7: With an asynchonous start pulse, up to 8 clock periods may be required before the
internal clock phases are proper to start the conversion process. The start request
is internally latched.
Note 8: The CS input is assumed to bracket the WR strobe input and therefore timing is
dependent on the WR pulse width. An arbitarily wide pulse width will hold the
converter in a reset mode and the start of conversion is initiated by low to high
transition of the WR pulse.
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MILITARY DATA SHEET
MNADC0802L-X REV 0A0
Graphics and Diagrams
GRAPHICS# DESCRIPTION
5743HR CERDIP (J), 20 LEAD (B/I CKT)
J20ARM CERDIP (J), 20 LEAD (P/P DWG)
See attached graphics following this page.
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