M306N4FGTFP#U0 - Renesas Electronics

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Old Company Name in Catalogs and Other Documents

On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

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April 1st, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

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Notice

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M16C/6N Group (M16C/6N4)

Hardware Manual

Rev.2.40 2006.04

Renesas MCU

M16C Family / M16C/60 Series

All information contained in this material, including products and product specifications at the time

of publication of this material, is subject to change by Renesas Electronics Corp. without notice.

Please review the latest information published by Renesas Electronics Corp. through various

means, including the Renesas Electronics Corp. website (http://www.renesas.com).

Keep safety first in your circuit designs!

Notes regarding these materials

•Renesas Technology Corporation puts the maximum effort into making semiconductor prod-

ucts better and more reliable, but there is always the possibility that trouble may occur with

them. Trouble with semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with ap-

propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-

flammable material or (iii) prevention against any malfunction or mishap.

• These materials are intended as a reference to assist our customers in the selection of the

Renesas Technology Corporation product best suited to the customer's application; they do

not convey any license under any intellectual property rights, or any other rights, belonging

to Renesas Technology Corporation or a third party.

• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-

ment of any third-party's rights, originating in the use of any product data, diagrams, charts,

programs, algorithms, or circuit application examples contained in these materials.

• All information contained in these materials, including product data, diagrams, charts, pro-

grams and algorithms represents information on products at the time of publication of these

materials, and are subject to change by Renesas Technology Corporation without notice

due to product improvements or other reasons. It is therefore recommended that custom-

ers contact Renesas Technology Corporation or an authorized Renesas Technology Cor-

poration product distributor for the latest product information before purchasing a product

listed herein.

The information described here may contain technical inaccuracies or typographical errors.

Renesas Technology Corporation assumes no responsibility for any damage, liability, or

other loss rising from these inaccuracies or errors.

Please also pay attention to information published by Renesas Technology Corporation by

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• When using any or all of the information contained in these materials, including product

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General Precautions in the Handling of MPU/MCU Products

The following usa ge notes a re applicable to all MPU/MCU pr o duct s fr om Renesas. For detail ed usage n ote s on the

products covered by this manual, refer to the relevant sect i o ns of the manu al . If the descri pt i ons un der General

Precautions in the Handling of MPU/MCU Produ cts and in the body of the manual differ from each other, the description

in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation with an

unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an

associated shoot-through current flows internally, and malfunctions occur due to the false

recognition of the pin state as an input signal become possible. Unused pins should be handled as

described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register settings and pins

are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states of pins are

not guaranteed from the moment when power is supplied until the reset process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function

are not guaranteed from the moment when power is supplied until the power reaches the level at

which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do not access

these addresses; the correct operation of LSI is not guaranteed if they are accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become stable.

When switching the clock signal during program execution, wait until the target clock signal has

stabilized.

 When the clock signal is generated with an external resonator (or from an external oscillator) during

a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover,

when switching to a clock signal produced with an external resonator (or by an external oscillator)

while program execution is in progress, wait until the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different type number, confirm that the

change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different type numbers may differ

because of the differences in internal memory capacity and layout pattern. When changing to

products of different type numbers, implement a system-evaluation test for each of the products.

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How to Use This Manual

1. Purpose and Target Readers

This manual is designed to provide the user with an understanding of the hardware functions and electrical

characteristics of the MCU. It is intended for users designing application systems incorporating the MCU.

A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.

The manual comprises an overview of the product; descriptions of the CPU, system control functions,

peripheral functions, and electrical characteristics; and usage notes.

Particular attention should be paid to the precautionary notes when using the manual. These notes occur

within the body of the text, at the end of each section, and in the Usage Notes section.

The revision history summarizes the locations of revisions and additions. It does not list all revisions.

Refer to the text of the manual for details.

The following documents apply to the M16C/6N Group (M16C/6N4). Make sure to refer to the latest

versions of these documents. The newest versions of the documents listed may be obtained from the

Renesas Technology Web site.

Document Type Description Document Title Document No.

Datasheet Hardware overview and M16C/6N Group REJ03B0003

electrical characteristics (M16C/6N4)

Datasheet

Hardware manual Hardware specifications (pin assignments, M16C/6N Group This hardware

memory maps, peripheral function specifications, (M16C/6N4) manual

electrical characteristics, timing charts) and Hardware Manual (REJ09B0009)

operation description

Note: Refer to the application notes for details

on using peripheral functions.

Software manual Description of CPU instruction set M16C/60, REJ09B0137

M16C/20,

M16C/Tiny Series

Software Manual

Application note Information on using peripheral functions and Available from Renesas

application examples Technology web site

Sample programs

Information on writing programs in assembly

language and C

Renesas Product specifications, updates on documents,

technical update etc.

2. Notation of Numbers and Symbols

The notation conventions for register names, bit names, numbers, and symbols used in this manual are

described below.

(1) Register Names, Bit Names, and Pin Names

Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the

word “register,” “bit,” or “pin” to distinguish the three categories.

Examples the PM03 bit in the PM0 register

P3_5 pin, VCC pin

(2) Notation of Numbers

The indication “b” is appended to numeric values given in binary format. However, nothing is

appended to the values of single bits. The indication “h” is appended to numeric values given in

hexadecimal format. Nothing is appended to numeric values given in decimal format.

Examples Binary: 11b

Hexadecimal: EFA0h

Decimal: 1234

3. Register Notation

The symbols and terms used in register diagrams are described below.

Blank: Set to 0 or 1 according to the application

0 : Set to 0

1 : Set to 1

X : Nothing is assigned

RW : Read and write

RO : Read only

WO : Write only

– : Nothing is assigned

• Reserved bit

Reserved bit. Set to specified value.

• Nothing is assigned

Nothing is assigned to the bit. As the bit may be used for future functions, if necessary,

set to 0.

• Do not set a value

Operation is not guaranteed when a value is set.

• Function varies depending on operating mode

The function of the bit varies with the peripheral function mode.

Refer to the register diagram for information on the individual modes.

Function

XXX Register

Bit Name

Bit

Symbol

XXX

Address

XXX

After Reset

00h

XXX

(b2)

(b4-b3)

XXX bits

Reserved bits Set to 0

0: XXX

1: XXX

Nothing is assigned. If necessary, set to 0,

When read, the content is undefined.

XXX bits

0 0: XXX

0 1: XXX

1 0: Do not set a value

1 1: XXX

b1 b0

XXX bit

Function varies depending on

operating mode

XXX5

XXX

b7 b6 b5 b4 b3 b2 b1 b0

4. List of Abbreviations and Acronyms

Abbreviation Full Form

ACIA Asynchronous Communication Interface Adapter

bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant Bit

NC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SFR Special Function Registers

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

A-1

Table of Contents

SFR Page Reference ............................................................................................................ B-1

1. Overview ............................................................................................................................... 1

1.1 Applications .................................................................................................................................................. 1

1.2 Performance Overview ................................................................................................................................ 2

1.3 Block Diagram .............................................................................................................................................. 3

1.4 Product Information ...................................................................................................................................... 4

1.5 Pin Assignments .......................................................................................................................................... 5

1.6 Pin Functions ............................................................................................................................................... 9

2. Central Processing Unit (CPU) ........................................................................................... 12

2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................ 12

2.2 Address Registers (A0 and A1) .................................................................................................................. 12

2.3 Frame Base Register (FB) ......................................................................................................................... 13

2.4 Interrupt Table Register (INTB) .................................................................................................................. 13

2.5 Program Counter (PC) ............................................................................................................................... 13

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ........................................................................... 13

2.7 Static Base Register (SB) .......................................................................................................................... 13

2.8 Flag Register (FLG) ................................................................................................................................... 13

2.8.1 Carry Flag (C Flag) ............................................................................................................................ 13

2.8.2 Debug Flag (D Flag) .......................................................................................................................... 13

2.8.3 Zero Flag (Z Flag) .............................................................................................................................. 13

2.8.4 Sign Flag (S Flag) .............................................................................................................................. 13

2.8.5 Register Bank Select Flag (B Flag).................................................................................................... 13

2.8.6 Overflow Flag (O Flag)....................................................................................................................... 13

2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................................. 13

2.8.8 Stack Pointer Select Flag (U Flag)..................................................................................................... 13

2.8.9 Processor Interrupt Priority Level (IPL) .............................................................................................. 13

2.8.10 Reserved Area ................................................................................................................................. 13

3. Memory ............................................................................................................................... 14

4. Special Function Registers (SFRs) ..................................................................................... 15

5. Resets ................................................................................................................................. 31

5.1 Hardware Reset ......................................................................................................................................... 31

5.1.1 Reset on a Stable Supply Voltage ..................................................................................................... 31

5.1.2 Power-on Reset ................................................................................................................................. 31

5.2 Software Reset .......................................................................................................................................... 33

5.3 Watchdog Timer Reset............................................................................................................................... 33

5.4 Oscillation Stop Detection Reset ............................................................................................................... 33

5.5 Internal Space ............................................................................................................................................ 33

6. Processor Mode .................................................................................................................. 34

6.1 Types of Processor Mode .......................................................................................................................... 34

6.2 Setting Processor Modes ........................................................................................................................... 34

7. Bus ...................................................................................................................................... 40

7.1 Bus Mode ................................................................................................................................................... 40

7.1.1 Separate Bus ..................................................................................................................................... 40

7.1.2 Multiplexed Bus.................................................................................................................................. 40

A-2

7.2 Bus Control ................................................................................................................................................ 41

7.2.1 Address Bus ....................................................................................................................................... 41

7.2.2 Data Bus ............................................................................................................................................ 41

7.2.3 Chip Select Signal.............................................................................................................................. 41

7.2.4 Read and Write Signals ..................................................................................................................... 43

7.2.5 ALE Signal ......................................................................................................................................... 43

________

7.2.6 RDY Signal ........................................................................................................................................ 44

__________

7.2.7 HOLD Signal ...................................................................................................................................... 45

7.2.8 BCLK Output ...................................................................................................................................... 45

7.2.9 External Bus Status when Internal Area Accessed ............................................................................ 47

7.2.10 Software Wait................................................................................................................................... 47

8. Clock Generation Circuit .....................................................................................................51

8.1 Types of Clock Generation Circuit.............................................................................................................. 51

8.1.1 Main Clock ......................................................................................................................................... 58

8.1.2 Sub Clock........................................................................................................................................... 59

8.1.3 On-chip Oscillator Clock .................................................................................................................... 60

8.1.4 PLL Clock ........................................................................................................................................... 60

8.2 CPU Clock and Peripheral Function Clock ................................................................................................ 62

8.2.1 CPU Clock and BCLK ........................................................................................................................ 62

8.2.2 Peripheral Function Clock .................................................................................................................. 62

8.3 Clock Output Function ............................................................................................................................... 62

8.4 Power Control ............................................................................................................................................ 63

8.4.1 Normal Operating Mode..................................................................................................................... 63

8.4.2 Wait Mode .......................................................................................................................................... 65

8.4.3 Stop Mode.......................................................................................................................................... 67

8.5 Oscillation Stop and Re-oscillation Detection Function ............................................................................. 72

8.5.1 Operation when CM27 Bit = 0 (Oscillation Stop Detection Reset) ..................................................... 72

8.5.2 Operation when CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) ......................... 72

8.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function .................................................. 73

9. Protection ............................................................................................................................ 74

10. Interrupts ........................................................................................................................... 75

10.1 Type of Interrupts ..................................................................................................................................... 75

10.2 Software Interrupts ................................................................................................................................... 76

10.2.1 Undefined Instruction Interrupt......................................................................................................... 76

10.2.2 Overflow Interrupt ............................................................................................................................ 76

10.2.3 BRK Interrupt ................................................................................................................................... 76

10.2.4 INT Instruction Interrupt ................................................................................................................... 76

10.3 Hardware Interrupts ................................................................................................................................. 77

10.3.1 Special Interrupts ............................................................................................................................. 77

10.3.2 Peripheral Function Interrupts.......................................................................................................... 77

10.4 Interrupts and Interrupt Vector ................................................................................................................. 78

10.4.1 Fixed Vector Tables .......................................................................................................................... 78

10.4.2 Relocatable Vector Tables ............................................................................................................... 79

10.5 Interrupt Control ....................................................................................................................................... 80

10.5.1 I Flag ................................................................................................................................................ 82

10.5.2 IR Bit ................................................................................................................................................ 82

10.5.3 Bits ILVL2 to ILVL0 and IPL ............................................................................................................. 82

A-3

10.5.4 Interrupt Sequence .......................................................................................................................... 83

10.5.5 Interrupt Response Time.................................................................................................................. 84

10.5.6 Variation of IPL when Interrupt Request is Accepted ....................................................................... 84

10.5.7 Saving Registers .............................................................................................................................. 85

10.5.8 Returning from Interrupt Routine ..................................................................................................... 86

10.5.9 Interrupt Priority ............................................................................................................................... 86

10.5.10 Interrupt Priority Level Select Circuit.............................................................................................. 86

______

10.6 INT Interrupt ............................................................................................................................................. 88

______

10.7 NMI Interrupt ............................................................................................................................................ 90

10.8 Key Input Interrupt ................................................................................................................................... 90

10.9 CAN0/1 Wake-up Interrupt ....................................................................................................................... 90

10.10 Address Match Interrupt ......................................................................................................................... 91

11. Watchdog Timer ................................................................................................................ 93

11.1 Count Source Protective Mode ................................................................................................................ 94

12. DMAC................................................................................................................................ 95

12.1 Transfer Cycle ........................................................................................................................................ 100

12.1.1 Effect of Source and Destination Addresses .................................................................................. 100

12.1.2 Effect of BYTE Pin Level................................................................................................................ 100

12.1.3 Effect of Software Wait................................................................................................................... 100

________

12.1.4 Effect of RDY Signal ...................................................................................................................... 100

12.2 DMA Transfer Cycles ............................................................................................................................. 102

12.3 DMA Enable ........................................................................................................................................... 103

12.4 DMA Request ......................................................................................................................................... 103

12.5 Channel Priority and DMA Transfer Timing ........................................................................................... 104

13. Timers ............................................................................................................................. 105

13.1 Timer A ................................................................................................................................................... 107

13.1.1 Timer Mode .................................................................................................................................... 111

13.1.2 Event Counter Mode ...................................................................................................................... 112

13.1.3 One-shot Timer Mode .................................................................................................................... 117

13.1.4 Pulse Width Modulation (PWM) Mode ........................................................................................... 119

13.2 Timer B ................................................................................................................................................... 122

13.2.1 Timer Mode .................................................................................................................................... 125

13.2.2 Event Counter Mode ...................................................................................................................... 126

13.2.3 Pulse Period and Pulse Width Measurement Mode ...................................................................... 127

14. Three-Phase Motor Control Timer Function .................................................................... 130

15. Serial Interface ................................................................................................................ 141

15.1 UARTi ..................................................................................................................................................... 141

15.1.1 Clock Synchronous Serial I/O Mode .............................................................................................. 151

15.1.2 Clock Asynchronous Serial I/O (UART) Mode ............................................................................... 159

15.1.3 Special Mode 1 (I2C Mode) ............................................................................................................ 167

15.1.4 Special Mode 2 .............................................................................................................................. 176

15.1.5 Special Mode 3 (IE Mode) ............................................................................................................. 181

15.1.6 Special Mode 4 (SIM Mode) (UART2) ........................................................................................... 183

15.2 SI/O3 ...................................................................................................................................................... 188

15.2.1 SI/O3 Operation Timing ................................................................................................................. 191

15.2.2 CLK Polarity Selection ................................................................................................................... 191

15.2.3 Functions for Setting SOUT3 Initial Value ...................................................................................... 192

A-4

16. A/D Converter.................................................................................................................. 193

16.1 Mode Description ................................................................................................................................... 197

16.1.1 One-shot Mode .............................................................................................................................. 197

16.1.2 Repeat Mode ................................................................................................................................. 199

16.1.3 Single Sweep Mode ....................................................................................................................... 201

16.1.4 Repeat Sweep Mode 0 .................................................................................................................. 203

16.1.5 Repeat Sweep Mode 1 .................................................................................................................. 205

16.2 Function ................................................................................................................................................. 207

16.2.1 Resolution Select Function ............................................................................................................ 207

16.2.2 Sample and Hold ........................................................................................................................... 207

16.2.3 Extended Analog Input Pins ........................................................................................................... 207

16.2.4 External Operation Amplifier (Op-Amp) Connection Mode ............................................................ 207

16.2.5 Current Consumption Reducing Function ...................................................................................... 208

16.2.6 Output Impedance of Sensor under A/D Conversion ..................................................................... 208

17. D/A Converter.................................................................................................................. 210

18. CRC Calculation.............................................................................................................. 212

19. CAN Module .................................................................................................................... 214

19.1 CAN Module-Related Registers ............................................................................................................. 215

19.1.1 CANi Message Box ........................................................................................................................ 215

19.1.2 Acceptance Mask Registers........................................................................................................... 215

19.1.3 CAN SFR Registers ....................................................................................................................... 215

19.2 CANi Message Box ................................................................................................................................ 216

19.3 Acceptance Mask Registers ................................................................................................................... 218

19.4 CAN SFR Registers ............................................................................................................................... 219

19.5 Operational Modes ................................................................................................................................. 225

19.5.1 CAN Reset/Initialization Mode ....................................................................................................... 225

19.5.2 CAN Operation Mode..................................................................................................................... 226

19.5.3 CAN Sleep Mode ........................................................................................................................... 226

19.5.4 CAN Interface Sleep Mode ............................................................................................................ 226

19.5.5 Bus Off State.................................................................................................................................. 227

19.6 CAN Module System Clock Configuration ............................................................................................. 228

19.7 Bit Timing Configuration ......................................................................................................................... 228

19.8 Bit-rate ................................................................................................................................................... 229

19.8.1 Calculation of Bit-rate..................................................................................................................... 229

19.9 Acceptance Filtering Function and Masking Function ............................................................................ 230

19.10 Acceptance Filter Support Unit (ASU) .................................................................................................. 231

19.11 Basic CAN Mode .................................................................................................................................. 232

19.12 Return from Bus Off Function .............................................................................................................. 233

19.13 Time Stamp Counter and Time Stamp Function .................................................................................. 233

19.14 Listen-Only Mode ................................................................................................................................. 233

19.15 Reception and Transmission ................................................................................................................ 234

19.15.1 Reception ..................................................................................................................................... 235

19.15.2 Transmission ................................................................................................................................ 236

19.16 CAN Interrupt ....................................................................................................................................... 237

A-5

20. Programmable I/O Ports ................................................................................................. 238

20.1 PDi Register ........................................................................................................................................... 238

20.2 Pi Register ............................................................................................................................................. 238

20.3 PURj Register ........................................................................................................................................ 238

20.4 PCR Register ......................................................................................................................................... 239

21. Flash Memory Version .................................................................................................... 251

21.1 Memory Map .......................................................................................................................................... 252

21.1.1 Boot Mode...................................................................................................................................... 252

21.2 Functions to Prevent Flash Memory from Rewriting .............................................................................. 253

21.2.1 ROM Code Protect Function .......................................................................................................... 253

21.2.2 ID Code Check Function ................................................................................................................ 253

21.3 CPU Rewrite Mode ................................................................................................................................ 255

21.3.1 EW0 Mode ..................................................................................................................................... 256

21.3.2 EW1 Mode ..................................................................................................................................... 256

21.3.3 Registers FMR0 and FMR1 ........................................................................................................... 257

21.3.4 Notes on CPU Rewrite Mode ......................................................................................................... 262

21.3.5 Software Commands ..................................................................................................................... 264

21.3.6 Data Protect Function .................................................................................................................... 269

21.3.7 Status Register (SRD Register) ..................................................................................................... 269

21.3.8 Full Status Check ........................................................................................................................... 271

21.4 Standard Serial I/O Mode ...................................................................................................................... 273

21.4.1 ID Code Check Function ................................................................................................................ 273

21.4.2 Example of Circuit Application in Standard Serial I/O Mode .......................................................... 277

21.5 Parallel I/O Mode ................................................................................................................................... 278

21.5.1 User ROM and Boot ROM Areas ................................................................................................... 278

21.5.2 ROM Code Protect Function .......................................................................................................... 278

21.6 CAN I/O Mode ........................................................................................................................................ 279

21.6.1 ID Code Check Function ................................................................................................................ 279

21.6.2 Example of Circuit Application in CAN I/O Mode ........................................................................... 282

21.7 Electrical Characteristics ........................................................................................................................ 283

21.7.1 Electrical Characteristics (T/V-ver.) ................................................................................................ 283

21.7.2 Electrical Characteristics (Normal-ver.) .......................................................................................... 284

22. Electrical Characteristics ................................................................................................. 285

22.1 Electrical Characteristics (T/V-ver.) ........................................................................................................ 285

22.2 Electrical Characteristics (Normal-ver.) .................................................................................................. 306

23. Usage Notes ................................................................................................................... 342

23.1 SFRs ...................................................................................................................................................... 342

23.2 External Bus ........................................................................................................................................... 343

23.3 PLL Frequency Synthesizer ................................................................................................................... 344

23.4 Power Control ........................................................................................................................................ 345

23.5 Protection ............................................................................................................................................... 347

23.6 Interrupts ................................................................................................................................................ 348

23.6.1 Reading Address 00000h............................................................................................................... 348

23.6.2 Setting SP ...................................................................................................................................... 348

_______

23.6.3 NMI Interrupt .................................................................................................................................. 348

23.6.4 Changing Interrupt Source ............................................................................................................. 349

_____

23.6.5 INT Interrupt ................................................................................................................................... 349

23.6.6 Rewrite Interrupt Control Register ................................................................................................. 350

23.6.7 Watchdog Timer Interrupt .............................................................................................................. 350

A-6

23.7 DMAC .................................................................................................................................................... 351

23.7.1 Write to DMAE Bit in DMiCON Register ........................................................................................ 351

23.8 Timers .................................................................................................................................................... 352

23.8.1 Timer A ........................................................................................................................................... 352

23.8.2 Timer B ........................................................................................................................................... 355

23.9 Serial Interface ....................................................................................................................................... 357

23.9.1 Clock Synchronous Serial I/O Mode .............................................................................................. 357

23.9.2 Special Modes ............................................................................................................................... 358

23.9.3 SI/O3 .............................................................................................................................................. 359

23.10 A/D Converter ...................................................................................................................................... 360

23.11 CAN Module ......................................................................................................................................... 362

23.11.1 Reading CiSTR Register .............................................................................................................. 362

23.11.2 Performing CAN Configuration ..................................................................................................... 364

23.11.3 Suggestions to Reduce Power Consumption ............................................................................... 365

23.11.4 CAN Transceiver in Boot Mode .................................................................................................... 366

23.12 Programmable I/O Ports ...................................................................................................................... 367

23.13 Electrical Characteristic Differences between Mask ROM and Flash Memory Version MCUs ............ 368

23.14 Mask ROM Version .............................................................................................................................. 369

23.15 Flash Memory Version ......................................................................................................................... 370

23.15.1 Functions to Prevent Flash Memory from Rewriting .................................................................... 370

23.15.2 Stop Mode.................................................................................................................................... 370

23.15.3 Wait Mode .................................................................................................................................... 370

23.15.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode ................. 370

23.15.5 Writing Command and Data......................................................................................................... 370

23.15.6 Program Command...................................................................................................................... 370

23.15.7 Lock Bit Program Command ........................................................................................................ 370

23.15.8 Operating Speed .......................................................................................................................... 370

23.15.9 Prohibited Instructions ................................................................................................................. 371

23.15.10 Interrupts .................................................................................................................................... 371

23.15.11 How to Access ............................................................................................................................ 371

23.15.12 Rewriting in User ROM Area ...................................................................................................... 371

23.15.13 DMA Transfer ............................................................................................................................. 371

23.16 Flash Memory Programming Using Boot Program .............................................................................. 372

23.16.1 Programming Using Serial I/O Mode ........................................................................................... 372

23.16.2 Programming Using CAN I/O Mode ............................................................................................. 372

23.17 Noise .................................................................................................................................................... 373

Appendix 1. Package Dimensions ........................................................................................ 374

Register Index ....................................................................................................................... 375

Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free

of error. Specifications in this manual may be changed for functional or performance improvements.

Please make sure your manual is the latest edition.

B-1

SFR Page Reference

Address Register Symbol Page

Blank spaces are reserved. No access is allowed.

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

PM0

PM1

CM0

CM1

CSR

AIER

PRCR

CM2

WDTS

WDC

RMAD0

RMAD1

CSE

PLC0

PM2

SAR0

DAR0

TCR0

DM0CON

SAR1

DAR1

TCR1

DM1CON

Processor Mode Register 0

Processor Mode Register 1

System Clock Control Register 0

System Clock Control Register 1

Chip Select Control Register

Address Match Interrupt Enable Register

Protect Register

Oscillation Stop Detection Register

Watchdog Timer Start Register

Watchdog Timer Control Register

Address Match Interrupt Register 0

Address Match Interrupt Register 1

Chip Select Expansion Control Register

PLL Control Register 0

Processor Mode Register 2

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

DMA1 Source Pointer

DMA1 Destination Pointer

DMA1 Transfer Counter

DMA1 Control Register

Address Register Symbol Page

C01WKIC

C0RECIC

C0TRMIC

INT3IC

TB5IC

TB4IC

U1BCNIC

TB3IC

U0BCNIC

C1RECIC

INT5IC

C1TRMIC

S3IC

INT4IC

U2BCNIC

DM0IC

DM1IC

C01ERRIC

ADIC

KUPIC

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

TA3IC

TA4IC

TB0IC

TB1IC

TB2IC

INT0IC

INT1IC

INT2IC

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

CAN0/1 Wake-up Interrupt Control Register

CAN0 Successful Reception Interrupt Control Register

CAN0 Successful Transmission Interrupt Control Register

INT3 Interrupt Control Register

Timer B5 Interrupt Control Register

Timer B4 Interrupt Control Register

UART1 Bus Collision Detection Interrupt Control Register

Timer B3 Interrupt Control Register

UART0 Bus Collision Detection Interrupt Control Register

CAN1 Successful Reception Interrupt Control Register

INT5 Interrupt Control Register

CAN1 Successful Transmission Interrupt Control Register

SI/O3 Interrupt Control Register

INT4 Interrupt Control Register

UART2 Bus Collision Detection Interrupt Control Register

DMA0 Interrupt Control Register

DMA1 Interrupt Control Register

CAN0/1 Error Interrupt Control Register

A/D Conversion Interrupt Control Register

Key Input Interrupt Control Register

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

Timer A3 Interrupt Control Register

Timer A4 Interrupt Control Register

Timer B0 Interrupt Control Register

Timer B1 Interrupt Control Register

Timer B2 Interrupt Control Register

INT0 Interrupt Control Register

INT1 Interrupt Control Register

INT2 Interrupt Control Register

CAN0 Message Box 0: Identifier / DLC

CAN0 Message Box 0: Data Field

CAN0 Message Box 0: Time Stamp

CAN0 Message Box 1: Identifier / DLC

CAN0 Message Box 1: Data Field

CAN0 Message Box 1: Time Stamp

216

217

B-2

Address Register Symbol Page

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

CAN0 Message Box 2: Identifier / DLC

CAN0 Message Box 2: Data Field

CAN0 Message Box 2: Time Stamp

CAN0 Message Box 3: Identifier / DLC

CAN0 Message Box 3: Data Field

CAN0 Message Box 3: Time Stamp

CAN0 Message Box 4: Identifier / DLC

CAN0 Message Box 4: Data Field

CAN0 Message Box 4: Time Stamp

CAN0 Message Box 5: Identifier / DLC

CAN0 Message Box 5: Data Field

CAN0 Message Box 5: Time Stamp

216

217

Address Register Symbol Page

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

CAN0 Message Box 6: Identifier / DLC

CAN0 Message Box 6: Data Field

CAN0 Message Box 6: Time Stamp

CAN0 Message Box 7: Identifier / DLC

CAN0 Message Box 7: Data Field

CAN0 Message Box 7: Time Stamp

CAN0 Message Box 8: Identifier / DLC

CAN0 Message Box 8: Data Field

CAN0 Message Box 8: Time Stamp

CAN0 Message Box 9: Identifier / DLC

CAN0 Message Box 9: Data Field

CAN0 Message Box 9: Time Stamp

216

217

B-3

Address Register Symbol Page

Blank spaces are reserved. No access is allowed.

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

CAN0 Message Box 10: Identifier / DLC

CAN0 Message Box 10: Data Field

CAN0 Message Box 10: Time Stamp

CAN0 Message Box 11: Identifier / DLC

CAN0 Message Box 11: Data Field

CAN0 Message Box 11: Time Stamp

CAN0 Message Box 12: Identifier / DLC

CAN0 Message Box 12: Data Field

CAN0 Message Box 12: Time Stamp

CAN0 Message Box 13: Identifier / DLC

CAN0 Message Box 13: Data Field

CAN0 Message Box 13: Time Stamp

216

217

C0GMR

C0LMAR

C0LMBR

Address Register Symbol Page

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

CAN0 Message Box 14: Identifier /DLC

CAN0 Message Box 14: Data Field

CAN0 Message Box 14: Time Stamp

CAN0 Message Box 15: Identifier /DLC

CAN0 Message Box 15: Data Field

CAN0 Message Box 15: Time Stamp

CAN0 Global Mask Register

CAN0 Local Mask A Register

CAN0 Local Mask B Register

216

217

218

B-4

Blank spaces are reserved. No access is allowed.

FMR1

FMR0

RMAD2

AIER2

RMAD3

Address Register Symbol Page

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

Flash Memory Control Register 1

Flash Memory Control Register 0

Address Match Interrupt Register 2

Address Match Interrupt Enable Register 2

Address Match Interrupt Register 3

257

Address Register Symbol Page

TBSR

TA11

TA21

TA41

INVC0

INVC1

IDB0

IDB1

DTT

ICTB2

TB3

TB4

TB5

TB3MR

TB4MR

TB5MR

IFSR0

IFSR1

S3TRR

S3C

S3BRG

U0SMR4

U0SMR3

U0SMR2

U0SMR

U1SMR4

U1SMR3

U1SMR2

U1SMR

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

U2BRG

U2TB

U2C0

U2C1

U2RB

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

Timer B3, B4, B5 Count Start Flag

Timer A1-1 Register

Timer A2-1 Register

Timer A4-1 Register

Three-Phase PWM Control Register 0

Three-Phase PWM Control Register 1

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

Timer B2 Interrupt Generation Frequency Set Counter

Timer B3 Register

Timer B4 Register

Timer B5 Register

Timer B3 Mode Register

Timer B4 Mode Register

Timer B5 Mode Register

Interrupt Source Select Register 0

Interrupt Source Select Register 1

SI/O3 Transmit/Receive Register

SI/O3 Control Register

SI/O3 Bit Rate Register

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

UART0 Special Mode Register

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

UART1 Special Mode Register

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Register

UART2 Transmit Buffer Register

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

124

135

132

133

134

136

123

125

126

128

189

150

149

148

150

149

148

150

149

148

146

145

146

147

145

B-5

C0MCTL0

C0MCTL1

C0MCTL2

C0MCTL3

C0MCTL4

C0MCTL5

C0MCTL6

C0MCTL7

C0MCTL8

C0MCTL9

C0MCTL10

C0MCTL11

C0MCTL12

C0MCTL13

C0MCTL14

C0MCTL15

C0CTLR

C0STR

C0SSTR

C0ICR

C0IDR

C0CONR

C0RECR

C0TECR

C0TSR

C1MCTL0

C1MCTL1

C1MCTL2

C1MCTL3

C1MCTL4

C1MCTL5

C1MCTL6

C1MCTL7

C1MCTL8

C1MCTL9

C1MCTL10

C1MCTL11

C1MCTL12

C1MCTL13

C1MCTL14

C1MCTL15

C1CTLR

C1STR

C1SSTR

C1ICR

C1IDR

C1CONR

C1RECR

C1TECR

C1TSR

Address Register Symbol Page

Blank spaces are reserved. No access is allowed.

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

020Eh

020Fh

0210h

0211h

0212h

0213h

0214h

0215h

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

021Eh

021Fh

0220h

0221h

0222h

0223h

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

0230h

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh

CAN0 Message Control Register 0

CAN0 Message Control Register 1

CAN0 Message Control Register 2

CAN0 Message Control Register 3

CAN0 Message Control Register 4

CAN0 Message Control Register 5

CAN0 Message Control Register 6

CAN0 Message Control Register 7

CAN0 Message Control Register 8

CAN0 Message Control Register 9

CAN0 Message Control Register 10

CAN0 Message Control Register 11

CAN0 Message Control Register 12

CAN0 Message Control Register 13

CAN0 Message Control Register 14

CAN0 Message Control Register 15

CAN0 Control Register

CAN0 Status Register

CAN0 Slot Status Register

CAN0 Interrupt Control Register

CAN0 Extended ID Register

CAN0 Configuration Register

CAN0 Receive Error Count Register

CAN0 Transmit Error Count Register

CAN0 Time Stamp Register

CAN1 Message Control Register 0

CAN1 Message Control Register 1

CAN1 Message Control Register 2

CAN1 Message Control Register 3

CAN1 Message Control Register 4

CAN1 Message Control Register 5

CAN1 Message Control Register 6

CAN1 Message Control Register 7

CAN1 Message Control Register 8

CAN1 Message Control Register 9

CAN1 Message Control Register 10

CAN1 Message Control Register 11

CAN1 Message Control Register 12

CAN1 Message Control Register 13

CAN1 Message Control Register 14

CAN1 Message Control Register 15

CAN1 Control Register

CAN1 Status Register

CAN1 Slot Status Register

CAN1 Interrupt Control Register

CAN1 Extended ID Register

CAN1 Configuration Register

CAN1 Receive Error Count Register

CAN1 Transmit Error Count Register

CAN1 Time Stamp Register

219

220

221

222

223

224

219

220

221

222

223

224

C0AFS

C1AFS

PCLKR

CCLKR

Address Register Symbol Page

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

0248h

0249h

024Ah

024Bh

024Ch

024Dh

024Eh

024Fh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

0268h

0269h

026Ah

026Bh

026Ch

026Dh

026Eh

026Fh

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

CAN0 Acceptance Filter Support Register

CAN1 Acceptance Filter Support Register

Peripheral Clock Select Register

CAN0/1 Clock Select Register

CAN1 Message Box 0: Identifier / DLC

CAN1 Message Box 0: Data Field

CAN1 Message Box 0:Time Stamp

CAN1 Message Box 1: Identifier / DLC

CAN1 Message Box 1: Data Field

CAN1 Message Box 1:Time Stamp

224

216

217

B-6

Address Register Symbol Page

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

028Ch

028Dh

028Eh

028Fh

0290h

0291h

0292h

0293h

0294h

0295h

0296h

0297h

0298h

0299h

029Ah

029Bh

029Ch

029Dh

029Eh

029Fh

02A0h

02A1h

02A2h

02A3h

02A4h

02A5h

02A6h

02A7h

02A8h

02A9h

02AAh

02ABh

02ACh

02ADh

02AEh

02AFh

02B0h

02B1h

02B2h

02B3h

02B4h

02B5h

02B6h

02B7h

02B8h

02B9h

02BAh

02BBh

02BCh

02BDh

02BEh

02BFh

CAN1 Message Box 2: Identifier / DLC

CAN1 Message Box 2: Data Field

CAN1 Message Box 2: Time Stamp

CAN1 Message Box 3: Identifier / DLC

CAN1 Message Box 3: Data Field

CAN1 Message Box 3: Time Stamp

CAN1 Message Box 4: Identifier / DLC

CAN1 Message Box 4: Data Field

CAN1 Message Box 4: Time Stamp

CAN1 Message Box 5: Identifier / DLC

CAN1 Message Box 5: Data Field

CAN1 Message Box 5: Time Stamp

216

217

Address Register Symbol Page

02C0h

02C1h

02C2h

02C3h

02C4h

02C5h

02C6h

02C7h

02C8h

02C9h

02CAh

02CBh

02CCh

02CDh

02CEh

02CFh

02D0h

02D1h

02D2h

02D3h

02D4h

02D5h

02D6h

02D7h

02D8h

02D9h

02DAh

02DBh

02DCh

02DDh

02DEh

02DFh

02E0h

02E1h

02E2h

02E3h

02E4h

02E5h

02E6h

02E7h

02E8h

02E9h

02EAh

02EBh

02ECh

02EDh

02EEh

02EFh

02F0h

02F1h

02F2h

02F3h

02F4h

02F5h

02F6h

02F7h

02F8h

02F9h

02FAh

02FBh

02FCh

02FDh

02FEh

02FFh

CAN1 Message Box 6: Identifier / DLC

CAN1 Message Box 6: Data Field

CAN1 Message Box 6: Time Stamp

CAN1 Message Box 7: Identifier / DLC

CAN1 Message Box 7: Data Field

CAN1 Message Box 7: Time Stamp

CAN1 Message Box 8: Identifier / DLC

CAN1 Message Box 8: Data Field

CAN1 Message Box 8: Time Stamp

CAN1 Message Box 9: Identifier / DLC

CAN1 Message Box 9: Data Field

CAN1 Message Box 9: Time Stamp

216

217

B-7

Address Register Symbol Page

Blank spaces are reserved. No access is allowed.

0300h

0301h

0302h

0303h

0304h

0305h

0306h

0307h

0308h

0309h

030Ah

030Bh

030Ch

030Dh

030Eh

030Fh

0310h

0311h

0312h

0313h

0314h

0315h

0316h

0317h

0318h

0319h

031Ah

031Bh

031Ch

031Dh

031Eh

031Fh

0320h

0321h

0322h

0323h

0324h

0325h

0326h

0327h

0328h

0329h

032Ah

032Bh

032Ch

032Dh

032Eh

032Fh

0330h

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

033Ah

033Bh

033Ch

033Dh

033Eh

033Fh

CAN1 Message Box 10: Identifier / DLC

CAN1 Message Box 10: Data Field

CAN1 Message Box 10: Time Stamp

CAN1 Message Box 11: Identifier / DLC

CAN1 Message Box 11: Data Field

CAN1 Message Box 11: Time Stamp

CAN1 Message Box 12: Identifier / DLC

CAN1 Message Box 12: Data Field

CAN1 Message Box 12: Time Stamp

CAN1 Message Box 13: Identifier / DLC

CAN1 Message Box 13: Data Field

CAN1 Message Box 13: Time Stamp

216

217

C1GMR

C1LMAR

C1LMBR

Address Register Symbol Page

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

035Eh

035Fh

0360h

0361h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

CAN1 Message Box 14: Identifier / DLC

CAN1 Message Box 14: Data Field

CAN1 Message Box 14: Time Stamp

CAN1 Message Box 15: Identifier / DLC

CAN1 Message Box 15: Data Field

CAN1 Message Box 15: Time Stamp

CAN1 Global Mask Register

CAN1 Local Mask A Register

CAN1 Local Mask B Register

216

217

218

B-8

TABSR

CPSRF

ONSF

TRGSR

UDF

TA0

TA1

TA2

TA3

TA4

TB0

TB1

TB2

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

U0MR

U0BRG

U0TB

U0C0

U0C1

U0RB

U1MR

U1BRG

U1TB

U1C0

U1C1

U1RB

UCON

DM0SL

DM1SL

CRCD

CRCIN

Blank spaces are reserved. No access is allowed.

Address Register Symbol Page

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

039Ah

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

03BDh

03BEh

03BFh

Count Start Flag

Clock Prescaler Reset Flag

One-Shot Start Flag

Trigger Select Register

Up/Down Flag

Timer A0 Register

Timer A1 Register

Timer A2 Register

Timer A3 Register

Timer A4 Register

Timer B0 Register

Timer B1 Register

Timer B2 Register

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

Timer A3 Mode Register

Timer A4 Mode Register

Timer B0 Mode Register

Timer B1 Mode Register

Timer B2 Mode Register

Timer B2 Special Mode Register

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

UART0 Transmit Buffer Register

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Register

UART1 Transmit Buffer Register

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

UART Transmit/Receive Control Register 2

DMA0 Request Source Select Register

DMA1 Request Source Select Register

CRC Data Register

CRC Input Register

109,124,137

110,124

110

110,137

109

108

135

108

135

108

135

123

135

138

136

146

145

146

147

145

146

145

146

147

145

148

212

138

115,138

115

115,138

108

111

113

118

120

123,125

126,128

Address Register Symbol Page

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADCON2

ADCON0

ADCON1

DA0

DA1

DACON

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

P10

PD10

PUR0

PUR1

PUR2

PCR

03C0h

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

03D0h

03D1h

03D2h

03D3h

03D4h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh

A/D Register 0

A/D Register 1

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

A/D Control Register 2

A/D Control Register 0

A/D Control Register 1

D/A Register 0

D/A Register 1

D/A Control Register

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

Port P3 Register

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

Port P5 Register

Port P4 Direction Register

Port P5 Direction Register

Port P6 Register

Port P7 Register

Port P6 Direction Register

Port P7 Direction Register

Port P8 Register

Port P9 Register

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

Port P10 Direction Register

Pull-up Control Register 0

Pull-up Control Register 1

Pull-up Control Register 2

Port Control Register

196

195,198,200

202,204,206

211

246

245

246

245

246

245

246

245

246

245

246

245

247

248

Rev.2.40 Apr 14, 2006 page 1 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4)

Renesas MCU

1. Overview

The M16C/6N Group (M16C/6N4) of MCUs are built using the high-performance silicon gate CMOS process

using the M16C/60 Series CPU core and are packaged in 100-pin plastic molded QFP and LQFP. These

MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of

address space, they are capable of executing instructions at high speed. Being equipped with two CAN

(Controller Area Network) modules in the M16C/6N Group (M16C/6N4), the MCU is suited to drive automotive

and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this MCU

contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable

for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/

logic operations.

1.1 Applications

• Automotive, industrial control systems and other automobile, other (T/V-ver. product)

• Car audio and industrial control systems, other (Normal-ver. product)

Rev.2.40 Apr 14, 2006 page 2 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

Item Specification

Normal-ver. T/V-ver.

CPU Number of fundamental 91 instructions

instructions

Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, 50.0 ns (f(BCLK) = 20 MHz,

execution time

1/1 prescaler, without software wait) 1/1 prescaler, without software wait)

Operating mode Single-chip, memory expansion, and microprocessor modes

Address space 1 Mbyte

Memory capacity Refer to Table 1.2 Product Information

Peripheral Ports Input/Output: 87 pins, Input: 1 pin

Function Multifunction timers Timer A: 16 bits ✕ 5 channels

Timer B: 16 bits ✕ 6 channels

Three-phase motor control circuit

Serial interfaces 3 channels

Clock synchronous, UART, I2C-bus (1), IEBus (2)

1 channel

Clock synchronous

A/D converter 10-bit A/D converter: 1 circuit, 26 channels

D/A converter 8 bits ✕ 2 channels

DMAC 2 channels

CRC calculation circuit CRC-CCITT

CAN module 2 channels with 2.0B specification

Watchdog timer 15 bits ✕ 1 channel (with prescaler)

Interrupts Internal: 31 sources, External: 9 sources

Software: 4 sources, Priority levels: 7 levels

Clock generation circuits 4 circuits

• Main clock oscillation circuit (*)

• Sub clock oscillation circuit (*)

• On-chip oscillator

• PLL frequency synthesizer

(*) Equipped with on-chip feedback resistor

Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function

Electrical Supply voltage

VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,

Characteristics

1/1 prescaler, without software wait) 1/1 prescaler, without software wait)

Consumption Mask ROM 20 mA (f(BCLK) = 24 MHz, 18 mA (f(BCLK) = 20 MHz,

current PLL operation, no division) PLL operation, no division)

Flash memory

22 mA (f(BCLK) = 24 MHz, 20 mA (f(BCLK) = 20 MHz,

PLL operation, no division) PLL operation, no division)

Mask ROM 3 µA

(f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)

Flash memory

0.8 µA (Stop mode, Topr = 25°C)

Flash Memory Programming and erasure voltage

3.0 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V

Version

Programming and erasure endurance

100 times

I/O I/O withstand voltage 5.0 V

Characteristics

Output current 5 mA

Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C

V version: -40 to 125°C

(option)

Device Configuration CMOS high-performance silicon gate

Package 100-pin molded-plastic QFP, LQFP

1.2 Performance Overview

Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N4).

Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N4)

NOTES:

1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V.

2. IEBus is a trademark of NEC Electronics Corporation.

option: All options are on request basis.

Rev.2.40 Apr 14, 2006 page 3 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

1.3 Block Diagram

Figure 1.1 shows a Block Diagram.

Figure 1.1 Block Diagram

NOTES:

1: ROM size depends on MCU type.

2: RAM size depends on MCU type.

Timer (16 bits)

Output (timer A): 5

Input (timer B): 6

Three-phase motor

control circuit

Internal peripheral functions

Watchdog timer

(15 bits)

A/D converter

(10 bits ✕ 8 channels

Expandable up to 26 channels)

UART or

Clock synchronous serial I/O

(3 channels)

System clock generation circuit

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Port P0

Port P1

Port P2

8 8 8 8

Port P6

8788

Port P10

Port P9

Port P8_5

Port P8

Port P7

Port P5Port P4Port P3

CRC calculation circuit (CCITT)

(Polynomial: X

+1)

Clock synchronous serial I/O

(8 bits ✕ 1 channel)

CAN module

(2 channels)

DMAC

(2 channels)

D/A converter

(8 bits ✕ 2 channels)

MemoryM16C/60 Series CPU core

R0H R0L

R1H R1L

Multiplier

INTB

USP

ISP

FLG

ROM

(1)

RAM

(2)

Rev.2.40 Apr 14, 2006 page 4 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

1.4 Product Information

Table 1.2 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages.

Table 1.2 Product Information As of Apr. 2006

Type No.

M30 6N 4

M C T

XXX FP

Package type:

FP: Package PRQP0100JB-A (100P6S-A)

GP: Package PLQP0100KB-A (100P6Q-A)

ROM No.

Omitted on flash memory version

Characteristics

(no): Normal-ver.

T : T-ver. (Automotive 85°C version)

V : V-ver.(Automotive 125°C version)

ROM capacity:

C: 128 Kbytes

G: 256 Kbytes

Memory type:

M: Mask ROM version

F: Flash memory version

Shows the number of CAN module, pin count, etc.

6N Group

M16C Family

NOTES:

1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A).

2. The correspondence between new and old package types is as follows.

PRQP0100JB-A: 100P6S-A

PLQP0100KB-A: 100P6Q-A

Type No. ROM Capacity RAM Capacity Package Type (2) Remarks

M306N4FCFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A Flash Normal-ver.

M306N4FCGP PLQP0100KB-A memory

M306N4FGFP 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A version (1)

M306N4FGGP PLQP0100KB-A

M306N4FCTFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A T-ver.

M306N4FCTGP PLQP0100KB-A

M306N4FGTFP 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A

M306N4FGTGP PLQP0100KB-A

M306N4FCVFP 128 K + 4 Kbytes 5 Kbytes PRQP0100JB-A V-ver.

M306N4FCVGP PLQP0100KB-A

M306N4FGVFP 256 K + 4 Kbytes 10 Kbytes PRQP0100JB-A

M306N4FGVGP PLQP0100KB-A

M306N4MC-XXXGP 128 Kbytes 5 Kbytes PLQP0100KB-A Mask Normal-ver.

M306N4MG-XXXGP 256 Kbytes 10 Kbytes PLQP0100KB-A ROM

M306N4MCT-XXXFP 128 Kbytes 5 Kbytes PRQP0100JB-A version T-ver.

M306N4MCT-XXXGP PLQP0100KB-A

M306N4MGT-XXXFP 256 Kbytes 10 Kbytes PRQP0100JB-A

M306N4MGT-XXXGP PLQP0100KB-A

M306N4MCV-XXXFP 128 Kbytes 5 Kbytes PRQP0100JB-A V-ver.

M306N4MCV-XXXGP PLQP0100KB-A

M306N4MGV-XXXFP 256 Kbytes 10 Kbytes PRQP0100JB-A

M306N4MGV-XXXGP PLQP0100KB-A

Figure 1.2 Type Number, Memory Size, and Package

Rev.2.40 Apr 14, 2006 page 5 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

1.5 Pin Assignments

Figures 1.3 and 1.4 show the Pin Assignment (Top View). Tables 1.3 and 1.4 list the List of Pin Names.

P4_4/CS0

P4_5/CS1

P4_6/CS2

P4_7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P9_6/ANEX1/CTX0

P9_5/ANEX0/CRX0

P9_4/DA1/TB4IN

P9_3/DA0/TB3IN

P9_2/TB2IN/SOUT3

(1)

P9_1/TB1IN/SIN3

P9_0/TB0IN/CLK3

BYTE

CNVSS

P8_7/XCIN

P8_6/XCOUT

RESET

XOUT

VSS

XIN

VCC1

P8_5/NMI

P8_4/INT2/ZP

P8_3/INT1

P8_2/INT0

P8_1/TA4IN/U

P8_0/TA4OUT/U

P7_7/TA3IN/CRX1

P7_6/TA3OUT/CTX1

P7_5/TA2IN/W

P7_4/TA2OUT/W

P7_3/CTS2/RTS2/TA1IN/V

P7_2/CLK2/TA1OUT/V

(1)

P7_1/RXD2/SCL2/TA0IN/TB5IN

P7_0/TXD2/SDA2/TA0OUT

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG

100

P1_0/D8

P1_1/D9

P1_2/D10

P1_3/D11

P1_4/D12

P1_5/D13/INT3

P1_6/D14/INT4

P1_7/D15/INT5

P2_0/AN2_0/A0(/D0/-)

P2_1/AN2_1/A1(/D1/D0)

P2_2/AN2_2/A2(/D2/D1)

P2_3/AN2_3/A3(/D3/D2)

P2_4/AN2_4/A4(/D4/D3)

P2_5/AN2_5/A5(/D5/D4)

P2_6/AN2_6/A6(/D6/D5)

P2_7/AN2_7/A7(/D7/D6)

VSS

P3_0/A8(/-/D7)

VCC2

P3_1/A9

P3_2/A10

P3_3/A11

P3_4/A12

P3_5/A13

P3_6/A14

P3_7/A15

P4_0/A16

P4_1/A17

P4_2/A18

P4_3/A19

M16C/6N Group

(M16C/6N4)

Figure 1.3 Pin Assignments (Top View) (1)

Package: PRQP0100JB-A (100P6S-A)

NOTE:

1. P7_1 and P9_1 are N channel open-drain pins.

Rev.2.40 Apr 14, 2006 page 6 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

Figure 1.4 Pin Assignments (Top View) (2)

100

P0_0/AN0_0/D0

P0_1/AN0_1/D1

P0_2/AN0_2/D2

P0_3/AN0_3/D3

P0_4/AN0_4/D4

P0_5/AN0_5/D5

P0_6/AN0_6/D6

P0_7/AN0_7/D7

P1_0/D8

P1_1/D9

P1_2/D10

P1_3/D11

P1_4/D12

VREF

AVSS

VCC1

XIN

XOUT

VSS

RESET

CNVSS

P8_7/XCIN

P8_6/XCOUT

BYTE P2_0/AN2_0/A0(/D0/-)

P2_1/AN2_1/A1(/D1/D0)

P2_2/AN2_2/A2(/D2/D1)

P2_3/AN2_3/A3(/D3/D2)

P2_4/AN2_4/A4(/D4/D3)

P2_5/AN2_5/A5(/D5/D4)

P2_6/AN2_6/A6(/D6/D5)

P2_7/AN2_7/A7(/D7/D6)

P3_0/A8(/-/D7)

P3_1/A9

P3_2/A10

P3_3/A11

P3_4/A12

P3_5/A13

P3_6/A14

P3_7/A15

P4_0/A16

P4_1/A17

P4_2/A18

P4_3/A19

P7_4/TA2OUT/W

P7_6/TA3OUT/CTX1

P5_6/ALE

P7_7/TA3IN/CRX1

P5_5/HOLD

P5_4/HLDA

P5_3/BCLK

P5_2/RD

VCC2

VSS

P5_7/RDY/CLKOUT

P4_5/CS1

P4_6/CS2

P4_7/CS3

AVCC

P6_3/TXD0/SDA0

P6_5/CLK1

P6_6/RXD1/SCL1

P6_7/TXD1/SDA1

P6_1/CLK0

P6_2/RXD0/SCL0

P10_0/AN0

P10_1/AN1

P10_2/AN2

P10_3/AN3

P9_3/DA0/TB3IN

P9_4/DA1/TB4IN

P9_5/ANEX0/CRX0

P9_6/ANEX1/CTX0

(1)

P9_1/TB1IN/SIN3

P9_2/TB2IN/SOUT3

P8_0/TA4OUT/U

P6_0/CTS0/RTS0

P6_4/CTS1/RTS1/CTS0/CLKS1

P8_2/INT0

P8_3/INT1

P8_5/NMI

P9_7/ADTRG

P4_4/CS0

P5_0/WRL/WR

P5_1/WRH/BHE

P9_0/TB0IN/CLK3

P8_4/INT2/ZP

P7_2/CLK2/TA1OUT/V

P7_1/RXD2/SCL2/TA0IN/TB5IN

(1)

P7_0/TXD2/SDA2/TA0OUT

P7_5/TA2IN/W

P7_3/CTS2/RTS2/TA1IN/V

P1_5/D13/INT3

P1_6/D14/INT4

P1_7/D15/INT5

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P8_1/TA4IN/U

M16C/6N Group

(M16C/6N4)

NOTE:

1. P7_1 and P9_1 are N channel open-drain pins.

Package: PLQP0100KB-A (100P6Q-A)

Rev.2.40 Apr 14, 2006 page 7 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

Table 1.3 List of Pin Names (1)

Pin No. Control Port Interrupt Timer Pin UART Pin Analog

CAN Module

Bus Control Pin

FP GP Pin Pin Pin Pin

1 99 P9_6 ANEX1 CTX0

2 100 P9_5 ANEX0 CRX0

3 1 P9_4 TB4IN DA1

4 2 P9_3 TB3IN DA0

5 3 P9_2 TB2IN SOUT3

6 4 P9_1 TB1IN SIN3

7 5 P9_0 TB0IN CLK3

8 6 BYTE

9 7 CNVSS

10 8 XCIN P8_7

11 9 XCOUT P8_6

12 10

____________

RESET

13 11 XOUT

14 12 VSS

15 13 XIN

16 14 VCC1

17 15 P8_5

_______

NMI

18 16 P8_4

________

INT2 ZP

19 17 P8_3 INT1

20 18 P8_2 INT0

21 19 P8_1

___

TA4IN/U

22 20 P8_0 TA4OUT/U

23 21 P7_7 TA3IN CRX1

24 22 P7_6 TA3OUT CTX1

25 23 P7_5

____

TA2IN/W

26 24 P7_4 TA2OUT/W

27 25 P7_3

___

TA1IN/V

__________ __________

CTS2/RTS2

28 26 P7_2 TA1OUT/V CLK2

29 27 P7_1 TA0IN/TB5IN RXD2/SCL2

30 28 P7_0 TA0OUT TXD2/SDA2

31 29 P6_7 TXD1/SDA1

32 30 P6_6 RXD1/SCL1

33 31 P6_5 CLK1

34 32 P6_4

_________ _________ _________

CTS1/RTS1/CTS0/CLKS1

35 33 P6_3 TXD0/SDA0

36 34 P6_2 RXD0/SCL0

37 35 P6_1 CLK0

38 36 P6_0

__________ __________

CTS0/RTS0

39 37 P5_7

________

RDY/CLKOUT

40 38 P5_6 ALE

41 39 P5_5

__________

HOLD

42 40 P5_4

__________

HLDA

43 41 P5_3 BCLK

44 42 P5_2

_____

45 43 P5_1

_________ ________

WRH/BHE

46 44 P5_0

________ ______

WRL/WR

47 45 P4_7

_______

CS3

48 46 P4_6

_______

CS2

49 47 P4_5

_______

CS1

50 48 P4_4

_______

CS0

FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A)

Rev.2.40 Apr 14, 2006 page 8 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

Pin No. Control Port Interrupt Timer Pin UART Pin Analog

CAN Module

Bus Control Pin

FP GP Pin Pin Pin Pin

51 49 P4_3 A19

52 50 P4_2 A18

53 51 P4_1 A17

54 52 P4_0 A16

55 53 P3_7 A15

56 54 P3_6 A14

57 55 P3_5 A13

58 56 P3_4 A12

59 57 P3_3 A11

60 58 P3_2 A10

61 59 P3_1 A9

62 60 VCC2

63 61 P3_0 A8(/-/D7)

64 62 VSS

65 63 P2_7 AN2_7 A7(/D7/D6)

66 64 P2_6 AN2_6 A6(/D6/D5)

67 65 P2_5 AN2_5 A5(/D5/D4)

68 66 P2_4 AN2_4 A4(/D4/D3)

69 67 P2_3 AN2_3 A3(/D3/D2)

70 68 P2_2 AN2_2 A2(/D2/D1)

71 69 P2_1 AN2_1 A1(/D1/D0)

72 70 P2_0 AN2_0 A0(/D0/-)

73 71 P1_7

________

INT5 D15

74 72 P1_6

________

INT4 D14

75 73 P1_5

________

INT3 D13

76 74 P1_4 D12

77 75 P1_3 D11

78 76 P1_2 D10

79 77 P1_1 D9

80 78 P1_0 D8

81 79 P0_7 AN0_7 D7

82 80 P0_6 AN0_6 D6

83 81 P0_5 AN0_5 D5

84 82 P0_4 AN0_4 D4

85 83 P0_3 AN0_3 D3

86 84 P0_2 AN0_2 D2

87 85 P0_1 AN0_1 D1

88 86 P0_0 AN0_0 D0

89 87 P10_7

______

KI3 AN7

90 88 P10_6

______

KI2 AN6

91 89 P10_5

______

KI1 AN5

92 90 P10_4

______

KI0 AN4

93 91 P10_3 AN3

94 92 P10_2 AN2

95 93 P10_1 AN1

96 94 AVSS

97 95 P10_0 AN0

98 96 VREF

99 97 AVCC

100 98 P9_7

_____________

ADTRG

Table 1.4 List of Pin Names (2)

FP: PRQP0100JB-A (100P6S-A), GP: PLQP0100KB-A (100P6Q-A)

Rev.2.40 Apr 14, 2006 page 9 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

1.6 Pin Functions

Tables 1.5 to 1.7 list the Pin Functions.

Table 1.5 Pin Functions (1)

I/O

VCC1, VCC2,

VSS

AVCC, AVSS

_____________

RESET

CNVSS

BYTE

D0 to D7

D8 to D15

A0 to A19

A0/D0 to A7/D7

A1/D0 to A8/D7

_______ _______

CS0 to CS3

_________ ______

WRL/WR

_________ ________

WRH/BHE

______

ALE

__________

HOLD

__________

HLDA

________

RDY

Power supply

input

Analog power

supply input

Reset input

CNVSS

External data

bus width

select input

Bus control

pins

Apply 4.2 to 5.5 V (T/V-ver.), 3.0 to 5.5 V (Normal-ver.) to the VCC1

and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is

that VCC2 = VCC1 (1).

Applies the power supply for the A/D converter. Connect the AVCC

pin to VCC1. Connect the AVSS pin to VSS.

The MCU is in a reset state when applying “L” to the this pin.

Switches processor mode. Connect this pin to VSS to when after

a reset to start up in single-chip mode. Connect this pin to VCC1

to start up in microprocessor mode.

Switches the data bus in external memory space. The data bus

is 16-bit long when the this pin is held “L” and 8-bit long when

the this pin is held “H”. Set it to either one. Connect this pin to

VSS when single-chip mode.

Inputs and outputs data (D0 to D7) when these pins are set as

the separate bus.

Inputs and outputs data (D8 to D15) when external 16-bit data

bus is set as the separate bus.

Output address bits (A0 to A19).

Input and output data (D0 to D7) and output address bits (A0 to

A7) by time-sharing when external 8-bit data bus are set as the

multiplexed bus.

Input and output data (D0 to D7) and output address bits (A1 to

A8) by time-sharing when external 16-bit data bus are set as the

multiplexed bus.

_______ _______ _______ _______

Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals

to specify an external space.

________ _________ ______ ________ _____ ________ _________

Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or

________ ______

BHE, and WR can be switched by program.

________ _________ _____

• WRL, WRH, and RD are selected

________

The WRL signal becomes “L” by writing data to an even address

in an external memory space.

_________

The WRH signal becomes “L” by writing data to an odd address

in an external memory space.

_____

The RD pin signal becomes “L” by reading data in an external

memory space.

______ ________ _____

• WR, BHE, and RD are selected

______

The WR signal becomes “L” by writing data in an external

memory space.

_____

The RD signal becomes “L” by reading data in an external

memory space.

________

The BHE signal becomes “L” by accessing an odd address.

______ ________ _____

Select WR, BHE, and RD for an external 8-bit data bus.

ALE is a signal to latch the address.

__________

While the HOLD pin is held “L”, the MCU is placed in a hold

state. __________

In a hold state, HLDA outputs a “L” signal.

________

While applying a “L” signal to the RDY pin, the MCU is placed in

a wait state.

Signal Name Pin Name I/O Type Description

I: Input O: Output I/O: Input/Output

NOTE:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

Rev.2.40 Apr 14, 2006 page 10 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

Table 1.6 Pin Functions (2)

I/O

XIN

XOUT

XCIN

XCOUT

BCLK

CLKOUT

________ ________

INT0 to INT5

________

NMI

______ ______

KI0 to KI3

TA0OUT to TA4OUT

TA0IN to TA4IN

TB0IN to TB5IN

___ ___ ____

U, U, V, V, W, W

__________ __________

CTS0 to CTS2

__________ __________

RTS0 to RTS2

CLK0 to CLK3

RXD0 to RXD2

SIN3

TXD0 to TXD2

SOUT3

CLKS1

SDA0 to SDA2

SCL0 to SCL2

VREF

AN0 to AN7

AN0_0 to AN0_7

AN2_0 to AN2_7

_____________

ADTRG

ANEX0

ANEX1

DA0, DA1

CRX0, CRX1

CTX0, CTX1

Main clock

input

Main clock

output

Sub clock

input

Sub clock

output

BCLK output

Clock output

INT interrupt input

_______

NMI interrupt

input

Key input

interrupt input

Timer A

Timer B

Three-phase motor

control output

Serial interface

I2C mode

Reference

voltage input

A/D converter

D/A converter

CAN module

I/O pins for the main clock oscillation circuit. Connect a ceramic

resonator or crystal oscillator between XIN and XOUT (1).

To use the external clock, input the clock from XIN and leave

XOUT open.

I/O pins for a sub clock oscillation circuit. Connect a crystal

oscillator between XCIN and XCOUT (1).

To use the external clock, input the clock from XCIN and leave

XCOUT open.

Outputs the BCLK signal.

The clock of the same cycle as fC, f8, or f32 is output.

______

Input pins for the INT interrupt.

_______

Input pin for the NMI interrupt.

Input pins for the key input interrupt.

These are timer A0 to timer A4 I/O pins.

These are timer A0 to timer A4 input pins.

Input pin for the Z-phase.

These are timer B0 to timer B5 input pins.

These are Three-phase motor control output pins.

These are transmit control input pins.

These are receive control output pins.

These are transfer clock I/O pins.

These are serial data input pins.

These are serial data output pins.

This is output pin for transfer clock output from multiple pins

function.

These are serial data I/O pins.

These are transfer clock I/O pins. (however, SCL2 for the

N-channel open drain output.)

Applies the reference voltage for the A/D converter and D/A

converter.

Analog input pins for the A/D converter.

This is an A/D trigger input pin.

This is the extended analog input pin for the A/D converter,

and is the output in external op-amp connection mode.

This is the extended analog input pin for the A/D converter.

These are the output pins for the D/A converter.

These are the input pins for the CAN module.

These are the output pins for the CAN module.

Signal Name Pin Name I/O Type Description

I: Input O: Output I/O: Input/Output

NOTE:

1. Ask the oscillator maker the oscillation characteristic.

Rev.2.40 Apr 14, 2006 page 11 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 1. Overview

Table 1.7 Pin Functions (3)

8-bit I/O ports in CMOS, having a direction register to select

an input or output.

Each pin is set as an input port or output port. An input port

can be set for a pull-up or for no pull-up in 4-bit unit by

program.

(however, P7_1 and P9_1 for the N-channel open drain

output.)

_______

Input pin for the NMI interrupt.

Pin states can be read by the P8_5 bit in the P8 register.

I/O port

Input port

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_7

P6_0 to P6_7

P7_0 to P7_7

P8_0 to P8_4

P8_6, P8_7

P9_0 to P9_7

P10_0 to P10_7

P8_5

I/O

Signal Name Pin Name I/O Type Description

I: Input O: Output I/O: Input/Output

Rev.2.40 Apr 14, 2006 page 12 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU)

Figure 2.1 CPU Registers

2.1 Data Registers (R0, R1, R2, and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is analogous to R2R0.

2.2 Address Registers (A0 and A1)

The A0 register consists of 16 bits, and is used for address register indirect addressing and address

same as A0.

In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB

configure a register bank. There are two register banks.

USP

ISP

b15 b0

Static Base Register

User Stack Pointer

Interrupt Stack Pointer

b19 b15

INTBLINTBH

The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.

Interrupt Table Register

b19

Program Counter

R0H (R0's high bits) R0L (R0's low bits)

R1H (R1's high bits) R1L (R1's low bits)

b31 b15 b8 b7 b0

Data Registers

(1)

Address Registers

(1)

Frame Base Registers

(1)

NOTE:

1. These registers comprise a register bank. There are two register banks.

b15 b0

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Area

Processor Interrupt Priority Level

Reserved Area

b15 b0

FLG Flag Register

IPL U I O B S Z D C

b7b8

Rev.2.40 Apr 14, 2006 page 13 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 2. Central Processing Unit (CPU)

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

This flag is used exclusively for debugging purpose. During normal use, set to 0.

2.8.3 Zero Flag (Z Flag)

This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.

2.8.4 Sign Flag (S Flag)

This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set

to 0 when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0; USP is selected when the U flag is 1.

The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software

interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level

0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt request is enabled.

2.8.10 Reserved Area

When white to this bit, write 0. When read, its content is undefined.

Rev.2.40 Apr 14, 2006 page 14 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 3. Memory

3. Memory

Figure 3.1 shows a Memory Map. The address space extends the 1 Mbyte from address 00000h to FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a

128-Kbyte internal ROM is allocated to the addresses from E0000h to FFFFFh.

As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is

mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the

start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a

5-Kbyte internal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the

internal RAM also stores the stack used when calling subroutines and when interrupts are generated.

The Special Function Registers (SFRs) are allocated to the addresses from 00000h to 003FFh. Peripheral

function control registers are located here. Of the SFR, any area which has no functions allocated is reserved

for future use and cannot be accessed by user.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by

the JMPS or JSRS instruction. For details, refer to M16C/60, M16C/20, M16C/Tiny Series Software Manual.

In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be

used by users.

Figure 3.1 Memory Map

00000h

YYYYY

FFFFFh

00400h

0FFFFh

10000h

0F000h

27000h

28000h

80000h

XXXXX

Internal ROM

(data flash) (3)

Internal ROM

(program area) (4)

SFR

Internal RAM

Reserved area

External area

Reserved area (2)

External area

FFE00h

FFFDCh

FFFFFh

NOTES:

1. During memory expansion mode or microprocessor mode, cannot be used.

2. In memory expansion mode, cannot be used.

3. As for the flash memory version, 4-Kbyte space (block A) exists.

4. When using the masked ROM version, write nothing to internal ROM area.

5. Shown here is a memory map for the case where the PM10 bit in the PM1 register is 1 (block A enabled, addresses 10000h to

26FFFh for CS2 area) and the PM13 bit in the PM1 register is 1 (internal RAM area is expanded over 192 Kbytes).

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Oscillation stop and re-oscillation

detection / watchdog timer

Reset

Special page

vector table

DBC

NMI

Address XXXXX

Capacity

Internal RAM

10 Kbytes 02BFF

5 Kbytes 017FF

Address YYYYY

Capacity

Internal ROM (4)

256 Kbytes C0000

128 Kbytes E0000

Reserved area (1)

Rev.2.40 Apr 14, 2006 page 15 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

4. Special Function Registers (SFRs)

An SFR (Special Function Register) is a control register for a peripheral function.

Tables 4.1 to 4.16 list the SFR Information.

Table 4.1 SFR Information (1) (3)

0000h

0001h

0002h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

0020h

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

Processor Mode Register 0

(1)

Processor Mode Register 1

System Clock Control Register 0

System Clock Control Register 1

Chip Select Control Register

Address Match Interrupt Enable Register

Protect Register

Oscillation Stop Detection Register

(2)

Watchdog Timer Start Register

Watchdog Timer Control Register

Address Match Interrupt Register 0

Address Match Interrupt Register 1

Chip Select Expansion Control Register

PLL Control Register 0

Processor Mode Register 2

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

DMA1 Source Pointer

DMA1 Destination Pointer

DMA1 Transfer Counter

DMA1 Control Register

PM0

PM1

CM0

CM1

CSR

AIER

PRCR

CM2

WDTS

WDC

RMAD0

RMAD1

CSE

PLC0

PM2

SAR0

DAR0

TCR0

DM0CON

SAR1

DAR1

TCR1

DM1CON

X: Undefined

NOTES:

1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.

2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.

3. Blank spaces are reserved. No access is allowed.

Address Register Symbol After Reset

00000000b (CNVSS pin is "L")

00000011b (CNVSS pin is "H")

00001000b

01001000b

00100000b

00000001b

XXXXXX00b

XX000000b

0X000000b

XXh

00XXXXXXb

00h

X0h

00h

X0h

00h

0001X010b

XXX00000b

XXh

00000X00b

XXh

00000X00b

Rev.2.40 Apr 14, 2006 page 16 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.2 SFR Information (2) (1)

X: Undefined

NOTE:

1. Blank space is reserved. No access is allowed.

XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXXXX000b

XX00X000b

XXh

CAN0/1 Wake-up Interrupt Control Register

CAN0 Successful Reception Interrupt Control Register

CAN0 Successful Transmission Interrupt Control Register

INT3 Interrupt Control Register

Timer B5 Interrupt Control Register

Timer B4 Interrupt Control Register

UART1 Bus Collision Detection Interrupt Control Register

Timer B3 Interrupt Control Register

UART0 Bus Collision Detection Interrupt Control Register

CAN1 Successful Reception Interrupt Control Register

INT5 Interrupt Control Register

CAN1 Successful Transmission Interrupt Control Register

SI/O3 Interrupt Control Register

INT4 Interrupt Control Register

UART2 Bus Collision Detection Interrupt Control Register

DMA0 Interrupt Control Register

DMA1 Interrupt Control Register

CAN0/1 Error Interrupt Control Register

A/D Conversion Interrupt Control Register

Key Input Interrupt Control Register

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

Timer A3 Interrupt Control Register

Timer A4 Interrupt Control Register

Timer B0 Interrupt Control Register

Timer B1 Interrupt Control Register

Timer B2 Interrupt Control Register

INT0 Interrupt Control Register

INT1 Interrupt Control Register

INT2 Interrupt Control Register

CAN0 Message Box 0: Identifier / DLC

CAN0 Message Box 0: Data Field

CAN0 Message Box 0: Time Stamp

CAN0 Message Box 1: Identifier / DLC

CAN0 Message Box 1: Data Field

CAN0 Message Box 1: Time Stamp

0040h

0041h

0042h

0043h

0044h

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

C01WKIC

C0RECIC

C0TRMIC

INT3IC

TB5IC

TB4IC

U1BCNIC

TB3IC

U0BCNIC

C1RECIC

INT5IC

C1TRMIC

S3IC

INT4IC

U2BCNIC

DM0IC

DM1IC

C01ERRIC

ADIC

KUPIC

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

TA3IC

TA4IC

TB0IC

TB1IC

TB2IC

INT0IC

INT1IC

INT2IC

Address Register Symbol After Reset

Rev.2.40 Apr 14, 2006 page 17 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.3 SFR Information (3)

X: Undefined

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

0088h

0089h

008Ah

008Bh

008Ch

008Dh

008Eh

008Fh

0090h

0091h

0092h

0093h

0094h

0095h

0096h

0097h

0098h

0099h

009Ah

009Bh

009Ch

009Dh

009Eh

009Fh

00A0h

00A1h

00A2h

00A3h

00A4h

00A5h

00A6h

00A7h

00A8h

00A9h

00AAh

00ABh

00ACh

00ADh

00AEh

00AFh

00B0h

00B1h

00B2h

00B3h

00B4h

00B5h

00B6h

00B7h

00B8h

00B9h

00BAh

00BBh

00BCh

00BDh

00BEh

00BFh

CAN0 Message Box 2: Identifier / DLC

CAN0 Message Box 2: Data Field

CAN0 Message Box 2: Time Stamp

CAN0 Message Box 3: Identifier / DLC

CAN0 Message Box 3: Data Field

CAN0 Message Box 3: Time Stamp

CAN0 Message Box 4: Identifier / DLC

CAN0 Message Box 4: Data Field

CAN0 Message Box 4: Time Stamp

CAN0 Message Box 5: Identifier / DLC

CAN0 Message Box 5: Data Field

CAN0 Message Box 5: Time Stamp

Address Register Symbol After Reset

XXh

Rev.2.40 Apr 14, 2006 page 18 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.4 SFR Information (4)

X: Undefined

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

00C7h

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

00D5h

00D6h

00D7h

00D8h

00D9h

00DAh

00DBh

00DCh

00DDh

00DEh

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2h

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

CAN0 Message Box 6: Identifier / DLC

CAN0 Message Box 6: Data Field

CAN0 Message Box 6: Time Stamp

CAN0 Message Box 7: Identifier / DLC

CAN0 Message Box 7: Data Field

CAN0 Message Box 7: Time Stamp

CAN0 Message Box 8: Identifier / DLC

CAN0 Message Box 8: Data Field

CAN0 Message Box 8: Time Stamp

CAN0 Message Box 9: Identifier / DLC

CAN0 Message Box 9: Data Field

CAN0 Message Box 9: Time Stamp

Address Register Symbol After Reset

XXh

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.5 SFR Information (5)

X: Undefined

0100h

0101h

0102h

0103h

0104h

0105h

0106h

0107h

0108h

0109h

010Ah

010Bh

010Ch

010Dh

010Eh

010Fh

0110h

0111h

0112h

0113h

0114h

0115h

0116h

0117h

0118h

0119h

011Ah

011Bh

011Ch

011Dh

011Eh

011Fh

0120h

0121h

0122h

0123h

0124h

0125h

0126h

0127h

0128h

0129h

012Ah

012Bh

012Ch

012Dh

012Eh

012Fh

0130h

0131h

0132h

0133h

0134h

0135h

0136h

0137h

0138h

0139h

013Ah

013Bh

013Ch

013Dh

013Eh

013Fh

CAN0 Message Box 10: Identifier / DLC

CAN0 Message Box 10: Data Field

CAN0 Message Box 10: Time Stamp

CAN0 Message Box 11: Identifier / DLC

CAN0 Message Box 11: Data Field

CAN0 Message Box 11: Time Stamp

CAN0 Message Box 12: Identifier / DLC

CAN0 Message Box 12: Data Field

CAN0 Message Box 12: Time Stamp

CAN0 Message Box 13: Identifier / DLC

CAN0 Message Box 13: Data Field

CAN0 Message Box 13: Time Stamp

Address Register Symbol After Reset

XXh

Rev.2.40 Apr 14, 2006 page 20 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.6 SFR Information (6) (1)

X: Undefined

NOTE:

1. Blank spaces are reserved. No access is allowed.

0140h

0141h

0142h

0143h

0144h

0145h

0146h

0147h

0148h

0149h

014Ah

014Bh

014Ch

014Dh

014Eh

014Fh

0150h

0151h

0152h

0153h

0154h

0155h

0156h

0157h

0158h

0159h

015Ah

015Bh

015Ch

015Dh

015Eh

015Fh

0160h

0161h

0162h

0163h

0164h

0165h

0166h

0167h

0168h

0169h

016Ah

016Bh

016Ch

016Dh

016Eh

016Fh

0170h

0171h

0172h

0173h

0174h

0175h

0176h

0177h

0178h

0179h

017Ah

017Bh

017Ch

017Dh

017Eh

017Fh

CAN0 Message Box 14: Identifier /DLC

CAN0 Message Box 14: Data Field

CAN0 Message Box 14: Time Stamp

CAN0 Message Box 15: Identifier /DLC

CAN0 Message Box 15: Data Field

CAN0 Message Box 15: Time Stamp

CAN0 Global Mask Register

CAN0 Local Mask A Register

CAN0 Local Mask B Register

Address Register Symbol After Reset

XXh

C0GMR

C0LMAR

C0LMBR

Rev.2.40 Apr 14, 2006 page 21 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.7 SFR Information (7) (2)

X: Undefined

NOTES:

1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.

2. Blank spaces are reserved. No access is allowed.

0180h

0181h

0182h

0183h

0184h

0185h

0186h

0187h

0188h

0189h

018Ah

018Bh

018Ch

018Dh

018Eh

018Fh

0190h

0191h

0192h

0193h

0194h

0195h

0196h

0197h

0198h

0199h

019Ah

019Bh

019Ch

019Dh

019Eh

019Fh

01A0h

01A1h

01A2h

01A3h

01A4h

01A5h

01A6h

01A7h

01A8h

01A9h

01AAh

01ABh

01ACh

01ADh

01AEh

01AFh

01B0h

01B1h

01B2h

01B3h

01B4h

01B5h

01B6h

01B7h

01B8h

01B9h

01BAh

01BBh

01BCh

01BDh

01BEh

01BFh

Flash Memory Control Register 1

(1)

Flash Memory Control Register 0

(1)

Address Match Interrupt Register 2

Address Match Interrupt Enable Register 2

Address Match Interrupt Register 3

FMR1

FMR0

RMAD2

AIER2

RMAD3

Address Register Symbol After Reset

0X00XX0Xb

00000001b

00h

X0h

XXXXXX00b

00h

X0h

Rev.2.40 Apr 14, 2006 page 22 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.8 SFR Information (8) (1)

Timer B3, B4, B5 Count Start Flag

Timer A1-1 Register

Timer A2-1 Register

Timer A4-1 Register

Three-Phase PWM Control Register 0

Three-Phase PWM Control Register 1

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

Timer B2 Interrupt Generation Frequency Set Counter

Timer B3 Register

Timer B4 Register

Timer B5 Register

Timer B3 Mode Register

Timer B4 Mode Register

Timer B5 Mode Register

Interrupt Source Select Register 0

Interrupt Source Select Register 1

SI/O3 Transmit/Receive Register

SI/O3 Control Register

SI/O3 Bit Rate Register

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

UART0 Special Mode Register

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

UART1 Special Mode Register

UART2 Special Mode Register 4

UART2 Special Mode Register 3

UART2 Special Mode Register 2

UART2 Special Mode Register

UART2 Transmit/Receive Mode Register

UART2 Bit Rate Register

UART2 Transmit Buffer Register

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

UART2 Receive Buffer Register

01C0h

01C1h

01C2h

01C3h

01C4h

01C5h

01C6h

01C7h

01C8h

01C9h

01CAh

01CBh

01CCh

01CDh

01CEh

01CFh

01D0h

01D1h

01D2h

01D3h

01D4h

01D5h

01D6h

01D7h

01D8h

01D9h

01DAh

01DBh

01DCh

01DDh

01DEh

01DFh

01E0h

01E1h

01E2h

01E3h

01E4h

01E5h

01E6h

01E7h

01E8h

01E9h

01EAh

01EBh

01ECh

01EDh

01EEh

01EFh

01F0h

01F1h

01F2h

01F3h

01F4h

01F5h

01F6h

01F7h

01F8h

01F9h

01FAh

01FBh

01FCh

01FDh

01FEh

01FFh

Address Register Symbol After Reset

TBSR

TA11

TA21

TA41

INVC0

INVC1

IDB0

IDB1

DTT

ICTB2

TB3

TB4

TB5

TB3MR

TB4MR

TB5MR

IFSR0

IFSR1

S3TRR

S3C

S3BRG

U0SMR4

U0SMR3

U0SMR2

U0SMR

U1SMR4

U1SMR3

U1SMR2

U1SMR

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

U2BRG

U2TB

U2C0

U2C1

U2RB

000XXXXXb

XXh

00h

00111111b

XXh

00XX0000b

00XXX000b

00h

XXh

01000000b

XXh

00h

000X0X0Xb

X0000000b

00h

000X0X0Xb

X0000000b

00h

000X0X0Xb

X0000000b

00h

XXh

00001000b

00000010b

XXh

X: Undefined

NOTE:

1. Blank spaces are reserved. No access is allowed.

Rev.2.40 Apr 14, 2006 page 23 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

X: Undefined

0200h

0201h

0202h

0203h

0204h

0205h

0206h

0207h

0208h

0209h

020Ah

020Bh

020Ch

020Dh

020Eh

020Fh

0210h

0211h

0212h

0213h

0214h

0215h

0216h

0217h

0218h

0219h

021Ah

021Bh

021Ch

021Dh

021Eh

021Fh

0220h

0221h

0222h

0223h

0224h

0225h

0226h

0227h

0228h

0229h

022Ah

022Bh

022Ch

022Dh

022Eh

022Fh

0230h

0231h

0232h

0233h

0234h

0235h

0236h

0237h

0238h

0239h

023Ah

023Bh

023Ch

023Dh

023Eh

023Fh

CAN0 Message Control Register 0

CAN0 Message Control Register 1

CAN0 Message Control Register 2

CAN0 Message Control Register 3

CAN0 Message Control Register 4

CAN0 Message Control Register 5

CAN0 Message Control Register 6

CAN0 Message Control Register 7

CAN0 Message Control Register 8

CAN0 Message Control Register 9

CAN0 Message Control Register 10

CAN0 Message Control Register 11

CAN0 Message Control Register 12

CAN0 Message Control Register 13

CAN0 Message Control Register 14

CAN0 Message Control Register 15

CAN0 Control Register

CAN0 Status Register

CAN0 Slot Status Register

CAN0 Interrupt Control Register

CAN0 Extended ID Register

CAN0 Configuration Register

CAN0 Receive Error Count Register

CAN0 Transmit Error Count Register

CAN0 Time Stamp Register

CAN1 Message Control Register 0

CAN1 Message Control Register 1

CAN1 Message Control Register 2

CAN1 Message Control Register 3

CAN1 Message Control Register 4

CAN1 Message Control Register 5

CAN1 Message Control Register 6

CAN1 Message Control Register 7

CAN1 Message Control Register 8

CAN1 Message Control Register 9

CAN1 Message Control Register 10

CAN1 Message Control Register 11

CAN1 Message Control Register 12

CAN1 Message Control Register 13

CAN1 Message Control Register 14

CAN1 Message Control Register 15

CAN1 Control Register

CAN1 Status Register

CAN1 Slot Status Register

CAN1 Interrupt Control Register

CAN1 Extended ID Register

CAN1 Configuration Register

CAN1 Receive Error Count Register

CAN1 Transmit Error Count Register

CAN1 Time Stamp Register

C0MCTL0

C0MCTL1

C0MCTL2

C0MCTL3

C0MCTL4

C0MCTL5

C0MCTL6

C0MCTL7

C0MCTL8

C0MCTL9

C0MCTL10

C0MCTL11

C0MCTL12

C0MCTL13

C0MCTL14

C0MCTL15

C0CTLR

C0STR

C0SSTR

C0ICR

C0IDR

C0CONR

C0RECR

C0TECR

C0TSR

C1MCTL0

C1MCTL1

C1MCTL2

C1MCTL3

C1MCTL4

C1MCTL5

C1MCTL6

C1MCTL7

C1MCTL8

C1MCTL9

C1MCTL10

C1MCTL11

C1MCTL12

C1MCTL13

C1MCTL14

C1MCTL15

C1CTLR

C1STR

C1SSTR

C1ICR

C1IDR

C1CONR

C1RECR

C1TECR

C1TSR

Address Register Symbol After Reset

00h

X0000001b

XX0X0000b

00h

X0000001b

00h

XXh

00h

X0000001b

XX0X0000b

00h

X0000001b

00h

XXh

00h

Table 4.9 SFR Information (9)

Rev.2.40 Apr 14, 2006 page 24 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

X: Undefined

NOTE:

1. Blank spaces are reserved. No access is allowed.

XXh

00h

XXh

CAN0 Acceptance Filter Support Register

CAN1 Acceptance Filter Support Register

Peripheral Clock Select Register

CAN0/1 Clock Select Register

CAN1 Message Box 0: Identifier / DLC

CAN1 Message Box 0: Data Field

CAN1 Message Box 0:Time Stamp

CAN1 Message Box 1: Identifier / DLC

CAN1 Message Box 1: Data Field

CAN1 Message Box 1:Time Stamp

0240h

0241h

0242h

0243h

0244h

0245h

0246h

0247h

0248h

0249h

024Ah

024Bh

024Ch

024Dh

024Eh

024Fh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

025Fh

0260h

0261h

0262h

0263h

0264h

0265h

0266h

0267h

0268h

0269h

026Ah

026Bh

026Ch

026Dh

026Eh

026Fh

0270h

0271h

0272h

0273h

0274h

0275h

0276h

0277h

0278h

0279h

027Ah

027Bh

027Ch

027Dh

027Eh

027Fh

C0AFS

C1AFS

PCLKR

CCLKR

Address Register Symbol After Reset

Table 4.10 SFR Information (10) (1)

Rev.2.40 Apr 14, 2006 page 25 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.11 SFR Information (11)

X: Undefined

0280h

0281h

0282h

0283h

0284h

0285h

0286h

0287h

0288h

0289h

028Ah

028Bh

028Ch

028Dh

028Eh

028Fh

0290h

0291h

0292h

0293h

0294h

0295h

0296h

0297h

0298h

0299h

029Ah

029Bh

029Ch

029Dh

029Eh

029Fh

02A0h

02A1h

02A2h

02A3h

02A4h

02A5h

02A6h

02A7h

02A8h

02A9h

02AAh

02ABh

02ACh

02ADh

02AEh

02AFh

02B0h

02B1h

02B2h

02B3h

02B4h

02B5h

02B6h

02B7h

02B8h

02B9h

02BAh

02BBh

02BCh

02BDh

02BEh

02BFh

CAN1 Message Box 2: Identifier / DLC

CAN1 Message Box 2: Data Field

CAN1 Message Box 2: Time Stamp

CAN1 Message Box 3: Identifier / DLC

CAN1 Message Box 3: Data Field

CAN1 Message Box 3: Time Stamp

CAN1 Message Box 4: Identifier / DLC

CAN1 Message Box 4: Data Field

CAN1 Message Box 4: Time Stamp

CAN1 Message Box 5: Identifier / DLC

CAN1 Message Box 5: Data Field

CAN1 Message Box 5: Time Stamp

Address Register Symbol After Reset

XXh

Rev.2.40 Apr 14, 2006 page 26 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.12 SFR Information (12)

X: Undefined

02C0h

02C1h

02C2h

02C3h

02C4h

02C5h

02C6h

02C7h

02C8h

02C9h

02CAh

02CBh

02CCh

02CDh

02CEh

02CFh

02D0h

02D1h

02D2h

02D3h

02D4h

02D5h

02D6h

02D7h

02D8h

02D9h

02DAh

02DBh

02DCh

02DDh

02DEh

02DFh

02E0h

02E1h

02E2h

02E3h

02E4h

02E5h

02E6h

02E7h

02E8h

02E9h

02EAh

02EBh

02ECh

02EDh

02EEh

02EFh

02F0h

02F1h

02F2h

02F3h

02F4h

02F5h

02F6h

02F7h

02F8h

02F9h

02FAh

02FBh

02FCh

02FDh

02FEh

02FFh

CAN1 Message Box 6: Identifier / DLC

CAN1 Message Box 6: Data Field

CAN1 Message Box 6: Time Stamp

CAN1 Message Box 7: Identifier / DLC

CAN1 Message Box 7: Data Field

CAN1 Message Box 7: Time Stamp

CAN1 Message Box 8: Identifier / DLC

CAN1 Message Box 8: Data Field

CAN1 Message Box 8: Time Stamp

CAN1 Message Box 9: Identifier / DLC

CAN1 Message Box 9: Data Field

CAN1 Message Box 9: Time Stamp

Address Register Symbol After Reset

XXh

Rev.2.40 Apr 14, 2006 page 27 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.13 SFR Information (13)

X: Undefined

0300h

0301h

0302h

0303h

0304h

0305h

0306h

0307h

0308h

0309h

030Ah

030Bh

030Ch

030Dh

030Eh

030Fh

0310h

0311h

0312h

0313h

0314h

0315h

0316h

0317h

0318h

0319h

031Ah

031Bh

031Ch

031Dh

031Eh

031Fh

0320h

0321h

0322h

0323h

0324h

0325h

0326h

0327h

0328h

0329h

032Ah

032Bh

032Ch

032Dh

032Eh

032Fh

0330h

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

033Ah

033Bh

033Ch

033Dh

033Eh

033Fh

CAN1 Message Box 10: Identifier / DLC

CAN1 Message Box 10: Data Field

CAN1 Message Box 10: Time Stamp

CAN1 Message Box 11: Identifier / DLC

CAN1 Message Box 11: Data Field

CAN1 Message Box 11: Time Stamp

CAN1 Message Box 12: Identifier / DLC

CAN1 Message Box 12: Data Field

CAN1 Message Box 12: Time Stamp

CAN1 Message Box 13: Identifier / DLC

CAN1 Message Box 13: Data Field

CAN1 Message Box 13: Time Stamp

Address Register Symbol After Reset

XXh

Rev.2.40 Apr 14, 2006 page 28 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

Table 4.14 SFR Information (14) (1)

X: Undefined

NOTE:

1. Blank spaces are reserved. No access is allowed.

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

035Eh

035Fh

0360h

0361h

0362h

0363h

0364h

0365h

0366h

0367h

0368h

0369h

036Ah

036Bh

036Ch

036Dh

036Eh

036Fh

0370h

0371h

0372h

0373h

0374h

0375h

0376h

0377h

0378h

0379h

037Ah

037Bh

037Ch

037Dh

037Eh

037Fh

CAN1 Message Box 14: Identifier / DLC

CAN1 Message Box 14: Data Field

CAN1 Message Box 14: Time Stamp

CAN1 Message Box 15: Identifier / DLC

CAN1 Message Box 15: Data Field

CAN1 Message Box 15: Time Stamp

CAN1 Global Mask Register

CAN1 Local Mask A Register

CAN1 Local Mask B Register

Address Register Symbol After Reset

XXh

C1GMR

C1LMAR

C1LMBR

Rev.2.40 Apr 14, 2006 page 29 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

X: Undefined

NOTES:

1. Bits TA2P to TA4P in the UDF register are set to 0 after reset. However, the contents in these bits are undefined when read.

2. Blank spaces are reserved. No access is allowed.

0380h

0381h

0382h

0383h

0384h

0385h

0386h

0387h

0388h

0389h

038Ah

038Bh

038Ch

038Dh

038Eh

038Fh

0390h

0391h

0392h

0393h

0394h

0395h

0396h

0397h

0398h

0399h

039Ah

039Bh

039Ch

039Dh

039Eh

039Fh

03A0h

03A1h

03A2h

03A3h

03A4h

03A5h

03A6h

03A7h

03A8h

03A9h

03AAh

03ABh

03ACh

03ADh

03AEh

03AFh

03B0h

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

03B9h

03BAh

03BBh

03BCh

03BDh

03BEh

03BFh

Count Start Flag

Clock Prescaler Reset Flag

One-Shot Start Flag

Trigger Select Register

Up/Down Flag

Timer A0 Register

Timer A1 Register

Timer A2 Register

Timer A3 Register

Timer A4 Register

Timer B0 Register

Timer B1 Register

Timer B2 Register

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

Timer A3 Mode Register

Timer A4 Mode Register

Timer B0 Mode Register

Timer B1 Mode Register

Timer B2 Mode Register

Timer B2 Special Mode Register

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Register

UART0 Transmit Buffer Register

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Register

UART1 Transmit Buffer Register

UART1 Transmit/Receive Control Register 0

UART1 Transmit/Receive Control Register 1

UART1 Receive Buffer Register

UART Transmit/Receive Control Register 2

DMA0 Request Source Select Register

DMA1 Request Source Select Register

CRC Data Register

CRC Input Register

TABSR

CPSRF

ONSF

TRGSR

UDF

TA0

TA1

TA2

TA3

TA4

TB0

TB1

TB2

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

U0MR

U0BRG

U0TB

U0C0

U0C1

U0RB

U1MR

U1BRG

U1TB

U1C0

U1C1

U1RB

UCON

DM0SL

DM1SL

CRCD

CRCIN

Address Register Symbol After Reset

00h

0XXXXXXXb

00h

XXh

00h

00XX0000b

XXXXXX00b

00h

XXh

00001000b

00XX0010b

XXh

00h

XXh

00001000b

00XX0010b

XXh

X0000000b

00h

XXh

(1)

Table 4.15 SFR Information (15) (2)

Rev.2.40 Apr 14, 2006 page 30 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 4. Special Function Registers (SFRs)

X: Undefined

NOTES:

1. At hardware reset, the register is as follows:

00000000b where "L" is input to the CNVSS pin

00000010b where "H" is input to the CNVSS pin

At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:

00000000b where bits PM01 to PM00 in the PM0 register are 00b (single-chip mode)

00000010b where bits PM01 to PM00 in the PM0 register are 01b (memory expansion mode) or 11b (microprocessor mode)

2. Blank spaces are reserved. No access is allowed.

03C0h

03C1h

03C2h

03C3h

03C4h

03C5h

03C6h

03C7h

03C8h

03C9h

03CAh

03CBh

03CCh

03CDh

03CEh

03CFh

03D0h

03D1h

03D2h

03D3h

03D4h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

03FEh

03FFh

A/D Register 0

A/D Register 1

A/D Register 2

A/D Register 3

A/D Register 4

A/D Register 5

A/D Register 6

A/D Register 7

A/D Control Register 2

A/D Control Register 0

A/D Control Register 1

D/A Register 0

D/A Register 1

D/A Control Register

Port P0 Register

Port P1 Register

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

Port P3 Register

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

Port P5 Register

Port P4 Direction Register

Port P5 Direction Register

Port P6 Register

Port P7 Register

Port P6 Direction Register

Port P7 Direction Register

Port P8 Register

Port P9 Register

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

Port P10 Direction Register

Pull-up Control Register 0

Pull-up Control Register 1

Pull-up Control Register 2

Port Control Register

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ADCON2

ADCON0

ADCON1

DA0

DA1

DACON

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

P10

PD10

PUR0

PUR1

PUR2

PCR

Address Register Symbol After Reset

XXh

00h

00000XXXb

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00X00000b

00h

XXh

00h

00000000b (1)

00000010b

00h

Table 4.16 SFR Information (16) (2)

Rev.2.40 Apr 14, 2006 page 31 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 5. Resets

5. Resets

Hardware reset, software reset, watchdog timer reset, and oscillation stop detection reset are available to

reset the MCU.

5.1 Hardware Reset ____________

The MCU resets pins, the CPU and SFR by setting the RESET pin. If the supply voltage meets the

___________

recommended operating conditions, the MCU resets all pins when an “L” signal is applied to the RESET pin

____________

(see Table 5.1 Pin Status When RESET Pin Level is “L”). The oscillation circuit is also reset and the main

____________

clock starts oscillation. The MCU resets the CPU and SFR when the signal applied to the RESET pin

changes low (“L”) to high (“H”). The MCU executes the program in an address indicated by the reset vector.

____________

The internal RAM is not reset. When an “L” signal is applied to the RESET pin while writing data to the

internal RAM, the internal RAM is in an undefined state.

Figure 5.1 shows an Example Reset Circuit. Figure 5.2 shows a Reset Sequence. Table 5.1 lists the Pin

____________

States when RESET Pin Level is “L”.

5.1.1 Reset on a Stable Supply Voltage

____________

(1) Apply “L” to the RESET pin

(2) Apply 20 or more clock cycles to the XIN pin

____________

(3) Apply “H” to the RESET pin

5.1.2 Power-on Reset

____________

(1) Apply “L” to the RESET pin

(2) Raise the supply voltage to the recommended operating level

(3) Insert td(P-R) ms as wait time for the internal voltage to stabilize

(4) Apply 20 or more clock cycles to the XIN pin

____________

(5) Apply “H” to the RESET pin

Figure 5.1 Example Reset Circuit

RESET VCC

VCC

Supply a clock with td(P-R) +20

or more cycles to the XIN pin

0.2 VCC or

below 0.2 VCC or below

operation

NOTE

1. Use the shortest possible wiring to connect external circuit.

0 V

Rev.2.40 Apr 14, 2006 page 32 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 5. Resets

Figure 5.2 Reset Sequence

____________

Table 5.1 Pin Status when RESET Pin Level is “L”

td(P-R) More than

20 cycles

are needed

BCLK

Address

XIN

RESET

CS0

Content of reset vector

BCLK 28cycles

FFFFCh FFFFDh FFFFEh

Content of reset vector

FFFFCh FFFFEh

Content of reset vector

FFFFEh

FFFFCh

VCC

Single-chip

mode

Microprocessor

mode BYTE = H

Microprocessor

mode BYTE = L

Addres

P0 Input port Data input Data input

P1 Input port Data input Input port

P2, P3, P4_0 to P4_3 Input port Address output (undefined) Address output (undefined)

P4_4 Input port

______

CS0 output (“H” is output)

______

CS0 output (“H” is output)

P4_5 to P4_7 Input port Input port (Pulled high) Input port (Pulled high)

P5_0 Input port

______

WR output (“H” is output)

______

WR output (“H” is output)

P5_1 Input port

________

BHE output (undefined)

________

BHE output (undefined)

P5_2 Input port

______

RD output (“H” is output)

______

RD output (“H” is output)

P5_3 Input port BCLK output BCLK output

P5_4 Input port

___________

HLDA output

___________

HLDA output

(The output value depends on (The output value depends on

__________

the input to the HOLD pin)

__________

the input to the HOLD pin)

P5_5 Input port

__________

HOLD input

__________

HOLD input

P5_6 Input port ALE output (“L” is output) ALE output (“L” is output)

P5_7 Input port

________

RDY input

________

RDY input

P6, P7, P8_0 to P8_4, Input port Input port Input port

P8_6, P8_7, P9, P10

Pin Name

Status

CNVSS = VCC (1)

BYTE = VSS BYTE = VCC

CNVSS = VSS

NOTE:

1. Shown here is the valid pin state when the internal power supply voltage has stabilized after power-on.

When CNVSS = VCC, the pin state is undefined until the internal power supply voltage stabilizes.

Rev.2.40 Apr 14, 2006 page 33 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 5. Resets

Figure 5.3 CPU Register Status After Reset

0000h

b15 b0

Static Base Register (SB)

User Stack Pointer (USP)

Interrupt Stack Pointer (ISP)

b19

00000h

Interrupt Table Register (INTB)

Content of addresses FFFFEh to FFFFCh Program Counter (PC)

b15 b0

0000h

Data Register (R0)

Data Register (R1)

Data Register (R2)

Data Register (R3)

Address Register (A0)

Address Register (A1)

Frame Base Register (FB)

b15 b0

0000h Flag Register (FLG)

IPL U I O B S Z D C

b7b8

5.2 Software Reset

The MCU resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to 1 (MCU reset).

Then the MCU executes the program in an address determined by the reset vector.

Set the PM03 bit to 1 while the main clock is selected as the CPU clock and the main clock oscillation is stable.

In the software reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function Registers

(SFRs) for details.

Processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.

5.3 Watchdog Timer Reset

The MCU resets pins, the CPU and SFR when the PM12 bit in the PM1 register is set to 1 (reset when

watchdog timer underflows) and the watchdog timer underflows. Then the MCU executes the program in an

address determined by the reset vector.

In the watchdog timer reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function

Registers (SFRs) for details.

Processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.

5.4 Oscillation Stop Detection Reset

The MCU resets and stops pins, the CPU and SFR when the CM27 bit in the CM2 register is 0 (reset at

oscillation stop, re-oscillation detection), if it detects main clock oscillation circuit stop. Refer to 8.5 Oscillation

Stop and Re-Oscillation Detection Function for details.

In the oscillation stop detection reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function

Registers (SFRs) for details.

Processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.

5.5 Internal Space

Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Registers (SFRs) for

SFR states after reset.

Rev.2.40 Apr 14, 2006 page 34 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 6. Processor Mode

6. Processor Mode

6.1 Types of Processor Mode

Three processor modes are available to choose from: single-chip mode, memory expansion mode, and

microprocessor mode. Table 6.1 shows the Features of Processor Modes.

Table 6.1 Features of Processor Modes

Processor Mode Access Space Pins Which are Assigned I/O Ports

Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or

peripheral function I/O pins

Memory expansion mode SFR, internal RAM, internal ROM, Some pins serve as bus control pins (1)

external area (1)

Microprocessor mode SFR, internal RAM, external area (1) Some pins serve as bus control pins (1)

NOTE:

1. Refer to 7. Bus.

6.2 Setting Processor Modes

Processor mode is set by using the CNVSS pin and bits PM01 to PM00 in the PM0 register.

Table 6.2 shows the Processor Mode after Hardware Reset. Table 6.3 shows Bits PM01 to PM00 Set

Values and Processor Modes.

Table 6.2 Processor Mode after Hardware Reset

CNVSS Pin Input Level Processor Mode

VSS Single-chip mode

VCC (1) (2) Microprocessor mode

Bits PM01 to PM00 Processor Mode

00b Single-chip mode

01b Memory expansion mode

10b Do not set a value

11b Microprocessor mode

NOTES:

1. If the MCU is reset in hardware by applying VCC to the CNVSS pin, the internal ROM cannot be

accessed regardless of bits PM01 to PM00.

_____

The multiplexed bus cannot be assigned to the entire CS space.

Table 6.3 Bits PM01 to PM00 Set Values and Processor Modes

Rewriting bits PM01 to PM00 places the MCU in the corresponding processor mode regardless of whether

the input level on the CNVSS pin is “H” or “L”. Note, however, that bits PM01 to PM00 cannot be rewritten

to 01b (memory expansion mode) or 11b (microprocessor mode) at the same time bits PM07 to PM02 are

rewritten. Note also that these bits cannot be rewritten to enter microprocessor mode in the internal ROM,

nor can they be rewritten to exit microprocessor mode in areas overlapping the internal ROM.

If the MCU is reset in hardware by applying VCC to the CNVSS pin (hardware reset), the internal ROM

cannot be accessed regardless of bits PM01 to PM00.

Figures 6.1 and 6.2 show the PM0 Register and PM1 Register. Figure 6.3 shows the Memory Map in

_____

Single-chip Mode. Figures 6.4 to 6.7 show the Memory Map and CS Area in Memory Expansion Mode and

Microprocessor Mode.

Rev.2.40 Apr 14, 2006 page 35 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 6. Processor Mode

Figure 6.1 PM0 Register

NOTES:

1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. Bits PM01 to PM00 do not change at software reset, watchdog timer reset and oscillation stop detection reset.

3. Effective when bits PM01 to PM00 are set to 01b (memory expansion mode) or 11b (microprocessor mode).

4. To set bits PM01 to PM00 are 01b and bits PM05 to PM04 are 11b (multiplexed bus assigned to the entire

CS space), apply an "H" signal to the BYTE pin (external data bus is 8-bit width).

While the CNVSS pin is held "H" (VCC), do not rewrite bits PM05 to PM04 to 11b after reset.

If bits PM05 to PM04 are set to 11b during memory expansion mode, P3_1 to P3_7 and P4_0 to P4_3 become

I/O ports, in which case the accessible area for each CS is 256 bytes.

Processor Mode Register 0 (1)

Symbol Address

Bit Name Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

PM0 0004h

Processor mode bits (2)

R/W Mode select bit (3)

Software reset bit

Multiplexed bus space

select bits (3)

BCLK output disable

bit (3)

PM03

PM01

PM00

PM02

PM04

PM05

PM06

PM07

Port P4_0 to P4_3 function

select bit (3)

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Do not set a value

1 1 : Microprocessor mode

b1 b0

0 : RD, BHE, WR

1 : RD, WRH, WRL

Setting this bit to 1 resets the

MCU.

When read, the content is 0.

0 0 : Multiplexed bus is unused

(Separate bus in the entire CS space)

0 1 : Allocated to CS2 space

1 0 : Allocated to CS1 space

1 1 :

Allocated to the entire CS space (4)

b5 b4

0 : Address output

1 : Port function

(Address is not output)

0 : BCLK is output

1 : BCLK is not output

(Pin is left high-impedance)

After Reset (2)

00000000b (CNVSS pin = L)

00000011b (CNVSS pin = H)

Rev.2.40 Apr 14, 2006 page 36 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 6. Processor Mode

Figure 6.2 PM1 Register

Symbol Address After Reset

PM1 0005h 00001000b

PM17

PM13

PM12

PM10

PM11

(b6-b4)

CS2 area switch bit

(Data block enable bit)

(2)

Port P3_7 to P3_4 function

select bit

(3)

Watchdog timer function

select bit

0 : No wait state

1 : With wait state (1 wait)

Set to 0

Internal ROM area is:

0 : 192 Kbytes or smaller

1 : Expanded over 192 Kbytes

0 : Watchdog timer interrupt

1 : Watchdog timer reset

(4)

0 :

08000h to 26FFFh

(Block A disabled)

1 :

10000h to 26FFFh

(Block A enabled)

0 : Address output

1 : Port function

NOTES:

1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. For the mask ROM version, this bit is set to 0.

For the flash memory version, the PM10 bit controls whether block A is enabled or disabled. When the PM10

bit is set to 1, 0F000h to 0FFFFh (block A) can be used as internal ROM area.

In addition, the PM10 bit is automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU

rewrite mode).

3. Effective when bits PM01 to PM00 are set to 01b (memory expansion mode) or 11b (microprocessor mode).

4. The PM12 bit is set to 1 by writing a 1 in a program. (writing a 0 has no effect.)

5. Be sure to set this bit to 0 except for products with internal ROM area over 192 Kbytes.

The PM13 bit is automatically set to 1 while the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode).

6. When the PM17 bit is set to 1 (with wait state), one wait state is inserted when accessing the internal RAM

or internal ROM.

When the PM17 bit is set to 1 and accesses an external area, set the CSiW bit (i = 0 to 3) in the CSR register

to 0 (with wait state).

Bit Name Function

Internal reserved area

expansion bit

(5)

Reserved bits

Wait bit

(6)

Processor Mode Register 1 (1)

000

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Rev.2.40 Apr 14, 2006 page 37 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 6. Processor Mode

Figure 6.3 Memory Map in Single-chip Mode

Single-chip mode

SFR

Internal RAM

Cannot use

Internal ROM

Capacity

5 Kbytes

10 Kbytes

Address XXXXXh

017FFh

02BFFh

Capacity

128 Kbytes

256 Kbytes

Address YYYYYh

E0000h

D0000h

(1)

Internal RAM

PM13 bit in PM1 register = 0

Internal ROM

Capacity

5 Kbytes

10 Kbytes

Address XXXXXh

017FFh

02BFFh

Capacity

128 Kbytes

256 Kbytes

Address YYYYYh

E0000h

C0000h

Internal RAM

PM13 bit = 1

Internal ROM

00000h

00400h

XXXXXh

YYYYYh

FFFFFh

NOTES:

1. If the PM13 bit in the PM1 register is set to 0, 192 Kbytes of the internal ROM can be used.

2. For the mask ROM version, set the PM10 bit in the PM1 register to 0 (block A disabled,

addresses 08000h to 26FFFh for CS2 area).

Rev.2.40 Apr 14, 2006 page 38 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 6. Processor Mode

NOTE:

1. If the PM13 bit in the PM1 register is set to 0, 192 Kbytes of the internal ROM can be used.

XXXXXh

04000h

SFR

Internal RAM

Reserved area

Internal ROM

Reserved area

External area

SFR

Internal RAM

CS3

(16 Kbytes)

Reserved area

External area

00000h

YYYYYh

FFFFFh

Memory expansion mode Microprocessor mode

00400h

08000h

27000h

28000h

30000h

80000h

CS2

(124 Kbytes)

CS1

(32 Kbytes)

CS0

Memory expansion mode: 320 Kbytes

Microprocessor mode: 832 Kbytes

Reserved area

When PM13 = 0 and PM10 = 0

Address XXXXXh Capacity

Internal RAM

5 Kbytes

10 Kbytes

017FFh

02BFFh

Address YYYYYhCapacity

Internal ROM

128 Kbytes

256 Kbytes

E0000h

D0000h

(1)

_____

Figure 6.4 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (1)

XXXXXh

SFR

Internal RAM

Reserved area

Internal ROM

Reserved area

External area

SFR

Internal RAM

Reserved area

External area

00000h

YYYYYh

FFFFFh

Memory expansion mode Microprocessor mode

00400h

08000h

27000h

28000h

30000h

80000h

CS2

(124 Kbytes)

CS1

(32 Kbytes)

CS0

Memory expansion mode: 320 Kbytes

Microprocessor mode: 832 Kbytes

Reserved area

When PM13 = 1 and PM10 = 0

Address XXXXXh Capacity

Internal RAM

5 Kbytes

10 Kbytes

017FFh

02BFFh

Address YYYYYhCapacity

Internal ROM

128 Kbytes

256 Kbytes

E0000h

C0000h

_____

Figure 6.5 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (2)

Rev.2.40 Apr 14, 2006 page 39 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 6. Processor Mode

NOTES:

1. If the PM13 bit in the PM1 register is set to 0, 192 Kbytes of the internal ROM can be used.

2. For the flash memory version, when the PM10 bit is set to 1, 0F000h to 0FFFFh (block A)

can be used as internal ROM area.

XXXXXh

04000h

SFR

Internal RAM

Reserved area

Internal ROM

Reserved area

External area

SFR

Internal RAM

CS3

(16 Kbytes)

Reserved area

External area

00000h

YYYYYh

FFFFFh

Memory expansion mode Microprocessor mode

00400h

08000h

10000h

27000h

28000h

30000h

80000h

CS2

(92 Kbytes)

CS1

(32 Kbytes)

CS0

Memory expansion mode: 320 Kbytes

Microprocessor mode: 832 Kbytes

Reserved area

When PM13 = 0 and PM10 = 1

Address XXXXXh Capacity

Internal RAM

5 Kbytes

10 Kbytes

017FFh

02BFFh

Address YYYYYhCapacity

Internal ROM

128 Kbytes

256 Kbytes

E0000h

D0000h (1)

Reserved area (2) Reserved area (2)

_____

Figure 6.6 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (3)

NOTE:

1. For the flash memory version, when the PM10 bit is set to 1, 0F000h to 0FFFFh (block A)

can be used as internal ROM area.

XXXXXh

SFR

Internal RAM

Reserved

area

(1)

Reserved area

Internal ROM

Reserved area

External area

SFR

Internal RAM

Reserved area

External area

00000h

YYYYYh

FFFFFh

Memory expansion mode Microprocessor mode

00400h

10000h

27000h

28000h

30000h

80000h

CS2

(92 Kbytes)

CS1

(32 Kbytes)

CS0

Memory expansion mode: 320 Kbytes

Microprocessor mode: 832 Kbytes

Reserved

area

(1)

When PM13 = 1 and PM10 = 1

Address XXXXXh Capacity

Internal RAM

5 Kbytes

10 Kbytes

017FFh

02BFFh

Address YYYYYhCapacity

Internal ROM

128 Kbytes

256 Kbytes

E0000h

C0000h

_____

Figure 6.7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (4)

Rev.2.40 Apr 14, 2006 page 40 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

7. Bus

During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data

_______ _______

input/output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3,

_____ ________ ______ ________ ________ ________ __________ _________

RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK.

7.1 Bus Mode

The bus mode, either multiplexed or separate, can be selected using bits PM05 to PM04 in the PM0 register.

7.1.1 Separate Bus

In this bus mode, data and address are separate.

7.1.2 Multiplexed Bus

In this bus mode, data and address are multiplexed.

7.1.2.1 When the input level on BYTE pin is high (8-bit data bus)

D0 to D7 and A0 to A7 are multiplexed.

7.1.2.2 When the input level on BYTE pin is low (16-bit data bus)

D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15.

External devices connecting to a multiplexed bus are allocated to only the even addresses of the

MCU. Odd addresses cannot be accessed.

Table 7.1 shows the Difference between Separate Bus and Multiplexed Bus.

Table 7.1 Difference between Separate Bus and Multiplexed Bus

Pin Name (1) Separate Bus Multiplexed Bus

BYTE = H BYTE = L

P0_0 to P0_7/D0 to D7 D0 to D7 (NOTE 2) (NOTE 2)

P1_0 to P1_7/D8 to D15 D8 to D15 I/O Port (NOTE 2)

P1_0 to P1_7

P2_0/A0(/D0/-) A0 A0 D0 A0

P2_1 to P2_7/A1 to A7 A1 to A7 A1 to A7 D1 to D7 A1 to A7 D0 to D6

(/D1 to D7/D0 to D6)

P3_0/A8(/-/D7) A8 A8 A8 D7

NOTES :

1. See Table 7.6 Pin Functions for Each Processor Mode for bus control signals other than the above.

2. It changes with a setup of bits PM05 to PM04 in the PM0 register, and area to access. See Table 7.6

Pin Functions for Each Processor Mode for details.

Rev.2.40 Apr 14, 2006 page 41 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

Figure 7.1 CSR Register

7.2 Bus Control

The following describes the signals needed for accessing external devices and the functionality of software

wait.

7.2.2 Data Bus

When input on the BYTE pin is high (data bus is an 8-bit width), 8 lines D0 to D7 comprise the data bus;

when input on the BYTE pin is low (data bus is a 16-bit width), 16 lines D0 to D15 comprise the data bus.

Do not change the input level on the BYTE pin while in operation.

7.2.3 Chip Select Signal _____ ______

The chip select (hereafter referred to as the CS) signals are output from the CSi (i = 0 to 3) pins. These

_____

pins can be chosen to function as I/O ports or as CS by using the CSi bit in the CSR register.

Figure 7.1 shows the CSR Register. ______

During 1 Mbyte mode, the external area can be separated into up to 4 by the CSi signal which is output

______

from the CSi pin. ______

Figure 7.2 shows the Example of Address Bus and CSi Signal Output.

Set Value (1) Pin Function Address Bus Width

PM11 = 1 P3_4 to P3_7 12 bits

PM06 = 1 P4_0 to P4_3

PM11 = 0 A12 to A15 16 bits

PM06 = 1 P4_0 to P4_3

PM11 = 0 A12 to A15 20 bits

PM06 = 0 A16 to A19

NOTE:

1. No values other than those shown above can

be set.

7.2.1 Address Bus

The address bus consists of 20 lines, A0 to A19.

The address bus width can be chosen to be 12,

16 or 20 bits by using the PM06 bit in the PM0

Table 7.2 shows Bits PM06 and PM11 Set Values

and Address Bus Widths.

When processor mode is changed from single-chip

mode to memory expansion mode, the address

bus is undefined until any external area is

accessed.

Table 7.2 Bits PM06 and PM11 Set Value and

Address Bus Width

0 : Chip select output disabled

(functions as I/O port)

1 : Chip select output enabled

0 : With wait state

1 : Without wait state (1) (2) (3)

Chip Select Control Register

Symbol Address After Reset

Bit Name Function

Bit Symbol

NOTES:

1. Where the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplexed bus is used, set the

CSiW bit to 0 (wait state).

2. If the PM17 bit in the PM1 register is set to 1 (with wait state), set the CSiW bit to 0 (with wait state).

3. When the CSiW bit = 0 (with wait state), the number of wait states (in terms of clock cycles) can be selected

using bits CSEi1W to CSEi0W in the CSE register.

b7 b6 b5 b4 b3 b2 b1 b0

CSR 0008h 00000001b

CS3 wait bit

CS2 wait bit

CS1 wait bit

CS0 wait bit

CS3 output enable bit

CS2 output enable bit

CS0 output enable bit

CS1 output enable bit

CS1

CS0

CS3

CS2

CS1W

CS0W

CS3W

CS2W

Rev.2.40 Apr 14, 2006 page 42 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

______

Figure 7.2 Example of Address Bus and CSi Signal Output

NOTE:

1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be

extended more than two cycles depending on a combination of these examples.

Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however)

To access the external area indicated by CSj in the next cycle

after accessing the external area indicated by CSi.

The address bus and the chip select signal both change state

between these two cycles.

Example 2

To access the internal ROM or internal RAM in the next cycle

after accessing the external area indicated by CSi.

The chip s elect signal changes state but the address bus

does not change state.

Example 1

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

Access to the external

area indicated by CSj

Address

Data

CSj

Data

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

Access to the internal

ROM or internal RAM

Address

Data

Address

Example 4

Not to access any area (nor instruction prefetch generated)

in the next cycle after accessing the external area indicated

by CSi.

Neither the address bus nor the chip select signal changes

state between these two cycles.

To a ccess the external area indicated by CSi in the next cycle

after accessing the external area indicated by the same CSi.

The address bus changes state but the chip select signal

does not change state.

Example 3

BCLK

Read signal

Data bus

Address bus

CSi

Access to the external

area indicated by CSi

Access to the same

external area

Address

Data Data

BCLK

Read signal

CSi

Access to the external

area indicated by CSi

No access

Address

Data

Address

Data bus

Address bus

Rev.2.40 Apr 14, 2006 page 43 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

_____ ______ ________

Table 7.4 Operation of RD, WR, and BHE Signals

_____ ________ _________

Table 7.3 Operation of RD, WRL, and WRH Signals

7.2.4 Read and Write Signals _____

When the data bus is 16-bit width, the read and write signals can be chosen to be a combination of RD,

______ ________ _____ ________ ________

WR, and BHE or a combination of RD, WRL, and WRH by using the PM02 bit in the PM0 register. When

_____ ______ ________

the data bus is 8-bit width, use a combination of RD, WR, and BHE.

_____ ________ _________ _____

Table 7.3 shows the Operation of RD, WRL, and WRH Signals. Table 7.4 shows the Operation of RD,

______ ________

WR, and BHE Signals.

7.2.5 ALE Signal

The ALE signal latches the address when accessing the multiplexed bus space. Latch the address when

the ALE signal falls.

Figure 7.3 shows the ALE Signal, Address Bus and Data Bus.

Figure 7.3 ALE Signal, Address Bus, and Data Bus

Data Bus Width

_____

________

WRL

_________

WRH Status of External Data Bus

16 bits

(BYTE pin

input = L)

Read data

Write 1 byte of data to an even address

Write 1 byte of data to an odd address

Write data to both even and odd addresses

Data Bus Width

_____

______

________

BHE Status of External Data Bus

16 bits

(BYTE pin

input = L)

8 bits

(BYTE pin input = H)

Not used

Write 1 byte of data to an odd address

Read 1 byte of data from an odd address

Write 1 byte of data to an even address

Read 1 byte of data from an even address

Write data to both even and odd addresses

Read data from both even and odd addresses

Write 1 byte of data

Read 1 byte of data

H to L

Address Data

Address (1) Address Data

Address

NOTE:

1. If the entire CS space is assigned a multiplexed bus, these pins function as I/O ports.

A0/D0 to A7/D7

A8 to A19

ALE

A1/D0 to A8/D7

A9 to A19

ALE

When BYTE pin input = H When BYTE pin input = L

Rev.2.40 Apr 14, 2006 page 44 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

________

Figure 7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal

BCLK

CSi

(i=0 to 3)

RDY

tsu(RDY - BCLK)

BCLK

CSi

(i=0 to 3)

tsu(RDY - BCLK)

In an instance of separate bus

In an instance of multiplexed bus

Accept timing of RDY signal

: Wait using RDY signal

: Wait using software

Accept timing of RDY signal

tsu(RDY-BCLK): RDY input setup time

Shown above is the case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are

00b (one wait state).

RDY

________

7.2.6 RDY Signal

This signal is provided for accessing external devices which need to be accessed at low speed. If input on

________

the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in

________

the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY

signal was acknowledged.

_______ _______ _____ ________ ________ ______ ________ __________

A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA

________

Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle

________

is executed. Figure 7.4 shows an Example in which Wait State was Inserted into Read Cycle by RDY

________

Signal. To use the RDY signal, set the corresponding bit (bits CS3W to CS0W) in the CSR register to 0

________ ________

(with wait state). When not using the RDY signal, the RDY pin must be pulled-up.

Rev.2.40 Apr 14, 2006 page 45 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

__________

HOLD > DMAC > CPU

__________

7.2.7 HOLD Signal

This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the

__________

input on HOLD pin is pulled low, the MCU is placed in a hold state after the bus access then in process

__________ __________

finishes. The MCU remains in a hold state while the HOLD pin is held low, during which time the HLDA pin

outputs a low-level signal.

Table 7.5 shows the MCU Status in Hold State.

__________

Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence (see Figure

7.5 Bus-using Priorities). However, if the CPU is accessing an odd address in word units, the DMAC

cannot gain control of the bus during two separate accesses.

Figure 7.5 Bus-using Priorities

Table 7.5 MCU Status in Hold State

NOTES:

1. When I/O port function is selected.

2. The watchdog timer does not stop when the PM22 bit in the PM2 register is set to 1 (the count source

for the watchdog timer is the on-chip oscillator clock).

7.2.8 BCLK Output

If the PM07 bit in the PM0 register is set to 0 (output enable), a clock with the same frequency as that of

the CPU clock is output as BCLK from the BCLK pin. Refer to 8.2 CPU Clock and Peripheral Function

Clock.

Table 7.6 shows the Pin Functions for Each Processor Mode.

Item Status

BCLK Output

_______ _______ ______ _________ _________

A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, High-impedance

______ ________

WR, BHE

I/O ports P0, P1, P3, P4 (1) High-impedance

P6 to P10 Maintains status when hold signal is received

__________

HLDA Output “L”

Internal peripheral circuits ON (but watchdog timer stops (2))

ALE signal Undefined

Rev.2.40 Apr 14, 2006 page 46 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

Table 7.6 Pin Functions for Each Processor Mode

Processor Mode Memory Expansion Mode or Microprocessor Mode

Memory Expansion Mode

Bits PM05 to PM04 00b (separate bus)

_______

01b (CS2 is for multiplexed bus and

11b

others are for separate bus)

(multiplexed bus for

_______

10b (CS1 is for multiplexed bus and

the entire space) (1)

others are for separate bus)

Data bus width 8 bits 16 bits 8 bits 16 bits 8 bits

BYTE pin “H”“L”“H”“L” “H”

P0_0 to P0_7 D0 to D7 D0 to D7 (4) I/O ports

P1_0 to P1_7 I/O ports D8 to D15 I/O ports

D8 to D15

(4) I/O ports

P2_0 A0 A0/D0 (2) A0 A0/D0

P2_1 to P2_7 A1 to A7 A1 to A7 A1 to A7

A1 to A7/D1 to D7

/D1 to D7 (2) /D0 to D6 (2)

P3_0 A8 A8/D7 (2) A8

P3_1 to P3_3 A9 to A11 I/O ports

P3_4 PM11 = 0 A12 to A15 I/O ports

to P3_7 PM11 = 1 I/O ports

P4_0 PM06 = 0 A16 to A19 I/O ports

to P4_3 PM06 = 1 I/O ports

P4_4 CS0 = 0 I/O ports

CS0 = 1

_______

CS0

P4_5 CS1 = 0 I/O ports

CS1 = 1

_______

CS1

P4_6 CS2 = 0 I/O ports

CS2 = 1

_______

CS2

P4_7 CS3 = 0 I/O ports

CS3 = 1

_______

CS3

P5_0 PM02 = 0

_______

PM02 = 1

(3)

________

WRL

(3)

________

WRL

(3)

P5_1 PM02 = 0

________

BHE

PM02 = 1

(3)

_________

WRH

(3)

_________

WRH

(3)

P5_2

_____

P5_3 BCLK

P5_4

__________

HLDA

P5_5

__________

HOLD

P5_6 ALE

P5_7

________

RDY

I/O ports: Function as I/O ports or peripheral function I/O pins.

NOTES:

1. For setting bits PM01 to PM00 to 01b (memory expansion mode) and bits PM05 to PM04 to 11b

_____

(multiplexed bus assigned to the entire CS space), apply “H” to the BYTE pin (external data bus is an

8-bit width). While the CNVSS pin is held “H” (VCC), do not rewrite bits PM05 to PM04 to 11b after

reset. If bits PM05 to PM04 are set to 11b during memory expansion mode, P3_1 to P3_7 and P4_0 to

_____

P4_3 become I/O ports, in which case the accessible area for each CS is 256 bytes.

2. In separate bus mode, these pins serve as the address bus.

_____ ________ ______

If the data bus is 8-bit width, make sure the PM02 bit is set to 0 (RD, BHE, WR).

4. When accessing the area that uses a multiplexed bus, these pins output an undefined value during

a write.

Rev.2.40 Apr 14, 2006 page 47 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

7.2.10 Software Wait

Software wait states can be inserted by using the PM17 bit in the PM1 register, bits CS0W to CS3W in the

CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is always

accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See Table 7.8

Bit and Bus Cycle Related to Software Wait for details.

________

To use the RDY signal, set the corresponding bit of bits CS3W to CS0W to 0 (with wait state).

Figure 7.6 shows the CSE Register. Table 7.8 shows the Software Wait Related Bits and Bus Cycles.

Figures 7.7 and 7.8 show the Typical Bus Timings Using Software Wait.

7.2.9 External Bus Status when Internal Area Accessed

Table 7.7 shows the External Bus Status When Internal Area Accessed.

Table 7.7 External Bus Status When Internal Area Accessed

Figure 7.6 CSE Register

Item SFR Accessed Internal ROM, Internal RAM Accessed

A0 to A19 Address output Maintain status before accessed address

of external area or SFR

D0 to D15 When read High-impedance High-impedance

When write Output data Undefined

_____ ______ ________ _________

RD, WR, WRL, WRH

_____ ______ _________ __________

RD, WR, WRL, WRH output Output “H”

________

BHE

________

BHE output Maintain status before accessed status of

external area or SFR

_______ _______

CS0 to CS3 Output “H”Output “H”

ALE Output “L”Output “L”

CS0 wait expansion bits

(1)

CS1 wait expansion bits

(1)

CS2 wait expansion bits

(1)

CS3 wait expansion bits

(1)

0 0 : 1 wait

0 1 : 2 waits

1 0 : 3 waits

1 1 : Do not set a value

b1 b0

0 0 : 1 wait

0 1 : 2 waits

1 0 : 3 waits

1 1 : Do not set a value

b3 b2

0 0 : 1 wait

0 1 : 2 waits

1 0 : 3 waits

1 1 : Do not set a value

b5 b4

0 0 : 1 wait

0 1 : 2 waits

1 0 : 3 waits

1 1 : Do not set a value

b7 b6

Bit Name Function

Bit Symbol RW

Chip Select Expansion Control Register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address After Reset

CSE 001Bh 00h

CSE00W

CSE01W

CSE10W

CSE11W

CS20WE

CSE21W

CSE30W

CSE31W

NOTE:

1. Set the CSiW bit (i = 0 to 3) in the CSR register to 0 (with wait state) before writing to bits CSEi1W to CSEi0W.

If the CSiW bit needs to be set to 1 (without wait state), set bits CSEi1W to CSEi0W to 00b before setting it.

Rev.2.40 Apr 14, 2006 page 48 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

Table 7.8 Software Wait Related Bits and Bus Cycles

Area

Bus Mode

SFR

Internal

ROM, RAM

External

area

Separate

bus

Multiplexed

bus (2)

PM1 Register

PM17 Bit (5)

3 BCLK cycles (4)

2 BCLK cycles (4)

1 BCLK cycle (3)

2 BCLK cycles

1 BCLK cycle (read)

2 BCLK cycles (write)

2 BCLK cycles (3)

3 BCLK cycles

4 BCLK cycles

2 BCLK cycles

3 BCLK cycles

4 BCLK cycles

3 BCLK cycles

Bus Cycle

00b

01b

10b

00b

01b

10b

00b

CSR Register

CS3W Bit (1)

CS2W Bit (1)

CS1W Bit (1)

CS0W Bit (1)

CSE Register

Bits CS31W to CS30W

Bits CS21W to CS20W

Bits CS11W to CS10W

Bits CS01W to CS00W

NOTES:

________

To use the RDY signal, set this bit to 0.

2. To access in multiplexed bus mode, set the corresponding bit of bits CS0W to CS3W to 0 (with wait state).

3. After reset, the PM17 bit is set to 0 (without wait state), all of bits CS0W to CS3W are set to 0 (with wait

_______ _______

state), and the CSE register is set to 00h (one wait state for CS0 to CS3). Therefore, the internal RAM

and internal ROM are accessed with no wait state, and all external areas are accessed with one wait

state.

4. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the

PM20 bit in the PM2 register. When using PLL clock over 16 MHz, be sure to set the PM20 bit to 0

(2 wait cycles).

5. When the PM17 bit is set to 1 and access an external area, set the CSiW bits (i = 0 to 3) to 0 (with wait

state).

Software

Wait

No wait

1 wait

No wait

1 wait

2 waits

3 waits

1 wait

2 waits

3 waits

1 wait

PM2 Register

PM20 Bit

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

Figure 7.7 Typical Bus Timings Using Software Wait (1)

NOTE:

1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and

write cycles in succession.

Output

Input

Address Address

BCLK

Read signal

Write signal

Data bus

Address bus

(2) Separate bus, 1-wait setting

BCLK

Read signal

Write signal

Data bus

Address bus Address

Address

Bus cycle

(1)

Output Input

Bus cycle

(1)

Bus cycle

(1)

Bus cycle

(1)

(1) Separate bus, No wait setting

Output

Address Address

Input

BCLK

Read signal

Write signal

Data bus

Address bus

(3) Separate bus, 2-wait setting Bus cycle

(1)

Bus cycle

(1)

Rev.2.40 Apr 14, 2006 page 50 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 7. Bus

Figure 7.8 Typical Bus Timings Using Software Wait (2)

Address

Output Input

Address

BCLK

Write signal

Read signal

Data bus

Address bus

(1) Separate bus, 3-wait setting

Address bus/

Data bus Address

Address

Data output

Address

Input

ALE

BCLK

Write signal

Read signal

Address bus

(2)Multiplexed bus, 1- or 2-wait setting

Address

Data output

Address

Input

Read signal

Write signal

Address bus/

Data bus

Address bus

ALE

Address

BCLK

(3)Multiplexed bus, 3-wait setting

NOTE:

1. These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and

write cycles in succession.

Bus cycle (1) Bus cycle (1)

Rev.2.40 Apr 14, 2006 page 51 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8. Clock Generation Circuit

8.1 Types of Clock Generation Circuit

Four circuits are incorporated to generate the system clock signal:

• Main clock oscillation circuit

• Sub clock oscillation circuit

• On-chip oscillator

• PLL frequency synthesizer

Table 8.1 lists the Clock Generation Circuit Specifications. Figure 8.1 shows the Clock Generation Circuit.

Figures 8.2 to 8.8 show the clock-related registers.

Table 8.1 Clock Generation Circuit Specifications

Item Main Clock

Oscillation Circuit

Sub Clock

Oscillation Circuit On-chip Oscillator PLL Frequency

Synthesizer

Use of clock

Clock

frequency

Usable

oscillator

Pins to connect

oscillator

Oscillation stop

and re-oscillation

detection function

Oscillation status

after reset

Other

•CPU clock source

•Peripheral function

clock source

0 to 16 MHz

•Ceramic oscillator

•Crystal oscillator

XIN, XOUT

Available

Oscillating

Externally derived clock can be input

•CPU clock source

•Clock source of timer

A, B

32.768 kHz

•Crystal oscillator

XCIN, XCOUT

Available

Stopped

•CPU clock source

•Peripheral function

clock source

•CPU and peripheral

function clock sources

when the main clock

stops oscillating

About 1 MHz

Available

Stopped

•CPU clock source

•Peripheral function

clock source

16 MHz, 20 MHz,

24 MHz (1)

Available

Stopped

NOTE:

1. 24 MHz is available Normal-ver. only.

Rev.2.40 Apr 14, 2006 page 52 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.1 Clock Generation Circuit

1/16

CLKOUT

CM01-CM00=00b

PM01-PM00=00b, CM01-CM00=01b

PM01-PM00=00b, CM01-CM00=10b

PM01-PM00=00b,

CM01-CM00=11b

I/O ports

1/32 fC32

PCLK0=1

PCLK0=0

PCLK0=1

PCLK0=0

f1SIO

f2SIO

PCLK1=1

PCLK1=0

CM07=0

CPU clock

BCLK

CM07=1

f32

f8SIO

f32SIO

Divider

bcd e

CM21=1

CM21=0

0 CM11

PLL frequency

synthesizer

Oscillation stop,

re-oscillation

detection circuit

On-chip

oscillator

XOUTXIN

Main clock

oscillation circuit

Main clock

CM05

XCOUTXCIN

Sub clock oscillation circuit

CM04

PLL clock

On-chip oscillator

clock

CM02

CM10=1

(stop mode)

WAIT instruction

RESET

NMI

Software reset

Interrupt request level

judgment output

1/2 1/2 1/2 1/2 1/2

Details of divider

1/81/41/2

a1/32

CM06=0

CM17-CM16=11b

CM06=0

CM17-CM16=10b

CM06=1

CM06=0

CM17-CM16=01b

CM06=0

CM17-CM16=00b

PM00, PM01 : Bits in PM0 register

CM00, CM01, CM02, CM04, CM05, CM06, CM07 : Bits in CM0 register

CM10, CM11, CM16, CM17 : Bits in CM1 register

PCLK0, PCLK1 : Bits in PCLKR register

CM21, CM27 : Bits in CM2 register

CCLK0 to CCLK2, CCLK4 to CCLK6 : Bits in CCLKR register

Sub clock

CM21

CAN1

By CCLK0,1 and 2

By CCLK4,5 and 6

fCAN0

Divider

Reset

generating

circuit

Oscillation stop,

re-oscillation detection

interrupt generating

circuit

Main clock

Oscillation stop

detection reset

CM21 switch signal

Oscillation stop,

re-oscillation detection

interrupt signal

Oscillation stop, re-oscillation detection circuit

Charge,

discharge

circuit

Pulse generating circuit

for clock edge detection

and charge,

discharge control

CM27 = 0

CM27 = 1

Main clock

PLL clock

PLL frequency synthesizer

Phase

comparator

Voltage

controlled

oscillator

(VCO)

Internal

lowpass filter

Charge

pump

Programmable

counter 1/2

Rev.2.40 Apr 14, 2006 page 53 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.2 CM0 Register

System Clock Control Register 0 (1)

NOTES:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. The fC32 clock does not stop. In low-speed or low power dissipation mode, do not set this bit to 1 (peripheral

clock stops in wait mode).

3. The CM03 bit is set to 1 (high) while the CM04 bit is set to 0 (I/O port) or when entering stop mode.

4. To use a sub clock, set this bit to 1. Also make sure ports P8_6 and P8_7 are directed for input, with no

pull-ups.

5. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low

power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stops

or not. To stop the main clock, set bits as follows:

(a) Set the CM07 bit to 1 (sub clock selected) or the CM21 bit in the CM2 register to 1 (on-chip oscillator

selected) with the sub clock stably oscillating.

(b) Set the CM20 bit in the CM2 register to 0 (oscillation stop, re-oscillation detection function disabled).

6. To use the main clock as the clock source for the CPU clock, set bits as follows:

(a) Set the CM05 bit to 0 (oscillate).

(b) Wait until the main clock oscillation stabilizes.

7. When the CM21 bit = 0 (on-chip oscillator stops) and the CM05 bit = 1 (main clock stops), the CM06 bit is

fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capability high).

8. During external clock input, set the CM05 bit to 0 (oscillate).

9. When the CM05 bit is set to 1, the XOUT pin is held "H". Because the on-chip feedback resistor remains

connected, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor.

10. When entering stop mode from high-speed or medium-speed mode, on-chip oscillator mode or on-chip

oscillator low power dissipation mode, the CM06 bit is set to 1 (divide-by-8 mode).

11. After setting the CM04 bit to 1 (XCIN-XCOUT oscillator function), wait until the sub clock oscillates stably

before switching the CM07 bit from 0 to 1 (sub clock).

12. To return from on-chip oscillator mode to high-speed or medium-speed mode, set bits CM06 and CM15 to 1.

Bit Name FunctionBit Symbol

b1 b0

0 0 : I/O port P5_7

0 1 : Output fC

1 0 : Output f8

1 1 : Output f32

0 : Peripheral function clock does

not stop in wait mode

1 : Peripheral function clock stops

in wait mode (2)

0 : I/O port P8_6, P8_7

1 : XCIN-XCOUT oscillation

function (4)

0 : On

1 : Off (8) (9)

0 : Bits CM16 and CM17 enabled

1 : Divide-by-8 mode

0 : Main clock, PLL clock,

or on-chip oscillator clock

1 : Sub clock

0 : LOW

1 : HIGH

CM07

CM05

CM04

CM01

CM02

CM00

CM06

Clock output function

select bits

(Valid only in single-chip

mode)

CM03

WAIT mode peripheral

function clock stop bit

Port XC select bit (3)

Main clock stop bit (5) (6) (7)

Main clock division select

bit 0 (7) (10) (12)

XCIN-XCOUT drive

capacity select bit (3)

System clock select

bit (6) (11)

Symbol Address After Reset

CM0 0006h 01001000b

b7 b6 b5 b4 b3 b2 b1 b0

Rev.2.40 Apr 14, 2006 page 54 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.3 CM1 Register

Bit Name FunctionBit Symbol

CM10

CM15

CM16

CM17

CM11

(b4-b2)

All clock stop control

bit (2) (3)

XIN-XOUT drive capacity

select bit (6)

Reserved bits

Main clock division

select bits 1 (7)

System clock select bit 1 (4)

0 : Clock on

1 : All clocks off (stop mode)

0 : LOW

1 : HIGH

Set to 0

0 0 : No division mode

0 1 : Divide-by-2 mode

1 0 : Divide-by-4 mode

1 1 : Divide-by-16 mode

b7 b6

0 : Main clock

1 : PLL clock

(5)

Symbol Address After Reset

CM1 0007h 00100000b

System Clock Control Register 1 (1)

000

b7 b6 b5 b4 b3 b2 b1 b0

NOTES:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled)

2. If the CM10 bit is 1 (stop mode), XOUT is held "H" and the on-chip feedback resistor is disconnected.

Pins XCIN and XCOUT are in high-impedance state. When the CM11 bit is set to 1 (PLL clock), or the CM20

bit in the CM2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the

CM10 bit to 1.

3. When the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock is selected as watchdog timer

count source), this bit remains unchanged even if writing to the CM10 bit.

4. This bit is valid when the CM07 bit is 0 and the CM21 bit is 0.

5. After setting the PLC07 bit in the PLC0 register to 1 (PLL operation), wait tsu(PLL) elapses before setting

the CM11 bit to 1 (PLL clock).

6. When entering stop mode from high-speed or medium-speed mode, or when the CM05 bit is set to 1 (main

clock stops) in low-speed mode, the CM15 bit is set to 1 (drive capability high).

7. This bit is valid when the CM06 bit is 0 (bits CM16 and CM17 enabled).

Rev.2.40 Apr 14, 2006 page 55 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.4 CM2 Register

Oscillation Stop Detection Register (1)

Symbol Address After Reset

CM2 000Ch 0X000000b (2)

Function

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name

0 : Oscillation stop, re-oscillation

detection function disabled

1 : Oscillation stop, re-oscillation

detection function enabled

0 : Main clock or PLL clock

1 : On-chip oscillator clock

(On-chip oscillator oscillates)

CM20

CM21

CM22

0 : Main clock stop, re-oscillation

not detected

1 : Main clock stop, re-oscillation

detected

System clock select

bit 2 (2) (5) (6) (7) (8) (11)

CM23

(b5-b4)

(b6)

XIN monitor flag (10) 0 : Main clock oscillates

1 : Main clock stops

CM27

Operation select bit

(when an

oscillation stop,

re-oscillation is detected) (2)

0 : Oscillation stop detection reset

1 : Oscillation stop, re-oscillation

detection interrupt

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Reserved bits Set to 0

NOTES:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. Bits CM20, CM21, and CM27 remain unchanged at oscillation stop detection reset.

3. Set the CM20 bit to 0 (disabled) before entering stop mode. Exit stop mode before setting the CM20 bit

back to 1 (enabled).

4. Set the CM20 bit to 0 (disabled) before setting the CM05 bit in the CM0 register to 1 (main clock stops).

5. When the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the CM27 bit is

set to 1 (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock,

the CM21 bit is set to 1 (on-chip oscillator clock) if the main clock stop is detected.

6. If the CM20 bit is set to 1 and the CM23 bit is set to 1 (main clock stops), do not set the CM21 bit to 0.

7. This bit is valid when the CM07 bit in the CM0 register is set to 0.

8. Where the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the CM27 bit is

set to 1 (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to 1 (PLL clock is selected

as the CPU clock source), the CM21 bit remains unchanged even if a main clock stop is detected. When the

CM22 bit is set to 0 under these conditions, an oscillation stop, re-oscillation detection interrupt request is

generated at main clock stop detection. Set the CM21 bit to 1 (on-chip oscillator clock) in the interrupt routine.

9. This bit is set to 1 when the main clock is detected and the main clock re-oscillation is detected. When this

bit changes state from 0 to 1, an oscillation stop and re-oscillation detection interrupt request is generated.

Use this bit in an interrupt routine to discriminate the interrupt sources between the oscillation stop and

re-oscillation detection interrupt and the watchdog timer interrupt. This bit is set to 0 by writing 0 in a

program. (This bit remains unchanged even if writing 1. Nor is it set to 0 when an oscillation stop and

re-oscillation detection interrupt request is acknowledged.)

If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation

detection interrupt requests are generated.

10. Determine the main clock status by reading the CM23 bit several times in an oscillation stop or re-oscillation

detection interrupt routine.

11. When the CM21 bit is set to 0 (on-chip oscillator stops) and the CM05 bit is set to 1 (main clock stops),

the CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capability high).

Oscillation stop,

re-oscillation detection

enable bit (2) (3) (4)

Oscillation stop,

re-oscillation detection

flag (9)

Rev.2.40 Apr 14, 2006 page 56 of 376

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M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.5 PCLKR Register

NOTE:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

Peripheral Clock Select Register (1)

Symbol Address After Reset

PCLKR 025Eh 00h

00000 0

b7 b6 b5 b4 b3 b2 b1 b0

PCLK0

PCLK1

(b7-b2)

SI/O clock select bit

(Clock source for UART0 to UART2,

SI/O3)

0 : Divide-by-2 of fAD, f2

1 : fAD, f1

0 : f2SIO

1 : f1SIO

Reserved bits Set to 0

Bit Name Function

Bit Symbol RW

Timers A, B, and A/D clock

select bit

(Clock source for timers A, B,

the dead time timer and A/D)

Figure 8.6 CCLKR Register

0 0 0 No division

0 0 1 : Divide-by-2

0 1 0 : Divide-by-4

0 1 1 : Divide-by-8

1 0 0: Divide-by-16

1 0 1 :

1 1 0 : Do not set a value

1 1 1 :

b2 b1 b0

CAN0 clock select bits

(2)

CAN0 CPU interface

sleep bit

(3)

0: CAN0 CPU interface operating

1: CAN0 CPU interface in sleep

Bit Name FunctionBit Symbol RW

CCLK3

CCLK1

CCLK2

CCLK0

Symbol Address After Reset

CCLKR 025Fh 00h

CAN0/1 Clock Select Register

(1)

b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 No division

0 0 1 : Divide-by-2

0 1 0 : Divide-by-4

0 1 1 : Divide-by-8

1 0 0 : Divide-by-16

1 0 1 :

1 1 0 : Do not set a value

1 1 1 :

b6 b5 b4

CAN1 clock select bits

(2)

CAN1 CPU interface

sleep bit

(3)

0: CAN1 CPU interface operating

1: CAN1 CPU interface in sleep

CCLK7

CCLK5

CCLK6

CCLK4

NOTES:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. Set only when the Reset bit in the CiCTLR register (i = 0, 1) = 1 (reset/Initialization mode).

3. Before setting this bit to 1, set the Sleep bit in the CiCTLR to 1 (sleep mode enabled).

Rev.2.40 Apr 14, 2006 page 57 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Symbol Address After Reset

PM2 001Eh XXX00000b

Processor Mode Register 2 (1)

b7 b6 b5 b4 b3 b2 b1 b0

000

Specifying wait when

accessing SFR at PLL

operation (2)

0 : 2 waits

1 : 1 wait

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Reserved bits

WDT count source

protective bit (3) (4)

0 : CPU clock is used for the

watchdog timer count source

1 : On-chip oscillator clock is used for

the watchdog timer count source

Reserved bit Set to 0

Set to 0

Bit Name Function

Bit Symbol RW

PM20

(b1)

(b4-b3)

(b7-b5)

PM22

NOTES:

1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enable).

2. The PM20 bit become effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20

bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.

3. Once this bit is set to 1, it cannot be set to 0 in a program.

4. Setting the PM22 bit to 1 results in the following conditions:

The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source.

The CM10 bit in the CM1 register is disabled against write. (Writing a 1 has no effect, nor is stop mode entered.)

The watchdog timer does not stop when in wait mode or hold state.

Figure 8.7 PM2 Register

Figure 8.8 PLC0 Register

PLC07

Function

PLL Control Register 0 (1)

Operation enable bit

(3)

0 : PLL Off

1 : PLL On

Bit NameBit Symbol

Symbol Address After Reset

PLC0 001Ch 0001X010b

PLC00

b2 b1 b0

0 0 0 : Do not set a value

0 0 1 : Multiply-by-2

0 1 0 : Multiply-by-4

0 1 1 : Multiply-by-6

(4)

1 0 0 :

1 0 1 : Do not set a value

1 1 0 :

1 1 1 :

PLC01

PLC02

(b3)

(b4)

(b6-b5)

Reserved bit Set to 1

Reserved bits Set to 0

PLL multiplying factor

select bits

(2)

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

NOTES:

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. This bit can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit

cannot be modified.

3. Before setting this bit to 1, set the CM07 bit in the CM0 register to 0 (main clock), set bits CM17 to CM16

in the CM1 register to 00b (main clock undivided mode), and set the CM06 bit in the CM0 register to 0

(bits CM16 and CM17 enabled).

4. Multiply by 6 is available Normal-ver. only.

b7 b6 b5 b4 b3 b2 b1 b0

0 10

Rev.2.40 Apr 14, 2006 page 58 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.9 Examples of Main Clock Connection Circuit

The following describes the clocks generated by the clock generation circuit.

8.1.1 Main Clock

The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for

the CPU and peripheral function clocks. The main clock oscillation circuit is configured by connecting a

resonator between pins XIN and XOUT. The main clock oscillation circuit has an on-chip feedback resistor,

which is disconnected from the oscillation circuit during stop mode in order to reduce the amount of power

consumed in the chip. The main clock oscillation circuit may also be configured by feeding an externally

generated clock to the XIN pin. Figure 8.9 shows an Examples of Main Clock Connection Circuit.

After reset, the main clock divided by 8 is selected for the CPU clock.

The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to 1 (main

clock oscillation circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip

oscillator clock. In this case, XOUT goes “H”. Furthermore, because an on-chip feedback resistor remains

on, XIN is pulled “H” to XOUT via the feedback resistor. Note, that if an externally generated clock is fed

into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to 1, unless the sub clock is

selected as a CPU clock. If necessary, use an external circuit to turn off the clock.

During stop mode, all clocks including the main clock are turned off. Refer to 8.4 Power Control.

MCU

(On-chip feedback resistor)

MCU

(On-chip feedback resistor)

External clock

Open

VCC

VSS

XIN

XOUT

(1)

CIN

COUT

VSS

Oscillator

XIN

XOUT

NOTE:

1.Place a damping resistor if required. The resistance will vary depending on the oscillator

and the oscillation drive capacity setting. Use the value recommended by each oscillator

the oscillator manufacturer.

When the oscillation drive capacity is set to low, check that oscillation is stable.

Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer

recommends placing the resistor externally.

Rev.2.40 Apr 14, 2006 page 59 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.10 Examples of Sub Clock Connection Circuit

8.1.2 Sub Clock

The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for

the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same

frequency as that of the sub clock can be output from the CLKOUT pin.

The sub clock oscillation circuit is configured by connecting a crystal resonator between pins XCIN and

XCOUT. The sub clock oscillation circuit has an on-chip feedback resistor, which is disconnected from

the oscillation circuit during stop mode in order to reduce the amount of power consumed in the chip. The

sub clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN

pin. Figure 8.10 shows an Examples of Sub Clock Connection Circuit.

After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillation

circuit.

To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to 1 (sub clock) after the sub

clock becomes oscillating stably.

During stop mode, all clocks including the sub clock are turned off. Refer to 8.4 Power Control.

NOTE:

1.Place a damping resistor if required. The resistance will vary depending on the oscillator

and the oscillation drive capacity setting. Use the value recommended by each oscillator

the oscillator manufacturer.

When the oscillation drive capacity is set to low, check that oscillation is stable.

Also, place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer

recommends placing the resistor externally.

MCU

(On-chip feedback resistor)

MCU

(On-chip feedback resistor)

External clock

Open

VCC

VSS

XCIN

XCOUT

RCd

(1)

CCIN

CCOUT

VSS

Oscillator

XCIN

XCOUT

Rev.2.40 Apr 14, 2006 page 60 of 376

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M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.1.3 On-chip Oscillator Clock

This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source

for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip

oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog

timer (refer to 11.1 Count Source Protective Mode).

After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register

to 1 (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function clocks,

in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register is 1

(oscillation stop, re-oscillation detection function enabled) and the CM27 bit is 1 (oscillation stop,

re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the

necessary clock for the MCU.

8.1.4 PLL Clock

The PLL clock is generated PLL frequency synthesizer. This clock is used as the clock source for the

CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer

is activated by setting the PLC07 bit to 1 (PLL operation). When the PLL clock is used as the clock source

for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1

Before entering wait mode or stop mode, be sure to set the CM11 bit to 0 (CPU clock source is the main

clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to 0

(PLL stops). Figure 8.11 shows the Procedure to Use PLL Clock as CPU Clock Source.

The PLL clock frequency is determined by the equation below. When the PLL clock frequency is 16 MHz

or more, set the PM20 bit in the PM2 register to 0 (2 waits).

PLL clock frequency = f(XIN) ✕ (multiplying factor set by bits PLC02 to PLC00 in the PLC0 register)

(However, PLL clock frequency = 16 MHz, 20 MHz or 24 MHz (1) )

NOTE:

1. 24 MHz is available Normal-ver. only.

Bits PLC02 to PLC00 can be set only once after reset. Table 8.2 shows an Example for Setting PLL Clock

Frequencies.

Table 8.2 Example for Setting PLL Clock Frequencies

XIN

(MHz)

Multiply

Factor

PLL Clock

(MHz) (1)

PLC01 PLC00

24 (2)

NOTES:

1. PLL clock frequency = 16 MHz , 20 MHz or 24 MHz

2. 24 MHz is available Normal-ver. only.

3. Multiply by 6 is available Normal-ver. only.

PLC02

(3)

Rev.2.40 Apr 14, 2006 page 61 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source

Set bits PLC02 to PLC00 (multiplying factor).

(When PLL clock > 16 MHz)

Set the PM20 bit to 0 (2-wait state).

Set the PLC07 bit to 1 (PLL operation).

Set the CM11 bit to 1 (PLL clock for the CPU clock source).

END

Using the PLL clock as the clock source for the CPU

Set the CM07 bit to 0 (main clock), bits CM17 to CM16

to 00b (main clock undivided), and the CM06 bit to 0

(bits CM16 and CM17 enabled).

(1)

NOTE:

1. PLL operating mode can be entered from high-speed mode.

Wait until the PLL clock becomes stable (tsu(PLL)).

Rev.2.40 Apr 14, 2006 page 62 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.2 CPU Clock and Peripheral Function Clock

Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral

functions.

8.2.1 CPU Clock and BCLK

These are operating clocks for the CPU and watchdog timer.

The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock

or the PLL clock.

If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected

clock source can be divided by 1 (undivided), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit

in the CM0 register and bits CM17 to CM16 in the CM1 register to select the divide-by-n value.

When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to 0 and

bits CM17 to CM16 to 00b (undivided).

After reset, the main clock divided by 8 provides the CPU clock.

During memory expansion or microprocessor mode, a BCLK signal with the same frequency as the CPU

clock can be output from the BCLK pin by setting the PM07 bit of PM0 register to 0 (output enabled).

Note that when entering stop mode from high-speed or medium-speed mode, on-chip oscillator mode or

on-chip oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to 1 (main

clock turned off) in low-speed mode, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode).

8.2.2 Peripheral Function Clock

(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fCAN1, fC32)

These are operating clocks for the peripheral functions.

Two of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator

clock by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial interface.

The f8 and f32 clocks can be output from the CLKOUT pin.

The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the

A/D converter.

The fCANi (i =0, 1) clock is derived from the main clock, PLL clock or on-chip oscillator clock by dividing

them by 1 (undivided), 2, 4, 8, or 16, and is used for the CAN module.

When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral

function clock turned off during wait mode), or when the MCU is in low power dissipation mode, the fi,

fiSIO, fAD, fCAN0, and fCAN1 clocks are turned off (1).

The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used

when the sub clock is on.

NOTE:

1. fCAN0 and fCAN1 clocks stop at “H” in CAN0, 1 sleep mode.

8.3 Clock Output Function

During single-chip mode, the f8, f32, or fC clock can be output from the CLKOUT pin. Use bits CM01 to

CM00 in the CM0 register to select.

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M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.4 Power Control

Normal operating mode, wait mode and stop mode are provided as the power consumption control.

All mode states, except wait mode and stop mode, are called normal operating mode in this document.

8.4.1 Normal Operating Mode

Normal operating mode is further classified into seven sub modes.

In normal operating mode, because the CPU clock and the peripheral function clocks both are on, the

CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock

frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU

clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are

turned off, the power consumption is further reduced.

Before the clock sources for the CPU clock can be switched over, the new clock source to which switched

must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a

sufficient wait time in a program until it becomes oscillating stably.

Note that operating modes cannot be changed directly from low speed or low power dissipation mode to

on-chip oscillator or on-chip oscillator low power dissipation mode. Nor can operating modes be changed

directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low-speed or low power

dissipation mode. Where the CPU clock source is changed from the on-chip oscillator to the main clock,

change the operating mode to the medium-speed mode (divide-by-8 mode) after the clock was divided by

8 (the CM06 bit in the CM0 register was set to 1) in the on-chip oscillator mode.

8.4.1.1 High-Speed Mode

The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the

count source for timers A and B.

8.4.1.2 PLL Operating Mode

The main clock multiplied by 2, 4, or 6 (1) provides the PLL clock, and this PLL clock serves as the CPU

clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operating

mode can be entered from high speed mode. If PLL operating mode is to be changed to wait or stop

mode, first go to high speed mode before changing.

NOTE:

1. The main clock multiplied by 6 is available Normal-ver. only.

8.4.1.3 Medium-Speed Mode

The main clock divided by 2, 4, 8, or 16 provides the CPU clock. If the sub clock is on, fC32 can be used

as the count source for timers A and B.

8.4.1.4 Low-Speed Mode

The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral

function clock when the CM21 bit in the CM2 register is set to 0 (on-chip oscillator turned off), and the

on-chip oscillator clock is used when the CM21 bit is set to 1 (on-chip oscillator oscillating).

The fC32 clock can be used as the count source for timers A and B.

8.4.1.5 Low Power Dissipation Mode

In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides

the CPU clock. The fC32 clock can be used as the count source for timers A and B.

Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes 1 (divide-by-8

mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium

speed (divide-by-8) mode is to be selected when the main clock is operated next.

Rev.2.40 Apr 14, 2006 page 64 of 376

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M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.4.1.6 On-chip Oscillator Mode

The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip

oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can

be used as the count source for timers A and B. When the operating mode is returned to the high-speed

and medium-speed modes, set the CM06 bit in the CM0 register to 1 (divide-by-8 mode).

8.4.1.7 On-chip Oscillator Low Power Dissipation Mode

The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be

selected as in on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral

function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B.

Table 8.3 lists the Setting Clock Related Bit and Modes.

Table 8.3 Setting Clock Related Bit and Modes

Modes

CM2 Register

CM1 Register CM0 Register

CM21 CM11

CM17

CM16

CM07 CM06 CM05 CM04

PLL operating mode 0 1 00b 0 0 0 -

High-speed mode 0 0 00b 0 0 0 -

Medium-

Divide-by-2

0 0 01b 0 0 0 -

speed

Divide-by-4

0 0 10b 0 0 0 -

mode

Divide-by-8

00 -0 10-

Divide-by-16

0 0 11b 0 0 0 -

Low-speed mode - 0 - 1 - 0 1

Low power 0 0 - 1 1 (1) 1 (1) 1

dissipation mode

On-chip

No division

1 0 00b 0 0 0 -

oscillator

Divide-by-2

1 0 01b 0 0 0 -

mode

Divide-by-4

1 0 10b 0 0 0 -

Divide-by-8

10 -0 10-

Divide-by-16

1 0 11b 0 0 0 -

On-chip oscillator 1 0 (NOTE 2) 0 (NOTE 2) 1 -

low power dissipation

mode

-: 0 or 1

NOTES:

1. When the CM05 bit is set to 1 (main clock turned off) in low-speed mode, the mode goes to low power

dissipation mode and the CM06 bit is set to 1 (divide-by-8 mode) simultaneously.

2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.

Rev.2.40 Apr 14, 2006 page 65 of 376

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M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.4.2 Wait Mode

In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the

watchdog timer. However, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog

timer count source), the watchdog timer remains active. Because the main clock, sub clock and on-chip

oscillator clock all are on, the peripheral functions using these clocks keep operating.

8.4.2.1 Peripheral Function Clock Stop Function

If the CM02 bit in the CM0 register is 1 (peripheral function clocks turned off during wait mode), the f1, f2,

f8, f32, f1SIO, f8SIO, f32SIO, fAD, fCAN0, and fCAN1 clocks are turned off when in wait mode, with the

power consumption reduced that much. However, fC32 remains on.

8.4.2.2 Entering Wait Mode

The MCU is placed into wait mode by executing the WAIT instruction.

When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to set the CM11 bit in the CM1

the chip can be reduced by setting the PLC07 bit in the PLC0 register to 0 (PLL stops).

8.4.2.3 Pin Status During Wait Mode

Table 8.4 lists the Pin Status During Wait Mode.

Table 8.4 Pin Status During Wait Mode

8.4.2.4 Exiting Wait Mode ______

The MCU exits wait mode by a hardware reset, NMI interrupt or peripheral function interrupt.

______

If the MCU exits wait mode by a hardware reset or NMI interrupt, set the peripheral function interrupt

priority bits ILVL2 to ILVL0 to 000b (interrupt disabled) before executing the WAIT instruction.

The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is 0 (peripheral function

clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If

the CM02 bit is 1 (peripheral function clocks turned off during wait mode), the peripheral functions using

the peripheral function clocks stop operating, so that only the peripheral functions clocked by external

signals can be used to exit wait mode.

Table 8.5 lists the Interrupts to Exit Wait Mode and Use Conditions.

Pin Memory Expansion Mode Single-chip Mode

Microprocessor Mode

A0 to A19, D0 to D15, Retains status before wait mode Does not become a bus control pin

_______ _______ ________

CS0 to CS3, BHE

______ _______ _________ _________

RD, WR, WRL, WRH “H”

___________

HLDA, BCLK “H”

ALE “L”

I/O ports Retains status before wait mode Retains status before wait mode

CLKOUT Does not become a CLKOUT pin Does not stop

•CM02 bit = 0: Does not stop

•CM02 bit = 1: Retains status before

wait mode

When fC selected

When f8, f32

selected

Rev.2.40 Apr 14, 2006 page 66 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Interrupt CM02 Bit = 0 CM02 Bit = 1

_______

NMI interrupt Can be used Can be used

Serial interface interrupt Can be used when operating with Can be used when operating with

internal or external clock external clock

Key input interrupt Can be used Can be used

A/D conversion interrupt Can be used in one-shot mode or - (Do not use)

single sweep mode

Timer A interrupt Can be used in all modes Can be used in event counter mode

Timer B interrupt or when the count source is fC32

______

INT interrupt Can be used Can be used

CAN0/1 wake-up interrupt Can be used in CAN sleep mode Can be used in CAN sleep mode

If the MCU exits wait mode by a peripheral function interrupt, set up the following before executing the

WAIT instruction.

(1) Set bits ILVL2 to ILVL0 in the interrupt control register, for peripheral function interrupts used to exit

wait mode.

Bits ILVL2 to ILVL0 in all other interrupt control registers, for peripheral function interrupts not used

to exit wait mode, are set to 000b (interrupt disabled).

(2) Set the I flag to 1.

(3) Start operating the peripheral functions used to exit wait mode.

When the peripheral function interrupt is used, an interrupt routine is performed as soon as an

interrupt request is acknowledged and the CPU clock is supplied again.

When the MCU exits wait mode by the peripheral function interrupt, the CPU clock is the same clock as

the CPU clock executing the WAIT instruction.

Table 8.5 Interrupts to Exit Wait Mode and Use Conditions

Rev.2.40 Apr 14, 2006 page 67 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.4.3 Stop Mode

In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.

Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least

amount of power is consumed in this mode. If the voltage applied to VCC pin is VRAM or more, the

internal RAM is retained.

However, the peripheral functions clocked by external signals keep operating.

Table 8.6 lists the Interrupts to Stop Mode and Use Conditions.

Table 8.6 Interrupts to Stop Mode and Use Conditions

Pin Memory Expansion Mode Single-chip Mode

Microprocessor Mode

A0 to A19, D0 to D15, Retains status before stop mode Does not become a bus control pin

_______ _______ ________

CS0 to CS3, BHE

______ _______ _________ _________

RD, WR, WRL, WRH “H”

___________

HLDA, BCLK “H”

ALE undefined

I/O ports Retains status before stop mode Retains status before stop mode

CLKOUT Does not become a CLKOUT pin “H”

Retains status before stop mode

When fC selected

When f8, f32

selected

8.4.3.1 Entering Stop Mode

The MCU is placed into stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks turned off).

At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the

CM1 register is set to 1 (main clock oscillator circuit drive capability high).

Before entering stop mode, set the CM20 bit in the CM2 register to 0 (oscillation stop, re-oscillation

detection function disabled).

Also, if the CM11 bit in the CM1 register is 1 (PLL clock for the CPU clock source), set the CM11 bit to 0

(main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to 0 (PLL turned off) before

entering stop mode.

8.4.3.2 Pin Status in Stop Mode

Table 8.7 lists the Pin Status in Stop Mode.

Table 8.7 Pin Status in Stop Mode

Interrupt Condition

_______

NMI interrupt Can be used

Key input interrupt Can be used

______

INT interrupt Can be used

Timer A interrupt Can be used

Timer B interrupt (when counting external pulses in event counter mode)

Serial interface interrupt Can be used (when external clock is selected)

CAN0/1 wake-up interrupt Can be used (when CAN sleep mode is selected)

Rev.2.40 Apr 14, 2006 page 68 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.4.3.3 Exiting Stop Mode _______

Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt.

_______

When the hardware reset or NMI interrupt is used to exit stop mode, set all ILVL2 to ILVL0 bits in the

interrupt control registers for the peripheral function interrupt to 000b (interrupt disabled) before setting

the CM10 bit in the CM1 register to 1.

When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to 1 after the following

settings are completed.

(1) Set bits ILVL2 to ILVL0 in the interrupt control registers to decide the peripheral priority level of the

peripheral function interrupt.

Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to 0 by setting the

all ILVL2 to ILVL0 bits to 000b (interrupt disabled).

(2) Set the I flag to 1.

(3) Start operation of peripheral function being used to exit wait mode.

When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when

an interrupt request is generated and the CPU clock is supplied again.

_______

When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is

as follows, in accordance with the CPU clock source setting before the MCU had entered stop mode.

• When the sub clock is the CPU clock before entering stop mode: Sub clock

• When the main clock is the CPU clock source before entering stop mode:

Main clock divided by 8

• When the on-chip oscillator clock is the CPU clock source before entering stop mode:

On-chip oscillator clock divided by 8

Rev.2.40 Apr 14, 2006 page 69 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.12 State Transition to Stop Mode and Wait Mode

Stop mode

Reset

Normal mode

PLL operating mode

High-speed mode,

Medium-Speed Mode

Medium-speed mode

(divided-by-8 mode)

Low-speed mode,

low power dissipation mode

Stop mode

Wait mode

Stop mode

WAIT

instruction

WAIT

instruction

WAIT

instruction

WAIT

instruction

CPU operation stoppedAll oscillators stopped

CM05, CM06, CM07: Bits in CM0 register

CM10, CM11: Bits in CM1 register

NOTES:

Do not go directly from PLL operating mode to wait or stop mode.

2.PLL operating mode can be entered from high-speed mode. Similarly, PLL operating mode can be changed back to high-speed mode.

3.Write to registers CM0 and CM1 per 16 bits with the CM21bit in the CM2 register = 0 (on-chip oscillator stops).

Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.

4.The on-chip oscillator clock divided by 8 provides the CPU clock.

5.Before entering stop mode, be sure to set the CM20 bit in the CM2 register to 0 (oscillation stop, re-oscillation detection function disabled).

Interrupt

CM10 = 1

(5)

CM07 = 0

CM06 = 1

CM05 = 0

CM11 = 0

CM10 = 1

(3)

CM10 = 1

(5)

Interrupt

CM10 = 1

(5)

Interrupt

(NOTES 1, 2)

Wait mode

Interrupt

When

low

power

dissipation

mode

When

low-

speed

mode

On-chip oscillator mode,

on-chip oscillator dissipation mode

Stop mode

CM10 = 1

(5)

Interrupt

(4)

Wait mode

Interrupt

Figure 8.12 shows the State Transition to Stop Mode and Wait Mode. Figure 8.13 shows the State Transition

in Normal Operating Mode.

Table 8.8 shows a state transition matrix describing allowed transition and setting. The vertical line shows

current state and horizontal line show state after transition.

Rev.2.40 Apr 14, 2006 page 70 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Figure 8.13 State Transition in Normal Operating Mode

CPU clock

: f(PLL)

CM07 = 0

CM06 = 0

CM17 = 0

CM16 = 0

PLL operating mode

PLC07 = 0

CM11 = 0

PLC07 = 1

CM11 = 1

(6)

CM04 = 1CM04 = 1 CM04 = 0 CM04 = 0 CM04 = 1

CM04 = 0

CM04 = 1

CM04 = 0

CM07 =1

(3)

CM07 = 0

(2) (4)

CPU clock

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

On-chip oscillator

mode

CM21 = 1

CM21 = 0

(7)

High-speed mode

CPU clock

: f(XIN)

CM07 = 0

CM06 = 0

CM17 = 0

CM16 = 0

CPU clock

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

On-chip oscillator

low power dissipation mode

On-chip oscillator

mode

On-chip oscillator

low power dissipation mode

On-chip oscillator

clock oscillation

Main clock oscillation

CM05 = 1

(1)

CM05 = 0

CM04, CM05, CM06, CM07: Bits in CM0 register

CM11, CM15, CM16, CM17: Bits in CM1 register

CM20, CM21 : Bits in CM2 register

PLC07 : Bit in PLC0 register

NOTES:

1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).

Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.

2. Wait the main clock oscillation stabilizes.

3. Switch clock after oscillation of sub clock is sufficiently stable.

4. Change bits CM17 and CM16 before changing the CM06 bit.

5. Transit in accordance with arrow.

6. The PM20 bit in the PM2 register become effective when the PLC07 bit is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set

to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16 MHz.

7. Set the CM06 bit to 1 (divide-by-8 mode) before changing back the operating mode from on-chip oscillator mode to high-speed or middle-speed

mode.

8. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode)

and the CM15 bit is fixed to 1 (drive capability High).

Medium-speed mode

(divide-by-2)

CPU clock

: f(XIN)/2

CM07 = 0

CM06 = 0

CM17 = 0

CM16 = 1

Medium-speed mode

(divide-by-4)

CPU clock

: f(XIN)/4

CM07 = 0

CM06 = 0

CM17 = 1

CM16 = 0

Medium-speed mode

(divide-by-8)

CPU clock

: f(XIN)/8

CM07 = 0

CM06 = 1

Medium-speed mode

(divide-by-16)

CPU clock

: f(XIN)/16

CM07 = 0

CM06 = 0

CM17 = 1

CM16 = 1

CPU clock

: f(PLL)

CM07 = 0

CM06 = 0

CM17 = 0

CM16 = 0

PLC07 = 0

CM11 = 0

PLC07 = 1

CM11 = 1

(6)

CPU clock

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

CM21 = 1

CM21 = 0

(7)

CM21 = 1

CM21 = 0

High-speed mode

CPU clock

: f(XIN)

CM07 = 0

CM06 = 0

CM17 = 0

CM16 = 0

CPU clock

f(Ring)

f(Ring)/2

f(Ring)/4

f(Ring)/8

f(Ring)/16

Sub clock oscillation

CM05 = 1

(1)

CM05 = 0

Medium-speed mode

(divide-by-2)

CPU clock

: f(XIN)/2

CM07 = 0

CM06 = 0

CM17 = 0

CM16 = 1

Medium-speed mode

(divide-by-4)

CPU clock

: f(XIN)/4

CM07 = 0

CM06 = 0

CM17 = 1

CM16 = 0

Medium-speed mode

(divide-by-8)

CPU clock

: f(XIN)/8

CM07 = 0

CM06 = 1

Medium-speed mode

(divide-by-16)

CPU clock

: f(XIN)/16

CM07 = 0

CM06 = 0

CM17 = 1

CM16 = 1

CPU clock: f(XCIN)

CM07 = 0

CPU clock: f(XCIN)

CM07 = 0

Low-speed modeLow-speed mode

CM05 = 1

(1) (8)

CM05 = 0

CPU clock: f(XCIN)

CM07 = 0

CM06 = 1

CM15 = 1

Low power dissipation mode

Rev.2.40 Apr 14, 2006 page 71 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

Table 8.8 Allowed Transition and Setting (9)

State after Transition

High-Speed Mode,

Low-Speed Low Power

PLL Operating

On-chip Oscillator

Stop Wait

Medium-Speed

Mode (2)

Dissipation Mode

Mode (2) Mode

Low Power

Mode Mode

Mode

Dissipation Mode

High-speed mode, (NOTE 8) (9) (7)

(13) (3) (15)

(16) (1) (17)

medium-speed mode

Low-speed (8) (11) (1) (6)

---

(16) (1) (17)

mode (2)

Low power

(10)

---

(16) (1) (17)

dissipation mode

PLL operating (12) (3)

-- ----

mode (2)

On-chip oscillator (14) (4)

---

(NOTE 8) (11) (1) (16) (1) (17)

mode

On-chip oscillator low

----

(10) (NOTE 8) (16) (1) (17)

power dissipation mode

Stop mode (18) (5) (18) (18)

(18) (5) (18) (5)

Wait mode (18) (18) (18)

(18) (18)

Current State

Sub Clock Oscillating Sub Clock Turned Off

Divide- Divide- Divide- Divide-

Division

by-2 by-4 by-8 by-16

Division

by-2 by-4 by-8 by-16

No division

(4) (5) (7) (6) (1)

----

Divide-by-2

(3) (5) (7) (6)

(1)

---

Divide-by-4

(3) (4) (7) (6)

(1)

Divide-by-8

(3) (4) (5) (6)

---

(1)

Divide-by-16

(3) (4) (5) (7)

----

(1)

No division

(2)

----

(4) (5) (7) (6)

Divide-by-2

(2)

---

(3) (5) (7) (6)

Divide-by-4

(2)

(3) (4) (7) (6)

Divide-by-8

---

(2)

(3) (4) (5) (6)

Divide-by-16

----

(2) (3) (4) (5) (7)

Sub Clock Oscillating

Sub Clock Turned Off

Setting Operation

(1) CM04=0 Sub clock turned off

(2) CM04=1 Sub clock oscillating

(3) CM06=0 CPU clock no division

CM17=0 mode

CM16=0

(4) CM06=0 CPU clock divide-by-2

CM17=0 mode

CM16=1

(5) CM06=0 CPU clock divide-by-4

CM17=1 mode

CM16=0

(6) CM06=0 CPU clock divide-by-16

CM17=1 mode

CM16=1

(7) CM06=1

CPU clock divide-by-8 mode

(8) CM07=0 Main clock, PLL clock

or on-chip oscillator

clock selected

(9) CM07=1 Sub clock selected

(10)

CM05=0 Main clock oscillating

(11)

CM05=1 Main clock turned off

(12)

PLC07=0 Main clock selected

CM11=0

(13)

PLC07=1 PLL clock selected

CM11=1

(14)

CM21=0 Main clock or

PLL clock selected

(15)

CM21=1 On-chip oscillator clock

selected

(16)

CM10=1 Transition to stop mode

(17)

WAIT Transition to wait mode

instruction

(18)

Hardware Exit stop mode or wait

interrupt mode

-: Cannot transit

NOTES:

1. Avoid making a transition when the CM20 bit is set to 1 (oscillation

stop, re-oscillation detection function enabled). Set the CM20 bit to 0 (oscillation

stop, re-oscillation detection function disabled) before transiting.

2. On-chip oscillator clock oscillates and stops in low-speed mode. In this

mode, the on-chip oscillator can be used as peripheral function clock. Sub

clock oscillates and stops in PLL operating mode. In this mode, sub clock

can be used as peripheral function clock.

3. PLL operating mode can only be entered from and changed to high-speed

mode.

4. Set the CM06 bit to 1 (divide-by-8 mode) before transiting from on-chip

oscillator mode to high-speed or medium-speed mode.

5. When exiting stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

6. If the CM05 bit is set to 1 (main clock stop), then the CM06 bit is set to 1

(divide-by-8 mode).

7. A transition can be made only when sub clock is oscillating.

8. State transitions within the same mode (divide-by-n values changed or sub

clock oscillation turned on or off) are shown in the table below.

CM04, CM05, CM06, CM07: Bits in CM0 register

CM10, CM11, CM16, CM17: Bits in CM1 register

CM20, CM21 : Bits in CM2 register

PLC07 : Bit in PLC0 register

9. ( ):setting method. See right table.

Rev.2.40 Apr 14, 2006 page 72 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.5 Oscillation Stop and Re-oscillation Detection Function

The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and

re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation

detection interrupt request are generated. Which is to be generated can be selected using the CM27 bit in

the CM2 register.

The oscillation stop and re-oscillation detection function can be enabled and disabled using the CM20 bit in

the CM2 register.

Table 8.9 lists a Specification Overview of Oscillation Stop and Re-oscillation Detection Function.

Table 8.9 Specification Overview of Oscillation Stop and Re-oscillation Detection Function

Item Specification

Oscillation stop detectable clock and f(XIN) ≥ 2 MHz

frequency bandwidth

Enabling condition for oscillation stop Set CM20 bit to 1 (enabled)

and re-oscillation detection function

Operation at oscillation stop, •Reset occurs (when CM27 bit = 0)

re-oscillation detection •

Oscillation stop, re-oscillation detection interrupt is generated (when CM27 bit =1)

8.5.1 Operation when CM27 Bit = 0 (Oscillation Stop Detection Reset)

Where main clock stop is detected when the CM20 bit is 1 (oscillation stop, re-oscillation detection function

enabled), the MCU is initialized, coming to a halt (oscillation stop reset; refer to 4. Special Function

Registers (SFRs), 5. Resets).

This status is reset with hardware reset. Also, even when re-oscillation is detected, the MCU can be

initialized and stopped; it is, however, necessary to avoid such usage (During main clock stop, do not set

the CM20 bit to 1 and the CM27 bit to 0).

8.5.2 Operation when CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt)

Where the main clock corresponds to the CPU clock source and the CM20 bit is 1 (oscillation stop, re-oscillation

detection function enabled), the system is placed in the following state if the main clock comes to a halt:

•Oscillation stop, re-oscillation detection interrupt request is generated.

•The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source for

CPU clock and peripheral functions in place of the main clock.

•CM21 bit = 1 (on-chip oscillator clock is the clock source for CPU clock)

•CM22 bit = 1 (main clock stop detected)

•CM23 bit = 1 (main clock stopped)

Where the PLL clock corresponds to the CPU clock source and the CM20 bit is 1, the system is placed in

the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to 1

(on-chip oscillator clock) inside the interrupt routine.

•Oscillation stop, re-oscillation detection interrupt request is generated.

•CM22 bit = 1 (main clock stop detected)

•CM23 bit = 1 (main clock stopped)

•CM21 bit remains unchanged

Where the CM20 bit is 1, the system is placed in the following state if the main clock re-oscillates from the

stop condition:

•Oscillation stop, re-oscillation detection interrupt request is generated.

•CM22 bit = 1 (main clock re-oscillation detected)

•CM23 bit = 0 (main clock oscillation)

•CM21 bit remains unchanged

Rev.2.40 Apr 14, 2006 page 73 of 376

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M16C/6N Group (M16C/6N4) 8. Clock Generation Circuit

8.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function

•The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt.

If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the

CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.

•Where the main clock re-oscillated after oscillation stop, the clock source for the CPU clock and peripheral

function must be switched to the main clock in the program. Figure 8.14 shows the Procedure to Switch

Clock Source from On-chip Oscillator to Main Clock.

•Simultaneously with oscillation stop, re-oscillation detection interrupt request occurrence, the CM22 bit

becomes 1. When the CM22 bit is set at 1, oscillation stop, re-oscillation detection interrupt are disabled.

By setting the CM22 bit to 0 in the program, oscillation stop, re-oscillation detection interrupt are

enabled.

•If the main clock stops during low speed mode where the CM20 bit is 1, an oscillation stop, re-oscillation

detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating. In this

case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the

peripheral function clocks now are derived from the on-chip oscillator clock.

•To enter wait mode while using the oscillation stop and re-oscillation detection function, set the CM02

bit to 0 (peripheral function clocks not turned off during wait mode).

•Since the oscillation stop and re-oscillation detection function is provided in preparation for main clock

stop due to external sources, set the CM20 bit to 0 (oscillation stop, re-oscillation detection function

disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is

selected or the CM05 bit is altered.

•This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to 0.

Figure 8.14 Procedure to Switch Clock Source from On-chip Oscillator to Main Clock

Switch the main clock

YES

Determine several times

whether the CM23 bit is set to 0

(main clock oscillates)

Set the CM22 bit to 0 (main clock stop,

re-oscillation not detected)

Set the CM06 bit to 1 (divide-by-8)

Set the CM21 bit to 0 (main clock

or PLL clock as CPU clock source)

(1)

End

CM06 bit : Bit in CM0 register

Bits CM21, CM22, CM 23: Bits in CM2 register

NOTE:

1. If the clock source for CPU clock is to be changed to PLL clock,

set to PLL operating mode after set to high-speed mode.

Rev.2.40 Apr 14, 2006 page 74 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 9. Protection

9. Protection

In the event that a program runs out of control, this function protects the important registers so that they will

not be rewritten easily.

Figure 9.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.

• Registers protected by the PRC0 bit: Registers CM0, CM1, CM2, PLC0, PCLKR, and CCLKR

• Registers protected by the PRC1 bit: Registers PM0, PM1, PM2, TB2SC, INVC0, and INVC1

• Registers protected by the PRC2 bit: Registers PD7, PD9, and S3C

Set the PRC2 bit to 1 (write enabled) and then write to given address, and the PRC2 bit will be set to 0 (write

protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting

the PRC2 bit to 1. Make sure no interrupts or DMA transfers will occur between the instruction in which the

PRC2 bit is set to 1 and the next instruction. Bits PRC0 and PRC1 are not automatically set to 0 by writing

to given address. They can only be set to 0 in a program.

Figure 9.1 PRCR Register

PRC1

PRC0

PRC2

Protect bit 1

Protect bit 0

Protect bit 2

Writing to registers CM0, CM1,

CM2, PLC0, PCLKR, CCLKR

is enabled

0 : Write protected

1 : Write enabled

Writing to registers PM0, PM1,

PM2, TB2SC, INVC0, INVC1

is enabled

0 : Write protected

1 : Write enabled

Writing to registers PD7, PD9,

S3C is enabled

0 : Write protected

1 : Write enabled (1)

Reserved bits Set to 0 RW

(b5-b3)

(b7-b6) Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

b7 b6 b5 b4 b3 b2 b1 b0

Protect Register

Symbol Address After Reset

PRCR 000Ah XX000000b

Bit NameBit Symbol Function

NOTE:

1. The PRC2 bit is set to 0 by writing to given address after setting it to 1. Other bits are not set to 0 by writing to

given address, and must therefore be set in a program.

0 0

Rev.2.40 Apr 14, 2006 page 75 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.1 Types of Interrupts

• Maskable interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority can be changed by priority level.

• Non-maskable interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority cannot be changed by priority level.

Interrupt











Software

(Non-maskable interrupt)

Hardware











Special

(Non-maskable interrupt)

Peripheral function (1)

(Maskable interrupt)











Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

INT instruction











_______

NMI

________

DBC (2)

Oscillation stop and re-oscillation detection

Watchdog timer

Single step (2)

Address match

NOTES:

1. The peripheral functions in the MCU are used to generate the peripheral interrupt.

2. Do not normally use this interrupt because it is provided exclusively for use by development

tools.

10. Interrupts

10.1 Type of Interrupts

Figure 10.1 shows the Types of Interrupts.

Rev.2.40 Apr 14, 2006 page 76 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.2 Software Interrupts

A software interrupt is generated when executing certain instructions. Software interrupts are non-

maskable interrupts.

10.2.1 Undefined Instruction Interrupt

An undefined instruction interrupt is generated when executing the UND instruction.

10.2.2 Overflow Interrupt

An overflow interrupt is generated when executing the INTO instruction with the O flag in the FLG register

set to 1 (the operation resulted in an overflow). The following are instructions whose O flag changes by

arithmetic:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

10.2.3 BRK Interrupt

A BRK interrupt is generated when executing the BRK instruction.

10.2.4 INT Instruction Interrupt

An INT instruction interrupt is generated when executing the INT instruction. Software interrupt Nos. 0 to

63 can be specified for the INT instruction. Because software interrupt Nos. 1 to 31 are assigned to

peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be

executed by executing the INT instruction.

In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is set

to 0 (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when

returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state

during instruction execution, and the SP then selected is used.

Rev.2.40 Apr 14, 2006 page 77 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.3 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.

10.3.1 Special Interrupts

Special interrupts are non-maskable interrupts.

_______

10.3.1.1 NMI Interrupt

_______ _______

An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details,

_______

refer to 10.7 NMI Interrupt.

________

10.3.1.2 DBC Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development tools.

10.3.1.3 Watchdog Timer Interrupt

Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the

watchdog timer. For details about the watchdog timer, refer to 11. Watchdog Timer.

10.3.1.4 Oscillation Stop and Re-oscillation Detection Interrupt

Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation

stop and re-oscillation detection function, refer to 8. Clock Generation Circuit.

10.3.1.5 Single-Step Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development tools.

10.3.1.6 Address Match Interrupt

An address match interrupt is generated immediately before executing the instruction at the address

indicated by registers RMAD0 to RMAD3 that corresponds to one of the AIER0 or AIER1 bit in the AIER

For details, refer to 10.10 Address Match Interrupt.

10.3.2 Peripheral Function Interrupts

The peripheral function interrupt is generated when a request from the peripheral functions in the MCU is

acknowledged. The peripheral function interrupt is a maskable interrupt. See Table 10.2 Relocatable

Vector Tables about how the peripheral function interrupt occurs. Refer to the descriptions of each

function for details.

Rev.2.40 Apr 14, 2006 page 78 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.2 Interrupt Vector

10.4.1 Fixed Vector Tables

The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 10.1 lists the Fixed

Vector Tables. In the flash memory version of MCU, the vector addresses (H) of fixed vectors are used by

the ID code check function. For details, refer to 21.2 Functions to Prevent Flash Memory from Rewriting.

Table 10.1 Fixed Vector Tables

10.4 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective

interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the

corresponding interrupt vector. Figure 10.2 shows the Interrupt Vector.

Low-order address

Middle-order address

Vector address (L)

Vector address (H)

0 0 0 0

0 0 0 0 0 0 0 0

MSB LSB

High-order address

Interrupt Source

Vector table Addresses

Reference

Address (L) to Address (H)

Undefined instruction (UND instruction) FFFDChto FFFDFh M16C/60, M16C/20, M16C/Tiny

Overflow (INTO instruction) FFFE0h to FFFE3h Series Software Manual

BRK instruction (2) FFFE4h to FFFE7h

Address match FFFE8h to FFFEBh 10.10 Address Match Interrupt

Single step (1) FFFECh to FFFEFh -

Oscillation stop and re-oscillation detection, FFFF0h to FFFF3h 8. Clock Generation Circuit

Watchdog timer 11. Watchdog Timer

________

DBC (1) FFFF4h to FFFF7h -

_______

NMI FFFF8h to FFFFBh

_______

10.7 NMI Interrupt

Reset FFFFCh to FFFFFh 5. Resets

NOTES:

1. Do not normally use this interrupt because it is provided exclusively for use by development tools.

2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the

vector in the relocatable vector table.

Rev.2.40 Apr 14, 2006 page 79 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

BRK Instruction (2)

CAN0/1 wake-up (10)

CAN0 successful reception

CAN0 successful transmission

________

INT3

Timer B5

Timer B4, UART1 bus collision detection

(3) (9)

Timer B3, UART0 bus collision detection

(4) (9)

________

CAN1 successful reception, INT5 (5)

________

SI/O3, CAN1 successful transmission, INT4

(6)

UART2 bus collision detection (9)

DMA0

DMA1

CAN0/1 error (11)

A/D, key input (7)

UART2 transmission, NACK2 (8)

UART2 reception, ACK2 (8)

UART0 transmission, NACK0 (8)

UART0 reception, ACK0 (8)

UART1 transmission, NACK1 (8)

UART1 reception, ACK1 (8)

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

Timer B0

Timer B1

Timer B2

________

INT0

________

INT1

________

INT2

INT instruction interrupt (2)

+0 to +3 (0000h to 0003h)

+4 to +7 (0004h to 0007h)

+8 to +11 (0008h to 000Bh)

+12 to +15 (000Ch to 000Fh)

+16 to +19 (0010h to 0013h)

+20 to +23 (0014h to 0017h)

+24 to +27 (0018h to 001Bh)

+28 to +31 (001Ch to 001Fh)

+32 to +35 (0020h to 0023h)

+36 to +39 (0024h to 0027h)

+40 to +43 (0028h to 002Bh)

+44 to +47 (002Ch to 002Fh)

+48 to +51 (0030h to 0033h)

+52 to +55 (0034h to 0037h)

+56 to +59 (0038h to 003Bh)

+60 to +63 (003Ch to 003Fh)

+64 to +67 (0040h to 0043h)

+68 to +71 (0044h to 0047h)

+72 to +75 (0048h to 004Bh)

+76 to +79 (004Ch to 004Fh)

+80 to +83 (0050h to 0053h)

+84 to +87 (0054h to 0057h)

+88 to +91 (0058h to 005Bh)

+92 to +95 (005Ch to 005Fh)

+96 to +99 (0060h to 0063h)

+100 to +103 (0064h to 0067h)

+104 to +107 (0068h to 006Bh)

+108 to +111 (006Ch to 006Fh)

+112 to +115 (0070h to 0073h)

+116 to +119 (0074h to 0077h)

+120 to +123 (0078h to 007Bh)

+124 to +127 (007Ch to 007Fh)

+128 to +131 (0080h to 0083h)

+252 to + 255 (00FCh to 00FFh)

Software

Interrupt Number

M16C/60, M16C/20, M16C/Tiny

Series Software Manual

19. CAN Module

______

10.6 INT Interrupt

13. Timers

15. Serial Interface

______

19. CAN Module, 10.6 INT Interrupt

______

15. Serial Interface, 19. CAN Module, 10.6 INT Interrupt

15. Serial Interface

12. DMAC

19. CAN Module

16. A/D Convertor, 10.8 Key Input Interrupt

15. Serial Interface

13. Timers

______

10.6 INT Interrupt

M16C/60, M16C/20, M16C/Tiny

Series Software Manual

Interrupt Source Vector Address (1)

Address (L) to Address (H) Reference

NOTES:

1. Address relative to address in INTB.

2. These interrupts cannot be disabled using the I flag.

3. Use the IFSR07 bit in the IFSR0 register to select.

4. Use the IFSR06 bit in the IFSR0 register to select.

5. Use the IFSR17 bit in the IFSR1 register to select.

6. Use the IFSR16 bit in the IFSR1 register to select.

Furthermore, use the IFSR00 bit in the IFSR0 register to select, when selecting SI/O3 or CAN1 successful transmission.

7. Use the IFSR01 bit in the IFSR0 register to select.

8. During I2C mode, NACK and ACK interrupts comprise the interrupt source.

9. Bus collision detection: During IE mode, this bus collision detection constitutes the interrupt source.

During I2C mode, a start condition or a stop condition detection constitutes the interrupt source.

10. Use the IFSR02 bit in the IFSR0 register to select. When the IFSR02 bit = 0, CAN0/1 wake-up is selected. When the

IFSR02 bit = 1, CAN0 wake-up/error is selected.

11. Use the IFSR02 bit in the IFSR0 register to select. When the IFSR02 bit = 0, CAN0/1 error is selected. When the IFSR02

bit = 1, CAN1 wake-up/error is selected.

10.4.2 Relocatable Vector Tables

The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector

table area. Table 10.2 lists the Relocatable Vector Tables. Setting an even address in the INTB register

results in the interrupt sequence being executed faster than in the case of odd addresses.

Table 10.2 Relocatable Vector Tables

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.5 Interrupt Control

The following describes how to enable/disable the maskable interrupts, and how to set the priority in which

order they are accepted. What is explained here does not apply to non-maskable interrupts.

Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to

enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the

each interrupt control register.

Figures 10.3 and 10.4 show the Interrupt Control Registers.

Figure 10.3 Interrupt Control Registers (1)

0041h

0042h

0043h

0045h

0046h

0047h

004Ah

004Bh, 004Ch

004Dh

004Eh

0051h, 0053h, 004Fh

0052h, 0054h, 0050h

0055h to 0059h

005Ah to 005Ch

Interrupt Control Register (1)

C01WKIC (5)

C0RECIC

C0TRMIC

TB5IC

TB4IC/U1BCNIC (2)

TB3IC/U0BCNIC (3)

U2BCNIC

DM0IC, DM1IC

C01ERRIC (6)

ADIC/KUPIC (7)

S0TIC to S2TIC

S0RIC to S2RIC

TA0IC to TA4IC

TB0IC to TB2IC

XXXXX000b

NOTES:

1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that

2. Use the IFSR07 bit in the IFSR0 register to select.

3. Use the IFSR06 bit in the IFSR0 register to select.

4. This bit can only be reset by writing 0 (do not write 1).

5. When the IFSR02 bit in the IFSR0 register = 0 (CAN0/1 wake-up or error), CAN0/1 wake-up is selected.

When the IFSR02 bit = 1 (CAN0 wake-up/error or CAN1 wake-up/error), CAN0 wake-up/error is selected.

6. When the IFSR02 bit = 0, CAN0/1 error is selected. When the IFSR02 bit = 1, CAN1 wake-up/error is selected.

7. Use the IFSR01 bit in the IFSR0 register to select.

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

0 : Interrupt not requested

1 : Interrupt requested

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

RW (4)

Interrupt request bit

Interrupt priority level

select bits

Bit Name FunctionBit Symbol

ILVL0

ILVL1

ILVL2

(b7-b4)

Symbol Address After Reset

b7 b6 b5 b4 b3 b2 b1 b0

Rev.2.40 Apr 14, 2006 page 81 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.4 Interrupt Control Registers (2)

0044h

0048h

0049h

005Dh to 005Fh

Interrupt Control Register

(1)

INT3IC

(2)

C1RECIC/INT5IC

(2) (6)

C1TRMIC/S3IC/INT4IC

(2) (7)

INT0IC to INT2IC

XX00X000b

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

0 : Interrupt not requested

1 : Interrupt requested

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

(3)

Interrupt request bit

Interrupt priority level

select bits

Bit Name FunctionBit Symbol RW

Symbol Address After Reset

b7 b6 b5 b4 b3 b2 b1 b0

ILVL0

0 : Selects falling edge

(4) (5)

1 : Selects rising edge

ILVL1

ILVL2

(b7-b6)

Set to 0

Polarity select bit

POL

Reserved bit

(b5)

NOTES:

1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that

2. When the BYTE pin is low and the processor mode is memory expansion or microprocessor mode, set bits

ILVL2 to ILVL0 in registers INT5IC to INT3IC to 000b (interrupt disabled).

3. This bit can only be reset by writing 0 (do not write 1).

4. If bits IFSR10 to IFSR15 in the IFSR1 register are 1 (both edges), set the POL bit in registers INT0IC to INT5IC

to 0 (falling edge).

5. Set the POL bit in the S3IC register to 0 (falling edge) when the IFSR00 bit in the IFSR0 register = 1 and the

IFSR16 bit in the IFSR1 register = 0 (SI/O3 selected).

6. Use the IFSR17 bit in the IFSR1 register to select.

7. Use the IFSR16 bit in the IFSR1 register and the IFSR00 bit in the IFSR0 register to select.

Rev.2.40 Apr 14, 2006 page 82 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.5.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the

maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.

10.5.2 IR Bit

The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the inter-

rupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set to

0 (interrupt not requested).

The IR bit can be set to 0 in a program. Note that do not write 1 to this bit.

10.5.3 Bits ILVL2 to ILVL0 and IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0.

Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority levels

enabled by the IPL.

The following are conditions under which an interrupt is accepted:

· I flag = 1

· IR bit = 1

· interrupt priority level > IPL

The I flag, IR bit, bits ILVL2 to ILVL0 and IPL are independent of each other. In no case do they affect one

another.

Table 10.4 Interrupt Priority Levels Enabled by IPL

Table 10.3 Settings of Interrupt Priority Levels

IPL Enabled Interrupt Priority Levels

000b

Interrupt levels 1 and above are enabled

001b

Interrupt levels 2 and above are enabled

010b

Interrupt levels 3 and above are enabled

011b

Interrupt levels 5 and above are enabled

100b

Interrupt levels 5 and above are enabled

101b

Interrupt levels 6 and above are enabled

110b

Interrupt levels 7 and above are enabled

111b

All maskable interrupts are disabled

Bits ILVL2 to ILVL0

Interrupt Priority Level

Priority Order

000b Level 0

(Interrupt disabled)

001b Level 1 Low

010b Level 2

011b Level 3

100b Level 4

101b Level 5

110b Level 6

111b Level 7 High

Rev.2.40 Apr 14, 2006 page 83 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.5.4 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the

instant the interrupt routine is executed — is described here.

If an interrupt request is generated while an instruction is being executing, the CPU determines its priority

when the execution of the instruction is completed, and transfers control to the interrupt sequence from

the next cycle. However, for the SMOVB, SMOVF, SSTR or RMPA instruction, if an interrupt request is

generated while the instruction is being executing, the MCU temporarily suspends the instruction being

executed, and transfers control to the interrupt sequence.

The CPU behavior during the interrupt sequence is described below.

Figure 10.5 shows the Time Required for Executing Interrupt Sequence.

(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading

address 000000h. Then, the IR bit applicable to the interrupt information is set to 0 (interrupt

requested).

(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register (1) within the CPU.

(3) Flags I, D, and U in the FLG register become as follows:

• The I flag is set to 0 (interrupt disabled)

• The D flag is set to 0 (single-step interrupt disabled)

• The U flag is set to 0 (ISP selected)

However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is

executed.

(4) The temporary register (1) within the CPU is saved to the stack.

(5) The PC is saved to the stack.

(6) The interrupt priority level of the acknowledged interrupt in IPL is set.

(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, an instruction is executed from the starting address of the

interrupt routine.

NOTE:

1. This register cannot be accessed by user.

Figure 10.5 Time Required for Executing Interrupt Sequence

123456789 101112 13 14 15 16 17 18

SP-2

contents SP-4

contents vec

contents vec+2

contents

Interrupt

information

Address

0000h SP-2 SP-4 vec vec+2 PC

CPU clock

Address bus

Data bus

WR (2)

NOTES:

1. The undefined state depends on the instruction queue buffer.

A read cycle occurs when the instruction queue buffer is ready to accept instructions.

2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.

Undefined (1)

Rev.2.40 Apr 14, 2006 page 84 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.6 Interrupt Response Time

10.5.6 Variation of IPL when Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set

in the IPL.

When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed

in Table 10.5 is set in the IPL. Table 10.5 shows the IPL Level that is Set to IPL when Software or Special

Interrupts is Accepted.

Table 10.5 IPL Level that is Set to IPL when Software or Special Interrupt is Accepted

10.5.5 Interrupt Response Time

Figure 10.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time

denotes a time from when an interrupt request is generated till when the first instruction in the interrupt

routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when

the instruction then executing is completed ((a) on Figure 10.6) and a time during which the interrupt

sequence is executed ((b) on Figure 10.6).

Interrupt Sources Value that is Set to IPL

_______

Oscillation stop and re-oscillation detection, Watchdog timer, NMI

_________

Software, Address match, DBC, Single-step

Interrupt Vector Address SP Value 16-bit Bus, without Wait 8-bit Bus, without Wait

Even

Odd

Even

Odd

Even

Odd

18 cycles

19 cycles

20 cycles

Instruction Interrupt sequence Instruction in

interrupt routine

Time

Interrupt response time

(a) (b)

Interrupt request acknowledgedInterrupt request generated

(a) A time from when an interrupt request is generated till when the instruction then

executing is completed. The length of this time varies with the instruction being

executed. The DIVX instruction requires the longest time, which is equal to 30 cycles

(without wait state, the divisor being a register).

(b) A time during which the interrupt sequence is executed. For details, see the table

below. Note, however, that the values in this table must be increased 2 cycles for the

DBC interrupt and 1 cycle for the address match and single-step interrupts.

Not changed

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.5.7 Saving Registers

In the interrupt sequence, the FLG register and PC are saved to the stack.

At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG

Figure 10.7 shows the Stack Status Before and After Acceptance of Interrupt Request.

The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use

the PUSHM instruction, and all registers except SP can be saved with a single instruction.

Figure 10.7 Stack Status Before and After Acceptance of Interrupt Request

The register saving operation carried out in the interrupt sequence is dependent on whether the SP (1), at

the time of acceptance of an interrupt request, is even or odd. If the SP (1) is even, the FLG register and

the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.

Figure 10.8 shows the Register Saving Operation.

NOTE:

1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated

by the U flag. Otherwise, it is the ISP.

m + 1

[SP]

SP value before

interrupt request

is accepted.

Stack status before interrupt request is acknowledged

Address

MSB LSB

Stack

m + 1

[SP]

New SP value

Stack status after interrupt request is acknowledged

Address

MSB LSB

Stack

PCL

PCM

FLGL

Content of previous stack

FLGH PCH

PCL : 8 low-order bits of PC

PCM : 8 middle-order bits of PC

PCH : 4 high-order bits of PC

FLGL : 8 low-order bits of FLG

FLGH: 4 high-order bits of FLG

Figure 10.8 Register Saving Operation

[SP]

5 (Odd)

[SP]

4 (Even)

[SP]

3 (Odd)

[SP]

2 (Even)

[SP]

1 (Odd)

[SP]

(Even)

[SP]

5 (Even)

[SP]

4 (Odd)

[SP]

3 (Even)

[SP]

2 (Odd)

[SP]

1 (Even)

[SP]

(Odd)

(2)

Saved simultaneously,

all 16 bits

(1)

Saved simultaneously,

all 16 bits

Address Stack Sequence in which order

registers are saved

Sequence in which order

registers are saved

Address Stack

PCL

PCM

FLGL

NOTE:

1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.

FLGH PCH

PCL

PCM

FLGL

FLGH PCH

(1)SP contains even number (2)SP contains odd number

Finished saving registers

in two operations.

Finished saving registers

in four operations.

(3)

(4)

(1)

(2)

Saved,8 bits

at a time

PCL : 8 low-order bits of PC

PCM : 8 middle-order bits of PC

PCH : 4 high-order bits of PC

FLGL : 8 low-order bits of FLG

FLGH: 4 high-order bits of FLG

Rev.2.40 Apr 14, 2006 page 86 of 376

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M16C/6N Group (M16C/6N4) 10. Interrupts

10.5.8 Returning from Interrupt Routine

The FLG register and PC in the state in which they were immediately before entering the interrupt

sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.

Thereafter the CPU returns to the program which was being executed before accepting the interrupt

request.

Return the other registers saved by a program within the interrupt routine using the POPM or similar

instruction before executing the REIT instruction.

10.5.9 Interrupt Priority

If two or more interrupt requests are sampled at the same sampling points (a timing to detect whether an

interrupt request is generated or not), the interrupt request with the highest priority is acknowledged.

For maskable interrupts (peripheral functions interrupt), any desired priority level can be selected using

bits ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their

interrupt priority is resolved by hardware, with the highest priority interrupt accepted.

The watchdog timer and other special interrupts have their priority levels set in hardware.

Figure 10.9 shows the Hardware Interrupts Priority.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Figure 10.9 Hardware Interrupt Priority

10.5.10 Interrupt Priority Level Select Circuit

The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt

requests are sampled at the same sampling point.

Figure 10.10 shows the Interrupts Priority Select Circuit.

Reset

Oscillation stop and re-oscillation detection

Watchdog timer

Peripheral function

Single step

Address match

High

Low

NMI

DBC

Rev.2.40 Apr 14, 2006 page 87 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.10 Interrupts Priority Select Circuit

Timer B2

Timer B0

Timer A3

Timer A1

Timer B1

Timer A4

DMA1

DMA0

SI/O3, CAN1 successful transmission, INT4

INT1

UART2 reception, ACK2

Level 0

(initial value)

Priority level of each interrupt Highest

Lowest

Priority of peripheral function interrupts

(if priority levels are same)

UART1 reception, ACK1

UART0 reception, ACK0

Timer A2

Timer A0

INT2

INT0

INT3

Timer B5

Interrupt request level resolution output to clock generation circuit

(Figure 8.1 Clock Generation Circuit)

Interrupt request accepted

IPL

I flag

DBC

NMI

CAN1 successful reception, INT5

UART1 transmission, NACK1

UART0 transmission, NACK0

A/D conversion, Key input

UART2 bus collision detection

CAN0 successful reception

UART2 transmission, NACK2

CAN0/1 error

Timer B4, UART1 bus collision detection

Timer B3, UART0 bus collision detection

CAN0 successful transmission

CAN0/1 wake-up

Oscillation stop and re-oscillation detection

Watchdog timer

Address match

Rev.2.40 Apr 14, 2006 page 88 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 10. Interrupts

______

10.6 INT Interrupt

_______

INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using bits

IFSR10 to IFSR15 in the IFSR1 register.

________

INT4 share the interrupt vector and interrupt control register with CAN1 successful transmission and SI/O3.

________

INT5 share the interrupt vector and interrupt control register with CAN1 successful reception. To use the

________ ________ ________

INT4 interrupt, set the IFSR16 bit in the IFSR1 register to 1 (INT4). To use the INT5 interrupt, set the

________

IFSR17 bit in the IFSR1 register to 1 (INT5).

After modifying the IFSR16 or IFSR17 bit, set the corresponding IR bit to 0 (interrupt not requested) before

enabling the interrupt.

Figure 10.11 shows Registers IFSR0 and IFSR1.

Rev.2.40 Apr 14, 2006 page 89 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.11 Registers IFSR0 and IFSR1

NOTES:

1.Timer B3 and UART0 bus collision detection share the vector and interrupt control register.

When using the timer B3 interrupt, set the IFSR06 bit to 0 (tmer B3).

When using UART0 bus collision detection, set the IFSR06 bit to 1 (UART0 bus collision detection).

2.Timer B4 and UART1 bus collision detection share the vector and interrupt control register.

When using the timer B4 interrupt, set the IFSR07 bit to 0 (timer B4).

When using UART1 bus collision detection, set the IFSR07 bit to 1 (UART1 bus collision detection).

3.If this bit is set to 0, the software interrupt number 1 is selected CAN0/1 wake-up and the interrupt

number 13 is selected CAN0/1 error. If this bit is set to 1, the interrupt number 1 is selected CAN0

wake-up/error and the interrupt number 13 is selected CAN1 wake-up/error.

0 : CAN0/1 wake-up or error

1 : CAN0 wake-up/error or

CAN1 wake-up/error

IFSR00

IFSR01

Interrupt request source

select bit

Interrupt request source

delect bit

IFSR02 Interrupt request source

select bit

(3)

IFSR06

0 : Timer B4

1 :

UART1 bus collision detection

IFSR07 Interrupt request source

select bit (2)

Interrupt Source Select Register 0

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address After Reset

IFSR0 01DEh 00XXX000h

Function

0 :

CAN1 successful transmission

1 : SI/O3

0 : A/D conversion

1 : Key input

0 : Timer B3

1 :

UART0 bus collision detection

Interrupt request source

select bit (1)

Bit Name

(b5-b3)

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Interrupt Source Select Register 1

Symbol Address After Reset

IFSR1 01DFh 00h

b7 b6 b5 b4 b3 b2 b1 b0

0 :

SI/O3/CAN1 successful transmission

(3)

1 : INT4

0 : CAN1 successful reception

1 : INT5

0 : One edge

1 : Both edges (1)

0 : One edge

1 : Both edges (1)

0 : One edge

1 : Both edges (1)

0 : One edge

1 : Both edges (1)

0 : One edge

1 : Both edges (1)

0 : One edge

1 : Both edges (1)

IFSR10

Interrupt request source

select bit (2)

Interrupt request source

select bit (2)

IFSR11

IFSR12

IFSR13

IFSR14

IFSR15

IFSR16

IFSR17

Bit Name FunctionBit Symbol

INT0 interrupt polarity

switching bit

INT1 interrupt polarity

switching bit

INT2 interrupt polarity

switching bit

INT3 interrupt polarity

switching bit

INT4 interrupt polarity

switching bit

INT5 interrupt polarity

switching bit

NOTES:

1.When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC is set to

0 (falling edge).

2.During memory expansion and microprocessor modes, when the data bus is 16-bit width (BYTE pin is

"L"), set this bit to 0.

3.When setting this bit to 0 (SI/O3, CAN1 successful transmission), make sure the IFSR00 bit in the

IFSR0 register is set to 0 (CAN1 successful transmission) or 1 (SI/O3).

And, make sure the POL bit in registers S3IC and C1TRMIC are set to 0 (falling edge).

Rev.2.40 Apr 14, 2006 page 90 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 10. Interrupts

______

10.7 NMI Interrupt

_______ _______ ______

An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI

interrupt is a non-maskable interrupt.

_______

The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.

This pin cannot be used as an input port.

10.8 Key Input Interrupt

Of P10_4 to P10_7, a key input interrupt request is generated when input on any of pins P10_4 to P10_7

which has had bits PD10_4 to PD10_7 in the PD10 register set to 0 (input) goes low. Key input interrupts

can be used as a key-on wake up function, the function which gets the MCU out of wait or stop mode.

However, if you intend to use the key input interrupt, do not use P10_4 to P10_7 as analog input ports.

Figure 10.12 shows the Key Input Interrupt Block Diagram. Note, however, that while input on any pin which

has had bits PD10_4 to PD10_7 set to 0 (input mode) is pulled low, inputs on all other pins of the port are

not detected as interrupts.

Interrupt control circuit

KUPIC register

Key input interrupt

request

KI3

KI2

KI1

KI0

PU25 bit in PUR2 register

PD10_7 bit in PD10 register

Pull-up

transistor

PD10_7 bit in PD10 register

PD10_6 bit in

PD10 register

PD10_5 bit in

PD10 register

PD10_4 bit in

PD10 register

Pull-up

transistor

Pull-up

transistor

Pull-up

transistor

Figure 10.12 Key Input Interrupt Block Diagram

10.9 CAN0/1 Wake-up Interrupt

CAN0/1 wake-up interrupt request is generated when a falling edge is input to CRX0 or CRX1. One interrupt

is allocated to CAN0/1. The CAN0/1 wake-up interrupt is enabled only when the PortEn bit = 1 (CTX/CRX

function) and Sleep bit = 1 (sleep mode enabled) in the CiCTLR register (i = 0, 1). Figure 10.13 shows the

CAN0/1 Wake-up Interrupt Block Diagram. Please note that the wake-up message will be lost.

Figure 10.13 CAN0/1 Wake-up Interrupt Block Diagram

CRX1

Interrupt control

circuit

C01WKIC register

PortEn bit in C0CTLR register

PortEn bit in C1CTLR register

Sleep bit in C0CTLR register

Sleep bit in C1CTLR register

CRX0

CAN0/1 wake-up

interrupt request

Rev.2.40 Apr 14, 2006 page 91 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 10. Interrupts

10.10 Address Match Interrupt

An address match interrupt request is generated immediately before executing the instruction at the

address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi

to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.

For address match interrupts, the value of the PC that is saved to the stack area varies depending on the

instruction being executed (refer to 10.5.7 Saving Registers). (The value of the PC that is saved to the

stack area is not the correct return address.) Therefore, follow one of the methods described below to

return from the address match interrupt.

•Rewrite the content of the stack and then use the REIT instruction to return.

•Restore the stack to its previous state before the interrupt request was accepted by using the POP or

similar other instruction and then use a jump instruction to return.

Table 10.6 shows the Value of PC that is Saved to Stack Area when Address Match Interrupt Request is

Accepted. Table 10.7 shows the Relationship between Address Match Interrupt Sources and Associated

Registers.

Note that when using the external bus in 8-bit width, no address match interrupts can be used for external

areas.

Figure 10.14 shows Registers AIER, AIER2, and RMAD0 to RMAD3.

Table 10.6

Value of PC that is Saved to Stack Area when Address Match Interrupt Request is Accepted

Address Match Interrupt Sources

Address Match Interrupt Enable Bit Address Match Interrupt Register

Address match interrupt 0 AIER0 RMAD0

Address match interrupt 1 AIER1 RMAD1

Address match interrupt 2 AIER20 RMAD2

Address match interrupt 3 AIER21 RMAD3

Instruction at Address Indicated by RMADi Register

• 16-bit operation code instruction

• Instruction shown below among 8-bit operation code instructions

ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest

OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest

STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest

CMP.B:S #IMM8,dest PUSHM src POPM dest

JMPS #IMM8 JSRS #IMM8

MOV.B:S #IMM,dest (However, dest = A0 or A1)

Instructions other than the above

Value of PC that is saved to stack area: Refer to 10.5.7 Saving Registers.

Table 10.7 Relationship between Address Match Interrupt Sources and Associated Registers

Value of PC that is Saved to Stack Area

Address indicated by RMADi

Rev.2.40 Apr 14, 2006 page 92 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 10. Interrupts

Figure 10.14 Registers AIER, AIER2, and RMAD0 to RMAD3

Address Match Interrupt Enable Register

Address match interrupt 0

enable bit

Address match interrupt 1

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Symbol Address After Reset

AIER 0009h XXXXXX00b

AIER0

AIER1

(b7-b2)

Bit Name Function

Bit Symbol RW

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

b7 b6 b5 b4 b3 b2 b1 b0

Address Match Interrupt Enable Register 2

Address match interrupt 2

enable bit

Address match interrupt 3

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

0 : Interrupt disabled

1 : Interrupt enabled

Symbol Address After Reset

AIER2 01BBh XXXXXX00b

AIER20

AIER21

(b7-b2)

Bit Name Function

Bit Symbol RW

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

b7 b6 b5 b4 b3 b2 b1 b0

(b19-b0)

(b23-b20)

Bit Symbol

AddressSymbol After Reset

0012h to 0010h

0016h to 0014h

01BAh to 01B8h

01BEh to 01BCh

RMAD0

RMAD1

RMAD2

RMAD3

X00000h

Function Setting Range RW

Address setting register for address

match interrupt

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Address Match Interrupt Register i (i = 0 to 3)

00000h to FFFFFh

b0 b7 b0b3

(b19) (b16)

b7 b0

(b15) (b8)

(b23)

Rev.2.40 Apr 14, 2006 page 93 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 11. Watchdog Timer

11. Watchdog Timer

The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend

using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter

which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a

watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the

watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit in the PM1

0 (watchdog timer interrupt) in a program. Refer to 5.3 Watchdog Timer Reset for details about watchdog

timer reset.

When the main clock, on-chip oscillator clock or PLL clock is selected for CPU clock, the divide-by-n value for

the prescaler can be selected to be 16 or 128. If a sub clock is selected for CPU clock, the divide-by-n value

for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be

calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler.

For example, when CPU clock = 16 MHz and the divide-by-n value for the prescaler = 16, the watchdog timer

period is approx. 32.8 ms.

The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note

that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is

activated to start counting by writing to the WDTS register.

In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed

from the held value when the modes or state are released.

Figure 11.1 shows the Watchdog Timer Block Diagram. Figure 11.2 shows Registers WDC and WDTS.

With main clock, on-chip oscillator clock or PLL clock selected for CPU clock

Watchdog timer period =

Prescaler dividing (16 or 128) ✕ Watchdog timer count (32768)

CPU clock

With sub clock selected for CPU clock

Watchdog timer period =

Prescaler dividing (2) ✕ Watchdog timer count (32768)

CPU clock

Figure 11.1 Watchdog Timer Block Diagram

1/16

CM07 = 0

WDC7 = 0

PM22 = 0

PM22 = 1

Set to

7FFFh

On-chip oscillator clock

Write to WDTS register

Internal RESET signal

("L" active)

PM12 = 0

Watchdog timer

Interrupt request

PM12 = 1

Watchdog timer

Reset

CPU clock

HOLD

CM07 = 0

WDC7 = 1

CM07 = 1

Prescaler

1/128

1/2 Watchdog timer

CM07 : Bit in CM0 register

WDC7 : Bit in WDC register

PM12 : Bit in PM1 register

PM22 : Bit in PM2 register

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 11. Watchdog Timer

Figure 11.2 Registers WDC and WDTS

11.1 Count Source Protective Mode

In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer can

be kept being clocked even when CPU clock stops as a result of runaway.

Before this mode can be used, the following register settings are required:

(1) Set the PRC1 bit in the PRCR register to 1 (write to registers PM1 and PM2 enabled).

(2) Set the PM12 bit in the PM1 register to 1 (reset when the watchdog timer underflows).

(3) Set the PM22 bit in the PM2 register to 1 (on-chip oscillator clock used for the watchdog timer count source).

(4) Set the PRC1 bit in the PRCR register to 0 (write to registers PM1 and PM2 disabled).

(5) Write to the WDTS register (watchdog timer starts counting).

Setting the PM22 bit to 1 results in the following conditions:

•The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer

count source.

•The CM10 bit in the CM1 register is disabled against write. (Writing a 1 has no effect, nor is stop mode entered.)

•The watchdog timer does not stop when in wait mode or hold state.

High-order bits of watchdog timer

Prescaler select bit 0 : Divide-by-16

1 : Divide-by-128

Reserved bits Set to 0

WDC7

Watchdog Timer Control Register

b7 b6 b5 b4 b3 b2 b1 b0

(b4-b0)

(b6-b5)

FunctionBit Symbol Bit Name

Symbol Address After Reset

WDC 000Fh 00XXXXXXb

The watchdog timer is initialized and starts counting after a write instruction to

this register. The watchdog timer value is always initialized to 7FFFh regardless

of whatever value is written.

Watchdog Timer Start Register (1)

Symbol Address After Reset

WDTS 000Eh Undefined

Function RW

b7 b0

NOTE

1. Write to the WDTS register after the watchdog timer interrupt request is generated.

Watchdog timer count (32768)

On-chip oscillator clock

Watchdog timer period =

Rev.2.40 Apr 14, 2006 page 95 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

12. DMAC

The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.

Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit)

data from the source address to the destination address. The DMAC uses the same data bus as used by the

CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a

cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after

a DMA request is generated. Figure 12.1 shows the DMAC Block Diagram. Table 12.1 lists the DMAC

Specifications. Figures 12.2 to 12.4 show the DMAC related-registers.

Figure 12.1 DMAC Block Diagram

A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0, 1), as well as by an

interrupt request which is generated by any function specified by bits DMS, and DSEL3 to DSEL0 in the

DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag

and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request

can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect

interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.

A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register

= 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA

transfer cycle, the number of transfer requests generated and the number of times data is transferred may

not match. For details, refer to 12.4 DMA Request.

Data bus low-order bits

DMA latch high-order bits DMA latch low-order bits

DMA0 source pointer SAR0

DMA0 destination pointer DAR0

DMA0 forward address pointer

(1)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1

DMA1 source pointer SAR1

DMA1 forward address pointer

(1)

NOTE:

1.Pointer is incremented by a DMA request.

DMA0 transfer counter reload register TCR0

DMA0 transfer counter TCR0

DMA1 transfer counter reload register TCR1

DMA1 transfer counter TCR1

Rev.2.40 Apr 14, 2006 page 96 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

Item Specification

No. of channels 2 (cycle steal method)

Transfer memory space •From given address in the 1-Mbyte space to a fixed address

•From a fixed address to given address in the 1-Mbyte space

•From a fixed address to a fixed address

Maximum no. of bytes transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)

DMA request sources (1) (2)

________ ________

Falling edge of INT0 or INT1

________ ________

Both edge of INT0 or INT1

Timers A0 to A4 interrupt requests

Timers B0 to B5 interrupt requests

UART0 transmit, UART0 receive interrupt requests

UART1 transmit, UART1 receive interrupt requests

UART2 transmit, UART2 receive interrupt requests

SI/O3 interrupt request

A/D conversion interrupt requests

Software triggers

Channel priority DMA0 > DMA1 (DMA0 takes precedence)

Transfer unit 8 bits or 16 bits

Transfer address direction forward or fixed (The source and destination addresses cannot both be

in the forward direction.)

Transfer mode Single transfer Transfer is completed when the DMAi transfer counter underflows

after reaching the terminal count.

Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value

of the DMAi transfer counter reload register and a DMA transfer is

continued with it.

DMA interrupt request When the DMAi transfer counter underflowed

generation timing

DMA start up Data transfer is initiated each time a DMA request is generated when the

The DMAE bit in the DMAiCON register = 1 (enabled).

DMA shutdown Single transfer •When the DMAE bit is set to 0 (disabled)

•After the DMAi transfer counter underflows

Repeat transfer When the DMAE bit is set to 0 (disabled)

Reload timing for forward When a data transfer is started after setting the DMAE bit to 1 (enabled),

address pointer and transfer the forward address pointer is reloaded with the value of the SARi or the

counter DARi pointer whichever is specified to be in the forward direction and the

DMAi transfer counter is reloaded with the value of the DMAi transfer

counter reload register.

DMA transfer cycles Minimum 3 cycles between SFR and internal RAM

Table 12.1 DMAC Specifications

i = 0, 1

NOTES:

1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the

interrupt control register.

2. The selectable DMA request sources differ with each channel.

3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.

Rev.2.40 Apr 14, 2006 page 97 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

Figure 12.2 DM0SL Register

DMA0 Request Source Select Register

Symbol Address After Reset

DM0SL 03B8h 00h

DSEL0

DSEL1

DSEL2

DSEL3

DSR

DMS

(b5-b4)

FunctionBit Symbol Bit Name

DMA request source

select bits

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Software DMA

request bit

A DMA request is generated by setting

this bit to 1 when the DMS bit is 0

(basic source) and bits DSEL3 to DSEL0

are 0001b (software trigger).

When read, the content is 0.

DMA request source

expansion select bit

0 : Basic request source

1 : Extended request source

See NOTE 1

NOTE:

1. The DMA0 request sources can be selected by a combination of the DMS bit and bits DSEL3 to DSEL0 in the

manner described below.

Bits DSEL3 to DSEL0

DMS = 0 (basic request source) DMS = 1 (extended request source)

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

Falling edge of INT0 pin –

Software trigger –

Timer A0 –

Timer A1 –

Timer A2 –

Timer A3 –

Timer A4 Two edges of INT0 pin

Timer B0 Timer B3

Timer B1 Timer B4

Timer B2 Timer B5

UART0 transmit –

UART0 receive –

UART2 transmit –

UART2 receive –

A/D conversion –

UART1 transmit –

b7 b6 b5 b4 b3 b2 b1 b0

Rev.2.40 Apr 14, 2006 page 98 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

Figure 12.3 Registers DM1SL, DM0CON, and DM1CON

DMA1 Request Source Select Register

Symbol Address After Reset

DM1SL 03BAh 00h

DSEL0

DSEL1

DSEL2

DSEL3

DSR

DMS

(b5-b4)

FunctionBit Symbol Bit Name

DMA request source

select bits

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Software DMA

request bit

A DMA request is generated by setting

this bit to 1 when the DMS bit is 0

(basic source) and the DSEL3 to DSEL0

bits are 0001b (software trigger).

When read, the content is 0.

DMA request source

expansion select bit

0 : Basic request source

1 : Extended request source

See NOTE 1

NOTE:

1. The DMA1 request sources can be selected by a combination of the DMS bit and bits DSEL3 to DSEL0 in the

manner described below.

Bits DSEL3 to DSEL0

DMS = 0 (basic request source) DMS = 1 (extended request source)

Falling edge of INT1 pin –

Software trigger –

Timer A0 –

Timer A1 –

Timer A2 –

Timer A3 SI/O3

Timer A4

Timer B0 Two edges of INT1 pin

Timer B1

Timer B2

UART0 transmit –

–

UART0 receive/ACK0 –

UART2 transmit –

UART2 receive/ACK2 –

A/D conversion –

UART1 receive/ACK1 –

b7 b6 b5 b4 b3 b2 b1 b0

DMAi Control Register (i = 0, 1)

DMBIT

DMASL

DMAS

DAD

DSD

(b7-b6)

FunctionBit Symbol Bit Name

Transfer unit bit

select bit

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Destination address

direction select bit (2)

Source address direction

select bit (2)

0 : 16 bits

1 : 8 bits RW

(1)

NOTES:

1. The DMAS bit can be set to 0 by writing 0 in a program. (This bit remains unchanged even if 1 is written.)

2. At least one of bits DAD and DSD is set to 0 (address direction fixed).

b7 b6 b5 b4 b3 b2 b1 b0

Repeat transfer mode

select bit

0 : Single transfer

1 : Repeat transfer

DMA request bit

DMAE DMA enable bit

0 : DMA not requested

1 : DMA requested

0 : Disabled

1 : Enabled

0 : Fixed

1 : Forward

0 : Fixed

1 : Forward

Symbol Address After Reset

DM0CON 002Ch 00000X00b

DM1CON 003Ch 00000X00b

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

Rev.2.40 Apr 14, 2006 page 99 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

Figure 12.4 Registers SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1

Symbol After Reset

SAR0

SAR1

Undefined

Setting Range RW

00000h to FFFFFh

b0 b7 b0b3

(b19) (b16)

b7 b0

(b15) (b8)

(b23)

DMAi Source Pointer (i = 0, 1)

(1)

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Set the source address of transfer

Function

Address

0022h to 0020h

0032h to 0030h

NOTE:

1. If the DSD bit in the DMiCON register is 0 (fixed), this register can only be written to when the DMAE bit in the

DMiCON register is 0 (DMA disabled).

If the DSD bit is 1 (forward direction), this register can be written to at any time.

If the DSD bit is 1 and the DMAE bit is 1 (DMA enabled), the DMAi forward address pointer can be read from

this register. Otherwise, the value written to it can be read.

Set the transfer count minus 1.

The written value is stored in the DMAi transfer counter

reload register, and when the DMAE bit in the DMiCON

counter underflows when the DMASL bit in the DMiCON

transfer counter reload register is transferred to the DMAi

transfer counter.

When read, the DMAi transfer counter is read.

Function

Address

0029h, 0028h

0039h, 0038h

DMAi Transfer Counter (i = 0, 1)

Symbol After Reset

TCR0

TCR1

Undefined

b0 b7

(b8)

b0b7

(b15)

Setting Range RW

0000h to FFFFh

Symbol After Reset

DAR0

DAR1

Undefined

Setting Range RW

00000h to FFFFFh

b0 b7 b0b3

(b19) (b16)

b7 b0

(b15) (b8)

(b23)

DMAi Destination Pointer (i = 0, 1)

(1)

Function

Set the destination address of transfer

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Address

0026h to 0024h

0036h to 0034h

NOTE:

1. If the DAD bit in the DMiCON register is 0 (fixed), this register can only be written to when the DMAE bit in the

DMiCON register is 0 (DMA disabled).

If the DAD bit is 1 (forward direction), this register can be written to at any time.

If the DAD bit is 1 and the DMAE bit is 1 (DMA enabled), the DMAi forward address pointer can be read from

this register. Otherwise, the value written to it can be read.

Rev.2.40 Apr 14, 2006 page 100 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

12.1 Transfer Cycle

The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)

bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of

transfer. During memory expansion and microprocessor modes, it is also affected by the BYTE pin level.

________

Furthermore, the bus cycle itself is extended by a software wait or RDY signal.

12.1.1 Effect of Source and Destination Addresses

If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd

address, the source read cycle consists of one more bus cycle than when the source address of transfer

begins with an even address.

Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins

with an odd address, the destination write cycle consists of one more bus cycle than when the destination

address of transfer begins with an even address.

12.1.2 Effect of BYTE Pin Level

During memory expansion and microprocessor modes, if 16 bits of data are to be transferred on an 8-bit

data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data twice.

Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.

Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike in

the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.

12.1.3 Effect of Software Wait

For memory or SFR accesses in which one or more software wait states are inserted, the number of bus

cycles required for that access increases by an amount equal to software wait states.

________

12.1.4 Effect of RDY Signal

During memory expansion and microprocessor modes, DMA transfers to and from an external area are

________ ________

affected by the RDY signal. Refer to 7.2.6 RDY Signal.

Figure 12.5 shows the Transfer Cycles for Source Read. For convenience, the destination write cycle is

shown as one cycle and the source read cycles for the different conditions are shown. In reality, the

destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle

changing accordingly. When calculating transfer cycles, take into consideration each condition for the

source read and the destination write cycle, respectively. For example, when data is transferred in 16-bit

unit using an 8-bit bus ((2) on Figure 12.5), two source read bus cycles and two destination write bus cycles

are required.

Rev.2.40 Apr 14, 2006 page 101 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

Figure 12.5 Transfer Cycles for Source Read

NOTE:

1. The same timing changes occur with the respective conditions at the destination as at the source.

(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the

transfer unit is 16 bits and an 8-bit bus is used

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(3) When the source read cycle under condition (1) has one wait state inserted

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(4) When the source read cycle under condition (2) has one wait state inserted

BCLK

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

Rev.2.40 Apr 14, 2006 page 102 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

12.2 DMA Transfer Cycles

Any combination of even or odd transfer read and write addresses is possible.

Table 12.2 lists the DMA Transfer Cycles. Table 12.3 lists the Coefficient j, k.

The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k

Table 12.2 DMA Transfer Cycles

NOTES:

1. Depends on the set value of the PM20 bit in the PM2 register.

2. Depends on the set value of the CSE register.

: This condition does not exist.

Table 12.3 Coefficient j, k

Single-chip Mode Memory Expansion Mode

Transfer Unit Bus Width Access Address

Microprocessor Mode

No. of Read No. of Write No. of Read No. of Write

Cycles Cycles Cycles Cycles

16 bits Even 1111

8-bit transfer (BYTE = L) Odd 1111

(DMBIT =1) 8 bits Even

(BYTE= H) Odd

-11

16 bits Even 1111

16-bit transfer (BYTE =L) Odd 2222

(DMBIT = 0) 8 bits Even

(BYTE = H) Odd

Internal Area External Area

Internal ROM, RAM

SFR Separate Bus Multiplexed Bus

No Wait

With Wait 1 Wait (1) 2 Waits (1)

No Wait With Wait (2) With Wait (2)

1 Wait 2 Waits 3 Waits 1 Wait 2 Waits 3 Waits

j122312 34334

k122322 34334

Rev.2.40 Apr 14, 2006 page 103 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

12.3 DMA Enable

When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the

DMAC operates as follows:

(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register

is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward).

(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.

If the DMAE bit is set to 1 again while it remains set, the DMAC performs the above operation.

However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps

below.

Step 1: Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously.

Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.

If the DMAi is not in an initial state, the above steps should be repeated.

12.4 DMA Request

The DMAC can generate a DMA request as triggered by the request source that is selected with bits DMS,

and DSEL3 to DSEL0 in the DMiSL register (i = 0, 1) on either channel.

Table 12.4 lists the Timing at which DMAS Bit Changes State.

Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of whether or

not the DMAE bit is set. If the DMAE bit was set to 1 (enabled) when this occurred, the DMAS bit is set to

0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 in a program (it

can only be set to 0).

The DMAS bit may be set to 1 when the DMS bit or bits DSEL3 to DSEL0 change state. Therefore, always

be sure to set the DMAS bit to 0 after changing the DMS bit or bits DSEL3 to DSEL0.

Because if the DMAE bit is 1, a data transfer starts immediately after a DMA request is generated, the

DMAS bit in almost all cases is 0 when read in a program. Read the DMAE bit to determine whether the

DMAC is enabled.

Table 12.4 Timing at which DMAS Bit Changes State

i = 0, 1

DMA Source DMAS Bit in DMiCON Register

Timing at which the bit is set to 1 Timing at which the bit is set to 0

Software trigger When the DSR bit in the DMiSL register • Immediately before a data transfer starts

is set to 1 • When set by writing 0 in a program

Peripheral function When the interrupt control register for

the peripheral function that is selected

by bits DSEL3 to DSEL0, and DMS in

the DMiSL register has its IR bit set to 1.

Rev.2.40 Apr 14, 2006 page 104 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 12. DMAC

12.5 Channel Priority and DMA Transfer Timing

If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are

detected active in the same sampling period (one period from a falling edge to the next falling edge of

BCLK), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA

requests are arbitrated according to the channel priority, DMA0 > DMA1.

The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same

sampling period.

Figure 12.6 shows an example of DMA Transfer by External Sources.

In Figure 12.6, DMA0 request having priority is received first to start a transfer when a DMA0 request and

DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is

returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one

DMA1 transfer is completed, the bus arbitration is again returned to the CPU.

In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when

DMA requests, as DMA1 in Figure 12.6, occurs more than one time, the DMAS bit is set to 0 as soon as

getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.

__________

Refer to 7.2.7 HOLD Signal for details about bus arbitration between the CPU and DMA.

Figure 12.6 DMA Transfer by External Sources

An example where DMA requests for external sources are detected active at the same time,

a DMA transfer is executed in the shortest cycle.

BCLK

DMA0

DMA1

DMA0

request bit

DMA1

request bit

CPU

INT0

INT1

Bus arbitration

Rev.2.40 Apr 14, 2006 page 105 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

13. Timers

Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as

either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer

operations as counting, reloading, etc.

Figures 13.1 and 13.2 show the Timer A and Timer B Configurations.

TA0IN

TA1IN

TA2IN

TA3IN

TA4IN

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

f1 or f2 f8 f32 fC32

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Timer B2 overflow or underflow

PCLK0: Bit in PCLKR register

TCK1 to TCK0, TMOD1 to TMOD0: Bits in TAiMR register (i = 0 to 4)

TAiTGH to TAiTGL: Bits in ONSF register or TRGSR register

NOTE:

1. Be aware that TA0IN shares the pin with RXD2, SCL2, and TB5IN.

TCK1 to TCK0

TA0TGH to TA0TGL

TMOD1 to TMOD0 00:

Timer mode

10 :

One-shot timer mode

11 :

Pulse width measuring (PWM) mode

01:

Event counter mode

TMOD1 to TMOD0 00:

Timer mode

10 :

One-shot timer mode

11 :

PWM mode

01:

Event counter mode

TMOD1 to TMOD0 00:

Timer mode

10 :

One-shot timer mode

11 :

PWM mode

01:

Event counter mode

TMOD1 to TMOD0 00:

Timer mode

10 :

One-shot timer mode

11 :

PWM mode

01:

Event counter mode

TMOD1 to TMOD0 00:

Timer mode

10 :

One-shot timer mode

11 :

PWM mode

01:

Event counter mode

TCK1 to TCK0

11 TA1TGH t0 TA1TGL

11 TA2TGH to TA2TGL

11 TA3TGH to TA3TGL

11 TA4TGH to TA4TGL

1/32

fC32

XCIN

Reset

Clock prescaler

Set the CPSR bit in the

CPSRF register to 1

(prescaler reset)

1/8

1/4

f1 or f2

f32

1/2

f2 PCLK0 = 0

PCLK0 = 1

Main clock

PLL clock

On-chip

oscillator clock

Noise

filter

Figure 13.1 Timer A Configuration

Rev.2.40 Apr 14, 2006 page 106 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.2 Timer B Configuration

f1 or f2 f8 f32 fC32

TCK1

TMOD1 to TMOD0

00:

Timer mode

10:

Pulse width / period measuring mode

01:

Event counter mode

TCK1 to TCK0

TCK1

TMOD1 to TMOD0

00:

Timer mode

10:

Pulse width / period measuring mode

01:

Event counter mode

TCK1 to TCK0

TCK1

TMOD1 to TMOD0

00:

Timer mode

10:

Pulse width / period measuring mode

01:

Event counter mode

TCK1 to TCK0

TCK1

TMOD1 to TMOD0

00:

Timer mode

10:

Pulse width / period measuring mode

01:

Event counter mode

TCK1 to TCK0

TCK1

TMOD1 to TMOD0

00:

Timer mode

10:

Pulse width / period measuring mode

01:

Event counter mode

TCK1 to TCK0

TCK1

TMOD1 to TMOD0

00:

Timer mode

10:

Pulse width / period measuring mode

01:

Event counter mode

TCK1 to TCK0

TB0IN

TB1IN

TB2IN

TB3IN

TB4IN

TB5IN

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Timer B2 overflow or underflow (to a count source of the timer A)

Timer B0

Timer B1

Timer B2

Timer B3

Timer B4

Timer B5

Timer B2 interrupt

Timer B3 interrupt

Timer B4 interrupt

Timer B5 interrupt

Timer B0 interrupt

Timer B1 interrupt

PCLK0: Bit in PCLKR register

TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register (i = 0 to 5)

NOTE:

1. Be aware that TB5IN shares the pin with RXD2, SCL2, and TA0IN.

1/32 fC32

XCIN

Reset

Clock prescaler

Set the CPSR bit in the

CPSRF register to 1

(prescaler reset)

1/8

1/4

f1 or f2

f32

1/2

f2 PCLK0 = 0

PCLK0 = 1

Main clock

PLL clock

On-chip

oscillator clock

Rev.2.40 Apr 14, 2006 page 107 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

13.1 Timer A

Figure 13.3 shows the Timer A Block Diagram. Figures 13.4 to 13.6 show the timer A-related registers.

The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the

same function. Use bits TMOD1 to TMOD0 in the TAiMR register (i = 0 to 4) to select the desired mode.

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external device or overflows and

underflows of other timers.

• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum

count 0000h.

• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.

TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1: Bits in TAiMR register

TAiTGH to TAiTGL: Bits in ONSF register If i = 0, bits in TRGSR register if i = 1 to 4

TAiS: Bit in TABSR register

TAiUD: Bit in UDF register

i = 0 to 4

j = i - 1except j = 4 when i = 0

k = i + 1 except k = 0 when i = 4

NOTE:

1. Overflow or underflow

TCK1 to TCK0

Select clock source

TAiIN

Select clock

f1 or f2

f32

fC32

Timer

: TMOD1 to TMOD0 = 00, MR2 = 0

One shot

: TMOD1 to TMOD0 = 10

Pulse width modulation : TMOD1 to TMOD0 = 11

Timer (gate function) : TMOD1 to TMOD0 = 00, MR2 = 1

Event counter : TMOD1 to TMOD0 = 01

TMOD1 to TMOD0,

MR2

TAiTGH to TAiTGL

TB2 overflow (1)

TAj overflow (1)

TAk overflow (1)

TMOD1 to TMOD0

Polarity

selector

To external trigger circuit

Pulse output

Decrement

MR2

TAiS

TAiUD

TAiOUT

High-order bits of data bus

Low-order bits of data bus

Reload register

Low-order

8 bits High-order

8 bits

Counter

Increment/Decrement

Always counts down except

in event counter mode

Toggle Flip-Flop

TAi Addresses TAj TAk

Timer A0 0387h - 0386h Timer A4 Timer A1

Timer A1 0389h - 0388h Timer A0 Timer A2

Timer A2 038Bh- 038Ah Timer A1 Timer A3

Timer A3 038Dh- 038Ch Timer A2 Timer A4

Timer A4 038Fh- 038Eh Timer A3 Timer A0

Figure 13.3 Timer A Block Diagram

Rev.2.40 Apr 14, 2006 page 108 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.4 Registers TA0MR to TA4MR, and TA0 to TA4

Timer Ai Mode Register (i = 0 to 4)

TA0MR to TA4MR

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Timer mode

0 1 : Event counter mode

1 0 : One-shot timer mode

1 1 : Pulse width modulation mode

b1 b0

Count source select bits

Function varies depending on

operating mode

Symbol

Function varies depending on operating mode

Operating mode select bits

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

0396h to 039Ah 00h

Address After Reset

Symbol Address After Reset

TA0 0387h, 0386h

0389h, 0388h

038Bh, 038Ah

038Dh, 038Ch

038Fh, 038Eh

Undefined

TA1 Undefined

TA2 Undefined

TA3 Undefined

TA4

b7 b0 b7 b0

(b15) (b8)

Timer Ai Register (i = 0 to 4) (1)

Divide the count source by n + 1 where n =

set value

Function Setting Range

Divide the count source by n where n = set

value and cause the timer to stop

Modify the pulse width as follows:

PWM period: (216

–

1) / fj

High level PWM pulse width: n / fj

where n = set value, fj = count source

frequency

NOTES:

1.The register must be accessed in 16-bit unit.

2.The timer counts pulses from an external device or overflows or underflows in other timers.

3.If the TAi register is set to 0000h, the counter does not work and timer Ai interrupt requests are

not generated either. Furthermore, if "pulse output" is selected, no pulses are output from the

TAiOUT pin.

4.Use the MOV instruction to write to the TAi register.

5.If the TAi register is set to 0000h, the pulse width modulator does not work, the output level on

the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either.

The same applies when the 8 high-order bits in the TAi register are set to 00h while operating as

an 8-bit pulse width modulator.

Timer

mode

Event

counter

mode

One-shot

timer mode

Pulse width

modulation

mode

(16-bit PWM )

Pulse width

modulation

mode

(8-bit PWM )

0000h to FFFFh

00h to FEh

(High-order address)

00h to FFh (4) (5)

(Low-order address)

0000h to FFFFh

(3) (4)

0000h to FFFEh

(4) (5)

Mode

Modify the pulse width as follows:

PWM period: (28

–

1) ✕ (m + 1)/ fj

High level PWM pulse width: (m + 1)n / fj

where n = high-order address set value,

m = low-order address set value, fj =

count source frequency

Divide the count source by FFFFh

–

n + 1

where n = set value when counting up or

by n + 1 when counting down (2)

Undefined

Rev.2.40 Apr 14, 2006 page 109 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.5 Registers TABSR and UDF

Timer A4 up/down flag

Timer A3 up/down flag

Timer A2 up/down flag

Timer A1 up/down flag

Timer A0 up/down flag

Timer A2 two-phase pulse

signal processing select bit

Timer A3 two-phase pulse

signal processing select bit

Timer A4 two-phase pulse

signal processing select bit

Symbol Address After Reset

UDF 0384h 00h

TA4P

TA3P

TA2P

Up/Down Flag (1)

Bit Name FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

TA4UD

TA3UD

TA2UD

TA1UD

TA0UD 0 : Down count

1 : Up count

Enabled by setting the MR2 bit in

the TAiMR register to 0

(= switching source in UDF register)

during event counter mode.

0 : Two-phase pulse signal

processing disabled

1 : Two-phase pulse signal

processing enabled (2) (3)

Symbol Address After Reset

TABSR 0380h 00h

Count Start Flag

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S RW

NOTES:

1.Use the MOV instruction to write to this register.

2.Make sure the port direction bits for pins TA2IN to TA4IN, and TA2OUT to TA4OUT are set to 0

(input mode).

3.When not using the two-phase pulse signal processing function, set the corresponding bit to timers

A2 to A4 to 0.

Timer A0 count start flag 0 : Count stops

1 : Count starts

Rev.2.40 Apr 14, 2006 page 110 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.6 Registers ONSF, TRGSR, and CPSRF

One-Shot Start Flag

Symbol Address

ONSF 0382h

Timer A0 one-shot start flag

Timer A1 one-shot start flag

Timer A2 one-shot start flag

Timer A3 one-shot start flag

Timer A4 one-shot start flag

Bit Name FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Input on TA0IN is selected

(1)

0 1 : TB2 is selected

(2)

1 0 : TA4 is selected

(2)

1 1 : TA1 is selected

(2)

Timer A0 event/trigger

select bits

b7 b6

The timer starts counting by setting

this bit to 1 while bits TMOD1 to TMOD0

in the TAiMR register (i = 0 to 4) =

10b (one-shot timer mode) and the

MR2 bit in the TAiMR register = 0

(TAiOS bit enabled).

When read, its content is 0.

Z-phase input enable bit 0 : Z-phase input disabled

1 : Z-phase input enabled

NOTES:

1.Make sure the PD7_1 bit in the PD7 register is set to 0 (input mode).

2.Overflow or underflow.

TA1OS

TA2OS

TA0OS

TA3OS

TA4OS

TA0TGL

TA0TGH

TAZIE

Symbol Address After Reset

TRGSR 0383h 00h

Timer A1 event/trigger

select bits

Trigger Select Register

Bit Name FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Timer A2 event/trigger

select bits

Timer A3 event/trigger

select bits

Timer A4 event/trigger

select bits

b1 b0

b3 b2

b5 b4

b7 b6

NOTES:

1.Make sure the port direction bits for pins TA1IN to TA4IN are set to 0 (input mode).

2.Overflow or underflow.

0 0 : Input on TA1IN is selected

(1)

0 1 : TB2 is selected

(2)

1 0 : TA0 is selected

(2)

1 1 : TA2 is selected

(2)

0 0 : Input on TA2IN is selected

(1)

0 1 : TB2 is selected

(2)

1 0 : TA1 is selected

(2)

1 1 : TA3 is selected

(2)

0 0 : Input on TA3IN is selected

(1)

0 1 : TB2 is selected

(2)

1 0 : TA2 is selected

(2)

1 1 : TA4 is selected

(2)

0 0 : Input on TA4IN is selected

(1)

0 1 : TB2 is selected

(2)

1 0 : TA3 is selected

(2)

1 1 : TA0 is selected

(2)

TA1TGL

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

After Reset

00h

Symbol

CPSRF

Clock Prescaler Reset Flag

Bit Name FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

(b6-b0)

Setting this bit to 1 initializes the

prescaler for the timekeeping clock.

(When read, the content is 0.)

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

CPSR Clock prescaler reset flag

Address After Reset

0381h 0XXXXXXXb

Rev.2.40 Apr 14, 2006 page 111 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source f1, f2, f8, f32, fC32

Count operation • Down-count

•

When the timer underflows, it reloads the reload register contents and continues counting

Divide ratio 1/(n+1) n: set value of the TAi register 0000h to FFFFh

Count start condition Set the TAiS bit in the TABSR register to 1 (count starts)

Count stop condition Set the TAiS bit to 0 (count stops)

Interrupt request generation timing

Timer underflow

TAiIN pin function I/O port or gate input

TAiOUT pin function I/O port or pulse output

Read from timer Count value can be read by reading the TAi register

Write to timer •When not counting and until the 1st count source is input after counting start

Value written to the TAi register is written to both reload register and counter

•When counting (after 1st count source input)

Value written to the TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function •Gate function

Counting can be started and stopped by an input signal to TAiIN pin

•Pulse output function

Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.

When TAiS bit is set to 0 (count stops), the pin outputs a low.

13.1.1 Timer Mode

In timer mode, the timer counts a count source generated internally.

Table 13.1 lists the Timer Mode Specifications. Figure 13.7 shows Registers TA0MR to TA4MR in Timer Mode.

Table 13.1 Timer Mode Specifications

NOTES:

1. The port direction bit for the TAiIN pin is set to 0 (input mode).

2. Selected by the PCLK0 bit in the PCLKR register.

Timer Ai Mode Register (i = 0 to 4)

Symbol

TA0MR to TA4MR

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode

select bits

0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0 Pulse output function

select bit

0 : Pulse is not output

(TAiOUT pin is a normal port pin)

1 : Pulse is output

(TAiOUT pin is a pulse output pin)

Gate function select bits

0 0 :

Gate function not available

0 1 : (TAiIN pin functions as I/O port)

1 0 : Counts while input on the TAiIN pin

is low

(1)

1 1 : Counts while input on the TAiIN pin

is high

(1)

b4 b3

MR2

MR1

MR3 Set to 0 in timer mode

0 0 : f1 or f2

(2)

0 1 : f8

1 0 : f32

1 1 : fC32

b7 b6

TCK1

TCK0

Count source select bits

000

}

Address

0396h to 039Ah

After Reset

00h

i = 0 to 4

Figure 13.7 Registers TA0MR to TA4MR in Timer Mode

Rev.2.40 Apr 14, 2006 page 112 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source •External signals input to TAiIN pin (effective edge can be selected in program)

•Timer B2 overflows or underflows,

Timer Aj overflows or underflows,

Timer Ak overflows or underflows

Count operation •Up-count or down-count can be selected by external signal or program

•When the timer overflows or underflows, it reloads the reload register

contents and continues counting. When operating in free-running mode,

the timer continues counting without reloading.

Divided ratio 1/ (FFFFh - n + 1) for up-count

1/ (n + 1) for down-count n : set value of the TAi register 0000h to FFFFh

Count start condition Set the TAiS bit in the TABSR register to 1 (count starts)

Count stop condition Set the TAiS bit to 0 (count stops)

Interrupt request generation timing

Timer overflow or underflow

TAiIN pin function I/O port or count source input

TAiOUT pin function I/O port, pulse output, or up/down-count select input

Read from timer Count value can be read by reading the TAi register

Write to timer •When not counting and until the 1st count source is input after counting start

Value written to the TAi register is written to both reload register and counter

•When counting (after 1st count source input)

Value written to the TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function •Free-run count function

Even when the timer overflows or underflows, the reload register content

is not reloaded to it

•Pulse output function

Whenever the timer underflows or underflows, the output polarity of

TAiOUT pin is inverted.

When TAiS bit is set to 0 (count stops), the pin outputs a low.

13.1.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of

other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 13.2 lists the Event

Counter Mode Specifications (when not using two-phase pulse signal processing). Figure 13.8 shows

TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing). Table 13.3

lists the Event Counter Mode Specifications (when using two-phase pulse signal processing with timers

A2, A3, and A4). Figure 13.9 shows Registers TA2MR to TA4MR in Event Counter Mode (when using

two-phase pulse signa processing with timers A2, A3, and A4).

Table 13.2 Event Counter Mode Specifications (when not using two-phase pulse signal processing)

i = 0 to 4

j = i - 1, except j = 4 if i = 0

k = i + 1, except k = 0 if i = 4

Rev.2.40 Apr 14, 2006 page 113 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.8 Registers TA0MR to TA4MR in Event Counter Mode (when not using two-phase pulse

signal processing)

Symbol Address After Reset

TA0MR to TA4MR 0396h to 039Ah 00h

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode select bits 0 1 : Event counter mode

(1)

b1 b0

TMOD0

MR0

Pulse output function

select bit

0 : Pulse is not output

(TAiOUT pin functions as I/O port)

1 : Pulse is output

(TAiOUT pin functions as pulse output pin)

Count polarity select bit

(2)

MR2

MR1

MR3 Set to 0 in event counter mode

TCK0 Count operation type

select bit

010

0 : Counts falling edge of external signal

1 : Counts rising edge of external signal

Up/down switching

source select bit

0 : UDF register

1 : Input signal to TAiOUT pin

(3)

0 : Reload type

1 : Free-run type

Bit Symbol Bit Name Function RW

TCK1 Can be 0 or 1 when not using two-phase pulse signal processing.

TMOD1

Timer Ai Mode Register (i = 0 to 4)

(When not using two-phase pulse signal processing)

NOTES:

1.During event counter mode, the count source can be selected using registers ONSF and TRGSR.

2.Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 00b (TAiIN pin input).

3. Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port direction

bit for TAiOUT pin is set to 0 (input mode).

Rev.2.40 Apr 14, 2006 page 114 of 376

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M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source •Two-phase pulse signals input to TAiIN or TAiOUT pins

Count operation •Up-count or down-count can be selected by two-phase pulse signal

•When the timer overflows or underflows, it reloads the reload register

contents and continues counting. When operating in free-running mode,

the timer continues counting without reloading.

Divide ratio 1/ (FFFFh - n + 1) for up-count

1/ (n + 1) for down-count n : set value of the TAi register 0000h to FFFFh

Count start condition Set the TAiS bit in the TABSR register to 1 (count starts)

Count stop condition Set the TAiS bit to 0 (count stops)

Interrupt request generation timing

Timer overflow or underflow

TAiIN pin function Two-phase pulse input

TAiOUT pin function Two-phase pulse input

Read from timer Count value can be read by reading the TAi register

Write to timer •When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

•When counting (after 1st count source input)

Value written to TAi register is written to reload register

(Transferred to counter when reloaded next)

Select function (1) •Normal processing operation (timers A2 and A3)

The timer counts up rising edges or counts down falling edges on TAjIN

pin when input signals on TAjOUT pin is “H”.

Table 13.3

Event Counter Mode Specifications (when using two-phase pulse signal processing with timers A2, A3, and A4)

• Counter initialization by Z-phase input (timer A3)

The timer count value is initialized to 0 by Z-phase input.

Up-

count

Up-

count

Up-

count

Down-

count

Down-

count

Down-

count

TAjOUT

TAjIN

Count up all edges

Count down all edges

TAkOUT

TAkIN

•Multiply-by-4 processing operation (timers A3 and A4)

If the phase relationship is such that TAkIN pin goes “H” when the input

signal on TAkOUT pin is “H”, the timer counts up rising and falling edges

on pins TAkOUT and TAkIN. If the phase relationship is such that TAkIN

pin goes “L” when the input signal on TAkOUT pin is “H”, the timer counts

down rising and falling edges on pins TAkOUT and TAkIN.

i = 2 to 4

j = 2, 3

k = 3, 4

NOTE:

1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to

multiply-by-4 processing operation.

Rev.2.40 Apr 14, 2006 page 115 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.9 Registers TA2MR to TA4MR in Event Counter Mode (when using two-phase pulse

signal processing with timers A2, A3, and A4)

Timer Ai Mode Register (i = 2 to 4)

(When using two-phase pulse signal processing)

Symbol

TA2MR to TA4MR

b6 b5 b4 b3 b2 b1 b0

Operating mode select bits 0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0

MR2

MR1

MR3

TCK1

TCK0

010

Bit NameBit Symbol Function RW

Count operation type

select bit

Two-phase pulse signal

processing operation

select bit (1) (2)

0 : Reload type

1 : Free-run type

0 : Normal processing operation

1 : Multiply-by-4 processing operation

001

To use two-phase pulse signal processing, set this bit to 0.

To use two-phase pulse signal processing, set this bit to 1.

To use two-phase pulse signal processing, set this bit to 0.

NOTES:

1. The TCK1 bit is valid for the TA3MR register. No matter how this bit is set, timers A2 and A4 always operate in

normal processing mode and x4 processing mode, respectively.

2. If two-phase pulse signal processing is desired, following register settings are required:

Set the TAiP bit in the UDF register to 1 (two-phase pulse signal processing function enabled).

Set bits TAiTGH and TAiTGL in the TRGSR register to 00b (TAiIN pin input).

Set the port direction bits for TAiIN and TAiOUT to 0 (input mode).

Address After Reset

0398h to 039Ah 00h

Rev.2.40 Apr 14, 2006 page 116 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing

This function initializes the timer count value to 0 by Z-phase (counter initialization) input during two-

phase pulse signal processing.

This function can only be used in timer A3 event counter mode during two-phase pulse signal processing,

free-running type, x4 processing, with Z-phase entered from the ZP pin.

Counter initialization by Z-phase input is enabled by writing 0000h to the TA3 register and setting the

TAZIE bit in the ONSF register to 1 (Z-phase input enabled).

Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be selected

to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width

________

applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.

The counter is initialized at the next count timing after recognizing Z-phase input. Figure 13.10 shows

the relationship between the two-phase pulse (A phase and B phase) and the Z-phase.

If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3

interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this

function.

m m+1 1 2 3 4 5

T3OUT

(A phase)

Count source

TA3IN

(B phase)

Timer A3

(1)

Input equal to or greater than one clock cycle

of count source

NOTE:

1. This timing diagram is for the case where the POL bit in the INT2IC register = 1 (rising edge).

Figure 13.10 Two-phase Pulse (A Phase and B Phase) and Z Phase

Rev.2.40 Apr 14, 2006 page 117 of 376

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M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Down-count

•When the counter reaches 0000h, it stops counting after reloading a new value

•If a trigger occurs when counting, the timer reloads a new count and restarts counting

Divide ratio 1/n n : set value of the TAi register 0000h to FFFFh

However, the counter does not work if the divide-by-n value is set to 0000h.

Count start condition The TAiS bit in the TABSR register = 1 (count starts) and one of the following

triggers occurs.

•External trigger input from the TAiIN pin

•Timer B2 overflow or underflow,

Timer Aj overflow or underflow,

Timer Ak overflow or underflow

•The TAiOS bit in the ONSF register is set to 1 (timer starts)

Count stop condition •When the counter is reloaded after reaching 0000h

•TAiS bit is set to 0 (count stops)

Interrupt request generation timing

When the counter reaches 0000h

TAiIN pin function I/O port or trigger input

TAiOUT pin function I/O port or pulse output

Read from timer An undefined value is read by reading the TAi register

Write to timer •When not counting and until the 1st count source is input after counting start

Value written to the TAi register is written to both reload register and counter

•When counting (after 1st count source input)

Value written to the TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function •Pulse output function

The timer outputs a low when not counting and a high when counting.

13.1.3 One-shot Timer Mode

In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer

starts up and continues operating for a given period. Table 13.4 lists the One-shot Timer Mode Specifications.

Figure 13.11 shows Registers TA0MR to TA4MR in One-shot Timer Mode.

Table 13.4 One-shot Timer Mode Specifications

i = 0 to 4

j = i - 1, except j = 4 if i = 0

k = i + 1, except k = 0 if i = 4

Rev.2.40 Apr 14, 2006 page 118 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Bit Name

Symbol

TA0MR to TA4MR

Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode select bits 1 0 : One-shot timer mode

b1 b0

TMOD1

TMOD0

MR0 Pulse output function

select bit

0 : Pulse is not output

(TAiOUT pin functions as I/O port)

1 : Pulse is output

(TAiOUT pin functions as a pulse output pin)

MR2

MR1

MR3 Set to 0 in one-shot timer mode

0 0 : f1 or f2 (3)

0 1 : f8

1 0 : f32

1 1 : fC32

b7 b6

TCK1

TCK0

Count source select bits

100

0 : TAiOS bit is enabled

1 : Selected by bits TAiTGH to TAiTGL

Trigger select bit

External trigger select

bit (1)

0 : Falling edge of input signal to TAiIN pin (2)

1 : Rising edge of input signal to TAiIN pin (2)

NOTES:

1. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 00b (TAiIN pin input).

2. The port direction bit for the TAiIN pin is set to 0 (input mode).

3. Selected by the PCLK0 bit in the PCLKR register.

Timer Ai Mode Register (i = 0 to 4)

After Reset

00h

Address

0396h to 039Ah

Figure 13.11 Registers TA0MR to TA4MR in One-shot Timer Mode

Rev.2.40 Apr 14, 2006 page 119 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

13.1.4 Pulse Width Modulation (PWM) Mode

In PWM mode, the timer outputs pulses of a given width in succession. The counter functions as either

16-bit pulse width modulator or 8-bit pulse width modulator.

Table 13.5 lists the PWM Mode Specifications. Figure 13.12 shows Registers TA0MR to TA4MR in PWM

Mode. Figures 13.13 and 13.14 show an Example of 16-bit Pulse Width Modulator Operation and 8-bit

Pulse Width Modulator Operation.

Table 13.5 PWM Mode Specifications

Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Down-count (operating as an 8-bit or a 16-bit pulse width modulator)

•The timer reloads a new value at a rising edge of PWM pulse and continues counting

•The timer is not affected by a trigger that occurs during counting

16-bit PWM •High level width n / fj n : set value of the TAi register

•Cycle time (216-1) / fj fixed fj : count source frequency (f1, f2, f8, f32, fC32)

8-bit PWM •High level width n ✕ (m+1) / fj n :

set value of the TAi register high-order address

•Cycle time (28-1) ✕ (m+1) / fj m :

set value of the TAi register low-order address

Count start condition • The TAiS bit in the TABSR register is set to 1 (count starts)

• The TAiS bit = 1 and external trigger input from the TAiIN pin

• The TAiS bit = 1 and one of the following external triggers occurs

Timer B2 overflow or underflow,

Timer Aj overflow or underflow,

Timer Ak overflow or underflow

Count stop condition The TAiS bit is set to 0 (count stops)

Interrupt request generation timing

On the falling edge of the PWM pulse

TAiIN pin function I/O port or trigger input

TAiOUT pin function Pulse output

Read from timer An undefined value is read by reading the TAi register

Write to timer •When not counting and until the 1st count source is input after counting start

Value written to the TAi register is written to both reload register and counter

•When counting (after 1st count source input)

Value written to the TAi register is written to only reload register

(Transferred to counter when reloaded next)

i = 0 to 4

j = i - 1, except j = 4 if i = 0

k = i + 1, except k = 0 if i = 4

Rev.2.40 Apr 14, 2006 page 120 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.12 Registers TA0MR to TA4MR in PWM Mode

Bit Name

Timer Ai Mode Register (i = 0 to 4)

FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode

select bits

Pulse output function

select bit

(3)

1 1 : PWM mode

b1 b0

TMOD1

TMOD0

MR0

After Reset

00h

Address

0396h to 039Ah

Symbol

TA0MR to TA4MR

MR2

MR1

MR3

b7 b6

TCK1

TCK0

Count source select bits

16/8-Bit PWM mode

select bit

Trigger select bit

External trigger select

bit

(1)

1 : Selected by bits TAiTGH to TAiTGL

0 : Falling edge of input signal to TAiIN pin

(2)

1 : Rising edge of input signal to TAiIN pin

(2)

0 : Pulse is not output

(TAiOUT pin is a normal port pin)

1 : Pulse is output

(TAiOUT pin is a pulse output pin)

0 :

Functions as a 16-bit pulse width modulator

1 :

Functions as an 8-bit pulse width modulator

0 : Write 1 to TAiS bit in the TABSR register

0 0 : f1 or f2

(4)

0 1 : f8

1 0 : f32

1 1 : fC32

NOTES:

1. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 00b (TAiIN pin input).

2. The port direction bit for the TAiIN pin is set to 0 (input mode).

3. Set to 1 (pulse is output), PWM pulse is output.

4. Selected by the PCLK0 bit in the PCLKR register.

Rev.2.40 Apr 14, 2006 page 121 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.13 Example of 16-bit Pulse Width Modulator Operation

1 / fi ✕ (2

–

Count source

Input signal to

TAiIN pin

PWM pulse output

from TAiOUT pin

Trigger is not generated by this signal

"H"

"L"

IR bit in TAiIC

i = 0 to 4

fj: Frequency of count source (f1, f2, f8, f32, fC32)

NOTES:

1. n = 0000h to FFFEh.

2. This timing diagram is the following case.

TAi register = 0003h

Bits TAiTGH and TAiTGL in the ONSF or TRGSR register = 00b (TAiIN pin input)

The MR1 bit in the TAiMR register = 1 (rising edge)

The MR2 bit in the TAiMR register = 1 (trigger selected by bits TAiTGH and TAiTGL)

1 / fj ✕ n

Set to 0 upon accepting an interrupt request or by writing in program

Count source

(1)

Input signal to

TAiIN pin

Underflow signal of

8-bit prescaler

(2)

PWM pulse output

from TAiOUT pin

"H"

"L"

Set to 0 upon accepting an interrupt request or by writing in program

1 / fj ✕ (m + 1) ✕ (2

–

1 / fj ✕ (m + 1) ✕ n

1 / fj ✕ (m + 1)

IR bit in TAiIC

i = 0 to 4

fj: Frequency of count source (f1, f2, f8, f32, fC32)

NOTES:

1. The 8-bit prescaler counts the count source.

2. The 8-bit pulse width modulator counts the output from the 8-bit prescaler underflow signal.

3. m = 00h to FFh; n = 00h to FEh.

4. This timing diagram is the following case.

TAi register = 0202h

Bits TAiTGH and TAiTGL in the ONSF or TRGSR register = 00b (TAiIN pin input)

The MR1 bit in the TAiMR register = 0 (falling edge)

The MR2 bit in the TAiMR register = 1 (trigger selected by bits TAiTGH and TAiTGL)

Figure 13.14 Example of 8-bit Pulse Width Modulator Operation

Rev.2.40 Apr 14, 2006 page 122 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

13.2 Timer B

Figure 13.15 shows a Timer B Block Diagram. Figures 13.16 and 13.17 show the timer B-related registers.

Timer B supports the following three modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5)

to select the desired mode.

• Timer mode : The timer counts an internal count source.

• Event counter mode : The timer counts pulses from an external device or over

flows or underflows of other timers.

• Pulse period/pulse width measuring mode : The timer measures pulse period or pulse width of an

external signal.

TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register

TBiS: Bit in TABSR register or TBSR register

i = 0 to 5

= i - 1 except j = 2 when i = 0, j = 5 when i = 3

NOTE:

1. Overflow or underflow

TCK1 to TCK0

Select clock source

TBiIN

TBj overflow

(1)

f1 or f2

f32

fC32

00: Timer

10: Pulse period and

pulse width measurement

01: Event counter

TMOD1 to TMOD0

TCK1

Polarity Switching

and Edge Pulse

TBiS

High-order bits of data bus

Low-order bits of data bus

Reload register

Counter

TBi Addresses TBj

Timer B0 0391h - 0390h Timer B2

Timer B1 0393h - 0392h Timer B0

Timer B2 0395h- 0394h Timer B1

Timer B3 01D1h- 01D0h Timer B5

Timer B4 01D3h- 01D2h Timer B3

Timer B5 01D5h- 01D4h Timer B4

Counter Reset Circuit

Low-order

8 bits High-order

8 bits

Figure 13.15 Timer B Block Diagram

Rev.2.40 Apr 14, 2006 page 123 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.16 Registers TB0MR to TB5MR, and TB0 to TB5

Timer Bi Mode Register (i = 0 to 5)

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Timer mode

0 1 : Event counter mode

1 0 : Pulse period measurement mode,

pulse width measurement mode

1 1 : Do not set a value

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

RW (1)

(2)

Function varies depending on

operating mode

Function varies depending on operating mode

Operating mode select bits

Count source select bits

Symbol Address After Reset

TB0MR to TB2MR 039Bh to 039Dh 00XX0000b

TB3MR to TB5MR 01DBh to 01DDh 00XX0000b

NOTES:

1. Timers B0 and B3.

2. Timers B1, B2, B4, and B5.

Symbol Address After Reset

TB0

TB1

TB2

TB3

TB4

TB5

0391h, 0390h

0393h, 0392h

0395h, 0394h

01D1h, 01D0h

01D3h, 01D2h

01D5h, 01D4h

Undefined

b7 b0 b7 b0

(b15) (b8)

Timer Bi Register (i = 0 to 5)

(1)

Measures a pulse period or width

Function

NOTES:

1.The register must be accessed in 16-bit unit.

2.The timer counts pulses from an external device or overflows or underflows of other timers.

Divide the count source by n + 1

where n = set value

Timer mode

Event counter

mode

0000h to FFFFh

Divide the count source by n + 1

where n = set value (2)

Pulse period

modulation mode,

Pulse width

modulation mode

Mode Setting Range

Rev.2.40 Apr 14, 2006 page 124 of 376

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M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.17 Registers TABSR, TBSR, and CPSRF

Symbol Address After Reset

TABSR 0380h 00h

Count Start Flag

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit Symbol

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag 0 : Count stops

1 : Count starts

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Function RW

Symbol Address After Reset

TBSR 01C0h 000XXXXXb

Timer B3, B4, B5 Count Start Flag

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit Symbol

Timer B5 count start flag

Timer B4 count start flag

Timer B3 count start flag 0 : Count stops

1 : Count starts

TB5S

TB4S

TB3S

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Function RW

(b4-b0)

(b6-b0)

Symbol Address After Reset

CPSRF 0381h 0XXXXXXXb

Clock Prescaler Reset Flag

Bit Name Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Clock prescaler reset flag

CPSR

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Setting this bit to 1 initializes the

prescaler for the timekeeping clock.

(When read, the content is 0.)

Rev.2.40 Apr 14, 2006 page 125 of 376

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M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Down-count

•When the timer underflows, it reloads the reload register contents and

continues counting

Divide ratio 1/(n+1) n: set value of the TBi register 0000h to FFFFh

Count start condition Set the TBiS bit (1) to 1 (count starts)

Count stop condition Set the TBiS bit to 0 (count stops)

Interrupt request generation timing

Timer underflow

TBiIN pin function I/O port

Read from timer Count value can be read by reading the TBi register

Write to timer •When not counting and until the 1st count source is input after counting start

Value written to the TBi register is written to both reload register and counter

•When counting (after 1st count source input)

Value written to the TBi register is written to only reload register

(Transferred to counter when reloaded next)

13.2.1 Timer Mode

In timer mode, the timer counts a count source generated internally.

Table 13.6 lists the Timer Mode Specifications. Figure 13.18 shows Registers TB0MR to TB5MR in Timer Mode.

Table 13.6 Timer Mode Specifications

Symbol After Reset

TB0MR to TB2MR 00XX0000b

TB3MR to TB5MR 00XX0000b

Bit Name Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode select bits 0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0 Has no effect in timer mode

Can be set to 0 or 1

MR2

MR1

MR3

0 0 : f1 or f2 (1)

0 1 : f8

1 0 : f32

1 1 : fC32

TCK1

TCK0

Count source select bits

Registers TB0MR and TB3MR

Set to 0 in timer mode

b7 b6

Registers TB1MR, TB2MR, TB4MR, and TB5MR

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

If necessary, set to 0 in timer mode.

When read in timer mode, the content is undefined.

Address

039Bh to 039Dh

01DBh to 01DDh

Timer Bi Mode Register (i = 0 to 5)

NOTE:

1. Selected by the PCLK0 bit in the PCLKR register.

i = 0 to 5

NOTE:

1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are

assigned to bits 5 to 7 in the TBSR register.

Figure 13.18 Registers TB0MR to TB5MR in Timer Mode

Rev.2.40 Apr 14, 2006 page 126 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source • External signals input to TBiIN pin (effective edge can be selected in program)

• Timer Bj overflow or underflow

Count operation •Down-count

•When the timer underflows, it reloads the reload register contents and

continues counting

Divide ratio 1/(n+1) n: set value of the TBi register 0000h to FFFFh

Count start condition Set TBiS bit (1) to 1 (count starts)

Count stop condition Set TBiS bit to 0 (count stops)

Interrupt request generation timing

Timer underflow

TBiIN pin function Count source input

Read from timer Count value can be read by reading the TBi register

Write to timer • When not counting and until the 1st count source is input after counting start

Value written to the TBi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to the TBi register is written to only reload register

(Transferred to counter when reloaded next)

13.2.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of

other timers. Table 13.7 lists the Event Counter Mode Specifications. Figure 13.19 shows Registers

TB0MR to TB5MR in Event Counter Mode.

Table 13.7 Event Counter Mode Specifications

Figure 13.19 Registers TB0MR to TB5MR in Event Counter Mode

Timer Bi Mode Register (i= 0 to 5)

Symbol

Bit Name FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode select bits 0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0

Count polarity select bits

(1)

MR2

MR1

MR3

TCK1

TCK0

0 0 :

Counts falling edge of external signal

0 1 :

Counts rising edge of external signal

1 0 : Counts falling and rising edges of

external signal

1 1 : Do not set a value

b3 b2

NOTES:

1. Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits can

be set to 0 or 1.

2. The port direction bit for the TBiIN pin is set to 0 (input mode).

Has no effect in event counter mode.

Can be set to 0 or 1.

Event clock select bit

0 : Input from TBiIN pin

(2)

1 : TBj overflow or underflow

(j = i

–

1, except j = 2 if i = 0,

j = 5 if i = 3)

Registers TB0MR and TB3MR

Set to 0 in event counter mode

Registers TB1MR, TB2MR, TB4MR, and TB5MR

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

If necessary, set to 0 in event counter mode.

When read in event counter mode, the content is undefined.

After Reset

TB0MR to TB2MR 00XX0000b

TB3MR to TB5MR 00XX0000b

Address

039Bh to 039Dh

01DBh to 01DDh

i = 0 to 5

j = i - 1, except j = 2 if i = 0, j = 5 if i = 3

NOTE:

1. Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are

assigned to bits 5 to 7 in the TBSR register.

Rev.2.40 Apr 14, 2006 page 127 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Up-count

•Counter value is transferred to reload register at an effective edge of

measurement pulse. The counter value is set to 0000h to continue counting.

Count start condition Set the TBiS bit (1) to 1 (count starts)

Count stop condition Set the TBiS bit to 0 (count stops)

Interrupt request • When an effective edge of measurement pulse is input (2)

generation timing • Timer overflow. If an overflow occurs, the MR3 bit in the TBiMR register

is set to 1 (overflow) simultaneously. The MR3 bit is set to 0 (no overflow)

by writing to the TBiMR register at the next count timing or later after the

MR3 bit was set to 1. At this time, make sure the TBiS bit is set to 1

(count starts).

TBiIN pin function Measurement pulse input

Read from timer Contents of the reload register (measurement result) can be read by reading

TBi register (3)

Write to timer Value written to the TBi register is written to neither reload register nor counter

13.2.3 Pulse Period and Pulse Width Measurement Mode

In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an

external signal. Table 13.8 lists the Pulse Period and Pulse Width Measurement Mode Specifications.

Figure 13.20 shows Registers TB0MR to TB5MR in Pulse Period and Pulse Width Measurement mode.

Figure 13.21 shows the Operation Timing when Measuring Pulse Period. Figure 13.22 shows the Operation

Timing when Measuring Pulse Width.

Table 13.8 Pulse Period and Pulse Width Measurement Mode Specifications

i = 0 to 5

NOTES:

1.Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are

assigned to bits 5 to 7 in the TBSR register.

2. Interrupt request is not generated when the first effective edge is input after the timer started counting.

3. Value read from the TBi register is undefined until the second valid edge is input after the timer starts

counting.

Rev.2.40 Apr 14, 2006 page 128 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.20

Registers TB0MR to TB5MR in Pulse Period and Pulse Width Measurement Mode

Timer Bi Mode Register (i = 0 to 5)

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Operating mode

select bits 1 0 : Pulse period / pulse width measurement mode

b1 b0

TMOD1

TMOD0

MR0

Measurement mode

select bits

MR2

MR1

MR3

TCK1

TCK0

0 0 : Pulse period measurement

(Measurement between a falling edge and the

next falling edge of measured pulse)

0 1 : Pulse period measurement

(Measurement between a rising edge and the next

rising edge of measured pulse)

1 0 : Pulse width measurement

(Measurement between a falling edge and the

next rising edge of measured pulse and between

a rising edge and the next falling edge)

1 1 : Do not set a value

Function

b3 b2

Count source

select bits

Timer Bi overflow

flag (1)

0 : Timer did not overflow

1 : Timer has overflowed

0 0 : f1 or f2 (2)

0 1 : f8

1 0 : f32

1 1 : fC32

b7 b6

Registers TB0MR and TB3MR

Set to 0 in pulse period and pulse width measurement mode

Registers TB1MR, TB2MR, TB4MR, and TB5MR

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

NOTES:

1. This flag is undefined after reset. When the TBiS bit = 1 (count starts), the MR3 bit is set to 0 (no overflow) by writing to the TBiMR

register at the next count timing or later after the MR3 bit was set to 1 (overflow). The MR3 bit cannot be set to 1 in a program.

Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are assigned to bits 5 to 7 in the TBSR

2. Selected by the PCLK0 bit in the PCLKR register.

After Reset

TB0MR to TB2MR 00XX0000b

TB3MR to TB5MR 00XX0000b

Address

039Bh to 039Dh

01DBh to 01DDh

Symbol

Rev.2.40 Apr 14, 2006 page 129 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 13. Timers

Figure 13.22 Operation Timing When Measuring Pulse Width

Figure 13.21 Operation Timing When Measuring Pulse Period

Count source

Measurement pulse

TBiS bit

IR bit in

TBiIC register

Timing at which counter

reaches 0000h

"H"

Transfer

(undefined value)

"L"

MR3 bit in

TBiMR register

i = 0 to 5

NOTES:

1. Counter is initialized at completion of measurement.

2. Timer has overflowed.

3. This timing diagram is for the case where bits MR1 to MR0 in the TBiMR register are 00b (measure the interval

from falling edge to falling edge of the measurement pulse).

(NOTE 1)(NOTE 1) (NOTE 2)

Transfer

(measured value)

Reload register counter

transfer timing

Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are

assigned to bits 5 to 7 in the TBSR register.

Set to 0 upon accepting an interrupt request or by writing in program

Measurement pulse "H"

Count source

Timing at which counter

reaches 0000h

Transfer

(measured value)

Transfer

(measured value)

"L"

(NOTE 1)(NOTE 1)(NOTE 1)

Transfer

(measured

value)

(NOTE 1) (NOTE 2)

Transfer

(undefined

value)

Reload register counter

transfer timing

TBiS bit

Set to 0 upon accepting an interrupt request or by

writing in program

i = 0 to 5

NOTES:

1. Counter is initialized at completion of measurement.

2. Timer has overflowed.

3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are 10b (measure the

interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge

of the measurement pulse).

Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are

assigned to bits 5 to 7 in the TBSR register.

MR3 bit in

TBiMR register

IR bit in

TBiIC register

Rev.2.40 Apr 14, 2006 page 130 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

14. Three-Phase Motor Control Timer Function

Timers A1, A2, A4, and B2 can be used to output three-phase motor drive waveforms. Table 14.1 lists the

Three-phase Motor Control Timer Function Specifications. Figure 14.1 shows the Three-phase Motor Control

Timer Function Block Diagram. Figures 14.2 to 14.8 shows the Three-phase Motor Control Timer Function

related registers.

Table 14.1 Three-Phase Motor Control Timer Function Specifications

Item Specification

Three-Phase waveform output pin

___ ___ ___

Six pins (U, U, V, V, W, W)

Forced cutoff input (1)

_______

Input “L” to NMI pin

Used timers Timer A4, A1, A2 (used in the one-shot timer mode)

___

• Timer A4: U- and U-phase waveform control

___

• Timer A1: V- and V-phase waveform control

___

• Timer A2: W- and W-phase waveform control

Timer B2 (used in the timer mode)

• Carrier wave cycle control

Dead time timer (3 eight-bit timer and shared reload register)

• Dead time control

Output waveform Triangular wave modulation, Sawtooth wave modification

• Enable to output “H” or “L” for one cycle

•

Enable to set positive-phase level and negative-phase level respectively

Carrier wave cycle Triangular wave modulation: count source ✕ (m+1) ✕ 2

Sawtooth wave modulation: count source ✕ (m+1)

m: Setting value of the TB2 register, 0000h to FFFFh

Count source: f1, f2, f8, f32, fC32

Three-Phase PWM output width Triangular wave modulation: count source ✕ n ✕ 2

Sawtooth wave modulation: count source ✕ n

n: Setting value of registers TA4, TA1, and TA2 (of registers

TA4, TA41, TA1, TA11, TA2, and TA21 when setting the INV11

bit to 1), 0001h to FFFFh

Count source: f1, f2, f8, f32, fC32

Dead time Count source ✕ p, or no dead time

p: Setting value of the DTT register, 01h to FFh

Count source: f1, f2, f1 divided by 2, f2 divided by 2

Active level Enable to select “H” or “L”

Positive and negative-phase concurrent

Positive and negative-phases concurrent active disable function

active disable function Positive and negative-phases concurrent active detect function

Interrupt frequency For timer B2 interrupt, select a carrier wave cycle-to-cycle basis

through 15 times carrier wave cycle-to-cycle basis

NOTE:

_______

Forced cutoff with NMI input is effective when the IVPCR1 bit in the TB2SC register is set to 1 (three-phase

_______ _______

output forcible cutoff by NMI input enabled). If an “L” signal is applied to the NMI pin when the IVPCR1

bit is 1, the related pins go to a high-impedance state regardless of which functions of those pins are

being used.

Related pins: • P7_2/CLK2/TA1OUT/V

_________ _________ ___

• P7_3/CTS2/RTS2/TA1IN/V

• P7_4/TA2OUT/W

____

• P7_5/TA2IN/W

• P8_0/TA4OUT/U

___

• P8_1/TA4IN/U

Rev.2.40 Apr 14, 2006 page 131 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram

1/2

DUB1

bit

Trigger

RESET

NMI

PWCON

Write signal to

NOTE:

1. Transfer trigger is generated only when registers IDB0 and IDB1 are set and the first timer B2 underflows,

if the INV06 bit is set to 0 (triangular wave modulation mode).

Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram.

ICTB2 register n=1 to 15

INV13

ICTB2 counter

n=1 to 15

Reload register

n = 1 to 255

Dead time

timer

n = 1 to 255

Dead time

timer

n = 1 to 255

Dead time

timer

n = 1 to 255

INV00

INV01

INV11

Reload control signal for timer A1

Start trigger signal for timers A1, A2, A4

TA4 register

Reload

Reload control

signal for timer A4

Reload control

signal for timer A1

Reload control

signal for timer A2

TA41 register

TA1 register TA11 register

Timer A4 counter Timer A4

one-shot

pulse

Timer A1

one-shot

pulse

Timer A2

one-shot

pulse

Reload

Timer A1 counter

(One-shot timer mode)

TA2 register TA21 register

Reload

Timer A2 counter

(One-shot timer mode)

When setting the TA4S bit to 0,

signal is set to 0

When setting the TA1S bit to 0,

signal is set to 0

When setting the TA2S bit to 0,

signal is set to 0

INV11

INV10

INV07

INV11

Timer B2

Timer B2 underflow

(Timer mode)

f1 or f2

INV12

INV06

Circuit to set interrupt

generation frequency

Timer B2

interrupt

request bit

Value to be written to

INV03 bit

Write signal to INV03 bit

INV05

INV04

INV14

INV02

INV03

Inverse

control

Inverse

control

Inverse

control

Inverse

control

Inverse

control

Inverse

control

W-Phase

output signal

W-Phase

output signal

V-Phase

output signal

V-Phase

output signal

U-Phase

output signal

U-Phase

output signal

DUB0

bit

DU1

bit

DU0

bit

U-phase output

control circuit

Transfer trigger

(1)

Trigger

W-Phase output

control circuit

V-Phase output

control circuit

Three-Phase

output

shift register

(U Phase)

INV00 to INV07: Bits in INVC0 register

INV10 to INV15: Bits in INVC1 register

DUi, DUBi: Bits in IDBi register (i = 0, 1)

TA1S to TA4S: Bits in TABSR register

PWCON: Bits in TB2SC register

Rev.2.40 Apr 14, 2006 page 132 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.2 INVC0 Register

NOTES:

1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enabled).

Rewrite bits INV00 to INV02, and INV06 when the timers A1, A2, A4, and B2 stop.

2. Bits INV00 and INV01 are enabled only when the INV11 bit is set to 1 (three-phase mode 1). The ICTB2

counter is incremented by one every time the timer B2 underflows, regardless of INV00 and INV01 bit settings,

when the INV11 bit is set to 0 (three-phase mode 0).

When setting the INV01 bit to 1, set the timer A1 count start flag before the first timer B2 underflow.

When the INV00 bit is set to 1, the first interrupt is generated when the timer B2 underflows

n-1

times, if

the value set in the ICTB2 counter. Subsequent interrupts are generated every

times the timer B2 underflows.

3. Set the INV01 bit to 1 after setting the ICTB2 register .

4. Set the INV02 bit to 1 to operate the dead time timer, U-, V-, and W-phase output control circuits and ICTB2

counter.

5. When the INV03 bit is set to 1, the pins applied to U/V/W output three-phase PWM.

Pins U, U, V, V, W, and W, including pins shared with other output functions, are all placed in high-impedance

states when the following conditions are all met.

The INV02 bit is set to 1 (three-phase control timer function)

The INV03 bit is set to 0 (three-phase control timer output disabled)

Direction registers of each port are set to 0 (input mode)

6. The INV03 bit is set to 0 when the following conditions are all met.

Reset

A concurrent active state occurs while INV04 bit is set to 1

The INV03 bit is set to 0 by program

A signal applied to the NMI pin changes "H" to "L"

When both the INV04 and INV05 bits are set to 1, the INV03 bit is set to 0.

7. The INV05 bit cannot be set to 1 by program. Set the INV04 bit to 0, as well, when setting the INV05 bit to 0.

8. The following table describes how the INV06 bit works.

INV00

INV01

INV02

INV03

INV05

INV06

INV07

INV04

Function

Three-Phase PWM Control Register 0

(1)

Bit Name

Bit

Symbol

Symbol Address After Reset

INVC0 01C8h 00h

Item

INV06 = 0

INV06 =

Transfer trigger is generated when the INV07

bit is set to 1. Trigger to the dead time timer

is also generated when setting the INV06

bit to 1. Its value is 0 when read.

Transfer trigger : Timer B2 underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1

0: The ICTB2 counter is incremented by one on the

rising edge of the timer A1 reload control signal

1: The ICTB2 counter is incremented by one on the

falling edge of the timer A1 reload control signal

(

0: ICTB2 counter is incremented by one when

timer B2 underflows

1: Selected by the INV00 bit

(2)

9. When the INV06 bit is set to 1, set the INV11 bit to 0 (three-phase mode 0) and the PWCON bit in the TB2SC

Transferred once by generating a

transfer trigger after setting registers

IDB0 and IDB1

Interrupt enable output

polarity select bit

Interrupt enable output

specification bit (3)

Mode select bit (4)

0: No three-phase control timer functions

1: Three-phase control timer function

(5)

Three-phase control timer output disabled (5)

Three-phase control timer output enabled (6)

Output control bit

0: Concurrent active output enabled

1: Concurrent active output disabled

Positive and negative-

phases concurrent active

disable function enable bit

Positive and negative-

phases concurrent active

output detect flag

0: Not detected

1: Detected (7)

Modulation mode

select bit (8)

0: Triangular wave modulation mode

1: Sawtooth wave modulation mode (9)

Software trigger select

bit

Transferred every time a transfer trigger

is generated

By a transfer trigger, or the falling edge of

a one-shot pulse of timer A1, A2, or A4

On the falling edge of a one-shot pulse

of timer A1, A2, or A4

Timing to trigger the dead time

timer when the INV16 bit=0

INV13 bit Enabled when the INV11 bit=1 and the

INV06 bit=0

Disabled

Timing to transfer from registers

IDB0 and IDB1 to three-phase

output shift register

Mode Triangular wave modulation mode Sawtooth wave modulation mode

b7 b6 b5 b4 b3 b2 b1 b0

Rev.2.40 Apr 14, 2006 page 133 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.3 INVC1 Register

INV10

INV11

INV12

INV13

INV15

Registers TA11, TA21, and TA41

Bits INV00 and INV01

Not used Used

INV14

Function

Three-Phase PWM Control Register 1

(1)

Timers A1, A2, and A4

start trigger select bit

Carrier wave detect

flag

(4)

Dead time timer

trigger select bit

INV13 bit Disabled

Enabled

Output polarity control

bit

0: Timer A1 reload control signal is 0

1: Timer A1 reload control signal is 1

Timer A1-1, A2-1, A4-1

control bit

(2)

0: Three-phase mode 0

(3)

1: Three-phase mode 1

Dead time timer

count source select bit

0 : f1 or f2

(6)

1 : f1 divided-by-2 or f2 divided-by-2

0: Timer B2 underflow

1: Timer B2 underflow and write to

timer B2

0 : Active "L" of an output waveform

1 : Active "H" of an output waveform

Dead time disable bit 0: Dead time enabled

1: Dead time disabled

Bit Name

Bit

Symbol

Symbol Address After Reset

INVC1 01C9h 00h

Reserved bit Set to 0 RW

Item INV11 = 0 INV11 = 1

NOTES:

1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enabled).

Timers A1, A2, A4, and B2 must be stopped during rewrite.

2. The following table lists how the INV11 bit works.

3. When the INV06 bit is set to 1 (sawtooth wave modulation mode), set the INV11 bit to 0 (three-phase

mode 0). Also, when the INV11 bit is set to 0, set the PWCON bit in the TB2SC register to 0 (timer B2 is

reloaded when the timer B2 underflows).

4. The INV13 bit is enabled only when the INV06 bit is set to 0 (Triangular wave modulation mode) and the

INV11 bit to 1 (three-phase mode 1).

5. If the following conditions are all met, set the INV16 bit to 1 (rising edge of the three-phase output shift

The INV15 bit is set to 0 (dead time timer enabled)

The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit is set to

1. (The positive-phase and negative-phase always output opposite level signals.)

If above conditions are not met, set the INV16 bit to 0 (falling edge of a one-shot pulse of timers A1, A2,

and A4).

6. Selected by the PCLK0 bit in the PCLKR register.

Disabled.

The ICTB2 counter is incremented

whenever the timer B2 underflows

0: Falling edge of a one-shot pulse of

timers A1, A2, and A4

(5)

1: Rising edge of the three-phase output

shift register (U-, V-, W-phase)

INV16

(b7)

Enabled when INV11=1 and INV06=0

Three-phase mode 0 Three-phase mode 1Mode

b7 b6 b5 b4 b3 b2 b1 b0

Rev.2.40 Apr 14, 2006 page 134 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.4 Registers IDB0, IDB1, and DTT

Three-Phase Output Buffer Register i (i = 0, 1)

(1)

Symbol Address After Reset

IDB0, IDB1 01CAh, 01CBh 00111111b

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol

DUi

DUBi

DVi

U-phase output buffer i

DVBi

DWi

DWBi

(b7-b6)

Function

Write output level

0: Active level

1: Inactive level

When read, the value of the three-

phase shift register is read.

U-phase output buffer i

V-phase output buffer i

W-phase output buffer i

NOTE:

1. The values of registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer

trigger.

After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal

first. Then the value written in the IDB1 register on the falling edge of timers A1, A2, and A4 one-shot

pulse determines each phase output signal.

Reserved bits Set to 0

Dead Time Timer (1) (2)

Symbol Address After Reset

DTT 01CCh Undefined

Function

Setting Range

1 to 255

If setting value is

, the timer stops when counting

times a count source selected by the INV12 bit

in the INVC1 register after start trigger occurs.

Positive or negative phase, which changes from

inactive level to active level, shifts when the dead

time timer stops.

NOTES:

1. Use the MOV instruction to set the DTT register.

2. The DTT register is enabled when the INV15 bit in the INVC1 register is set to 0 (dead time enabled).

No dead time can be set when the INV15 bit is set to 1 (dead time disabled). The INV06 bit in the INVC0

Rev.2.40 Apr 14, 2006 page 135 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.5 Registers TA1, TA2, TA4, TA11, TA21, TA41, and TB2

Timer Ai, Ai-1 Register (i = 1, 2, 4)

(1) (2) (3) (4) (5) (6)

Symbol Address After Reset

TA1, TA2, TA4

0389h - 0388h, 038Bh - 038Ah, 038Fh - 038Eh

Undefined

TA11, TA21, TA41

(7)

01C3h - 01C2h, 01C5h - 01C4h, 01C7h - 01C6h

Undefined

Function

b0b8

Setting Range

0000h to FFFFh

b15 b7

If setting value is n, the timer stops when the nth

count

source is counted

after a start trigger is generated

Positive phase changes to negative phase, and vice

versa, when timers A1, A2, and A4 stop.

NOTES:

1. Use a 16-bit data for read and write.

2. If the TAi or TAi1 register is set to 0000h, no counters start and no timer Ai interrupt is generated.

3. Use the MOV instruction to set registers TAi and TAi1.

4. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled), phase switches from an

inactive level to an active level when the dead time timer stops.

5. When the INV11 bit in the INVC1 register is set to 0 (three-phase mode 0), the value of the TAi register

is transferred to the reload register by a timer Ai start trigger.

When the INV11 bit is set to 1 (three-phase mode 1), the value of the TAi1 register is first transferred to

the reload register by a timer Ai start trigger. Then, the value of the TAi register is transferred by the next

trigger. The values of registers TAi1 and TAi are transferred alternately to the reload register with every

timer Ai start trigger.

6. Do not write to these registers when the timer B2 underflows.

7. Follow the procedure below to set the TAi1 register.

(a) Write value to the TAi1 register,

(b) Wait one timer Ai count source cycle, and

Timer B2 Register

(1)

Symbol Address After Reset

TB2 0395h - 0394h Undefined

Function

b0b8

Setting Range

If setting value is

, count source is divided by

+1.

Timers A1, A2, and A4 start every time an underflow occurs.

0000h to FFFFh

NOTE:

1. Use a 16-bit data for read and write.

b15 b7

Rev.2.40 Apr 14, 2006 page 136 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.6 Registers ICTB2 and TB2SC

Timer B2 Interrupt Generation Frequency Set Counter

(1) (2) (3)

Symbol Address After Reset

ICTB2 01CDh Undefined

b7 b0

Function Setting Range

1 to 15

Nothing is assigned. If necessary, set to 0.

When the INV01 bit in the INVC0 register is set to 0

(the ICTB2 counter increments whenever the timer B2

underflows) and the setting value is

, the timer B2 interrupt

is generated every

th time timer B2 underflow occurs.

When the INV01 bit is set to 1 (the INV00 bit selects

count timing of the ICTB2 counter) and setting value is

, the timer B2 interrupt is generated every

th time

timer B2 underflow meeting the condition selected in

the INV00 bit occurs.

NOTES:

1. Use the MOV instruction to set the ICTB2 register.

2. If the INV01 bit is set to 1, set the ICTB2 register when the TB2S bit is set to 0 (timer B2 count stops), If

the INV01 bit is set to 0 and the TB2S bit to 1 (timer B2 count starts), do not set the ICTB2 register when

the timer B2 underflows.

3.If the INV00 bit is set to 1, the first interrupt is generated when the timer B2 underflows

n-1

times,

being the value set in the ICTB2 counter. Subsequent interrupts are generated every

times the timer

B2 underflows.

Timer B2 reload timing

switching bit

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

PWCON

IVPCR1

(b7-b2)

Timer B2 Special Mode Register

(1)

Symbol Address After Reset

TB2SC 039Eh XXXXXX00b

b7 b6 b5 b4 b3 b2 b1 b0

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. If the INV11 bit in the INVC1 register is 0 (three-phase mode 0) or the INV06 bit in the INVC0 register

is 1 (sawtooth wave modulation mode), set this bit to 0 (timer B2 underflow).

3. Related pins are U(P8_0/TA4OUT), U(P8_1/TA4IN), V(P7_2/CLK2/TA1OUT), V(P7_3/CTS2/RTS2/TA1IN),

W(P7_4/TA2OUT), W(P7_5/TA2IN).

If a low-level signal is applied to the NMI pin when the IVPCR1 bit = 1, the target pins go to a high-impedance

state regardless of which functions of those pins are being used.

After forced interrupt (cutoff), input "H" to the NMI pin and set the IVPCR1 bit to 0: this forced cutoff will

be reset.

Bit Name

Bit

Symbol Function

0 : Timer B2 underflow

1 : Timer A output at odd-numbered

occurrences

(2)

Three-phase output port

NMI control bit 1

(3)

0 : Three-phase output forcible cutoff

by NMI input (high-impedance)

disabled

1 : Three-phase output forcible cutoff

by NMI input (high-impedance)

enabled

Rev.2.40 Apr 14, 2006 page 137 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.7 Registers TRGSR and TRBSR

Trigger Select Register

Symbol Address After Reset

TRGSR 0383h 00h

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol

TA1TGL

TA1TGH

TA2TGL

Timer A1 event/trigger

select bits

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

Function

Set to 01b (TB2 underflow) before

using a V-phase output control circuit

Timer A2 event/trigger

select bits

Set to 01b (TB2 underflow) before

using a W-phase output control circuit

Input on TA3IN pin is selected (1)

: TB2 is selected (2)

: TA2 is selected (2)

: TA4 is selected (2)

Timer A3 event/trigger

select bits

Timer A4 event/trigger

select bits

Set to 01b (TB2 underflow) before

using a U-phase output control circuit

NOTES:

1. Set the corresponding port direction bit to 0 (input mode).

2. Overflow or underflow.

Count Start Flag

Symbol Address After Reset

TABSR 0380h 00h

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol

TA0S

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

Function

0 : Count stops

1 : Count starts

Timer A0 count start flag

Timer A1 count start flag

Timer A2 count start flag

Timer A3 count start flag

Timer A4 count start flag

Timer B0 count start flag

Timer B1 count start flag

Timer B2 count start flag

Rev.2.40 Apr 14, 2006 page 138 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.8 Registers TA1MR, TA2MR, TA4MR, and TB2MR

Timer Ai Mode Register (i = 1, 2, 4)

Symbol Address After Reset

TA1MR, TA2MR, TA4MR 0397h, 0398h, 039Ah 00h

Bit Name Function

Bit

Symbol

TMOD0

TMOD1

MR0

Operating mode

select bits

MR1

MR2

MR3

TCK0

TCK1

Set to 10b (one-shot timer mode)

when using the three-phase motor

control timer function

Set to 0 when using the three-phase

motor control timer function

Set to 1 (selected by the TRGSR

motor control timer function

: f1 or f2

(1)

: f8

: f32

: fC32

External trigger

select bit

Trigger select bit

Set to 0 when using the three-phase motor control timer function

Count source select bits

Pulse output function

select bit

Set to 0 when using the three-phase

motor control timer function

b6 b5 b3 b2 b1b4b7 b0

110000

NOTE:

1. Selected by the PCLK0 bit in the PCLKR register.

Timer B2 Mode Register

Symbol Address After Reset

TB2MR 039Dh 00XX0000b

Bit Name Function

Bit

Symbol

TMOD0

TMOD1

MR0

Operating mode

select bits

MR1

MR2

MR3

TCK0

TCK1

Set to 00b (timer mode) when using

the three-phase motor control timer

function

: f1 or f2

(1)

: f8

: f32

: fC32

Disabled when using the three-phase motor control timer function.

If necessary, set to 0.

When read, the content is undefined.

Set to 0 when using the three-phase motor control timer function

If necessary, set to 0 when using the three-phase motor control

timer function.

When read when using the three-phase motor control timer

function, the content is undefined.

Count source select bits

b6 b5 b3 b2 b1b4b7 b0

000

NOTE:

1. Selected by the PCLK0 bit in the PCLKR register.

Rev.2.40 Apr 14, 2006 page 139 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.9 Triangular Wave Modulation Operation

The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1.

When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1, and A2 are

__ ___ ___

used to control three-phase PWM outputs (U, U, V, V, W, and W). The dead time is controlled by a

dedicated dead-time timer. Figure 14.9 shows an Example of Triangular Wave Modulation Opertation and

Figure 14.10 shows an Example of Sawtooth Wave Modulation Operation.

TA4 register

(2)

TA4-1 register

(2)

Reload register

(2)

nn pp

Timer A1

reload control signal

(1)

m n n

n p

Triangular Wave

Signal Wave

Triangular waveform as a carrier wave

Timer B2

TB2S bit in

TABSR register

Timer A4

start trigger signal

(1)

Timer A4

one-shot pulse

(1)

Rewrite registers IDB0 and IDB1

Transfer a counter

value to the three-phase

shift register

U-phase output

signal

(1)

U-phase output

signal

(1)

U-phase

INV14 = 0

("L" active)

U-phase

Dead time

INV14 = 1

("H" active)

U-phase

NOTES:

1.Internal signals. See Figure 14.1 Three-Phase Motor Control Timer Functions Block Diagram.

2.Applies only when the INV11 bit is set to 1 (three-phase mode).

Examples of PWM output change are

(a) When INV11=1 (three-phase mode 1)

- INV01=0 and ICTB2=2h (The timer B2 interrupt is

generated with every second timer B2 underflow) or

INV01= 1, INV00=1 and ICTB2=1h (The timer B2 interrupt is

generated on the falling edge of the timer A reload control

signal)

- Default value of the timer: TA41=m, TA4=m

Registers TA4 and TA41 are changed whenever the

timer B2 interrupt is generated.

First time: TA41=n, TA4=n.

Second time: TA41=p, TA4=p.

- Default value of registers IDB0 and IDB1

DU0=1, DUB0=0, DU1=0, DUB1=1

They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0

by the third timer B2 interrupt.

(b) When INV11=0 (three-phase mode 0)

- INV01=0, ICTB2=1h (The timer B2 interrupt is generated

whenever the timer B2 underflows)

- Default value of the timer: TA4=m

The TA4 register is changed whenever the timer B2

interrupt is generated.

First time: TA4=m. Second time: TA4=n.

Third time: TA4=n. Fourth time: TA=p.

Fifth time: TA4=p.

- Default value of registers IDB0 and IDB1:

DU0=1, DUB0=0, DU1=0, DUB1=1

They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by

the sixth timer B2 interrupt.

The above applies to INVC0 = 00XX11XXb and INVC1 = 010XXXX0b (X varies depending on each system.)

INV00, INV01: Bits in the INVC0 register

INV11, INV14: Bits in the INVC1 register

Rev.2.40 Apr 14, 2006 page 140 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 14. Three-Phase Motor Control Timer Function

Figure 14.10 Sawtooth Wave Modulation Operation

Timer B2

U-phase

Sawtooth wave

Signal wave

U-Phase output

signal(1)

U-Phase output

signal(1)

INV14 = 0

("L" active)

Sawtooth waveform as a carrier wave

Transfer the counter to the

three-phase shift register

Rewrite registers

IDB0 and IDB1

NOTES:

1. Internal signals. See Figure 14.1 Three-Phase Motor Control Timer Functions Block Diagram.

The examples of PWM output change are

- Default value of registers IDB0 and IDB1: DU0=0, DUB0=1, DU1=1, DUB1=1

They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt.

The above applies to INVC0 = 01XX110Xb and INVC1 = 010XXX00b (X varies depending on each system.)

INV14 = 1

("H" active) U-phase

U-phase

Dead time

Timer A4 one-shot

pulse(1)

Timer A4 start

trigger signal(1)

INV14: Bits in the INVC1 register

Rev.2.40 Apr 14, 2006 page 141 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15. Serial Interface

Serial interface is configured with 4 channels: UART0 to UART2 and SI/O3.

15.1 UARTi (i = 0 to 2)

UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.

Figures 15.1 to 15.3 show the UARTi Block Diagram. Figure 15.4 shows the UARTi Transmit/Receive Unit.

UARTi has the following modes:

• Clock synchronous serial I/O mode

• Clock asynchronous serial I/O mode (UART mode).

• Special mode 1 (I2C mode)

• Special mode 2

• Special mode 3 (Bus collision detection function, IE mode)

• Special mode 4 (SIM mode) : UART2

Figures 15.5 to 15.10 show the UARTi-related registers.

Refer to tables listing each mode for register setting.

Rev.2.40 Apr 14, 2006 page 142 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.1 UART0 Block Diagram

RXD0

1 / (n0+1)

1/16

1/2

U0BRG

Clock synchronous type

(when internal clock is selected)

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

Clock synchronous

type

(when external clock

is selected)

CLK0

Clock source selection

CTS0 /

RTS0

f1SIO or f2SIO

f8SIO

f32SIO

Internal

External

RTS0

CTS0

TXD0

Transmit/

receive

unit

(UART0)

CLK1 to CLK0

00h

01h

10h

CKDIR

CKPOL

UART reception

UART transmission

Clock synchronous type

CKDIR

RXD polarity

reversing circuit

RCSP

PCLK1

f1SIO or f2SIO

1/2

Main clock, PLL clock, or on-chip oscillator clock

1/2

1/8 f8SIO

f32SIO

f1SIO

f2SIO 0

SMD2 to SMD0

010, 100, 101, 110

001

010, 100, 101, 110

001

CRS

1/4

Receive

clock

Transmit

clock

Reception

control circuit

Transmission

control circuit

TXD

polarity

reversing

circuit

CTS/RTS disabled

CTS/RTS selected

CTS0 from UART1

CLK

polarity

reversing

circuit

n0: Values set to the U0BRG register

PCLK1: Bit in PCLKR register

SMD2 to SMD0, CKDIR: Bits in U0MR register

CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register

RCSP: Bit in UCON register

1CRD

VSS

Figure 15.2 UART1 Block Diagram

RXD1

Reception

control circuit

Transmission

control circuit

1 / (n1+1)

1/16

1/2

U1BRG

Clock synchronous type

(when internal clock is selected)

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

Clock synchronous type

(when external clock is selected))

CLK1

Clock source selection

f1SIO or f2SIO

f8SIO

f32SIO

Internal

External

TXD1

(UART1)

CLK1 to CLK0

CKDIR

UART reception

UART transmission

Clock synchronous

type

CKDIR

RXD polarity reversing

circuit

SMD2 to SMD0

010, 100, 101, 110

001

010, 100, 101, 110

001

RTS1

CTS1

Clock output

pin select

CTS1 / RTS1/

CTS0 / CLKS1

CRS

CLKMD0

CLK

polarity

reversing

circuit

CKPOL

CLKMD1

RCSP

n1: Values set to the U1BRG register

PCLK1: Bit in PCLKR register

SMD2 to SMD0, CKDIR: Bits in U1MR register

CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register

CLKMD0, CLKMD1, RCSP: Bits in UCON register

PCLK1

f1SIO or f2SIO

1/2

Main clock, PLL clock, or on-chip oscillator clock

1/2

1/8 f8SIO

f32SIO

f1SIO

f2SIO 0

1/4

Receive

clock

Transmit

clock

Transmit/

receive

unit

TXD

polarity

reversing

circuit

CTS0 from UART0

CTS/RTS disabled

CTS/RTS selected

VSS

CRD

Rev.2.40 Apr 14, 2006 page 143 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.3 UART2 Block Diagram

RXD2

1 / (n2+1)

1/16

1/2

U2BRG

Clock synchronous type

(when internal clock is selected)

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

Clock synchronous type

(when external clock is selected)

CLK2

Clock source selection

f1SIO or f2SIO

f8SIO

f32SIO

Internal

External

RTS2

CTS2

TXD2

(UART2)

CLK

polarity

reversing

circuit

CLK1 to CLK0

CKDIR

CKPOL

UART reception

UART transmission

Clock synchronous

type

CKDIR

RXD polarity reversing

circuit

SMD2 to SMD0

010, 100, 101, 110

001

010, 100, 101, 110

001

CRS

CTS2 /

RTS2

n2: Values set to the U2BRG register

PCLK1: Bit in PCLKR register

SMD2 to SMD0, CKDIR: Bits in U2MR register

CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register

CTS/RTS disabled

CTS/RTS selected

Reception

control circuit

Transmission

control circuit

Receive

clock

Transmit

clock

TXD

polarity

reversing

circuit

Transmit/

receive

unit

PCLK1

f1SIO or f2SIO

1/2

Main clock, PLL clock, or on-chip oscillator clock

1/2

1/8 f8SIO

f32SIO

f1SIO

f2SIO 0

1/4

VSS

1CRD

Rev.2.40 Apr 14, 2006 page 144 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.4 UARTi Transmit/Receive Unit

SP SP

PAR

2SP

1SP

UART

TXDi

D8 D7 D6 D5 D4 D3 D2 D1 D0

2SP

1SP

UART

RXDi

D7 D6 D5 D4 D3 D2 D1 D0D80000000

SP SP

PAR

SMD2 to SMD0

IOPOL

STPS

IOPOL

UiERE

PRYE

SMD2 to SMD0

STPS PRYE

Reverse

No reverse

RXD data

reverse circuit

Clock

synchronous

type

PAR

enabled

PAR

disabled

UART

(7 bits)

UART

(8 bits)

Clock

synchronous type

UART(7 bits)

UART

(9 bits)

Clock

synchronous type

UART

(8 bits)

UART

(9 bits)

UARTi receive register

UiTB register

UiRB register

Data bus low-order bits

Data bus high-order bits

Logic reverse circuit + MSB/LSB conversion circuit

UART(7 bits)

UARTi transmit register

UART

(8 bits)

UART

(9 bits)

Clock

synchronous type

UART

(7 bits)

UART

(8 bits)

Clock

synchronous

type

Clock

synchronous type

PAR

disabled

PAR

enabled

Error signal

output circuit

Error signal output

enable

Error signal output

disable

Reverse

No reverse

TXD data

reverse circuit

i = 0 to 2

SP: Stop bit

PAR: Parity bit

SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register

CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register

UiERE: Bit in UiC1 register

UART

(9 bits)

Rev.2.40 Apr 14, 2006 page 145 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.5 Registers U0TB to U2TB, U0RB to U2RB, and U0BRG to U2BRG

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

(b15-b9)

(b8-b0)

b7 b0 b0b7

Function

UARTi Transmit Buffer Register (i = 0 to 2)

(1)

Bit

Symbol

Symbol Address After Reset

U0TB 03A3h to 03A2h

Undefined

U1TB 03ABh to 03AAh

Undefined

U2TB 01FBh to 01FAh

Undefined

Transmit data WO

NOTE:

1. Use the MOV instruction to write to this register.

(b15) (b8)

(b7-b0)

Assuming that set value = n, UiBRG

divides the count source by n + 1

00h to FFh

b7 b0

Function Setting Range

UARTi Bit Rate Register (i = 0 to 2)

(1) (2) (3)

Bit

Symbol

Symbol Address After Reset

U0BRG 03A1h

Undefined

U1BRG 03A9h

Undefined

U2BRG 01F9h

Undefined

NOTES:

1. Write to this register while serial interface is neither transmitting nor receiving.

2. Use the MOV instruction to write to this register.

3. Write to this register after setting bits CLK1 to CLK0 in the UiC0 register.

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

(b10-b9)

(b7-b0)

(b8)

b7 b0

(b15) (b8) b7 b0

Function

UARTi Receive Buffer Register (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0RB 03A7h to 03A6h

Undefined

U1RB 03AFh to 03AEh

Undefined

U2RB 01FFh to 01FEh

Undefined

ABT Arbitration lost

detecting flag (1)

Receive data (

D7 to D0)

Receive data (

D8)

0 : Not detected

1 : Detected

Error sum flag (2) (3)

SUM 0 : No error

1 : Error found RO

Parity error flag (2) (3)

PER 0 : No parity error

1 : Parity error found RO

Framing error

flag (2) (3)

FER 0 : No framing error

1 : Framing error found RO

Overrun error flag (2)

OER 0 : No overrun error

1 : Overrun error found RO

NOTES:

1. The ABT bit is set to 0 by writing 0 in a program. (Writing 1 has no effect.)

2. When bits SMD2 to SMD0 in the UiMR register = 000b (serial interface disabled) or the RE bit in the UiC1 register = 0

(reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The SUM bit is set to 0 (no error) when

all of the PER, FER and OER bits are = 0 (no error).

Also, the PER and FER bits are set to 0 by reading the lower byte of the UiRB register.

3. These error flags are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous serial

I/O mode) or to 010b (I

C mode). When read, the content is undefined.

Rev.2.40 Apr 14, 2006 page 146 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.6 Registers U0MR to U2MR and U0C0 to U2C0

Function

UARTi Transmit/Receive Control Register 0 (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0C0 to U2C0 03A4h, 03ACh, 01FCh 00001000b

CLK0

CLK1

UiBRG count source

select bits (5)

Transmit register

empty flag

0 0 : f1SIO or f2SIO is selected (6)

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Do not set a value

TXEPT

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit register

(transmission completed)

Transfer format

select bit (4)

UFORM 0 : LSB first

1 : MSB first RW

Data output

select bit (3)

NCH

0 :

Pins TXDi/SDAi and SCLi are CMOS output

1 : Pins TXDi/SDAi and SCLi are

N channel open-drain output

CTS/RTS function

select bit (1)

CRS

Effective when CRD = 0

0 : CTS function is selected (2)

1 : RTS function is selected RW

CTS/RTS disable bit

CRD

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

(P6_0, P6_4, P7_3 can be used as I/O ports)

CLK polarity

select bit

CKPOL

0 : Transmit data is output at falling edge

of transfer clock and receive data is

input at rising edge

1 : Transmit data is output at rising edge

of transfer clock and receive data is

input at falling edge

b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

NOTES:

1. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the

RCSP bit in the UCON register = 0 (CTS0/RTS0 not separated).

2. Set the corresponding port direction bit for each CTSi pin to 0 (input mode).

3. SCL2/P7_1 is N channel open-drain output. The NCH bit in the U2C0 register is N channel open-drain

output regardless of the NCH bit.

4. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous

serial I/O mode), or 101b (UART mode, 8-bit transfer data).

Set this bit to 1 when bits SMD2 to SMD0 are set to 010b (I2C mode), and to 0 when bits SMD2 to SMD0

are set to 100b (UART mode, 7-bit transfer data) or 110b (UART mode, 9-bit transfer data).

5. When changing bits CLK1 to CLK0, set the UiBRG register.

6. Selected by the PCLK1 bit in the PCLKR register.

b7 b6 b5 b4 b3 b2 b1 b0

Function

UARTi Transmit/Receive Mode Register (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0MR to U2MR 03A0h, 03A8h, 01F8h 00h

SMD0

SMD1

SMD2

Serial I/O mode

select bits (1)

CKDIR Internal/external clock

select bit

Stop bit length

select bit

0 0 0 : Serial interface disabled

0 0 1 : Clock synchronous serial I/O mode

0 1 0 : I2C mode (2)

1 0 0 : UART mode transfer data 7-bit long

1 0 1 : UART mode transfer data 8-bit long

1 1 0 : UART mode transfer data 9-bit long

Do not set a value except above

0 : Internal clock

1 : External clock (3)

STPS 0 : 1 stop bit

1 : 2 stop bits

NOTES:

1. To receive data, set the corresponding port direction bit for each RXDi pin to 0 (input mode).

2. Set the corresponding port direction bit for pins SCL and SDA to 0 (input mode).

3. Set the corresponding port direction bit for each CLKi pin to 0 (input mode).

TXD, RXD I/O polarity

reverse bit

IOPOL 0 : No reverse

1 : Reverse RW

Parity enable bit

PRYE 0 : Parity disabled

1 : Parity enabled RW

Odd/even parity

select bit

PRY

Effective when the PRYE bit = 1

0 : Odd parity

1 : Even parity

b2 b1 b0

Rev.2.40 Apr 14, 2006 page 147 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.7 Registers U0C1, U1C1, and U2C1

b7 b6 b5 b4 b3 b2 b1 b0

Function

UARTj Transmit/Receive Control Register 1 (j = 0, 1)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0C1, U1C1 03A5h, 03ADh 00XX0010b

Transmit buffer

empty flag

Receive enable bit

Transmit enable bit

RI Receive complete

flag

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

0 : Transmission disabled

1 : Transmission enabled

0 : Data present in the UjTB register

1 : No data present in the UjTB register

0 : Reception disabled

1 : Reception enabled

0 : No data present in the UjRB register

1 : Data present in the UjRB register

(b5-b4)

Error signal output

enable bit

UjERE 0 : Output disabled

1 : Output enabled RW

Data logic

select bit

(1)

UjLCH 0 : No reverse

1 : Reverse RW

b7 b6 b5 b4 b3 b2 b1 b0

Function

UART2 Transmit/Receive Control Register 1

Bit Name

Bit

Symbol

Symbol Address After Reset

U2C1 01FDh 00000010b

Transmit buffer

empty flag

Receive enable bit

Transmit enable bit

RI Receive complete

flag

0 : Transmission disabled

1 : Transmission enabled

0 : Data present in U2TB register

1 :

No data present in U2TB register

0 : Reception disabled

1 : Reception enabled

0 :

No data present in U2RB register

1 : Data present in U2RB register

Error signal output

enable bit

U2ERE 0 : Output disabled

1 : Output enabled RW

Data logic

select bit

(1)

U2LCH 0 : No reverse

1 : Reverse RW

UART2 continuous

receive mode enable bit

U2RRM 0 : Continuous receive mode disabled

1 : Continuous receive mode enabled RW

UART2 transmit interrupt

source select bit

U2IRS 0 : Transmit buffer empty (TI bit = 1)

1 : Transmission completed

(TXEPT bit = 1)

NOTE:

1. The UjLCH bit is enabled when bits SMD2 to SMD0 in the UjMR register are set to 001b (clock synchronous

serial I/O mode), 100b (UART mode, 7-bit transfer data) or 101b (UART mode, 8-bit transfer data).

Set this bit to 0 when bits SMD2 to SMD0 are set to 010b (I

C mode) or 110b (UART mode, 9-bit transfer

data).

NOTE:

1. The U2LCH bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous

serial I/O mode), 100b (UART mode, 7-bit transfer data) or 101b (UART mode, 8-bit transfer data).

Set this bit to 0 when bits SMD2 to SMD0 are set to 010b (I

C mode) or 110b (UART mode, 9-bit transfer

data).

Rev.2.40 Apr 14, 2006 page 148 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.8 Registers UCON, and U0SMR to U2SMR

b7 b6 b5 b4 b3 b2 b1 b0

Function

UART Transmit/Receive Control Register 2

Bit Name

Bit

Symbol

Symbol Address After Reset

UCON 03B0h X0000000b

U0IRS

U1IRS

U0RRM

UART1 transmit interrupt

source select bit

UART0 continuous

receive mode enable bit

UART0 transmit interrupt

source select bit

U1RRM UART1 continuous

receive mode enable bit

0 : Transmit buffer empty (Tl bit = 1)

1 :

Transmission completed (TXEPT bit = 1)

0 : Transmit buffer empty (Tl bit = 1)

1 :

Transmission completed (TXEPT bit = 1)

0 : Continuous receive mode disabled

1 : Continuous receive mode enabled

0 : Continuous receive mode disabled

1 : Continuous receive mode enabled

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Separate UART0

CTS/RTS bit

RCSP

0 : CTS/RTS shared pin

1 : CTS/RTS separated

(CTS0 supplied from the P6_4 pin)

UART1 CLK/CLKS

select bit 1 (1)

CLKMD1

0 : CLK output is only CLK1

1 : Transfer clock output from multiple

pins function selected

UART1 CLK/CLKS

select bit 0

CLKMD0

Effective when the CLKMD1 bit = 1

0 : Clock output from CLK1

1 : Clock output from CLKS1

NOTE:

1. When using multiple transfer clock output pins, make sure the following conditions are met:

The CKDIR bit in the U1MR register = 0 (internal clock)

(b7)

b7 b6 b5 b4 b3 b2 b1 b0

Function

UARTi Special Mode Register (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0SMR to U2SMR 01EFh, 01F3h, 01F7h X0000000b

IICM

ABC

BBS

Arbitration lost detecting

flag control bit

Bus busy flag

I2C mode select bit

(b3) Reserved bit

0 : Other than I2C mode

1 : I2C mode

0 : Update per bit

1 : Update per byte

0 : STOP condition detected

1 : START condition detected (busy)

Set to 0

(1)

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

(b7)

Transmit start condition

select bit

SSS 0 : Not synchronized to RXDi

1 : Synchronized to RXDi (3) RW

Auto clear function

select bit of transmit

enable bit

ACSE

0 : No auto clear function

1 : Auto clear at occurrence of bus

collision

Bus collision detect

sampling clock select bit

ABSCS 0 : Rising edge of transfer clock

1 : Underflow signal of timer Aj (2) RW

NOTES:

1. The BBS bit is set to 0 by writing 0 in a program (writing 1 has no effect).

2. Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer

A0 in UART2.

3. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXDi).

Rev.2.40 Apr 14, 2006 page 149 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.9 Registers U0SMR2 to U2SMR2 and U0SMR3 to U2SMR3

b7 b6 b5 b4 b3 b2 b1 b0

Function

UARTi Special Mode Register 2 (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0SMR2 to U2SMR2 01EEh, 01F2h, 01F6h X0000000b

IICM2

CSC

SWC

Clock-synchronous

bit

SCL wait output bit

I2C mode select bit 2

ALS SDA output stop bit

See Table 15.12 I2C Mode Functions

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

(b7)

SDA output disable

bit

SDHI 0: Enabled

1: Disabled (high-impedance) RW

SCL wait output

bit 2

SWC2 0: Transfer clock

1: "L" output RW

UARTi initialization

bit

STAC 0 : Disabled

1 : Enabled RW

b7 b6 b5

NOTES:

1. Bits DL2 to DL0 are used to generate a delay in SDAi output by digital means during I2C mode.

In other than I2C mode, set these bits to 000b (no delay).

2. The amount of delay varies with the load on pins SCLi and SDAi. Also, when using an external clock,

the amount of delay increases by about 100 ns.

b7 b6 b5 b4 b3 b2 b1 b0

Function

UARTi Special Mode Register 3 (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0SMR3 to U2SMR3 01EDh, 01F1h, 01F5h 000X0X0Xb

(b0)

CKPH

(b2)

Clock phase set bit

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

(b4)

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

NODC Clock output select

bit

0 : Without clock delay

1 : With clock delay

0 : CLKi is CMOS output

1 : CLKi is N channel open-drain output

DL2

DL1 RW

SDAi digital delay

setup bits (1) (2)

DL0 0 0 0 : Without delay

0 0 1 :

1 to 2 cycle(s) of UiBRG count source

0 1 0 :

2 to 3 cycles of UiBRG count source

0 1 1 :

3 to 4 cycles of UiBRG count source

1 0 0 :

4 to 5 cycles of UiBRG count source

1 0 1 :

5 to 6 cycles of UiBRG count source

1 1 0 :

6 to 7 cycles of UiBRG count source

1 1 1 :

7 to 8 cycles of UiBRG count source

Rev.2.40 Apr 14, 2006 page 150 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.10 Registers U0SMR4 to U2SMR4

b7 b6 b5 b4 b3 b2 b1 b0

Function

UARTi Special Mode Register 4 (i = 0 to 2)

Bit Name

Bit

Symbol

Symbol Address After Reset

U0SMR4 to U2SMR4 01ECh, 01F0h, 01F4h 00h

STAREQ

RSTAREQ

STPREQ

Restart condition

generate bit (1)

Stop condition

generate bit (1)

Start condition

generate bit (1)

STSPSEL

SCL,SDA output

select bit

0 : Clear

1 : Start

0 : Clear

1 : Start

0 : Clear

1 : Start

0 : Start and stop conditions not output

1 : Start and stop conditions output

SCL wait bit 3SWC9 0 : SCL "L" hold disabled

1 : SCL "L" hold enabled RW

SCL output stop

enable bit

SCLHI 0 : Disabled

1 : Enabled RW

ACK data output

enable bit

ACKC 0 : Serial interface data output

1 : ACK data output RW

ACK data bitACKD 0 : ACK

1 : NACK RW

NOTE:

1. Set to 0 when each condition is generated.

Rev.2.40 Apr 14, 2006 page 151 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data.

Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers to

be Used in and Setting in Clock Synchronous Serial I/O Mode.

Table 15.1 Clock Synchronous Serial I/O Mode Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))

• fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

The CKDIR bit = 1 (external clock) : Input from CLKi pin

Transmit/receive control

_______ _______ _______ _______

Selectable from CTS function, RTS function or CTS/RTS function disabled

Transmit start condition Before transmission can start, meet the following requirements (1)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

_______ _______

• If CTS function is selected, input on the CTSi pin = L

Receive start condition Before reception can start, meet the following requirements (1)

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Interrupt request For transmission, one of the following conditions can be selected

generation timing • The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the

UiTB register to the UARTi transmit register (at start of transmission)

• The UiIRS bit =1 (transmission completed): when the serial interface finished

transmitting data from the UARTi transmit register

For reception

• When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection Overrun error (3)

This error occurs if the serial interface started receiving the next data before reading

the UiRB register and received the 7th bit of the next data

Select function • CLK polarity selection

Transfer data input/output can be selected to occur synchronously with the rising or

the falling edge of the transfer clock

• LSB first, MSB first selection

Whether to start transmitting or receiving data begins with bit 0 or begins with bit 7

can be selected

• Continuous receive mode selection

Reception is enabled immediately by reading the UiRB register

• Switching serial data logic

This function reverses the logic value of the transmit/receive data

• Transfer clock output from multiple pins selection (UART1)

The output pin can be selected in a program from two UART1 transfer clock pins that

have been set

_______ _______

• Separate CTS/RTS pins (UART0)

_________ _________

CTS0 and RTS0 are input/output from separate pins

i = 0 to 2

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0

(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the

external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge

and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register.

3. If an overrun error occurs, the receive data of UiRB register will be undefined. The IR bit in the SiRIC register

remains unchanged.

Rev.2.40 Apr 14, 2006 page 152 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.2 Registers to be Used and Settings in Clock Synchronous Serial I/O Mode

UiTB (1) 0 to 7 Set transmit data

UiRB (1) 0 to 7 Receive data can be read

OER Overrun error flag

UiBRG 0 to 7 Set a bit rate

UiMR (1) SMD2 to SMD0 Set to 001b

CKDIR Select the internal clock or external clock

IOPOL Set to 0

UiC0 CLK1 to CLK0 Select the count source for the UiBRG register

CRS

_______ _______

Select CTS or RTS to use

TXEPT Transmit register empty flag

CRD

_______ _______

Select CTS/RTS function enabled or disabled

NCH Select TXDi pin output mode

CKPOL Select the transfer clock polarity

UFORM Select the LSB first or MSB first

UiC1 TE Set this bit to 1 to enable transmission

TI Transmit buffer empty flag

RE Set this bit to 1 to enable reception

RI Reception complete flag

U2IRS (2) Select the UART2 transmit interrupt source

U2RRM (2) Set this bit to 1 to use continuous receive mode

UiLCH Set this bit to 1 to use inverted data logic

UiERE Set to 0

UiSMR 0 to 7 Set to 0

UiSMR2 0 to 7 Set to 0

UiSMR3 0 to 2 Set to 0

NODC Select clock output mode

4 to 7 Set to 0

UiSMR4 0 to 7 Set to 0

UCON U0IRS, U1IRS Select the UART0/UART1 transmit interrupt source

U0RRM, U1RRM Set this bit to 1 to use continuous receive mode

CLKMD0 Select the transfer clock output pin when the CLKMD1 bit = 1

CLKMD1 Set this bit to 1 to output UART1 transfer clock from two pins

RCSP

_________

Set this bit to 1 to accept as input the CTS0 signal of the UART0 from the P6_4 pin

7 Set to 0

i = 0 to 2

NOTES:

1. Not all register bits are described above. Set those bits to 0 when writing to the registers in clock

synchronous serial I/O mode.

2.Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in

the UCON register.

Rev.2.40 Apr 14, 2006 page 153 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.3 lists the I/O Pin Functions (when not select multiple transfer clock output pin select function) in

clock synchronous serial I/O mode. Table 15.4 lists the P6_4 Pin Functions in clock synchronous serial I/O

mode.

Note that for a period from when the UARTi operating mode is selected to when transfer starts, the TXDi

pin outputs an “H”.

Figure 15.11 shows the Transmit/Receive Operation during clock synchronous serial I/O mode.

Table 15.3 I/O Pin Functions (when not select multiple transfer clock output pin select function)

i = 0 to 2

Table 15.4 P6_4 Pin Functions

TXDi

(P6_3, P6_7, P7_0)

RXDi

(P6_2, P6_6, P7_1)

CLKi

(P6_1, P6_5, P7_2)

_________ ________

CTSi/RTSi

(P6_0, P6_4, P7_3)

Pin Name Function Method of Selection

Serial data output

Serial data input

Transfer clock output

Transfer clock input

________

CTS input

________

RTS output

I/O port

(Outputs dummy data when performing reception only)

Bits PD6_2 and PD6_6 in PD6 register = 0

PD7_1 bit in PD7 register = 0

(Can be used as an input port when performing transmission only)

CKDIR bit in UiMR register = 0

CKDIR bit = 1

Bits PD6_1 and PD6_5 in PD6 register = 0

PD7_2 bit in PD7 register = 0

CRD bit in UiC0 register = 0

CRS bit in UiC0 register = 0

Bits PD6_0 and PD6_4 in PD6 register = 0

PD7_3 bit in PD7 register = 0

CRD bit = 0

CRS bit = 1

CRD bit = 1

-: 0 or 1

NOTES:

__________ __________

In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0/RTS0 enabled) and the CRS bit

__________

in the U0C0 register to 1 (RTS0 selected).

2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:

• High if the CLKPOL bit in the U1C0 register = 0

• Low if the CLKPOL bit = 1

Bit set Value

Pin Function U1C0 Register UCON Register PD6 Register

CRD bit CRS bit RCSP bit CLKMD1 bit CLKMD0 bit PD6_4 bit

P6_4 1 - 0 0 - Input: 0, Output: 1

_________

CTS1 0 0 0 0 - 0

_________

RTS1 0 1 0 0 - -

_________

CTS0 (1) 0010 - 0

CLKS1 - - - 1 (2) 1-

Rev.2.40 Apr 14, 2006 page 154 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.11 Transmit and Receive Operation

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

TCLK

Transfer clock

TE bit in

UiC1 register

TI bit in

UiC1 register

CLK

TXDi

TXEPT bit in

UiC0 register

CTSi

IR bit in

SiTIC register

CLKi

RXDi

RTSi

RE bit in

UiC1 register

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5

D6 D6

TE bit in

UiC1 register

TI bit in

UiC1 register

OER flag in UiRB

IR bit in

SiRIC register

RI bit in

UiC1 register

"L"

"H"

"L"

"H"

The above timing diagram applies to the case where the register bits are set as follows:

CKDIR bit in UiMR register = 0 (internal clock)

CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit in UiC0 register = 0 (CTS selected)

CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data

taken in at the rising edge of the transfer clock)

UiIRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):

U0IRS bit is bit 0 in UCON register

U1IRS bit is bit 1 in UCON register

U2IRS bit is bit 4 in U2C1 register

Data is set to the UiTB register

Data is transferred from the UiTB register to the UARTi transmit register

Pulse stops because an "H" signal is

applied to CTSi Pulse stops because the TE bit is set to 0

Set to 0 by an interrupt request acknowledgement or by program

(1) Example of transmit timing (when internal clock is selected)

(2) Example of receive timing (when external clock is selected)

TC = TCLK = 2(n + 1) / fj

fj: frequency of UiBRG count source

(f1SIO, f2SIO, f8SIO, f32SIO)

n: value set to the UiBRG register

Dummy data is set to the UiTB register

Data is transferred from the UiTB register to the UARTi transmit register

An "L" signal is applied when

the UiRB register is read

1 / fEXT

Receive data is taken in

Read by the UiRB registerData is transferred from UARTi

receive register to the UiRB register

i = 0 to 2

The above timing diagram applies to the case where the register bits are set

as follows:

CKDIR bit in UiMR register = 1 (external clock)

CRD bit in UiC0 register = 0 (CTS/RTS enabled),

CRS bit in UiC0 register = 1 (RTS selected)

CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and

receive data taken in at the rising edge of

the transfer clock)

fEXT: frequency of external clock

i = 0 to 2

Make sure the following conditions are met when input

to the CLKi pin before receiving data is high:

TE bit in UiC1 register = 1 (transmission enabled)

RE bit in UiC1 register = 1 (reception enabled)

Write dummy data to the UiTB register

Rev.2.40 Apr 14, 2006 page 155 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.1.1 Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,

follow the procedures below.

• Resetting the UiRB register (i = 0 to 2)

(1) Set the RE bit in the UiC1 register to 0 (reception disabled)

(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)

(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode)

(4) Set the RE bit in the UiC1 register to 1 (reception enabled)

• Resetting the UiTB register (i = 0 to 2)

(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)

(2) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous serial I/O mode)

(3) 1 (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit

15.1.1.2 CLK Polarity Select Function

Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 15.12

shows the Transfer Clock Polarity.

(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive

data taken in at the falling edge of the transfer clock)

D1 D2 D3 D4 D5 D6 D7

TXDi

RXDi

CLKi

(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling

edge and the receive data taken in at the rising edge of the transfer clock)

D1 D2 D3 D4 D5 D6 D7D0

TXDi

RXDi

CLKi

* This applies to the case where the UFORM bit in the UiC0 register = 0

(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).

NOTES:

1. When not transferring, the CLKi pin outputs a high signal.

2. When not transferring, the CLKi pin outputs a low signal.

i = 0 to 2

(NOTE 1)

(NOTE 2)

Figure 15.12 Transfer Clock Polarity

Rev.2.40 Apr 14, 2006 page 156 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.1.3 LSB First/MSB First Select Function

Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.

Figure 15.13 shows the Transfer Format.

Figure 15.13 Transfer Format

15.1.1.4 Continuous Receive Mode

In continuous receive mode, receive operation becomes enable when the receive buffer register is read.

It is not necessary to write dummy data into the transmit buffer register to enable receive operation in

this mode. However, a dummy read of the receive buffer register is required when starting the operating

mode.

When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0

(data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write

dummy data to the UiTB register in a program. Bits U0RRM and U1RRM are bits 2 and 3 in the UCON

(1) When the UFORM bit in the UiC0 register = 0 (LSB first)

D1 D2 D3 D4 D5 D6 D7

TXDi

RXDi

CLKi

(2) When the UFORM bit = 1 (MSB first)

D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

TXDi

RXDi

CLKi

* This applies to the case where the CKPOL bit in the UiC0 register = 0

(transmit data output at the falling edge and the receive data taken in at

the rising edge of the transfer clock) and the UiLCH bit in the UiC1

i = 0 to 2

Rev.2.40 Apr 14, 2006 page 157 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.1.5 Serial Data Logic Switching Function

When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has

its logic reversed before being transmitted. Similarly, the receive data has its logic reversed when read

from the UiRB register. Figure 15.14 shows the Serial Data Logic Switching.

Figure

15.14

Serial Data Logic Switching

15.1.1.6 Transfer Clock Output From Multiple Pins (UART1)

Use bits CLKMD1 to CLKMD0 in the UCON register to select one of the two transfer clock output pins.

Figure 15.15 shows the Transfer Clock Output from Multiple Pins. This function can be used when the

selected transfer clock for UART1 is an internal clock.

Figure 15.15 Transfer Clock Output from Multiple Pins

D0 D1 D2 D3 D4 D5 D6 D7

Transfer clock

TXDi

(no reverse)

"H"

"L"

"H"

"L"

TXDi

(reverse) D0 D1 D2 D3 D4 D5 D6 D7

"H"

"L"

(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)

Transfer clock

"H"

"L"

(2) When the UiLCH bit = 1 (reverse)

* This applies to the case where the CKPOL bit in the UiC0 register = 0

(transmit data output at the falling edge and the receive data taken in

at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first).

i = 0 to 2

MCU

CLK

* This applies to the case where the CKDIR bit in the U1MR register

= 0 (internal clock) and the CLKMD1 bit in the UCON register = 1

(transfer clock output from multiple pins).

Transfer enabled when

the CLKMD0 bit in the

UCON register = 0

Transfer enabled when

the CLKMD0 bit = 1

TXD1(P6_7)

CLKS1(P6_4)

CLK1(P6_5)

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M16C/6N Group (M16C/6N4) 15. Serial Interface

_______ _______

15.1.1.7 CTS/RTS Function

_______ ________ ________

When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi

________ ________

(i = 0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal

is switched to “H” during a transmit or receive operation, the operation stops before the next data.

_______ ________ ________

When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the MCU is ready to

receive. The output level becomes “H” on the first falling edge of the CLKi pin.

_______ _______

• CRD bit in UiC0 register = 1 (CTS/RTS function disabled)

________ ________

CTSi/RTSi pin is programmable I/O function

_______

• CRD bit = 0, CRS bit in UiC0 register = 0 (CTS function is selected)

________ ________ _______

CTSi/RTSi pin is CTS function

_______

• CRD bit = 0, CRS bit = 1 (RTS function is selected)

________ ________ _______

CTSi/RTSi pin is RTS function

_______ _______

15.1.1.8 CTS/RTS Separate Function (UART0)

_______ _______ _______ _______

This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0

from the P6_4 pin. To use this function, set the register bits as shown below.

_______ _______

• CRD bit in U0C0 register = 0 (CTS/RTS of UART0 enabled)

_______

• CRS bit in U0C0 register = 1 (output RTS of UART0)

_______ _______

• CRD bit in U1C0 register = 0 (CTS/RTS of UART1 enabled)

_______

• CRS bit in U1C0 register = 0 (input CTS of UART1)

_______

• RCSP bit in UCON register = 1 (input CTS0 from the P6_4 pin)

• CLKMD1 bit in UCON register = 0 (CLKS1 not used)

_______ _______ _______ _______

Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be

used. _______ _______

Figure 15.16 shows the CTS/RTS Separate Function.

_______ _______

Figure 15.16 CTS/RTS Separate Function

MCU

OUT

CTS

RTS

CLK

TXD0(P6_3)

RXD0(P6_2)

CLK0(P6_1)

RTS0(P6_0)

CTS0(P6_4)

Rev.2.40 Apr 14, 2006 page 159 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Item Specification

Transfer data format •Character bit (transfer data): Selectable from 7, 8 or 9 bits

•Start bit: 1 bit

•Parity bit: Selectable from odd, even, or none

•Stop bit: Selectable from 1 or 2 bits

Transfer clock •CKDIR bit in UiMR register = 0 (internal clock) : fj/(16(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

•The CKDIR bit = 1 (external clock) : fEXT/(16(n+1))

fEXT: Input from CLKi pin. n :Setting value of the UiBRG register 00h to FFh

Transmit/receive control

_______ _______ _______ _______

Selectable from CTS function, RTS function or CTS/RTS function disabled

Transmit start condition Before transmission can start, meet the following requirements

•The TE bit in the UiC1 register = 1 (transmission enabled)

•The TI bit in the UiC1 register = 0 (data present in UiTB register)

•

_______ ________

If CTS function is selected, input on the CTSi pin = L

Receive start condition Before reception can start, meet the following requirements

•The RE bit in the UiC1 register = 1 (reception enabled)

•Start bit detection

Interrupt request For transmission, one of the following conditions can be selected

generation timing •The UiIRS bit (1) = 0 (transmit buffer empty): when transferring data from the UiTB register

to the UARTi transmit register (at start of transmission)

•The UiIRS bit =1 (transmission completed): when the serial interface finished

transmitting data from the UARTi transmit register

For reception

•When transferring data from the UARTi receive register to the UiRB register

(at completion of reception)

Error detection •Overrun error (2)

This error occurs if the serial interface started receiving the next data before reading

the UiRB register and received the bit one before the last stop bit of the next data

•Framing error (3)

This error occurs when the number of stop bits set is not detected

•Parity error (3)

This error occurs when if parity is enabled, the number of 1’s in parity and character

bits does not match the number of 1’s set

•Error sum flag

This flag is set to 1 when any of the overrun, framing, or parity errors occur

Select function •LSB first, MSB first selection

Whether to start transmitting or receiving data begins with bit 0 or begins with bit 7 can

be selected

•Serial data logic switch

This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.

•TXD, RXD I/O polarity switch

This function reverses the polarities of the TXD pin output and RXD pin input.

The logic levels of all I/O data is reversed.

•

_______ _______

Separate CTS/RTS pins (UART0)

_________ _________

CTS0 and RTS0 are input/output from separate pins

15.1.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data

format. Table 15.5 lists the UART Mode Specifications. Table 15.6 lists the Registers to be Used and

Setting in UART Mode.

Table 15.5 UART Mode Specifications

i = 0 to 2

NOTES:

1. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.

2. If an overrun error occurs, the receive data of UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged.

3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the

UARTi receive register to the UiRB register.

Rev.2.40 Apr 14, 2006 page 160 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.6 Registers to Be Used and Settings in UART Mode

UiTB 0 to 8 Set transmit data (1)

UiRB 0 to 8 Receive data can be read (1)

OER,FER,PER,SUM Error flag

UiBRG 0 to 7 Set a bit rate

UiMR SMD2 to SMD0 Set these bits to 100b when transfer data is 7-bit long

Set these bits to 101b when transfer data is 8-bit long

Set these bits to 110b when transfer data is 9-bit long

CKDIR Select the internal clock or external clock

STPS Select the stop bit

PRY, PRYE Select whether parity is included and whether odd or even

IOPOL Select the TXD/RXD input/output polarity

UiC0 CLK0 to CLK1 Select the count source for the UiBRG register

CRS

_______ _______

Select CTS or RTS to use

TXEPT Transmit register empty flag

CRD

_______ _______

Select CTS/RTS function enabled or disabled

NCH Select TXDi pin output mode

CKPOL Set to 0

UFORM LSB first or MSB first can be selected when transfer data is 8-bit long. Set this

bit to 0 when transfer data is 7- or 9-bit long.

UiC1 TE Set this bit to 1 to enable transmission

TI Transmit buffer empty flag

RE Set this bit to 1 to enable reception

RI Reception complete flag

U2IRS (2) Select the UART2 transmit interrupt source

U2RRM (2) Set to 0

UiLCH Set this bit to 1 to use inverted data logic

UiERE Set to 0

UiSMR 0 to 7 Set to 0

UiSMR2 0 to 7 Set to 0

UiSMR3 0 to 7 Set to 0

UiSMR4 0 to 7 Set to 0

UCON U0IRS, U1IRS Select the UART0/UART1 transmit interrupt source

U0RRM, U1RRM Set to 0

CLKMD0 Invalid because the CLKMD1 bit = 0

CLKMD1 Set to 0

RCSP

_________

Set this bit to 1 to accept as input the CTS0 of UART0 signal from the P6_4 pin

7 Set to 0

i = 0 to 2

NOTES:

1. The bits used for transmit/receive data are as follows:

• Bits 0 to 6 when transfer data is 7-bit long

• Bits 0 to 7 when transfer data is 8-bit long

• Bits 0 to 8 when transfer data is 9-bit long.

2. Set bits 4 to 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are included in the

UCON register.

Rev.2.40 Apr 14, 2006 page 161 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.7 lists the I/O Pins Functions in UART mode. Table 15.8 lists the P6_4 Pin Functions in UART

mode. Note that for a period from when the UARTi operating mode is selected to when transfer starts, the

TXDi pin outputs an “H”.

Figure 15.17 shows the Transmit Operation in UART mode. Figure 15.18 shows the Receive Operation in

UART mode.

Table 15.7 I/O Pin Functions

i = 0 to 2

Table 15.8 P6_4 Pin Functions

TXDi

(P6_3, P6_7, P7_0)

RXDi

(P6_2, P6_6, P7_1)

CLKi

(P6_1, P6_5, P7_2)

________ ________

CTSi/RTSi

(P6_0, P6_4, P7_3)

Pin Name Function Method of Selection

Serial data output

Serial data input

I/O port

Transfer clock input

_______

CTS input

________

RTS output

I/O port

(Outputs “H” when performing reception only)

Bits PD6_2 and PD6_6 in PD6 register = 0

PD7_1 bit in PD7 register = 0

(Can be used as an input port when performing transmission only)

CKDIR bit in UiMR register = 0

CKDIR bit in UiMR register = 1

Bits PD6_1 and PD6_5 in PD6 register = 0

PD7_2 bit in PD7 register = 0

CRD bit in UiC0 register = 0

CRS bit in UiC0 register = 0

Bits PD6_0 and PD6_4 in PD6 register = 0

PD7_3 bit in PD7 register = 0

CRD bit = 0

CRS bit = 1

CRD bit = 1

-: 0 or 1

NOTE:

__________ _________

In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0/RTS0 enabled) and the CRS

_________

bit in the U0C0 register to 1 (RTS0 selected).

Bit set Value

Pin Function U1C0 Register UCON Register PD6 Register

CRD bit CRS bit RCSP bit CLKMD1 bit PD6_4 bit

P6_4 1 - 0 0 Input: 0, Output: 1

_________

CTS1 0 0 0 0 0

_________

RTS1 0 1 0 0 -

_________

CTS0 (1) 0010 0

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.17 Transmit Operation

D0 D1 D2 D3 D4 D5 D6 D7ST P

TXDi

CTSi

D0 D1 D2 D3 D4 D5 D6 D7ST PD0 D1

TXDi

Transfer Clock

D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1 D2 D3 D4 D5 D6 D7ST D8 D0 D1

SP SPSP

TE bit in UiC1

TI bit in UiC1

TXEPT bit in

UiC0 register

IR bit in

SiTIC register

TE bit in UiC1

TI bit in UiC1

TXEPT bit in

UiC0 register

IR bit in

SiTIC register

SPSP

The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin,

when the stop bit is verified.

The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin.

Data is set to the UiTB register

Data is transferred from the UiTB register to

the UARTi transmit register

Parity

bit

Stop

bit

Start bit

Stop

bit Stop

bit

Start bit

Pulse stops because the TE bit is set to 0

Set to 0 by an interrupt request acknowledgement or by program

The above timing diagram applies to the case where the register bits are

set as follows:

PRYE bit in UiMR register = 1 (parity enabled)

STPS bit in UiMR register = 0 (1 stop bit)

CRD bit in UiC0 register = 0 (CTS/RTS enabled) and

CRS bit in UiC0 register = 0 (CTS selected)

UiIRS bit = 1 (an interrupt request is generated when transmission completed):

U0IRS bit is bit 0 in UCON register

U1IRS bit is bit 1 in UCON register

U2IRS bit is bit 4 in U2C1 register

i = 0 to 2

TC = 16(n+1) / fj or 16(n+1) / fEXT

fj: frequency of UiBRG count source

(f1SIO, f2SIO, f8SIO, f32SIO)

fEXT: frequency of UiBRG count source (external clock)

n: value set to the UiBRG register

TC = 16(n+1) / fj or 16(n+1) / fEXT

fj: frequency of UiBRG count source

(f1SIO, f2SIO, f8SIO, f32SIO)

fEXT: frequency of UiBRG count source (external clock)

n: value set to the UiBRG register

(2) 9-bit data transmit timing (with no parity and 2 stop bits)

(1) 8-bit data transmit timing (with a parity and 1 stop bit)

Data is set to the UiTB register

Data is transferred from the UiTB register to the UARTi transmit register

The above timing diagram applies to the case where the register bits are

set as follows:

PRYE bit in UiMR register = 0 (parity disabled)

STPS bit in UiMR register = 1 (2 stop bits)

CRD bit in UiC0 register = 1 (CTS/RTS disabled)

UiIRS bit = 0 (an interrupt request is generated when transmit buffer becomes empty):

U0IRS bit is bit 0 in UCON register

U1IRS bit is bit 1 in UCON register

U2IRS bit is bit 4 in U2C1 register

i = 0 to 2

"L"

"H"

Rev.2.40 Apr 14, 2006 page 163 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

• Example of receive timing when transfer data is 8-bit long (parity disabled, one stop bit)

The above timing diagram applies to the case where the register bits are set as follows:

PRYE bit in UiMR register = 0 (parity disabled)

STPS bit in UiMR register = 0 (1 stop bit)

CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)

i = 0 to 2

"H"

"L"

UiBRG count

source

RXDi

Transfer clock

RTSi

RE bit in

UiC1 register

RI bit in

UiC1 register

IR bit in

SiRIC register

Start bit

Sampled "L"

Stop bit

Reception triggered when transfer clock

is generated by falling edge of start bit

Set to 0 by an interrupt request acknowledgement or by program

Receive data taken in

Transferred from UARTi receive

Figure 15.18 Receive Operation

15.1.2.1 Bit Rates

In UART mode, the frequency set by the UiBRG register (i = 0 to 2) divided by 16 become the bit rates.

Table 15.9 lists an Example of Bit Rates and Settings.

Table 15.9 Example of Bit Rates and Settings

Bit Rate

Count Source

Peripheral Function Clock: 16 MHz Peripheral Function Clock: 20 MHz

Peripheral Function Clock: 24 MHz (1)

(bps) of UiBRG Set Value of Bit Rate Set Value of Bit Rate Set Value of Bit Rate

UiBRG: n (bps) UiBRG: n (bps) UiBRG: n (bps)

1200 f8 103 (67h) 1202 129 (81h) 1202 155 (9Bh) 1202

2400 f8 51 (33h) 2404 64 (40h) 2404 77 (4Dh) 2404

4800 f8 25 (19h) 4808 32(20h) 4735 38 (26h) 4808

9600 f1 103 (67h) 9615 129 (81h) 9615 155 (9Bh) 9615

14400 f1 68 (44h) 14493 86 (56h) 14368 103 (67h) 14423

19200 f1 51 (33h) 19231 64 (40h) 19231 77 (4Dh) 19231

28800 f1 34 (22h) 28571 42 (2Ah) 29070 51 (33h) 28846

31250 f1 31 (1Fh) 31250 39 (27h) 31250 47 (2Fh) 31250

38400 f1 25 (19h) 38462 32 (20h) 37879 38 (26h) 38462

51200 f1 19 (13h) 50000 23 (17h) 52083 28 (1Ch) 51724

i = 0 to 2

NOTE:

1. 24 MHz is available Normal-ver. only.

Rev.2.40 Apr 14, 2006 page 164 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.2.2 Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or receiving in UART mode, follow the procedures

below.

• Resetting the UiRB register (i = 0 to 2)

(1) Set the RE bit in the UiC1 register to 0 (reception disabled)

(2) Set the RE bit in the UiC1 register to 1 (reception enabled)

• Resetting the UiTB register (i = 0 to 2)

(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled)

(2) Set bits SMD2 to SMD0 in the UiMR register to 001b, 101b, 110b

(3) 1 (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit

15.1.2.3 LSB First/MSB First Select Function

As shown in Figure 15.19, use the UFORM bit in the UiC0 register to select the transfer format.

Figure 15.19 shows the Transfer Format. This function is valid when transfer data is 8-bit long.

Figure 15.19 Transfer Format

NOTE:

1. This applies to the case where the register bits are set as follows:

CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and the receive

data taken in at the rising edge of the transfer clock)

UiLCH bit in UiC1 register = 0 (no reverse)

STPS bit in UiMR register = 0 (1 stop bit)

PRYE bit in UiMR register = 1 (parity enabled)

(1) When the UFORM bit in the UiC0 register = 0 (LSB first)

(2) When the UFORM bit = 1 (MSB first)

D1 D2 D3 D4 D5 D6 SPD0

TXDi

RXDi

CLKi

D6 D5 D4 D3 D2 D1 D0

TXDi

RXDi

CLKi

D7 P

D6 D5 D4 D3 D2 D1 D0

i = 0 to 2

ST: Start bit

P: Parity bit

SP: Stop bit

Rev.2.40 Apr 14, 2006 page 165 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.21 TXD and RXD I/O Polarity Inverse

15.1.2.4 Serial Data Logic Switching Function

The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the

received data has its logic reversed when read from the UiRB register.

Figure 15.20 shows the Serial Data Logic Switching.

Figure 15.20 Serial Data Logic Switching

15.1.2.5 TXD and RXD I/O Polarity Inverse Function

This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/output

data (including the start, stop and parity bits) are inversed.

Figure 15.21 shows the TXD and RXD I/O Polarity Inverse.

Transfer clock

D0 D1 D2 D3 D4 D5 D6 D7 P SPST

TXDi

(no reverse)

TXDi

(reverse)

SPST D3 D4 D5 D6 D7 PD0 D1 D2

(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)

(2) When the UiLCH bit = 1 (reverse)

Transfer clock

i = 0 to 2

ST: Start bit

P: Parity bit

SP: Stop bit

NOTE:

1. This applies to the case where the register bit are set as follows:

CKPOL bit in UiC0 register = 0

(transmit data output at the falling edge of the transfer clock)

UFORM bit in UiC0 register = 0 (LSB first)

STPS bit in UiMR register = 0 (1 stop bit)

PRYE bit in UiMR register = 1 (parity enabled)

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

(1) When the IOPOL bit in the UiMR register = 0 (no reverse)

(2) When the IOPOL bit = 1 (reverse)

D0 D1 D2 D3 D4 D5 D6 D7 P SPST

SPST D3 D4 D5 D6 D7 PD0 D1 D2

D0 D1 D2 D3 D4 D5 D6 D7 P SPST

SPST D3 D4 D5 D6 D7 PD0 D1 D2

Transfer clock

TXDi

(no reverse)

RXDi

(no reverse)

Transfer clock

TXDi

(reverse)

RXDi

(reverse)

i = 0 to 2

ST: Start bit

P: Parity bit

SP: Stop bit

NOTE:

1. This applies to the case where the register bits are set as follows:

UFORM bit in UiC0 register = 0 (LSB first)

STPS bit in UiMR register = 0 (1 stop bit)

PRYE bit in UiMR register = 1 (parity enabled)

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

Rev.2.40 Apr 14, 2006 page 166 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

_______ _______

15.1.2.6 CTS/RTS Function

_______ ________ ________

When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i = 0 to 2)

________ ________

pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H”

during a transmit operation, the operation stops before the next data.

_______ ________ ________

When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the MCU is ready to

receive. The output level becomes “H” on the first falling edge of the CLKi pin.

•

_______ _______

CRD bit in UiC0 register = 1 (CTS/RTS function of UART0 disabled)

________ ________

CTSi/RTSi pin is programmable I/O function

•

_______

CRD bit = 0, CRS bit in UiC0 register= 0 (CTS function is selected)

________ ________ _______

CTSi/RTSi pin is CTS function

•

_______

CRD bit = 0, CRS bit = 1 (RTS function is selected)

________ ________ _______

CTSi/RTSi pin is RTS function

_______ _______

15.1.2.7 CTS/RTS Separate Function (UART0)

_________ _________ ________ _________

This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0

from the P6_4 pin. To use this function, set the register bits as shown below.

_______ _______

• CRD bit in U0C0 register = 0 (CTS/RTS of UART0 enabled)

_______

• CRS bit in U0C0 register = 1 (output RTS of UART0)

_______ _______

• CRD bit in U1C0 register = 0 (CTS/RTS of UART1 enabled)

_______

• CRS bit in U1C0 register = 0 (input CTS of UART1)

_______

• RCSP bit in UCON register = 1 (input CTS0 from the P6_4 pin)

• CLKMD1 bit in UCON register = 0 (CLKS1 not used)

_______ _______ _______ _______

Note that when using the CTS/RTS separate function, CTS/RTS of UART1 separate function cannot be

used. _______ _______

Figure 15.22 shows CTS/RTS separate function usage.

_______ _______

Figure 15.22 CTS/RTS Separate Function

MCU

OUT

CTS

RTS

TXD0(P6_3)

RXD0(P6_2)

RTS0(P6_0)

CTS0(P6_4)

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.3 Special Mode 1 (I2C Mode)

I2C mode is provided for use as a simplified I2C interface compatible mode. Table 15.10 lists the I2C Mode

Specifications. Figure 15.23 shows the I2C Mode Block Diagram. Table 15.11 lists the Registers to be

Used and Setting in I2C Mode. Table 15.12 lists the I2C Mode Functions. Figure 15.24 shows the Transfer

to UiRB Register and Interrupt Timing.

As shown in Table 15.12, the MCU is placed in I2C mode by setting bits SMD2 to SMD0 to 010b and the

IICM bit to 1. Because SDAi transmit output has a delay circuit attached, SDAi output does not change

state until SCLi goes low and remains stably low.

Table 15.10 I2C Mode Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock • During master

The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

• During slave

The CKDIR bit = 1 (external clock) : Input from SCLi pin

Transmit start condition Before transmission can start, meet the following requirements (1)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Receive start condition Before reception can start, meet the following requirements (1)

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

When start or stop condition is detected, acknowledge undetected, and acknowledge

detected

Error detection Overrun error (2)

This error occurs if the serial I/O started receiving the next data before reading the

UiRB register and received the 8th bit of the next data

Select function • Arbitration lost

Timing at which the ABT bit in the UiRB register is updated can be selected

• SDAi digital delay

No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable

• Clock phase setting

With or without clock delay selectable

Interrupt request

generation timing

i = 0 to 2

NOTES:

1. When an external clock is selected, the conditions must be met while the external clock is in the high state.

2. If an overrun error occurs, the value of UiRB register will be undefined. The IR bit in the SiRIC register

remains unchanged.

Rev.2.40 Apr 14, 2006 page 168 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.23 I2C Mode Block Diagram

CLK

control

Falling edge

detection

External

clock

Internal clock

Start/stop condition

detection

interrupt request

Start condition

detection

Stop condition

detection

Receive register

Bus

busy

Transmit

Arbitration

Noise

Filter

SDAi

SCLi

UARTi

NACK

ACK

UARTi

UARTi transmit,

NACK interrupt

request

UARTi receive,

ACK interrupt request,

DMA1 request

IICM=1 and

IICM2=0

ALS

SWC

IICM=1 and

IICM2=0

IICM2=1

SWC2

SDHI

DMA0, DMA1 request

(UART1: DMA0 only)

Noise

Filter

IICM=0

IICM=1

DMA0

(UART0, UART2)

STSPSEL=0

STSPSEL=1

STSPSEL=0

SDA(STSP)

SCL(STSP)

ACKC=1

ACKC=0

Port register

(1)

I/O port

9th bit falling edge

9th bit

ACKD bit

Delay

circuit

Start and stop condition generation block

This diagram applies to the case where bits SMD2 to SMD0 in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.

i = 0 to 2

IICM: Bit in UiSMR register

IICM2, SWC, ALS, SWC2, SDHI: Bits in UiSMR2 register

STSPSEL, ACKD, ACKC: Bits in UiSMR4 register

NOTE:

1. If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).

Rev.2.40 Apr 14, 2006 page 169 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.11 Registers to Be Used and Settings in I2C Mode

Master Slave

UiTB (1) 0 to 7 Set transmit data

UiRB (1) 0 to 7 Receive data can be read

8 ACK or NACK is set in this bit

ABT Arbitration lost detection flag Invalid

OER Overrun error flag

UiBRG 0 to 7 Set a bit rate Invalid

UiMR (1) SMD2 to SMD0 Set to 010b

CKDIR Set to 0 Set to 1

IOPOL Set to 0

UiC0 CLK1 to CLK0

Select the count source for the UiBRG register

Invalid

CRS Invalid because the CRD bit = 1

TXEPT Transmit register empty flag

CRD (3) Set to 1

NCH Set to 1

CKPOL Set to 0

UFORM Set to 1

UiC1 TE

Set this bit to 1 to enable transmission

TI Transmit buffer empty flag

RE Set this bit to 1 to enable reception

RI Reception complete flag

U2IRS (2) Invalid

U2RRM (2), Set to 0

UiLCH, UiERE

UiSMR IICM Set to 1

ABC Select the timing at which arbitration-lost Invalid

is detected

BBS Bus busy flag

3 to 7 Set to 0

UiSMR2 IICM2 See Table 15.12 I2C Mode Functions

CSC

Set this bit to 1 to enable clock synchronization

Set to 0

SWC

Set this bit to 1 to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock

ALS Set this bit to 1 to have SDAi output Set to 0

stopped when arbitration-lost is detected

STAC Set to 0 Set this bit to 1 to initialize UARTi at

start condition detection

SWC2 Set this bit to 1 to have SCLi output forcibly pulled low

SDHI Set this bit to 1 to disable SDAi output

7 Set to 0

UiSMR3 0, 2, 4, and NODC Set to 0

CKPH See Table 15.12 I2C Mode Functions

DL2 to DL0 Set the amount of SDAi digital delay

UiSMR4 STAREQ Set this bit to 1 to generate start condition Set to 0

RSTAREQ Set this bit to 1 to generate restart condition Set to 0

STPREQ Set this bit to 1 to generate stop condition Set to 0

STSPSEL Set this bit to 1 to output each condition Set to 0

ACKD Select ACK or NACK

ACKC Set this bit to 1 to output ACK data

SCLHI Set this bit to 1 to have SCLi output Set to 0

stopped when stop condition is detected

SWC9 Set to 0 Set this bit to 1 to set the SCLi to “L” hold

at the falling edge of the 9th bit of clock

IFSR0 IFSR06, ISFR07 Set to 1

UCON U0IRS, U1IRS Invalid

2 to 7 Set to 0

i = 0 to 2

NOTES:

1. Not all register bits are described above. Set those bits to 0 when writing to the registers in I2C mode.

2. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the UCON register.

_______ ________

When using UART1 in I2C mode and enabling the CTS/RTS separate function of UART0, set the CRD bit in the U1C0

_______ ________ _______

Rev.2.40 Apr 14, 2006 page 170 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

No acknowledgment detection

(NACK)

Rising edge of SCLi 9th bit

Acknowledgment detection (ACK)

Rising edge of SCLi 9th bit

Acknowledgment detection (ACK)

UARTi transmission

Falling edge of

SCLi next to the

9th bit

Falling and rising

edges of SCLi 9th

bit

1st to 8th bits are

stored into bit 7 to bit

0 in UiRB register

(3)

Bit 6 to bit 0 in the UiRB

7 to bit 1. Bit 8 in the UiRB

UARTi transmission

Rising edge of

SCLi 9th bit

Falling edge of

SCLi 9th bit

Table 15.12 I2C Mode Functions

i = 0 to 2

NOTES:

1. If the interrupt source is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to

1 (interrupt requested). (Refer to 23.6 Interrupts.)

If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set

the IR bit to 0 (interrupt not requested) after changing those bits.

• Bits SMD2 to SMD0 in UiMR register • IICM bit in UiSMR register

• IICM2 bit in UiSMR2 register • CKPH bit in UiSMR3 register

2. Set the initial value of SDAi output while bits SMD2 to SMD0 in the UiMR register = 000b (serial interface disabled).

3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)

4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)

5. See Figure 15.26 STSPSEL Bit Functions.

6. See Figure 15.24 Transfer to UiRB Register and Interrupt Timing.

7. When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to 1 (interrupt source: UART0 bus collision detection).

When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to 1 (interrupt source: UART1 bus collision detection).

Function

Clock

Synchronous

Serial I/O Mode

(SMD2 to SMD0 =

001b, IICM = 0)

I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)

IICM2 = 0

(NACK/ACK interrupt)

IICM2 = 1

(UART transmit/receive interrupt)

CKPH = 0

(No clock delay)

CKPH = 1

(Clock delay)

Source of interrupt

number 6, 7, and

(1) (5) (7)

Source of interrupt

number 15, 17, and

19 (1) (6)

Source of interrupt

number 16, 18, and

20 (1) (6)

Timing for transferring

data from UART

reception shift register

to UiRB register

UARTi transmission

output delay

Functions of pins

P6_3, P6_7, and P7_0

Functions of pins

P6_2, P6_6, and P7_1

Functions of pins

P6_1, P6_5, and P7_2

Noise filter width

Read RXDi and

SCLi pins levels

Initial value of TXDi

and SDAi outputs

Initial and end

value of SCLi

DMA1 source (6)

Store received

data

Read received

data

UARTi transmission

Transmission started

or completed

(selected by UiIRS)

UARTi reception

When 8th bit received

CKPOL = 0 (rising edge)

CKPOL = 1 (falling edge)

CKPOL = 0 (rising edge)

CKPOL = 1 (falling edge)

Not delayed

TXDi output

RXDi input

CLKi input or

output selected

15 ns

Possible when the

corresponding port

direction bit = 0

CKPOL = 0 (H)

CKPOL = 1 (L)

UARTi reception

The UiRB register status is read

CKPH = 0

(No clock delay)

CKPH = 1

(Clock delay)

1st to 8th bits of the received data are stored into bits

7 to 0 in the UiRB register

Start condition detection or stop condition detection

(See Table 15.13 STSPSEL Bit Functions)

UARTi reception

Falling edge of SCLi 9th bit

Delayed

SDAi input/output

SCLi input/output

- (Cannot be used in I2C mode)

200 ns

Always possible no matter how the corresponding port direction bit is set

The value set in the port register before setting I2C mode (2)

UARTi reception

Falling edge of SCLi 9th bit

1st to 7th bits of the received data are stored into

bits 6 to 0 in the UiRB

bit 8 in the UiRB register

Rev.2.40 Apr 14, 2006 page 171 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.24 Transfer to UiRB Register and Interrupt Timing

i = 0 to 2

This diagram applies to the case where the following condition is met.

The CKDIR bit in the UiMR register = 0 (slave selected)

(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)

ACK interrupt (DMA1 request),

NACK interrupt

Transfer to UiRB register

D6 D5 D4 D3 D2 D1 D8 (ACK, NACK)

D8 (ACK, NACK)

SDAi

SCLi

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

b15 b9 b8 b7 b0

D8D7D6D5D4D3D2D1D0

UiRB register

D6 D5 D4 D3 D2 D1

SDAi

SCLi

b15 b9 b8 b7 b0

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

(2) IICM2 = 0, CKPH = 1 (clock delay)

ACK interrupt (DMA1 request),

NACK interrupt

Transfer to UiRB register

UiRB register

(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0

Receive interrupt

(DMA1 request) Transmit interrupt

Transfer to UiRB register

D6 D5 D4 D3 D2 D1

SDAi

SCLi

b15 b9 b8 b7 b0

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

UiRB register

(4) IICM2 = 1, CKPH = 1

D6 D5 D4 D3 D2 D1

SDAi

SCLi

D0 D8 (ACK, NACK)

b15 b9 b8 b7 b0 b15 b9 b8 b7 b0

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

Transmit interrupt

Transfer to UiRB register

Receive interrupt

(DMA1 request)

Transfer to UiRB register

UiRB register UiRB register

D8 D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1D0

D8 D7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1D0

Rev.2.40 Apr 14, 2006 page 172 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.3.1 Detection of Start and Stop Condition

Whether a start or a stop condition has been detected is determined.

A start condition-detected interrupt request is generated when the SDAi pin changes state from high to

low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when

the SDAi pin changes state from low to high while the SCLi pin is in the high state.

Figure 15.25 shows the Detection of Start and Stop Condition.

Because the start and stop condition-detected interrupts share the interrupt control register and vector,

check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.

Figure 15.25 Detection of Start and Stop Condition

15.1.3.2 Output of Start and Stop Condition

A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to 1 (start).

A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to 1 (start).

A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to 1 (start).

The output procedure is described below.

(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start).

(2) Set the STSPSEL bit in the UiSMR4 register to 1 (output).

Table 15.13 and Figure 15.26 show the STSPSEL Bit Functions.

3 to 6 cycles < duration for setting-up (1)

3 to 6 cycles < duration for holding (1)

Duration for

setting-up

Duration for

holding

SCLi

SDAi

(Start condition)

SDA i

(Stop condition)

i = 0 to 2

NOTE:

1.When the PCLK1 bit in the PCLKR register = 1, this is the cycle number

of f1SIO, and when the PCLK1 bit = 0, this is the cycle number of f2SIO.

Rev.2.40 Apr 14, 2006 page 173 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.13 STSPSEL Bit Functions

Figure 15.26 STSPSEL Bit Functions

15.1.3.3 Arbitration

Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge

of SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB

unmatching is detected during check, and is set to 0 when not detected. In cases when the ABC bit is set

to 1, if unmatching is detected even once during check, the ABT bit is set to 1 (unmatching detected) at

the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated per byte, set the ABT bit

to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte.

Setting the ALS bit in the UiSMR2 register to 1 (SDA output stop enabled) causes arbitration-lost to

occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is

set to 1 (unmatching detected).

Function

Output of pins SCLi and SDAi

Start/stop condition interrupt

request generation timing

STSPSEL Bit = 0

Output of transfer clock and

data

Output of start/stop condition is

accomplished by a program

using ports (not automatically

generated in hardware)

Start/stop condition detection

STSPSEL Bit = 1

Output of a start/stop condition

depending on bits STAREQ,

RSTAREQ, and STPREQ

Finish generating start/stop

condition

Start condition

detection interrupt Stop condition

detection interrupt

(1) When slave

CKDIR bit = 1 (external clock)

Start condition

detection interrupt

Stop condition

detection interrupt

(2) When master

CKDIR bit = 0 (internal clock), CKPH bit = 1 (clock delayed)

SDAi

SCLi

Set STAREQ bit

= 1 (start) Set STPREQ bit

= 1 (start)

STSPSEL bit 0

SDAi

SCLi

STSPSEL bit

Set to 1 in

a program Set to 0 in

a program Set to 1 in

a program Set to 0 in

a program

1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.3.4 Transfer Clock

Data is transmitted/received using a transfer clock like the one shown in Figure 15.24 Transfer to UiRB

The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi)

and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to 1 (clock synchronization

enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi

goes low, at which time the value of the UiBRG register is reloaded with and starts counting in the

low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low, counting

stops, and when the SCLi pin goes high, counting restarts.

In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin

signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to

the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.

The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed

from low-level output at the falling edge of the 9th clock pulse.

If the SCLHI bit in the UiSMR4 register is set to 1 (enabled), SCLi output is turned off (placed in the high-

impedance state) when a stop condition is detected.

Setting the SWC2 bit in the UiSMR2 register = 1 (0 output) makes it possible to forcibly output a low-level

signal from the SCLi pin even while sending or receiving data. Setting the SWC2 bit to 0 (transfer clock)

allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal.

If the SWC9 bit in the UiSMR4 register is set to 1 (SCL hold low enabled) when the CKPH bit in the

UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next

to the 9th. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.

15.1.3.5 SDA Output

The data written to bits 7 to 0 (D7 to D0) in the UiTB register is sequentially output beginning with D7.

The 9th bit (D8) is ACK or NACK.

The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and bits SMD2 to

SMD0 in the UiMR register = 000b (serial interface disabled).

Bits DL2 to DL0 in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count source

clock cycles to SDAi output.

Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in the

high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi

transfer clock. This is because the ABT bit may inadvertently be set to 1 (detected).

15.1.3.6 SDA Input

When the IICM2 bit = 0, 1st to 8th bits (D7 to D0) of receive data are stored in bits 7 to 0 in the UiRB

When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of receive data are stored in bits 6 to 0 in the UiRB

providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the

UiRB register after the rising edge of the corresponding clock pulse of 9th bit.

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.3.7 ACK and NACK

If the STSPSEL bit in the UiSMR4 register is set to 0 (start and stop conditions not generated) and the

ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the UiSMR4

If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge

of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the

rising edge of the 9th bit of transmit clock pulse.

If ACKi is selected for the DMA1 request source, a DMA transfer can be activated by detection of an

acknowledge.

15.1.3.8 Initialization of Transmission/Reception

If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface

operates as described below.

•The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit

shift register. In this way, the serial interface starts transmitting data synchronously with the next clock

pulse applied. However, the UARTi output value does not change state and remains the same as

when a start condition was detected until the first bit of data is output synchronously with the input

clock.

•The receive shift register is initialized, and the serial interface starts receiving data synchronously with

the next clock pulse applied.

•The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the

falling edge of the 9th clock pulse.

Note that when UARTi transmission/reception is started using this function, the TI bit does not change

state. Note also that when using this function, the selected transfer clock should be an external clock.

Rev.2.40 Apr 14, 2006 page 176 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.4 Special Mode 2

Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are

selectable. Table 15.14 lists the Special Mode 2 Specifications. Figure 15.27 shows the Serial Bus

Communication Control Example (UART2). Table 15.15 lists the Registers to be Used an Settings in

Special Mode 2.

Table 15.14 Special Mode 2 Specifications

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock • Master mode

The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh

• Slave mode

The CKDIR bit = 1 (external clock selected) : Input from CLKi pin

Transmit/receive control Controlled by input/output ports

Transmit start condition Before transmission can start, meet the following requirements (1)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Receive start condition Before reception can start, meet the following requirements (1)

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

Interrupt request For transmission, one of the following conditions can be selected

generation timing • The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the UiTB

• The UiIRS bit =1 (transmission completed): when the serial interface finished

transmitting data from the UARTi transmit register

For reception

• When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection Overrun error (3)

This error occurs if the serial interface started receiving the next data before reading

the UiRB register and received the 7th bit of the next data

Select function Clock phase setting

Selectable from four combinations of transfer clock polarities and phases

i = 0 to 2

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0

the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at

the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock

is in the low state.

2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register ; the U2IRS bit is bit 4 in the U2C1 register.

3. If an overrun error occurs, the value of UiRB register will be undefined. The IR bit in SiRIC register

remains unchanged.

Rev.2.40 Apr 14, 2006 page 177 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.27 Serial Bus Communication Control Example (UART2)

MCU (Master) MCU (Slave)

MCU (Slave)

P1_3

P1_2

P7_2(CLK2)

P7_1(RXD2)

P7_0(TXD2)

P9_3

P7_2(CLK2)

P7_1(RXD2)

P7_0(TXD2)

P9_3

P7_2(CLK2)

P7_1(RXD2)

P7_0(TXD2)

Rev.2.40 Apr 14, 2006 page 178 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.15 Registers to Be Used and Settings in Special Mode 2

UiTB (1) 0 to 7 Set transmit data

UiRB (1) 0 to 7 Receive data can be read

OER Overrun error flag

UiBRG 0 to 7 Set a bit rate

UiMR (1) SMD2 to SMD0 Set to 001b

CKDIR Set this bit to 0 for master mode or 1 for slave mode

IOPOL Set to 0

UiC0 CLK1 to CLK0 Select the count source for the UiBRG register

CRS Invalid because the CRD bit = 1

TXEPT Transmit register empty flag

CRD Set to 1

NCH Select TXDi pin output format

CKPOL Clock phases can be set in combination with the CKPH bit in the UiSMR3 register

UFORM Set to 0

UiC1 TE Set this bit to 1 to enable transmission

TI Transmit buffer empty flag

RE Set this bit to 1 to enable reception

RI Reception complete flag

U2IRS (2) Select the UART2 transmit interrupt source

U2RRM (2), Set to 0

UiLCH, UiERE

UiSMR 0 to 7 Set to 0

UiSMR2 0 to 7 Set to 0

UiSMR3 CKPH Clock phases can be set in combination with the CKPOL bit in the UiC0 register

NODC Set to 0

0, 2, 4 to 7 Set to 0

UiSMR4 0 to 7 Set to 0

UCON U0IRS, U1IRS Select the UART0 and UART1 transmit interrupt source

U0RRM, U1RRM Set to 0

CLKMD0 Invalid because the CLKMD1 bit = 0

CLKMD1, RCSP, 7 Set to 0

i = 0 to 2

NOTES:

1. Not all register bits are described above. Set those bits to 0 when writing to the registers in Special

Mode 2.

2. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the

UCON register.

Rev.2.40 Apr 14, 2006 page 179 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.4.1 Clock Phase Setting Function

One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in

the UiSMR3 register and the CKPOL bit in the UiC0 register.

Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.

Figure 15.28 shows the Transmission and Reception Timing in Master Mode (internal clock).

Figure 15.29 shows the Transmission and Reception Timing (CKPH = 0) in Slave Mode (external clock).

Figure 15.30 shows the Transmission and Reception Timing (CKPH = 1) in Slave Mode (external clock).

D0 D1 D2 D3 D4 D6 D7D5

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

Clock output

(CKPOL = 0, CKPH = 0)

Clock output

(CKPOL = 1, CKPH = 0)

Clock output

(CKPOL = 0, CKPH = 1)

Clock output

(CKPOL = 1, CKPH = 1)

Data output timing

Data input timing

Figure 15.28 Transmission and Reception Timing in Master Mode (Internal Clock)

Rev.2.40 Apr 14, 2006 page 180 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.29 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock)

Figure 15.30 Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock)

D0 D1 D2 D3 D4 D6 D7D5

Undefined

Slave control input

Clock input

(CKPOL= 0, CKPH = 0)

Clock input

(CKPOL = 1, CKPH = 0)

Data output timing

Data input timing

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

D0 D1 D2 D3 D6 D7D4 D5

Slave control input

Clock input

(CKPOL = 0, CKPH = 1)

Clock input

(CKPOL = 1, CKPH = 1)

Data output timing

Data input timing

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

Rev.2.40 Apr 14, 2006 page 181 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.5 Special Mode 3 (IE Mode)

In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.

Table 15.16 lists the Registers to be Used and Settings in IE mode. Figure 15.31 shows the Bus Collision

Detect Function-Related Bits.

If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect

interrupt request is generated.

Use bits IFSR06 and IFSR07 in the IFSR0 register to enable the UART0/UART1 bus collision detect function.

Table 15.16 Registers to Be Used and Settings in IE Mode

UiTB 0 to 8 Set transmit data

UiRB (1) 0 to 8 Receive data can be read

OER,FER,PER,SUM Error flag

UiBRG 0 to 7 Set a bit rate

UiMR SMD2 to SMD0 Set to 110b

CKDIR Select the internal clock or external clock

STPS Set to 0

PRY Invalid because the PRYE bit = 0

PRYE Set to 0

IOPOL Select the TXD/RXD input/output polarity

UiC0 CLK1 to CLK0 Select the count source for the UiBRG register

CRS Invalid because the CRD bit = 1

TXEPT Transmit register empty flag

CRD Set to 1

NCH Select TXDi pin output mode

CKPOL Set to 0

UFORM Set to 0

UiC1 TE Set this bit to 1 to enable transmission

TI Transmit buffer empty flag

RE Set this bit to 1 to enable reception

RI Reception complete flag

U2IRS (2) Select the UART2 transmit interrupt source

U2RRM (2), Set to 0

UiLCH, UiERE

UiSMR 0 to 3, 7 Set to 0

ABSCS Select the sampling timing at which to detect a bus collision

ACSE Set this bit to 1 to use the auto clear function of transmit enable bit

SSS Select the transmit start condition

UiSMR2 0 to 7 Set to 0

UiSMR3 0 to 7 Set to 0

UiSMR4 0 to 7 Set to 0

IFSR0 IFSR06, IFSR07 Set to 1

UCON U0IRS, U1IRS Select the UART0/UART1 transmit interrupt source

U0RRM, U1RRM Set to 0

CLKMD0 Invalid because the CLKMD1 bit = 0

CLKMD1, RCSP, 7 Set to 0

i= 0 to 2

NOTES:

1. Not all register bits are described above. Set those bits to 0 when writing to the registers in IE mode.

2. Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the

UCON register.

Rev.2.40 Apr 14, 2006 page 182 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.31 Bus Collision Detect Function-Related Bits

(3) The SSS bit in UiSMR register (transmit start condition select)

Transmission enable condition is met

If SSS bit = 1, the serial interface starts transmitting data at the rising edge

(1)

of RXDi

TXDi

CLKi

TXDi

RXDi

ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

If SSS bit = 0, the serial interface starts transmitting data one transfer clock cycle after the transmission enable condition is met.

Transfer clock

(NOTE 2)

NOTES:

1.The falling edge of RXDi when IOPOL bit = 0; the rising edge of RXDi when IOPOL bit = 1.

2.The transmit condition must be met before the falling edge

(1)

of RXDi.

(2) The ACSE bit in UiSMR register (auto clear of transmit enable bit)

TXDi

RXDi

ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

Transfer clock

IR bit in

UiBCNIC register

TE bit in

UiC1 register

If the ACSE bit = 1 (automatically

clear when bus collision occurs),

the TE bit is set to 0

(transmission disabled) when

the IR bit in the UiBCNIC register = 1

(unmatching detected).

(1) The ABSCS bit in UiSMR register (bus collision detect sampling clock select)

If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock

Transfer clock

Timer Aj

TXDi

RXDi

ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

Trigger signal is applied to the TAjIN pin

If ABSCS bit = 1, bus collision is determined when timer

Aj (one-shot timer mode) underflows.

timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2

i = 0 to 2

This diagram applies to the case where IOPOL bit =1 (reversed).

Rev.2.40 Apr 14, 2006 page 183 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Item Specification

Transfer data format • Direct format

• Inverse format

Transfer clock • The CKDIR bit in the U2MR register = 0 (internal clock) : fi/(16(n+1))

fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the U2BRG register 00h to FFh

• The CKDIR bit = 1 (external clock) : fEXT/(16(n+1))

fEXT: Input from CLK2 pin. n: Setting value of the U2BRG register 00h to FFh

Transmit start condition Before transmission can start, meet the following requirements

• The TE bit in the U2C1 register = 1 (transmission enabled)

• The TI bit in the U2C1 register = 0 (data present in the U2TB register)

Receive start condition Before reception can start, meet the following requirements

• The RE bit in the U2C1 register = 1 (reception enabled)

• Start bit detection

• For transmission

When the serial interface finished sending data from the U2TB transfer register

(U2IRS bit = 1)

• For reception

When transferring data from the UART2 receive register to the U2RB register (at

completion of reception)

Error detection • Overrun error (1)

This error occurs if the serial interface started receiving the next data before reading

the U2RB register and received the bit one before the last stop bit of the next data

• Framing error (3)

This error occurs when the number of stop bits set is not detected

• Parity error (3)

During reception, if a parity error is detected, parity error signal is output from the

TXD2 pin.

During transmission, a parity error is detected by the level of input to the RXD2 pin

when a transmission interrupt occurs

• Error sum flag

This flag is set to 1 when any of the overrun, framing, and parity errors is encountered

15.1.6 Special Mode 4 (SIM Mode) (UART2)

Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be

implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.

Table 15.17 lists the SIM Mode Specifications. Table 15.18 lists the Registers to be Used and Settings in

SIM Mode. Figure 15.32 shows the Transmit and Receive Riming in SIM Mode.

Table 15.17 SIM Mode Specifications

Interrupt request

generation timing (2)

NOTES:

1. If an overrun error occurs, the value of the U2RB register will be undefined. The IR bit in the S2RIC

2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 (transmission

completed) and U2ERE bit in the U2C1 register to 1 (error signal output) after reset. Therefore, when

using SIM mode, set the IR bit to 0 (interrupt not requested) after setting these bits.

3. The timing at which the framing error flag and the parity error flag are set is detected when data is

transferred from the UARTi receive register to the UiRB register.

Rev.2.40 Apr 14, 2006 page 184 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Table 15.18 Registers to Be Used and Settings in SIM Mode

U2TB (1) 0 to 7 Set transmit data

U2RB (1) 0 to 7 Receive data can be read

OER,FER,PER,SUM Error flag

U2BRG 0 to 7 Set a bit rate

U2MR SMD2 to SMD0 Set to 101b

CKDIR Select the internal clock or external clock

STPS Set to 0

PRY Set this bit to 1 for direct format or 0 for inverse format

PRYE Set to 1

IOPOL Set to 0

U2C0 CLK1 to CLK0 Select the count source for the U2BRG register

CRS Invalid because the CRD bit = 1

TXEPT Transmit register empty flag

CRD Set to 1

NCH Set to 0

CKPOL Set to 0

UFORM Set this bit to 0 for direct format or 1 for inverse format

U2C1 TE Set this bit to 1 to enable transmission

TI Transmit buffer empty flag

RE Set this bit to 1 to enable reception

RI Reception complete flag

U2IRS Set to 1

U2RRM Set to 0

U2LCH Set this bit to 0 for direct format or 1 for inverse format

U2ERE Set to 1

U2SMR (1) 0 to 3 Set to 0

U2SMR2 0 to 7 Set to 0

U2SMR3 0 to 7 Set to 0

U2SMR4 0 to 7 Set to 0

NOTE:

1. Not all register bits are described above. Set those bits to 0 when writing to the registers in SIM mode.

Rev.2.40 Apr 14, 2006 page 185 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.32 Transmit and Receive Timing in SIM Mode

D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1 D2 D3 D4 D5 D6 D7ST P

Transfer clock

D0 D1 D2 D3 D4 D5 D6 D7ST P

TXD2

D0 D1 D2 D3 D4 D5 D6 D7ST P

Transfer clock

Transmit waveform

from the

Transmitting end

D0 D1 D2 D3 D4 D5 D6 D7ST P

RXD2 pin level (3)

D0 D1 D2 D3 D4 D5 D6 D7ST P SP

D0 D1 D2 D3 D4 D5 D6 D7ST P D0 D1 D2 D3 D4 D5 D6 D7ST P SPSP

TXD2

Parity Error signal

returned from

Receiving end

RXD2

pin level (2)

(NOTE 1)

RE bit in U2C1

RI bit in U2C0

IR bit in S2RIC

TE bit in U2C1

TI bit in U2C1

TXEPT bit in U2C0

IR bit in S2TIC

(1) Transmit timing

(2) Receive timing

Data is written to the U2TB register

Parity

bit

Stop

bit

Start

bit

Parity

bit

Stop

bit

Start

bit

Data is transferred from the U2TB

An "L" signal is applied from the

SIM card due to a parity error

TXD2 provides "L" output

due to a parity error

Read the U2RB register

An interrupt routine detects "H" or "L"

An interrupt routine

detects "H" or "L"

Set to 0 by an interrupt request acknowledgement or by program

TC = 16(n+1) / fi or 16(n+1) / fEXT

fi: frequency of U2BRG count source

(f1SIO, f2SIO, f8SIO, f32SIO)

fEXT: frequency of U2BRG count source (external clock)

n: value set to the U2BRG register

The above timing diagram applies to the case where data is

transmitted in the direct format.

STPS bit in U2MR register = 0 (1 stop bit)

PRY bit in U2MR register = 1 (even)

UFORM bit in U2C0 register = 0 (LSB first)

U2LCH bit in U2C1 register = 0 (no reverse)

U2IRS bit in U2C1 register = 1 (transmission completed)

TC = 16(n+1) / fi or 16(n+1) / fEXT

fi: frequency of U2BRG count source

(f1SIO, f2SIO, f8SIO, f32SIO)

fEXT: frequency of U2BRG count source (external clock)

n: value set to the U2BRG register

The above timing diagram applies to the case where data is

received in the direct format.

STPS bit in U2MR register = 0 (1 stop bit)

PRY bit in U2MR register = 1 (even)

UFORM bit in U2C0 register = 0 (LSB first)

U2LCH bit In U2C1 register = 0 (no reverse)

U2IRS bit in U2C1 register = 1 (transmission completed)

NOTES:

1. Data transmission starts when BRG overflows after a value is set to the U2TB register on the rising edge of the TI bit.

2. Because the TXD2 and RXD2 pins are connected, a composite waveform, consisting of transmit waveform from the TXD2 pin and

parity error signal from the receiving end, is generated.

3. Because the TXD2 and RxD2 pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end

and parity error signal from the TXD2 pin, is generated.

Rev.2.40 Apr 14, 2006 page 186 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.33 shows the SIM Interface Connection. Connect TXD2 and RXD2 and apply pull-up.

Figure 15.33 SIM Interface Connection

15.1.6.1 Parity Error Signal Output

The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (output enabled).

The parity error signal is output when a parity error is detected while receiving data. This is achieved by

pulling the TXD2 output low with the timing shown in Figure 15.32. If the U2RB register is read while

outputting a parity error signal, the PER bit in the U2RB register is set to 0 (no parity error) and at the

same time the TXD2 output is returned high.

When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer

clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned

can be determined by reading the port that shares the UXD2 pin in a transmission-finished interrupt

routine.

Figure 15.34 shows the output timing of the parity error signal

Figure 15.34 Parity Error Signal Output Timing

MCU

SIM card

TXD2

RXD2

D0 D1 D2 D3 D4 D5 D6 D7 P SPST

(NOTE 1)

Transfer

clock

RXD2

TXD2

"H"

"L"

"H"

"L"

"H"

"L"

This timing diagram applies to the case where the direct format is

implemented.

NOTE:

1: The output of MCU is in the high-impedance state (pulled up externally).

ST: Start bit

P: Even Parity

SP: Stop bit

RI bit in

U2C1 register

Rev.2.40 Apr 14, 2006 page 187 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.1.6.2 Format

When direct format, set the PRYE bit in the U2MR register to 1, the PRY bit to 1, the UFORM bit in the

U2C0 register to 0 and the U2LCH bit in the U2C1 register to 0. When data are transmitted, data set in

the U2TB register are transmitted with the even-numbered parity, starting from D0. When data are

received, received data are stored in the U2RB register, starting from D0. The even-numbered parity

determines whether a parity error occurs.

When inverse format, set the PRYE bit to 1, the PRY bit to 0, the UFORM bit to 1 and the U2LCH bit to

1. When data are transmitted, values set in the U2TB register are logically inversed and are transmitted with

the odd-numbered parity, starting from D7. When data are received, received data are logically inversed

to be stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a

parity error occurs.

Figure 15.35 shows the SIM Interface Format.

Figure 15.35 SIM Interface Format

P : Even parity

D0 D1 D2 D3 D4 D5 D6 D7 P

Transfer

clock

TXD2

TXD2 D7 D6 D5 D4 D3 D2 D1 D0 P

Transfer

clock

"H"

"L"

"H"

"L"

P : Odd parity

"H"

"L"

"H"

"L"

(1) Direct format

(2) Inverse format

Rev.2.40 Apr 14, 2006 page 188 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.2 SI/O3

SI/O3 is exclusive clock-synchronous serial I/Os.

Figure 15.36 shows the SI/O3 Block Diagram, and Figure 15.37 shows the SI/O3-related registers. Table

15.19 lists the SI/O3 Specifications.

Figure 15.36 SI/O3 Block Diagram

S3TRR register

SI/O counter 3

Synchronous

circuit

Data bus

SI/O3

interrupt

request

SM35 LSB MSB

SM32

SM33

SM36

SM31 to SM30

S3BRG register

SM36

n = A value set in the S3BRG register.

1/(n+1)

1/2

CLK polarity

reversing

circuit

1/2

f1SIO

1/8

1/4

f8SIO

f32SIO

f2SIO PCLK1=0

PCLK1=1

SM34

Clock source select

00b

01b

10b

CLK3

SOUT3

SIN3

Main clock,

PLL clock,

or on-chip oscillator clock

Rev.2.40 Apr 14, 2006 page 189 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

Figure 15.37 Registers S3C, S3BRG, and S3TRR

0 0 : f1SIO or f2SIO is selected (6)

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Do not set a value

0 : Input/output port

1 : SOUT3 output, CLK3 function

0 : SOUT3 output

1 : SOUT3 output disabled (high-impedance)

0 : Transmit data is output at falling edge of

transfer clock and receive data is input

at rising edge

1 : Transmit data is output at rising edge of

transfer clock and receive data is input

at falling edge

b1 b0

0 : LSB first

1 : MSB first

0 : External clock (3)

1 : Internal clock (4)

Effective when the SM33 bit = 0

0 : "L" output

1 : "H" output

b7 b6 b5 b4 b3 b2 b1 b0

SI/O3 Control Register

(1)

Symbol Address After Reset

S3C 01E2h 01000000b

Bit

Symbol Bit Name Description RW

SM35

SM31

SM30

SM33

SM36

SM37

SM32

SM34

Internal synchronous

clock select bits (5)

Transfer direction select

bit

SI/O3 port select bit

SOUT3 initial value set bit

Synchronous clock

select bit

SOUT3 output disable

bit (2)

CLK polarity select bit

NOTES:

1. Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to 1

(write enabled).

2. When the SM32 bit is set to 1, the target pin goes to a high-impedance state regardless of which functions of the

pin is being used.

3. Set the SM33 bit to 1 (SOUT3 output, CLK3 function) and the corresponding port direction bit to 0 (input mode).

4. Set the SM33 bit to 1 (SOUT3 output, CLK3 function).

5. When changing bits SM31 to SM30, set the S3BRG register.

6. Selected by the PCLK1 bit in the PCLKR register.

NOTES:

1. Write to this register while serial interface is neither transmitting nor receiving.

2. Use the MOV instruction to write to this register.

3. Write to this register after setting bits SM31 to SM30 in the S3C register.

Description RW

Assuming that set value = n, S3BRG divides the count

source by n + 1

Symbol Address After Reset

S3BRG 01E3h Undefined

b7 b0

00h to FFh

Setting Range

SI/O3 Bit Rate Register

(1) (2) (3)

NOTES:

1. Write to this register while serial interface is neither transmitting nor receiving.

2. To receive data, set the corresponding port direction bit for SIN3 to 0 (input mode).

b7 b0

Symbol Address After Reset

S3TRR 01E0h Undefined

Description

SI/O3 Transmit/Receive Register

(1) (2)

Transmission/reception starts by writing transmit data to this register.

After transmission/reception finishes, receive data can be read by reading this register.

Rev.2.40 Apr 14, 2006 page 190 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

Item Specification

Transfer data format Transfer data length: 8 bits

Transfer clock •SM36 bit in S3C register = 1 (internal clock) : fj/(2(n+1))

fj = f1SIO, f8SIO, f32SIO. n = Setting value of S3BRG register 00h to FFh

•SM36 bit = 0 (external clock) : Input from CLK3 pin (1)

Transmit/receive Before transmission/reception can start, meet the following requirements

start condition Write transmit data to the S3TRR register (2) (3)

Interrupt request •When SM34 bit in S3C register = 0

generation timing The rising edge of the last transfer clock pulse (4)

•When SM34 bit = 1

The falling edge of the last transfer clock pulse (4)

CLK3 pin function I/O port, transfer clock input, transfer clock output

SOUT3 pin function I/O port, transmit data output, high-impedance

SIN3 pin function I/O port, receive data input

Select function •LSB first or MSB first selection

Whether to start transmitting or receiving data begins with bit 0 or begins

with bit 7 can be selected

•Function for setting an SOUT3 initial value set function

When the SM36 bit in the S3C register = 0 (external clock), the SOUT3 pin

output level while not transmitting can be selected.

•CLK polarity selection

Whether transmit data is output/input timing at the rising edge or falling

edge of transfer clock can be selected.

Table 15.19 SI/O3 Specifications

NOTES:

1. To set the SM36 bit in the S3C register to 0 (external clock), follow the procedure described below.

•If the SM34 bit in the S3C register = 0, write transmit data to the S3TRR register while input on the

CLK3 pin is high. The same applies when rewriting the SM37 bit in the S3C register.

•If the SM34 bit = 1, write transmit data to the S3TRR register while input on the CLK3 pin is low. The

same applies when rewriting the SM37 bit.

• Because shift operation continues as long as the transfer clock is supplied to the SI/O3 circuit, stop

the transfer clock after supplying eight pulses. If the SM36 bit = 1 (internal clock), the transfer clock

automatically stops.

2. Unlike UART0 to UART2, SI/O3 is not separated between the transfer register and buffer. Therefore,

do not write the next transmit data to the S3TRR register during transmission.

3. When the SM36 bit = 1 (internal clock), SOUT3 retains the last data for a 1/2 transfer clock period after

completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is

written to the S3TRR register during this period, SOUT3 immediately goes to a high-impedance state,

with the data hold time thereby reduced.

4. When the SM36 bit = 1 (internal clock), the transfer clock stops in the high state if the SM34 bit = 0, or

stops in the low state if the SM34 bit = 1.

Rev.2.40 Apr 14, 2006 page 191 of 376

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M16C/6N Group (M16C/6N4) 15. Serial Interface

15.2.1 SI/O3 Operation Timing

Figure 15.38 shows the SI/O3 Operation Timing.

Figure 15.38 SI/O3 Operation Timing

15.2.2 CLK Polarity Selection

The SM34 bit in the S3C register allows selection of the polarity of the transfer clock.

Figure 15.39 shows the Polarity of Transfer Clock.

Figure 15.39 Polarity of Transfer Clock

D7D0 D1 D2 D3 D4 D5 D6

0.5 to 1.0 cycle (max.)

(NOTE 2)

(1)

SI/O3 internal clock

CLK3 output

Signal written to the

S3TRR register

SOUT3 output

SIN3 input

IR bit in S3IC register

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

* This diagram applies to the case where the bits in the S3C register are set as follows:

SM32 = 0 (SOUT3 output)

SM33 = 1 (SOUT3 output, CLK3 function)

SM34 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)

SM35 = 0 (LSB first)

SM36 = 1 (internal clock)

NOTES:

1. If the SM36 bit = 1 (internal clock), the serial interface starts transmitting or receiving data a maximum of 0.5 to 1.0 transfer clock cycles

after writing to the S3TRR register.

2. When the SM36 bit = 1 (internal clock), the SOUT3 pin is placed in the high-impedance state after the transfer finishes.

D1 D2 D3 D4 D5 D6 D7

SOUT3

SIN3

CLK3

D1 D2 D3 D4 D5 D6 D7D0

SOUT3

SIN3

CLK3

(2) When SM34 bit = 1

(1) When SM34 bit in S3C register = 0

*This diagram applies to the case where the bits in the S3C register are set as follows:

SM35 = 0 (LSB first)

SM36 = 1 (internal clock)

NOTES:

1. When the SM36 bit = 1 (internal clock), a high level is output from the CLK3 pin if not

transferring data.

2. When the SM36 bit = 1 (internal clock), a low level is output from the CLK3 pin if not

transferring data.

(NOTE 2)

(NOTE 1)

Rev.2.40 Apr 14, 2006 page 192 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 15. Serial Interface

15.2.3 Functions for Setting SOUT3 Initial Value

If the SM36 bit in the S3C register is set to 0 (external clock), the SOUT3 pin output can be fixed high or

low when not transferring. However, the last bit value of the former data is retained between data and

data when transmitting the continuous data.

Figure 15.40 shows the timing chart and how to set it for the SOUT3’s Initial Value Setting.

Figure 15.40 SOUT3’s Initial Value Setting

Setting the SOUT3

initial value to "H"

(2)

Port selection switching

(I/O port SOUT3)

Initial value = H

(1)

Port output D0

Signal written to

S3TRR register

SOUT3 (internal)

SM37 bit

SOUT3 output

SM33 bit

(Example) When "H" selected for SOUT3 initial value

* This diagram applies to the case where the bits in the S3C register are set as follows:

SM32 = 0 (SOUTi output)

SM35 = 0 (LSB first)

SM36 = 0 (external clock)

NOTES:

1.If the SM36 bit = 1 (internal clock) or if the SM32 bit = 1 (SOUT3 output disabled), this output

goes to the high-impedance state.

2.SOUT3 can only be initialized when input on the CLK3 pin is in the high state if the SM34 bit in

the S3C register = 0 (transmit data output at the falling edge of the transfer clock) or in the low

state if the SM34 bit = 1 (transmit data output at the rising edge of the transfer clock).

"H" level is output

from the SOUT3 pin

Serial transmit/reception starts

Setting of the initial value of SOUT3

output and starting of

transmission/reception

Set the SM33 bit to 1

(SOUT3 pin functions as SOUT3 output)

Write to the S3TRR register

Set the SM33 bit to 0

(SOUT3 pin functions as an I/O port)

Set the SM37 bit to 1

(SOUT3 initial value = H)

Rev.2.40 Apr 14, 2006 page 193 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Item Performance

Method of A/D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (1) 0 V to AVCC (VCC)

Operating clock φAD (2) fAD, divide-by-2 of fAD, divide-by-3 of fAD, divide-by-4 of fAD,

divide-by-6 of fAD, divide-by-12 of fAD

Resolution 8 bits or 10 bits (selectable)

Integral nonlinearity error When AVCC = VREF = 5 V

•With 8-bit resolution: ±2 LSB

•With 10-bit resolution: ±3 LSB

When external operation amp connection mode is selected: ±7 LSB

When AVCC = VREF = 3.3 V

•With 8-bit resolution: ±2 LSB

•With 10-bit resolution: ±5 LSB

When external operation amp connection mode is selected: ±7 LSB

Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins 8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)

+ 8 pins (AN2_0 to AN2_7)

A/D conversion •Software trigger

start condition The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)

•External trigger (retriggerable)

_____________

Input on the ADTRG pin changes state from high to low after the ADST bit

is set to 1 (A/D conversion starts)

Conversion speed per pin •Without sample and hold

8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles

•With sample and hold

8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles

NOTES:

1. Does not depend on use of sample and hold.

2. φAD frequency must be 10 MHz or less.

When sample and hold is disabled, φAD frequency must be 250 kHz or more.

When sample and hold is enabled, φAD frequency must be 1 MHz or more.

16. A/D Converter

The MCU contains one A/D converter circuit based on 10-bit successive approximation method configured

with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6,

_____________

P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using

these inputs, make sure the corresponding port direction bits are set to 0 (input mode).

When not using the A/D converter, set the VCUT bit to 0 (VREF unconnected), so that no current will flow

from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.

The A/D conversion result is stored in the bits in the ADi register for pins ANi, AN0_i, and AN2_i (i = 0 to 7).

Table 16.1 shows the A/D Converter Performance. Figure 16.1 shows the A/D Converter Block Diagram, and

Figures 16.2 and 16.3 show the A/D converter-related registers.

Table 16.1 A/D Converter Performance

Rev.2.40 Apr 14, 2006 page 194 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.1 A/D Converter Block Diagram

ANEX0

ANEX1

OPA0=1

OPA1=1

ADGSEL1 to ADGSEL0=00b

OPA1 to OPA0=11b

=000b

=001b

=010b

=011b

=100b

=101b

=110b

=111b

VREF

VIN

CH2 to CH0

PM00

PM01

Decoder

for channel

selection

Data bus low-order

VCUT

Data bus high-order

OPA1=1

Port P10 group

Port P0 group

ADGSEL1 to ADGSEL0=00b

OPA1 to OPA0=00b

OPA1 to OPA0

=01b

CKS0

1/3

CKS2

1/21/2

φAD

A/D conversion rate selection

Resistor ladder

Successive conversion register

Comparator

Decoder

for A/D register

Port P2 group

TRG

A/D trigger

Software trigger

=000b

=001b

=010b

=011b

=100b

=101b

=110b

=111b

=000b

=001b

=010b

=011b

=100b

=101b

=110b

=111b

CH2 to CH0

AD0 register

AD1 register

AD2 register

AD3 register

AD4 register

AD5 register

AD6 register

AD7 register

ADCON0 register

ADCON1 register

ADCON2 register

VREF

AVSS

fAD

ADTRG

PM01 to PM00=00b

(1)

ADGSEL1 to ADGSEL0=10b

OPA1 to OPA0=00b

PM01 to PM00=00b

ADGSEL1 to ADGSEL0=11b

OPA1 to OPA0=00b

AN0_0

AN0_1

AN0_2

AN0_3

AN0_4

AN0_5

AN0_6

AN0_7

AN2_0

AN2_1

AN2_2

AN2_3

AN2_4

AN2_5

AN2_6

AN2_7

AN0

(1)

PM01 to PM00=00b

ADGSEL1 to ADGSEL0=10b

OPA1 to OPA0=11b

PM01 to PM00=00b

ADGSEL1 to ADGSEL0=11b

OPA1 to OPA0=11b

CKS1

(1)

NOTE:

1. Port P0 group (AN0_0 to AN0_7) can be used as analog input pins even when bits PM01 to PM00 are set to 01b

(memory expansion mode) and bits PM05 to PM04 are set to 11b (multiplex bus allocated to the entire CS space).

Rev.2.40 Apr 14, 2006 page 195 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.2 Registers ADCON0 and ADCON1

CH0

CH1

CH2

MD0

MD1

TRG

ADST

CKS0

SCAN0

SCAN1

MD2

BITS

VCUT

OPA0

OPA1

CKS1

Function varies depending on

operating mode

0 0 : One-shot mode

0 1 : Repeat mode

1 0 : Single sweep mode

1 1 : Repeat sweep mode 0 or

Repeat sweep mode 1

0 : Software trigger

1 : ADTRG trigger

0 : A/D conversion disabled

1 : A/D conversion started

Refer to NOTE 2 for ADCON2

Trigger select bit

A/D conversion start flag

Frequency select bit 0

Analog input pin select bits

A/D operating mode

select bits 0

A/D Control Register 0 (1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function RW

Bit name Function

Bit symbol RW

Symbol Address After Reset

ADCON1 03D7h 00h

0 : 8-bit mode

1 : 10-bit mode

0 : Any mode other than repeat

sweep mode 1

1 : Repeat sweep mode 1

0 : VREF not connected

1 : VREF connected

Refer to NOTE 2 for ADCON2

Function varies depending on

operating mode

A/D sweep pin select bits

8/10-bit mode select bit

VREF connect bit (2)

A/D operating mode

select bit 1

External op-amp

connection mode bits

Frequency select bit 1

Function varies depending on

operating mode

b7 b6 b5 b4 b3 b2 b1 b0

A/D Control Register 1 (1)

Symbol Address After Reset

ADCON0 03D6h 00000XXXb

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.

2. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before

starting A/D conversion.

b4 b3

Rev.2.40 Apr 14, 2006 page 196 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.3 Registers ADCON2, and AD0 to AD7

NOTES:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined.

2. The φAD frequency must be 10 MHz or less. The selected φAD frequency is determined by a combination of the

CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.

b7 b6 b5 b4 b3 b2 b1 b0

0Symbol Address After Reset

ADCON2 03D4h 00h

A/D Control Register 2

(1)

Bit Symbol Bit Name Function RW

SMP

CKS2

ADGSEL0

ADGSEL1

(b3)

(b7-b5)

b2 b1

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

A/D input group select bits

A/D conversion method

select bit

Reserved bit

Frequency select bit 2 (2)

0 : Without sample and hold

1 : With sample and hold

0 0 : Port P10 group is selected

0 1 : Do not set a value

1 0 : Port P0 group is selected

1 1 : Port P2 group is selected

Set to 0

0 : Selects fAD, divide-by-2 of fAD, or

divide-by-4 of fAD.

1 : Selects divide-by-3 of fAD, divide-by-6

of fAD, or divide-by-12 of fAD.

Divide-by-4 of fAD

Divide-by-2 of fAD

fAD

Divide-by-12 of fAD

Divide-by-6 of fAD

Divide-by-3 of fAD

CKS2 CKS1 CKS0 φAD

(b15)

b7b7 b0 b0

(b8)

A/D Register i (i = 0 to 7)

Low-order 8 bits of

A/D conversion result

Function

When BITS bit in ADCON1

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

When read, the content is

undefined.

High-order 2 bits of

A/D conversion result

When BITS bit is 0

(8-bit mode)

A/D conversion result

Symbol Address After Reset

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

03C1h to 03C0h

03C3h to 03C2h

03C5h to 03C4h

03C7h to 03C6h

03C9h to 03C8h

03CBh to 03CAh

03CDh to 03CCh

03CFh to 03CEh

Undefined

Rev.2.40 Apr 14, 2006 page 197 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Item Specification

Function Bits CH2 to CH0 in the ADCON0 register, bits ADGSEL1 to ADGSEL0 in

the ADCON2 register, and bits OPA1 to OPA0 in the ADCON1 register select

a pin Analog voltage applied to the pin is converted to a digital code once.

A/D conversion •When the TRG bit in the ADCON0 register is 0 (software trigger)

start condition The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)

•

_____________

When the TRG bit is 1 (ADTRG trigger)

_____________

Input on the ADTRG pin changes state from high to low after the ADST

bit is set to 1 (A/D conversion starts)

A/D conversion •Completion of A/D conversion (If a software trigger is selected, the ADST

stop condition bit is set to 0 (A/D conversion halted).)

•Set the ADST bit to 0

Interrupt request Completion of A/D conversion

generation timing

Analog input pin Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,

ANEX0 to ANEX1

Reading of result of Read one of registers AD0 to AD7 that corresponds to the selected pin

A/D converter

16.1 Mode Description

16.1.1 One-shot Mode

In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once.

Table 16.2 lists the One-shot Mode Specifications. Figure 16.4 shows Registers ADCON0 and ADCON1 in

One-shot Mode.

Table 16.2 One-shot Mode Specifications

Rev.2.40 Apr 14, 2006 page 198 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.4 Registers ADCON0 and ADCON1 in One-shot Mode

CH0

CH1

CH2

MD0

MD1

TRG

ADST

CKS0

0 0 : One-shot mode (3)

0 : Software trigger

1 : ADTRG trigger

0 : A/D conversion disabled

1 : A/D conversion started

Refer to NOTE 2 for ADCON2

Trigger select bit

A/D conversion start flag

Frequency select bit 0

Analog input pin select bits

A/D operating mode

select bits 0

A/D Control Register 0 (1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function RW

Symbol Address After Reset

ADCON0 03D6h 00000XXXb

b4 b3

0 0 0 : AN0 is selected

0 0 1 : AN1 is selected

0 1 0 : AN2 is selected

0 1 1 : AN3 is selected

1 0 0 : AN4 is selected

1 0 1 : AN5 is selected

1 1 0 : AN6 is selected

1 1 1 : AN7 is selected (2) (3)

b2 b1 b0

SCAN0

SCAN1

MD2

BITS

VCUT

OPA0

OPA1

CKS1

Bit Name Function

Bit Symbol RW

Symbol Address After Reset

ADCON1 03D7h 00h

0 : 8-bit mode

1 : 10-bit mode

Set to 0 when one-shot mode

is selected

1 : VREF connected

Refer to NOTE 2 for ADCON2

Invalid in one-shot modeA/D sweep pin select bits

8/10-bit mode select bit

VREF connect bit (2)

A/D operating mode

select bit 1

External op-amp

connection mode bits

Frequency select bit 1

0 0 :

ANEX0 and ANEX1 are not used

0 1 : ANEX0 input is A/D converted

1 0 : ANEX1 input is A/D converted

1 1 :

External op-amp connection mode

b7 b6 b5 b4 b3 b2 b1 b0

A/D Control Register 1 (1)

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.

2. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before

starting A/D conversion.

b7 b6

NOTES:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.

2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use bits ADGSEL1 to

ADGSEL0 in the ADCON2 register to select the desired pin.

3. After rewriting bits MD1 to MD0, set bits CH2 to CH0 over again using another instruction.

Rev.2.40 Apr 14, 2006 page 199 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

16.1.2 Repeat Mode

In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code.

Table 16.3 lists the Repeat Mode Specifications. Figure 16.5 shows Registers ADCON0 and ADCON1 in

Repeat Mode.

Table 16.3 Repeat Mode Specifications

Item Specification

Function Bits CH2 to CH0 in the ADCON0 register, bits ADGSEL1 to ADGSEL0 in

the ADCON2 register, and bits OPA1 to OPA0 in the ADCON1 register select

a pin. Analog voltage applied to this pin is repeatedly converted to a digital

code.

A/D conversion • When the TRG bit in the ADCON0 register is 0 (software trigger)

start condition The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)

_____________

• When the TRG bit is 1 (ADTRG trigger)

_____________

Input on the ADTRG pin changes state from high to low after the ADST

bit is set to 1 (A/D conversion starts)

A/D conversion Set the ADST bit to 0 (A/D conversion halted)

stop condition

Interrupt request None generated

generation timing

Analog input pin Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,

ANEX0 to ANEX1

Reading of result of Read one of registers AD0 to AD7 that corresponds to the selected pin

A/D converter

Rev.2.40 Apr 14, 2006 page 200 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.5 Registers ADCON0 and ADCON1 in Repeat Mode

CH0

CH1

CH2

MD0

MD1

TRG

ADST

CKS0

SCAN0

SCAN1

MD2

BITS

VCUT

OPA0

OPA1

CKS1

0 1 : Repeat mode

(3)

0 : Software trigger

1 : ADTRG trigger

0 : A/D conversion disabled

1 : A/D conversion started

Refer to NOTE 2 for ADCON2

Trigger select bit

A/D conversion start flag

Frequency select bit 0

Analog input pin select bits

A/D operating mode

select bits 0

A/D Control Register 0

(1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function

Bit Name Function

Bit Symbol

Symbol Address After Reset

ADCON1 03D7h 00h

0 : 8-bit mode

1 : 10-bit mode

Set to 0 when repeat mode is

selected

1 : VREF connected

Refer to NOTE 2 for ADCON2

Invalid in repeat modeA/D sweep pin select bits

8/10-bit mode select bit

VREF connect bit

(2)

A/D operating mode

select bit 1

External op-amp

connection mode bits

Frequency select bit 1

0 0 :

ANEX0 and ANEX1 are not used

0 1 : ANEX0 input is A/D converted

1 0 : ANEX1 input is A/D converted

1 1 :

External op-amp connection mode

b7 b6 b5 b4 b3 b2 b1 b0

A/D Control Register 1

(1)

Symbol After Reset

ADCON0

Address

03D6h 00000XXXb

b4 b3

b7 b6

0 0 0 : AN0 is selected

0 0 1 : AN1 is selected

0 1 0 : AN2 is selected

0 1 1 : AN3 is selected

1 0 0 : AN4 is selected

1 0 1 : AN5 is selected

1 1 0 : AN6 is selected

1 1 1 : AN7 is selected

(2) (3)

b2 b1 b0

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.

2. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before

starting A/D conversion.

NOTES:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.

2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use bits ADGSEL1 to

ADGSEL0 in the ADCON2 register to select the desired pin.

3. After rewriting bits MD1 to MD0, set bits CH2 to CH0 over again using another instruction.

Rev.2.40 Apr 14, 2006 page 201 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

16.1.3 Single Sweep Mode

In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital

code. Table 16.4 lists the Single Sweep Mode Specifications. Figure 16.6 shows Registers ADCON0 and

ADCON1 in Single Sweep Mode.

Table 16.4 Single Sweep Mode Specifications

Item Specification

Function Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to ADGSEL0

in the ADCON2 register select pins. Analog voltage applied to this pins is

converted one-by-one to a digital code.

A/D conversion • When the TRG bit in the ADCON0 register is 0 (software trigger)

start condition The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)

_____________

• When the TRG bit is 1 (ADTRG trigger)

_____________

Input on the ADTRG pin changes state from high to low after the ADST

bit is set to 1 (A/D conversion starts)

A/D conversion • Completion of A/D conversion (If a software trigger is selected, the ADST

stop condition bit is set to 0 (A/D conversion halted).)

• Set the ADST bit to 0

Interrupt request Completion of A/D conversion

generation timing

Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),

AN0 to AN7 (8 pins) (1)

Reading of result of Read one of registers AD0 to AD7 that corresponds to the selected pin

A/D converter

NOTE:

1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.

Rev.2.40 Apr 14, 2006 page 202 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.6 Registers ADCON0 and ADCON1 in Single Sweep Mode

CH0

CH1

CH2

MD0

MD1

TRG

ADST

CKS0

1 0 : Single sweep mode

0 : Software trigger

1 : ADTRG trigger

0 : A/D conversion disabled

1 : A/D conversion started

Refer to NOTE 2 for ADCON2

Trigger select bit

A/D conversion start flag

Frequency select bit 0

Analog input pin select bits

A/D operating mode

select bits 0

A/D Control Register 0

(1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function

Invalid in single sweep mode

Symbol Address After Reset

ADCON0 03D6h 00000XXXb

b4 b3

SCAN0

SCAN1

MD2

BITS

VCUT

OPA0

OPA1

CKS1

Bit Name Function

Bit Symbol

Symbol Address After Reset

ADCON1 03D7h 00h

0 : 8-bit mode

1 : 10-bit mode

Set to 0 when single sweep mode

is selected

1 : VREF connected

Refer to NOTE 2 for ADCON2

When single sweep mode is selected

A/D sweep pin select bits

8/10-bit mode select bit

VREF connect bit

(3)

A/D operating mode

select bit 1

External op-amp

connection mode bits

Frequency select bit 1

0 0 :

ANEX0 and ANEX1 are not used

0 1 : Do not set a value

1 0 : Do not set a value

1 1 :

External op-amp connection mode

b7 b6 b5 b4 b3 b2 b1 b0

A/D Control Register 1

(1)

b7 b6

0 0 : AN0, AN1 (2 pins)

0 1 : AN0 to AN3 (4 pins)

1 0 : AN0 to AN5 (6 pins)

1 1 : AN0 to AN7 (8 pins)

(2)

b1 b0

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.

2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use bits ADGSEL1 to

ADGSEL0 in the ADCON2 register to select the desired pin.

3. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before

starting A/D conversion.

Rev.2.40 Apr 14, 2006 page 203 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

16.1.4 Repeat Sweep Mode 0

In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.

Table 16.5 lists the Repeat Sweep Mode 0 Specifications. Figure 16.7 shows Registers ADCON0 and

ADCON1 in Repeat Sweep Mode 0.

Table 16.5 Repeat Sweep Mode 0 Specifications

Item Specification

Function Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 to ADGSEL0

in the ADCON2 register select pins. Analog voltage applied to the pins is

repeatedly converted to a digital code.

A/D conversion • When the TRG bit in the ADCON0 register is 0 (software trigger)

start condition The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)

_____________

• When the TRG bit is 1 (ADTRG trigger)

_____________

Input on the ADTRG pin changes state from high to low after the ADST

bit is set to 1 (A/D conversion starts)

A/D conversion Set the ADST bit to 0 (A/D conversion halted)

stop condition

Interrupt request None generated

generation timing

Analog input pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),

AN0 to AN7 (8 pins) (1)

Reading of result of Read one of registers AD0 to AD7 that corresponds to the selected pin

A/D converter

NOTE:

1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.

Rev.2.40 Apr 14, 2006 page 204 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.7 Registers ADCON0 and ADCON1 in Repeat Sweep Mode 0

CH0

CH1

CH2

MD0

MD1

TRG

ADST

CKS0

1 1 : Repeat sweep mode 0 or

Repeat sweep mode 1

0 : Software trigger

1 : ADTRG trigger

0 : A/D conversion disabled

1 : A/D conversion started

Refer to NOTE 2 for ADCON2

Trigger select bit

A/D conversion start flag

Frequency select bit 0

Analog input pin select bits

A/D operating mode

select bits 0

A/D Control Register 0

(1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function

Invalid in repeat sweep mode 0

b4 b3

SCAN0

SCAN1

MD2

BITS

VCUT

OPA0

OPA1

CKS1

Bit Name Function

Bit Symbol

0 : 8-bit mode

1 : 10-bit mode

Set to 0 when repeat sweep

mode 0 is selected

1 : VREF connected

Refer to NOTE 2 for ADCON2

When repeat sweep mode 0 is selected

A/D sweep pin select bits

8/10-bit mode select bit

VREF connect bit

(3)

A/D operating mode

select bit 1

External op-amp

connection mode bits

Frequency select bit 1

0 0 :

ANEX0 and ANEX1 are not used

0 1 : Do not set a value

1 0 : Do not set a value

1 1 :

External op-amp connection mode

b7 b6 b5 b4 b3 b2 b1 b0

A/D Control Register 1

(1)

b7 b6

0 0 : AN0, AN1 (2 pins)

0 1 : AN0 to AN3 (4 pins)

1 0 : AN0 to AN5 (6 pins)

1 1 : AN0 to AN7 (8 pins)

(2)

b1 b0

1Symbol Address After Reset

ADCON0 03D6h 00000XXXb

Symbol Address After reset

ADCON1 03D7h 00h

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.

2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use bits ADGSEL1 to

ADGSEL0 in the ADCON2 register to select the desired pin.

3. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before

starting A/D conversion.

Rev.2.40 Apr 14, 2006 page 205 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Item Specification

Function The input voltages on all pins selected by bits ADGSEL1 to ADGSEL0 in

the ADCON2 register are A/D converted repeatedly, with priority given to

pins selected by bits SCAN1 to SCAN0 in the ADCON1 register and bits

ADGSEL1 to ADGSEL0.

Example : If AN0 selected, input voltages are A/D converted in order of

AN0 AN1 AN0 AN2 AN0 AN3, and so on.

A/D conversion • When the TRG bit in the ADCON0 register is 0 (software trigger)

start condition The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)

_____________

• When the TRG bit is 1 (ADTRG trigger)

_____________

Input on the ADTRG pin changes state from high to low after the ADST

bit is set to 1 (A/D conversion starts)

A/D conversion Set the ADST bit to 0 (A/D conversion halted)

stop condition

Interrupt request None generated

generation timing

Analog input pins to be given

Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),

priority when A/D converted

AN0 to AN3 (4 pins) (1)

Reading of result of Read one of registers AD0 to AD7 that corresponds to the selected pin

A/D converter

NOTE:

1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.

16.1.5 Repeat Sweep Mode 1

In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code.

Table 16.6 lists the Repeat Sweep Mode 1 Specifications. Figure 16.8 shows Registers ADCON0 and

ADCON1 in Repeat Sweep Mode 1.

Table 16.6 Repeat Sweep Mode 1 Specifications

Rev.2.40 Apr 14, 2006 page 206 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

Figure 16.8 Registers ADCON0 and ADCON1 in Repeat Sweep Mode 1

CH0

CH1

CH2

MD0

MD1

TRG

ADST

CKS0

1 1 : Repeat sweep mode 0 or

Repeat sweep mode 1

0 : Software trigger

1 : ADTRG trigger

0 : A/D conversion disabled

1 : A/D conversion started

Refer to NOTE 2 for ADCON2

Trigger select bit

A/D conversion start flag

Frequency select bit 0

Analog input pin select bits

A/D operating mode

select bits 0

A/D Control Register 0

(1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function

Invalid in repeat sweep mode 1

b4 b3

11 Symbol Address After Reset

ADCON0 03D6h 00000XXXb

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined.

SCAN0

SCAN1

MD2

BITS

VCUT

OPA0

OPA1

CKS1

Bit Name Function

Bit Symbol

0 : 8-bit mode

1 : 10-bit mode

Set to 1 when repeat sweep

mode 1 is selected

1 : VREF connected

Refer to NOTE 2 for ADCON2

When repeat sweep mode 1 is selected

A/D sweep pin select bits

8/10-bit mode select bit

VREF connect bit

(3)

A/D operating mode

select bit 1

External op-amp

connection mode bits

Frequency select bit 1

0 0 :

ANEX0 and ANEX1 are not used

0 1 : Do not set a value

1 0 : Do not set a value

1 1 :

External op-amp connection mode

b7 b6 b5 b4 b3 b2 b1 b0

A/D Control Register 1

(1)

b7 b6

0 0 : AN0 (1 pin)

0 1 : AN0, AN1 (2 pins)

1 0 : AN0 to AN2 (3 pins)

1 1 : AN0 to AN3 (4 pins)

(2)

b1 b0

11 Symbol Address After Reset

ADCON1 03D7h 00h

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined.

2. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use bits ADGSEL1 to

ADGSEL0 in the ADCON2 register to select the desired pin.

3. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before

starting A/D conversion.

Rev.2.40 Apr 14, 2006 page 207 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

16.2 Function

16.2.1 Resolution Select Function

The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to 1

(10-bit conversion accuracy), the A/D conversion result is stored in the bits 0 to 9 in the ADi register (i = 0

to 7). If the BITS bit is set to 0 (8-bit conversion accuracy), the A/D conversion result is stored in the bits

0 to 7 in the ADi register.

16.2.2 Sample and Hold

If the SMP bit in the ADCON2 register is set to 1 (with sample and hold), the conversion speed per pin is

increased to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. Sample and hold is

effective in all operating modes. Select whether or not to use the sample and hold function before starting

A/D conversion.

16.2.3 Extended Analog Input Pins

In one-shot and repeat modes, pins ANEX0 and ANEX1 can be used as analog input pins. Use bits OPA1

to OPA0 in the ADCON1 register to select whether or not use ANEX0 and ANEX1.

The A/D conversion results of ANEX0 and ANEX1 inputs are stored in registers AD0 and AD1, respectively.

16.2.4 External Operation Amplifier (Op-Amp) Connection Mode

Multiple analog inputs can be amplified using a single external op-amp via pins ANEX0 and ANEX1.

Set bits OPA1 to OPA0 in the ADCON1 register to 11b (external op-amp connection mode). The inputs

from ANi (i = 0 to 7) (1) are output from the ANEX0 pin. Amplify this output with an external op-amp before

sending it back to the ANEX1 pin. The A/D conversion result is stored in the corresponding ADi register.

The A/D conversion speed depends on the response characteristics of the external op-amp.

Figure 16.9 shows an External Op-Amp Connection.

NOTE:

1. AN0_i and AN2_i can be used the same as ANi.

Bits ADGSEL1 to ADGSEL0 in ADCON2 register = 00b

Successive conversion

Comparator

External op-amp

ANEX0

ANEX1

Bits ADGSEL1 to ADGSEL0 = 10b

Bits ADGSEL1 to ADGSEL0 = 11b

Resistor ladder

MCU

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN0_0

AN0_1

AN0_2

AN0_3

AN0_4

AN0_5

AN0_6

AN0_7

AN2_0

AN2_1

AN2_2

AN2_3

AN2_4

AN2_5

AN2_6

AN2_7

Figure 16.9 External Op-Amp Connection

Rev.2.40 Apr 14, 2006 page 208 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

16.2.5 Current Consumption Reducing Function

When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be

separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the

VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.

To use the A/D converter, set the VCUT bit to 1 (VREF connected) and then set the ADST bit in the

ADCON0 register to 1 (A/D conversion start). The VCUT and ADST bits cannot be set to 1 at the same time.

Nor can the VCUT bit be set to 0 (VREF unconnected) during A/D conversion.

Note that this does not affect VREF for the D/A converter (irrelevant).

16.2.6 Output Impedance of Sensor under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 16.10 has to be

completed within a specified period of time. T (sampling time) as the specified time. Let output impedance

of sensor equivalent circuit be R0, internal resistance of MCU be R, precision (error) of the A/D converter

be X, and the resolution of A/D converter be Y (Y is 1024 in 10-bit mode, and 256 in 8-bit mode).

VC is generally VC = VIN {1 – e}

And when t = T, VC=VIN – VIN = VIN(1 – )

e =

– T = ln

Hence, R0 = –– R

Figure 16.10 shows the Analog Input Pin and External Sensor Equivalent Circuit.

When the difference between VIN and VC becomes 0.1 LSB, we find impedance R0 when voltage

between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision

drop due to insufficient capacitor charge is held to 0.1 LSB at time of A/D conversion in 10-bit mode.

Actual error however is the value of absolute precision added to 0.1 LSB.

When f(φAD) = 10 MHz, T = 0.3 µs in the A/D conversion mode with sample & hold. Output impedance R0

for sufficiently charging capacitor C within time T is determined as follows.

T = 0.3 µs, R = 7.8 kΩ, C = 1.5 pF, X = 0.1, and Y = 1024. Hence,

R0 = ––7.8 ✕103 = 13.9 ✕ 103

Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1

LSB or less, is approximately 13.9 kΩ. maximum.

C (R0 + R)

C • ln

1.5 ✕ 10 –12 • ln 1024

0.1

0.3 ✕ 10-6

C (R0 + R)

–t

C (R0 + R)

–

Rev.2.40 Apr 14, 2006 page 209 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 16. A/D Converter

R0 R (7.8 kΩ)

C (1.5 pF)

VIN

MCU

Sensor equivalent

circuit

Sampling time

Sample and hold enabled:

Sample and hold disabled:

φAD

Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit

Rev.2.40 Apr 14, 2006 page 210 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 17. D/A Converter

17. D/A Converter

This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters.

D/A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the

DAiE bit in the DACON register to 1 (output enabled). Before D/A conversion can be used, the corresponding

port direction bit is set to 0 (input mode). Setting the DAiE bit to 1 removes a pull-up from the corresponding

port.

Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register.

V = VREF ✕ n/ 256 (n = 0 to 255)

VREF : reference voltage

Table 17.1 lists the D/A converter Performance. Figure 17.1 shows the D/A Converter Block Diagram.

Figure 17.2 shows the D/A converter-related registers. Figure 17.3 shows the D/A Converter Equivalent

Circuit.

Item Performance

D/A conversion method R-2R method

Resolution 8 bits

Analog output pin 2 channels (DA0 and DA1)

Table 17.1 D/A Converter Performance

DA0E bit

Data bus low-order

DA1E bit

DA0 register

R-2R resistor ladder

DA1 register

R-2R resistor ladder

DA0

DA1

Figure 17.1 D/A Converter Block Diagram

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 17. D/A Converter

Figure 17.2 Registers DACON, DA0, and DA1

Figure 17.3 D/A Converter Equivalent Circuit

D/A Control Register (1)

Symbol Address After Reset

DACON 03DCh

03D8h

03DAh

00h

b7 b6 b5 b4 b3 b2 b1 b0

D/A0 output enable bit

Bit Symbol Bit Name Function RW

D/A1 output enable bit

DA0

DA1

00h

b7 b0

Function

Output value of D/A conversion

DA0E

DA1E

(b7-b2)

0 : Output disabled

1 : Output enabled

0 : Output disabled

1 : Output enabled

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

NOTE:

1. When not using the D/A converter, set the DAiE bit (i = 0, 1) to 0 (output disabled) to reduce the unnecessary

current consumption in the chip and set the DAi register to 00h to prevent current from flowing into the R-2R

resistor.

NOTE:

1. When not using the D/A converter, set the DAiE bit (i = 0, 1) to 0 (output disabled) to reduce the unnecessary

current consumption in the chip and set the DAi register to 00h to prevent current from flowing into the R-2R

resistor.

D/A Register i (i = 0, 1) (1)

00h to FFh

Setting Range

DAiE bit

MSB LSB

DAi register

i = 0, 1

NOTES:

1. The above diagram shows an instance in which the DAi register is assigned 2Ah.

2. VREF is not related to VCUT bit setting in the ADCON1 register.

VREF

(2)

AVSS

DAi

Rev.2.40 Apr 14, 2006 page 212 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 18. CRC Calculation

18. CRC Calculation

The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The MCU uses a generator

polynomial of CRC-CCITT (X16 + X12 + X5 + 1) to generate CRC code.

The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit

unit. After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte

of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles.

Figure 18.1 shows the CRC Circuit Block Diagram. Figure 18.2 shows the CRC-related registers. Figure

18.3 shows the calculation example using the CRC operation.

Figure 18.2 Registers CRCD and CRCIN

Figure 18.1 CRC Circuit Block Diagram

When data is written to the CRCIN register after setting

the initial value in the CRCD register, the CRC code can

be read out from the CRCD register.

0000h to FFFFh

Function Setting Range

CRCD

Symbol After Reset

Undefined

03BDh to 03BCh

Address

b7 b0 b7 b0

(b15) (b8)

CRC Data Register

Data input 00h to FFh

Function Setting Range

CRCIN

Symbol After Reset

Undefined

03BEh

Address

b7 b0

CRC Input Register

High-order 8 bitsLow-order 8 bits

CRCIN register

Data bus high-order

Data bus low-order

CRCD register

CRC code generation circuit

Rev.2.40 Apr 14, 2006 page 213 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 18. CRC Calculation

Figure 18.3 CRC Calculation

b15

1189h

b15

0A41h

CRCD register

CRCIN register

Two cycles later, the CRC code for "80h," i.e.,

9188h, has its bit positions reversed to become

"1189h" which is stored in the CRCD register.

CRCD register

CRCIN register

Two cycles later, the CRC code for "80C4h," i.e.,

8250h, has its bit positions reversed to become

"0A41h" which is stored in the CRCD register.

CRCD register

Setup procedure and CRC operation when generating CRC code "80C4h"

CRC operation performed by the M16C

CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is

divided by the generator polynomial

Generator polynomial: X6 +X12 +X5+1(1 0001 0000 0010 0001b)

Setting procedure

(1) Reverse the bit positions of the value "80C4h" by program in 1-byte unit.

"80h" → "01h", "C4h" → "23h"

(2) Write 0000h (initial value)

(3) Write 01h

(4) Write 23h

Details of CRC operation

As shown in (3) above, bit position of "01h" (00000001b) written to the CRCIN register is inversed and becomes "10000000b".

Add "1000 0000 0000 0000 0000 0000b", as "10000000b" plus 16 digits, to "0000 0000 0000 0000 0000 0000b", as

"0000 0000 0000 0000b" plus 8 digits as the default value of the CRCD register to perform the modulo-2 division.

"0001 0001 1000 1001b (1189h)", the remainder "1001 0001 1000 1000b (9188h)" with inversed bit position, can be read

from the CRCD register.

When going on to (4) above, "23h (00100011b)" written in the CRCIN register is inversed and becomes "11000100b".

Add "1100 0100 0000 0000 0000 0000b", as "11000100b" plus 16 digits, to "1001 0001 1000 1000 0000 0000b", as

"1001 0001 1000 1000b" plus 8 digits as a remainder of (3) left in the CRCD register to perform the modulo-2 division.

"0000 1010 0100 0001b (0A41h)", the remainder with inversed bit position, can be read from CRCD register.

1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000

1000 1000 0001 0000 1

1000 0001 0000 1000 0

1000 1000 0001 0000 1

1001 0001 1000 1000

1000 1000 Modulo-2 operation is

operation that complies

with the law given below.

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0

-1 = 1

Generator polynomial

CRC code

Data

Rev.2.40 Apr 14, 2006 page 214 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19. CAN Module

The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6N4) of MCUs is a communication

controller implementing the CAN 2.0B protocol. The M16C/6N Group (M16C/6N4) contains two CAN modules

which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats.

Figure 19.1 shows the CAN Module Block Diagram.

External CAN bus driver and receiver are required.

Figure 19.1 CAN Module Block Diagram

CTX/CRX: CAN I/O pins.

Protocol controller: This controller handles the bus arbitration and the CAN protocol services, i.e. bit

timing, stuffing, error status etc.

Message box: This memory block consists of 16 slots that can be configured either as transmitter

or receiver. Each slot contains an individual ID, data length code, a data field

(8 bytes), and a time stamp.

Acceptance filter: This block performs filtering operation for received messages. For the filtering

operation, the CiGMR register (i = 0, 1), the CiLMAR register, or the CiLMBR

16 bit timer: Used for the time stamp function. When the received message is stored in the

message memory, the timer value is stored as a time stamp.

Wake-up function: CAN0/1 wake-up interrupt request is generated by a message from the CAN bus.

Interrupt generation function

: The interrupt requests are generated by the CAN module. CANi successful reception

interrupt, CANi successful transmission interrupt, CAN0/1 error interrupt, and

CAN0/1 wake-up interrupt.

CiCONR register CiCTLR register

i = 0, 1

j = 0 to 15

Interrupt

generation

function

Message box

slots 0 to 15

Message ID

DLC

Message data

Time stamp

CTX

CRX

CiGMR register

CiLMAR register

CiLMBR register

CAN0/1 error int

CAN0/1 wake-up int

Data bus

CiMCTLj register

CiTSR register

16 bit timer

Acceptance filter

slots 0 to 15

Protocol

controller

Wake-up

function

CiSSTR register CiICR register

CiSTR register

CiRECR register

CiTECR register

CANi successful reception int

CANi successful transmission int

CiIDR register

Rev.2.40 Apr 14, 2006 page 215 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.1 CAN Module-Related Registers

The CANi (i = 0, 1) module has the following registers.

19.1.1 CANi Message Box (i = 0, 1)

A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as

Basic CAN.

•Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and

reception.

•A program can define whether a slot is defined as transmitter or receiver.

19.1.2 Acceptance Mask Registers

A CAN module is equipped with 3 masks for the acceptance filter.

•CANi global mask register (i = 0, 1) (CiGMR register: 6 bytes)

Configuration of the masking condition for acceptance filtering processing to slots 0 to 13

• CANi local mask A register (CiLMAR register: 6 bytes)

Configuration of the masking condition for acceptance filtering processing to slot 14

•CANi local mask B register (CiLMBR register: 6 bytes)

Configuration of the masking condition for acceptance filtering processing to slot 15

19.1.3 CAN SFR Registers

• CANi message control register j (i = 0, 1, j = 0 to 15) (CiMCTLj register: 8 bits ✕ 16)

Control of transmission and reception of a corresponding slot

• CANi control register (CiCTLR register: 16 bits)

Control of the CAN protocol

• CANi status register (CiSTR register: 16 bits)

Indication of the protocol status

• CANi slot status register (CiSSTR register: 16 bits)

Indication of the status of contents of each slot

• CANi interrupt control register (CiICR register: 16 bits)

Selection of “interrupt enabled or disabled” for each slot

• CANi extended ID register (CiIDR register: 16 bits)

Selection of ID format (standard or extended) for each slot

• CANi configuration register (CiCONR register: 16 bits)

Configuration of the bus timing

• CANi receive error count register (CiRECR register: 8 bits)

Indication of the error status of the CAN module in reception: the counter value is incremented or

decremented according to the error occurrence.

• CANi transmit error count register (CiTECR register: 8 bits)

Indication of the error status of the CAN module in transmission: the counter value is incremented or

decremented according to the error occurrence.

• CANi time stamp register (CiTSR register: 16 bits)

Indication of the value of the time stamp counter

• CANi acceptance filter support register (CiAFS register: 16 bits)

Decoding the received ID for use by the acceptance filter support unit

Explanation of each register is given below.

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.2 CANi Message Box (i = 0, 1)

Table 19.1 shows the CANi Message Box Memory Mapping.

It is possible to access to the message box in byte or word.

Mapping of the message contents differs from byte access to word access. Byte access or word access can

be selected by the MsgOrder bit in the CiCTLR register.

Table 19.1 CANi Message Box Memory Mapping

i = 0, 1

n = 0 to 15: the number of the slot

Address Message Content (Memory Mapping)

CAN0 CAN1 Byte Access (8 bits) Word Access (16 bits)

0060h + n ✕ 16 + 0 0260h + n ✕ 16 + 0 SID10 to SID6 SID5 to SID0

0060h + n ✕ 16 + 1 0260h + n ✕ 16 + 1 SID5 to SID0 SID10 to SID6

0060h + n ✕ 16 + 2 0260h + n ✕ 16 + 2 EID17 to EID14 EID13 to EID6

0060h + n ✕ 16 + 3 0260h + n ✕ 16 + 3 EID13 to EID6 EID17 to EID14

0060h + n ✕ 16 + 4 0260h + n ✕ 16 + 4 EID5 to EID0 Data length code (DLC)

0060h + n ✕ 16 + 5 0260h + n ✕ 16 + 5 Data length code (DLC) EID5 to EID0

0060h + n ✕ 16 + 6 0260h + n ✕ 16 + 6 Data byte 0 Data byte 1

0060h + n ✕ 16 + 7 0260h + n ✕ 16 + 7 Data byte 1 Data byte 0

•• • •

0060h + n ✕ 16 + 13 0260h + n ✕ 16 + 13 Data byte 7 Data byte 6

0060h + n ✕ 16 + 14 0260h + n ✕ 16 + 14 Time stamp high-order byte Time stamp low-order byte

0060h + n ✕ 16 + 15 0260h + n ✕ 16 + 15 Time stamp low-order byte Time stamp high-order byte

Rev.2.40 Apr 14, 2006 page 217 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figures 19.2 and 19.3 show the Bit Mapping in Byte Access and Word Access. The content of each slot

remains unchanged unless transmission or reception of a new message is performed.

Figure 19.2 Bit Mapping in Byte Access

Figure 19.3 Bit Mapping in Word Access

NOTE:

1. When is read, the value is the one written upon the transmission slot configuration.

The value is 0 when read on the reception slot configuration.

SID10 SID9 SID8 SID7 SID6

SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14

EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

DLC3 DLC2 DLC1 DLC0

CAN data frame:

SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data byte 0 Data byte 1 Data byte 7

Data byte 0

Data byte 1

Data byte 7

Time stamp high-order byte

Time stamp low-order byte

b7 b0

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0 DLC3 DLC2 DLC1 DLC0

CAN data frame:

SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0

Data byte 0 Data byte 1 Data byte 7

Data byte 0

Time stamp high-order byte

Data byte 2

Data byte 4

Data byte 6

Data byte 1

Time stamp low-order byte

Data byte 3

Data byte 5

Data byte 7

b15 b0b8 b7

NOTE:

1. When is read, the value is the one written upon the transmission slot configuration.

The value is 0 when read on the reception slot configuration.

Rev.2.40 Apr 14, 2006 page 218 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.4 Mask Registers Bit Mapping in Byte Access

19.3 Acceptance Mask Registers

Figures 19.4 and 19.5 show the Mask registers Bit Mapping (registers CiGMR (i = 0, 1), CiLMAR, and

CiLMBR) in Byte Access and Word Access.

Figure 19.5 Mask Registers Bit Mapping in Word Access

i = 0, 1

NOTES:

1. is undefined.

2. These registers can be written in CAN reset/initialization mode of the CAN module.

SID10 SID9 SID8 SID7 SID6

SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14

EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

SID10 SID9 SID8 SID7 SID6

SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14

EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

SID10 SID9 SID8 SID7 SID6

SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14

EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

0160h

0161h

0162h

0163h

0164h

0166h

0167h

0168h

0169h

016Ah

016Ch

016Dh

016Eh

016Fh

0170h

Addresses

CAN0

CiGMR register

CiLMAR register

CiLMBR register

0360h

0361h

0362h

0363h

0364h

0366h

0367h

0368h

0369h

036Ah

036Ch

036Dh

036Eh

036Fh

0370h

CAN1

b7 b0

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6

EID5 EID4 EID3 EID2 EID1 EID0

0160h

0162h

0164h

0166h

0168h

016Ah

016Ch

016Eh

0170h

Addresses

CAN0

CiGMR register

CiLMAR register

CiLMBR register

0360h

0362h

0364h

0366h

0368h

036Ah

036Ch

036Eh

0370h

CAN1

b15 b0

i = 0, 1

NOTES:

1. is undefined.

2. These registers can be written in CAN reset/initialization mode of the CAN module.

Rev.2.40 Apr 14, 2006 page 219 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.4 CAN SFR Registers

Figures 19.6 to 19.11 show the CAN SFR registers.

Figure 19.6 Registers C0MCTLj and C1MCTLj

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function RW

RO (1)

NewData Successful

reception flag

SentData Successful

transmission flag

When set to reception slot

0: The content of the slot is read or still under

processing by the CPU.

1 The CAN module has stored new data in the slot.

When set to reception slot

0: The message is valid.

1: The message is invalid.

(The message is being updated.)

When set to reception slot

0: No message has been overwritten in this slot.

1: This slot already contained a message, but it has

been overwritten by a new one.

When set to transmission slot

0: Transmission is not started or completed yet.

1: Transmission is successfully completed.

When set to transmission slot

0: Waiting for bus idle or completion of arbitration.

1: Transmitting

InvalData

TrmActive

"Under reception"

flag

"Under

transmission"

flag

MsgLost Overwrite flag

Remote frame

transmission/

reception status

flag (2)

0: Data frame transmission/reception status

1: Remote frame transmission/reception status

RemActive

RspLock

Auto response

lock mode

select bit

Remote frame

corresponding

slot select bit

When set to reception remote frame slot

0: After a remote frame is received, it will be

answered automatically.

1: After a remote frame is received, no transmission

will be started as long as this bit is set to 1.

(Not responding)

0: Slot not corresponding to remote frame

1: Slot corresponding to remote frame

Remote

0: Not reception slot

1: Reception slot

RecReq Reception slot

request bit (3)

0: Not transmission slot

1: Transmission slot

TrmReq Transmission

slot request bit (3)

NOTES:

1. As for write, only writing 0 is possible. The value of each bit is written when the CAN module enters the respective state.

2. In Basic CAN mode, slots 14 and 15 serve as data format identification flag.

The RemActive bit is set to 0 if the data frame is received and it is set to 1 if the remote frame is received.

3. One slot cannot be defined as reception slot and transmission slot at the same time.

4. This register cannot be set in CAN reset/initialization mode of the CAN module.

CANi Message Control Register j (i = 0, 1) ( j = 0 to 15) (4)

Symbol

C0MCTL0 to C0MCTL15

C1MCTL0 to C1MCTL15

0200h to 020Fh

0220h to 022Fh

00h

After Reset

Address

Rev.2.40 Apr 14, 2006 page 220 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.7 Registers C0CTLR and C1CTLR

FunctionBit Symbol

Reset CAN module

reset bit

(1)

Loop back mode

LoopBack select bit

(2)

Message order

MsgOrder

BasicCAN

Basic CAN mode

select bit

(2)

select bit

(2)

BusErrEn

Bus error interrupt

enable bit

(2)

Sleep

Sleep mode

select bit

(2) (3)

CAN port enable

bit

(2) (3)

PortEn

(b7)

CANi Control Register (i = 0, 1)

Symbol Address After Reset

C0CTLR

C1CTLR

X0000001b

0210h

0230h

Symbol Address After Reset

C0CTLR

C1CTLR

XX0X0000b

0211h

0231h

b7 b6 b5 b4 b3 b2 b1 b0

NOTES:

1. When the Reset bit is set to 1 (CAN reset/initialization mode), check that the State_Reset bit in the CiSTR register is set to 1

(reset mode).

2. Change this bit only in CAN reset/initialization mode.

3. When using CAN0/1 wake-up interrupt, set these bits to 1.

4. When the PortEn bit is set to 1 (CTX/CRX function), set the corresponding port direction bit for the CRXi pin to 0 (input mode).

0: Operation mode

1: Reset/initialization mode

0: Word access

1: Byte access

0: Basic CAN mode disabled

1: Basic CAN mode enabled

0: Loop back mode disabled

1: Loop back mode enabled

0: Bus error interrupt disabled

1: Bus error interrupt enabled

0: Sleep mode disabled

1: Sleep mode enabled; clock supply stopped

0: I/O port function

1: CTX/CRX function

(4)

(b15) (b8)

b7 b6 b5 b4 b3 b2 b1 b0

TSPreScale

TSReset

RXOnly

RetBusOff

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

b1 b0

NOTES:

1. When the TSReset bit = 1, the CiTSR register is set to 0000h. After this, the bit is automatically set to 0.

2. When the RetBusOff bit = 1, registers CiRECR and CiTECR are set to 00h. After this, this bit is automatically set to 0.

3. Change this bit only in CAN reset/initialization mode.

4. When Listen-only mode is selected, do not request the transmission.

0 0: Period of 1 bit time

0 1: Period of 1/2 bit time

1 0: Period of 1/4 bit time

1 1: Period of 1/8 bit time

0: Nothing is occurred.

1: Force reset of the time stamp counter

0: Listen-only mode disabled

1: Listen-only mode enabled

(4)

0: Nothing is occurred.

1: Force return from bus off

Time stamp

prescaler

(3)

Time stamp counter

reset bit

(1)

Return from bus off

command bit

(2)

Listen-only mode

select bit

(3)

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

(b4)

(b7-b6)

Bit Name

FunctionBit Symbol Bit Name

Rev.2.40 Apr 14, 2006 page 221 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.8 Registers C0STR and C1STR

(b15) (b8)

b7 b6 b5 b4 b3 b2 b1 b0

Reset state flag

Loop back

state flag

Message order

state flag

Basic CAN mode

state flag

Bus error

state flag

Error passive

state flag

Error bus off

state flag

0: Operation mode

1: Reset mode

0:Word access

1: Byte access

0: Not Basic CAN mode

1: Basic CAN mode

0: No error has occurred.

1: A CAN bus error has occurred.

0: Not Loop back mode

1: Loop back mode

0: CAN module is not in error passive state.

1: CAN module is in error passive state.

0: CAN module is not in error bus off state.

1: CAN module is in error bus off state.

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

CANi Status Register (i = 0, 1)

NOTE:

1. These bits can be changed only when a slot which an interrupt is enabled by the CiICR register is transmitted or received

successfully.

b7 b6 b5 b4 b3 b2 b1 b0

Active slot bits (1)

b3 b2 b1 b0

Successful

reception flag (1)

Transmission flag

(transmitter)

Reception flag

(receiver)

0 0 0 0 : Slot 0

0 0 0 1 : Slot 1

0 0 1 0 : Slot 2

1 1 1 0 : Slot 14

1 1 1 1 : Slot 15

0: No [successful] reception

1: CAN module received a message successfully.

0: CAN module is idle or receiver.

1: CAN module is transmitter.

0: CAN module is idle or transmitter.

1: CAN module is receiver.

Successful

transmission

flag (1)

0: No [successful] transmission

1: The CAN module has transmitted a message

successfully.

State_Reset

State_

LoopBack

State_

MsgOrder

State_

BasicCAN

State_

BusError

State_

ErrPass

State_

BusOff

(b7)

MBOX

TrmSucc

RecSucc

TrmState

RecState

C0STR

C1STR

00h

0212h

0232h

Symbol Address After Reset

C0STR

C1STR

X0000001b

0213h

0233h

Symbol Address After Reset

RWFunctionBit Symbol Bit Name

Rev.2.40 Apr 14, 2006 page 222 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.9 Registers C0SSTR, C1SSTR, C0ICR, C1ICR, C0IDR, and C1IDR

(b15) (b8)

b7 b0 b7 b0

Function

Slot status bits

Each bit corresponds to the slot with the

same number.

0: Reception slot

The message has been read.

Transmission slot

Transmission is not completed.

1: Reception slot

The message has not been read.

Transmission slot

Transmission is completed.

CANi Slot Status Register (i = 0, 1)

Setting Values

C0SSTR

C1SSTR

0000h

0215h, 0214h

0235h, 0234h

Symbol Address After Reset

NOTE:

1. This register cannot be set in CAN reset/initialization mode of the CAN module.

(b15) (b8)

b7 b0 b7 b0

Function

Interrupt enable bits:

Each bit corresponds with a slot with the same

number.

Enabled/disabled of successful transmission

interrupt or successful reception interrupt can

be selected.

0: Interrupt disabled

1: Interrupt enabled

CANi Interrupt Control Register (i = 0, 1)

(1)

Setting Values

C0ICR

C1ICR

0000h

0217h, 0216h

0237h, 0236h

Symbol Address After Reset

NOTE:

1. This register cannot be set in CAN reset/initialization mode of the CAN module.

(b15) (b8)

b7 b0 b7 b0

Function

Extended ID bits:

Each bit corresponds with a slot with the same

number.

Selection of the ID format that each slot handles.

0: Standard ID

1: Extended ID

CANi Extended ID Register (i = 0, 1)

(1)

Setting Values

C0IDR

C1IDR

0000h

0219h, 0218h

0239h, 0238h

Symbol Address After Reset

Rev.2.40 Apr 14, 2006 page 223 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.10 Registers C0CONR and C1CONR

b7 b6 b5 b4 b3 b2 b1 b0

0 : One time sampling

1 : Three times sampling

0 0 0 0 : Divide-by-1 of fCAN

0 0 0 1 : Divide-by-2 of fCAN

0 0 1 0 : Divide-by-3 of fCAN

1 1 1 0 : Divide-by-15 of fCAN

1 1 1 1 : Divide-by-16 of fCAN

(1)

.....

0 0 0 : 1Tq

0 0 1 : 2Tq

0 1 0 : 2Tq

1 1 0 : 7Tq

1 1 1 : 8Tq

(b15) (b8)

b7 b6 b5 b4 b3 b2 b1 b0

Phase buffer

segment 1

control bits

Phase buffer

segment 2

control bits

Resynchronization

jump width

control bits

.....

CANi Configuration Register (i = 0, 1)

b3 b2 b1 b0

b7 b6 b5

b2 b1b0

b5 b4 b3

b7 b6

NOTE:

1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bit (i = 0 to 2, 4 to 6) in the CCLKR register.

Sampling control

bit

Prescaler division

ratio select bits

Propagation time

segment control

bits

..... .....

0 0 0 : Do not set a value

0 0 1 : 2Tq

0 1 0 : 3Tq

1 1 0 : 7Tq

1 1 1 : 8Tq

0 0 0 : Do not set a value

0 0 1 : 2Tq

0 1 0 : 3Tq

1 1 0 : 7Tq

1 1 1 : 8Tq

0 0 : 1Tq

0 1 : 2Tq

1 0 : 3Tq

1 1 : 4Tq

BRP

SAM

PTS

PBS1

PBS2

SJW

C0CONR

C1CONR

Undefined

021Ah

023Ah

Symbol Address After Reset

C0CONR

C1CONR

Undefined

021Bh

023Bh

Symbol Address After Reset

RWFunctionBit Symbol Bit Name

FunctionBit Symbol Bit Name

Rev.2.40 Apr 14, 2006 page 224 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.11 Registers C0RECR, C1RECR, C0TECR, C1TECR, C0TSR, C1TSR, C0AFS, and C1AFS

Reception error counting function

The value is incremented or decremented

according to the CAN module's error status.

00h to FFh (1)

CANi Receive Error Count Register (i = 0, 1)

b7 b0

Function Counter Value

NOTE:

1. The value is undefined in bus off state.

C0RECR

C1RECR

00h

021Ch

023Ch

Symbol Address After Reset

Transmission error counting function

The value is incremented or decremented

according to the CAN module's error status.

00h to FFh (1)

CANi Transmit Error Count Register (i = 0, 1)

b7 b0

Function Counter Value RW

C0TECR

C1TECR

00h

021Dh

023Dh

Symbol Address After Reset

NOTE:

1. The value is undefined in bus off state.

Time stamp function 0000h to FFFFh

Function Counter Value RW

C0TSR

C1TSR

0000h

021Fh, 021Eh

023Fh, 023Eh

Symbol Address After Reset

(b15) (b8)

b7 b0 b7 b0

CANi Time Stamp Register (i = 0, 1)

(1)

NOTE:

1. Use a 16-bit data for read.

(b15)

(b8)

b0 b7 b0

CANi Acceptance Filter Support Register (i = 0, 1)

Write the content equivalent to the standard frame

ID of the received message.

The value is "converted standard frame ID" when

read.

Standard frame ID

Function Setting Values RW

C0AFS

C1AFS

Undefined

0243h, 0242h

0245h, 0244h

Symbol Address After Reset

Rev.2.40 Apr 14, 2006 page 225 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.5 Operational Modes

The CAN module has the following four operational modes.

• CAN reset/Initialization mode

• CAN operation mode

• CAN sleep mode

• CAN interface sleep mode

Figure 19.12 shows the Transition between Operational Modes.

Figure 19.12 Transition between Operational Modes

19.5.1 CAN Reset/Initialization Mode

CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit in the CiCTLR

to 1.

Entering CAN reset/initialization mode initiates the following functions by the module:

•CAN communication is impossible.

•When CAN reset/initialization mode is activated during an ongoing transmission in operation mode,

the module suspends the mode transition until completion of the transmission (successful, arbitration

loss, or error detection). Then, the State_Reset bit is set to 1, and CAN reset/initialization mode is

activated.

• Registers CiMCTLj (j = 0 to 15), CiSTR, CiICR, CiIDR, CiRECR, CiTECR, and CiTSR are initialized.

All these registers are locked to prevent CPU modification.

•Registers CiCTLR, CiCONR, CiGMR, CiLMAR, and CiLMBR, and the CANi message box retain their

contents and are available for CPU access.

MCU Reset

CAN reset/initialization

mode

State_Reset = 1

CAN operation mode

State_Reset = 0

CAN sleep mode

CAN interface

sleep mode Bus off state

State_BusOff = 1

Reset = 0

Sleep = 1Sleep = 0 TEC > 255

Reset = 1

CCLK3, CCLK7: Bits in CCLKR register

Reset, Sleep, RetBusOff: Bits in CiCTLR register ( i = 0, 1)

State_Reset, State_BusOff: Bits in CiSTR register

CCLK3 = 1 or

CCLK7 = 1

CCLK3 = 0 or

CCLK7 = 0

when 11 consecutive

recessive bits are

detected 128 times

RetBusOff = 1

Rev.2.40 Apr 14, 2006 page 226 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.5.2 CAN Operation Mode

CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to 0. If the Reset

bit is set to 0, check that the State_Reset bit in the CiSTR register is set to 0.

If 11 consecutive recessive bits are detected after entering CAN operation mode, the module initiates the

following functions:

•The module's communication functions are released and it becomes an active node on the network

and may transmit and receive CAN messages.

•Release the internal fault confinement logic including receive and transmit error counters. The module

may leave CAN operation mode depending on the error counts.

Within CAN operation mode, the module may be in three different sub modes, depending on which type

of communication functions are performed:

•Module idle : The modules receive and transmit sections are inactive.

•Module receives : The module receives a CAN message sent by another node.

•Module transmits : The module transmits a CAN message. The module may receive its own message

simultaneously when the LoopBack bit in the CiCTLR register = 1 (Loop back mode

enabled).

Figure 19.13 shows the Sub Modes of CAN Operation Mode.

Figure 19.13 Sub Modes of CAN Operation Mode

19.5.3 CAN Sleep Mode

CAN sleep mode is activated by setting the Sleep bit to 1 in the CiCTLR register. It should never be

activated from CAN operation mode but only via CAN reset/initialization mode.

Entering CAN sleep mode instantly stops the clock supply to the module and thereby reduces power

dissipation.

19.5.4 CAN Interface Sleep Mode

CAN interface sleep mode is activated by setting the CCLK3 or CCLK7 bit in the CCLKR register to 1. It

should never be activated but only via CAN sleep mode.

Entering CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module and

thereby reduces power dissipation.

Finish

reception

Module idle

TrmState = 0

RecState = 0

TrmState = 1

RecState = 0

Finish

transmission

Detect

an SOF

Start

transmission

Lost in arbitration

Module transmits

TrmState = 0

RecState = 1

Module receives

TrmState, RecState: Bits in CiSTR register (i = 0, 1)

Rev.2.40 Apr 14, 2006 page 227 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.5.5 Bus Off State

The bus off state is entered according to the fault confinement rules of the CAN specification. When

returning to CAN operation mode from the bus off state, the module has the following two cases.

In this time, the value of any CAN registers, except registers CiSTR, CiRECR, and CiTECR, does not

change.

(1) When 11 consecutive recessive bits are detected 128 times

The module enters instantly into error active state and the CAN communication becomes possible

immediately.

(2) When the RetBusOff bit in the CiCTLR register = 1 (Force return from buss off)

The module enters instantly into error active state, and the CAN communication becomes possible

again after 11 consecutive recessive bits are detected.

Rev.2.40 Apr 14, 2006 page 228 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.6 CAN Module System Clock Configuration

The M16C/6N Group (M16C/6N4) has a CAN module system clock select circuit.

Configuration of the CAN module system clock can be done through manipulating the CCLKR register and

the BRP bit in the CiCONR register (i = 0, 1).

For the CCLKR register, refer to 8. Clock Generation Circuit.

Figure 19.14 shows the CAN Module System Clock Generation Circuit Block Diagram.

Figure 19.14 CAN Module System Clock Generation Circuit Block Diagram

19.7 Bit Timing Configuration

The bit time consists of the following four segments:

• Synchronization segment (SS)

This serves for monitoring a falling edge for synchronization.

• Propagation time segment (PTS)

This segment absorbs physical delay on the CAN network which amounts to double the total sum of

delay on the CAN bus, the input comparator delay, and the output driver delay.

• Phase buffer segment 1 (PBS1)

This serves for compensating the phase error. When the falling edge of the bit falls later than expected,

the segment can become longer by the maximum of the value defined in SJW.

• Phase buffer segment 2 (PBS2)

This segment has the same function as the phase buffer segment 1. When the falling edge of the bit

falls earlier than expected, the segment can become shorter by the maximum of the value defined in SJW.

Figure 19.15 shows the Bit Timing.

Figure 19.15 Bit Timing

1/2

Divide-by-1 (undivided)

Divide-by-2

Divide-by-4

Divide-by-8

Divide-by-16

Prescaler

Baud rate

prescaler

division value

: P + 1

fCAN

fCANCLK

fCAN : CAN module system clock

P : The value written in the BRP bit in the CiCONR register ( i = 0, 1). P = 0 to 15

fCANCLK : CAN communication clock fCANCLK = fCAN/2(P + 1)

CAN module

system clock

divider

CCLKR register

Value: 1, 2, 4, 8, 16

CAN module

The range of each segment: Bit time = 8 to 25Tq

SS = 1Tq

PTS = 1Tq to 8Tq

PBS1 = 2Tq to 8Tq

PBS2 = 2Tq to 8Tq

SJW = 1Tq to 4Tq

Configuration of PBS1 and PBS2: PBS1 ≥ PBS2

PBS1 ≥ SJW

PBS2 ≥ 2 when SJW = 1

PBS2 ≥ SJW when 2 ≤ SJW ≤ 4

Bit time

SS PTS PBS1

SJW

Sampling point

PBS2

SJW

Rev.2.40 Apr 14, 2006 page 229 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.8 Bit-rate

Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud

rate prescaler, and the number of Tq of one bit.

Table 19.2 shows the Examples of Bit-rate.

Table 19.2 Examples of Bit-rate

19.8.1 Calculation of Bit-rate

2 ✕ “fCAN division value (1)” ✕ “baud rate prescaler division value (2)” ✕ “number of Tq of one bit”

NOTES:

1. fCAN division value = 1, 2, 4, 8, 16

fCAN division value: a value selected in the CCLKR register

2. Baud rate prescaler division value = P + 1 (P: 0 to 15)

P: a value selected in the BRP bit in the CiCONR register (i = 0, 1)

NOTES:

1. The number in ( ) indicates a value of “fCAN division value” multiplied by “baud rate prescaler division value”.

2. 24 MHz is available Normal-ver. only.

Bit-rate 24 MHz (2) 20 MHz 16 MHz 10 MHz 8 MHz

1 Mbps 12 Tq (1) 10 Tq (1) 8 Tq (1)

500 kbps 8 Tq (3) 10 Tq (2) 8 Tq (2) 10 Tq (1) 8 Tq (1)

12 Tq (2) 20 Tq (1) 16 Tq (1)

24 Tq (1)

----

125 kbps 8 Tq (12) 8 Tq (10) 8 Tq (8) 8 Tq (5) 8 Tq (4)

12 Tq (8) 10 Tq (8) 16 Tq (4) 10 Tq (4) 16 Tq (2)

16 Tq (6) 16 Tq (5)

20 Tq (2)

24 Tq (4) 20 Tq (4)

---

83.3 kbps 8 Tq (18) 8 Tq (15) 8 Tq (12) 10 Tq (6) 8 Tq (6)

12 Tq (12) 10 Tq (12) 16 Tq (6) 20 Tq (3) 16 Tq (3)

16 Tq (9) 20 Tq (6)

---

24 Tq (6)

----

33.3 kbps 10 Tq (36) 10 Tq (30) 8 Tq (30) 10 Tq (15) 8 Tq (15)

12 Tq (30) 20 Tq (15) 10 Tq (24)

10 Tq (12)

20 Tq (18)

16 Tq (15)

20 Tq (6)

24 Tq (15)

20 Tq (12)

Rev.2.40 Apr 14, 2006 page 230 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

Figure 19.16 Correspondence of Mask Registers to Slots

Figure 19.17 Acceptance Function

When using the acceptance function, note the following points.

(1) When one ID is defined in two slots, the one with a smaller number alone is valid.

(2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15 receive

all IDs which are not stored into slots 0 to 13.

19.9 Acceptance Filtering Function and Masking Function

These functions serve the users to select and receive a facultative message. Registers CiGMR (i = 0, 1),

CiLMAR, and CiLMBR can perform masking to the standard ID and the extended ID of 29 bits. The CiGMR

corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits of a received ID according

to the value in the corresponding slot of the CiIDR register upon acceptance filtering operation. When the

masking function is employed, it is possible to receive a certain range of IDs.

Figure 19.16 shows the Correspondence of Mask Registers to Slots, Figure 19.17 shows the Acceptance

Function.

Slot #0

Slot #1

Slot #2

Slot #3

Slot #4

Slot #5

Slot #6

Slot #7

Slot #8

Slot #9

Slot #10

Slot #11

Slot #12

Slot #14

Slot #15

CiGMR register

Slot #13

CiLMAR register

CiLMBR register

i = 0, 1

ID of the

received message

ID stored in

the slot

The value of the

mask register

Acceptance Signal

Mask Bit Values

Acceptance judge signal

0: The CAN module ignores the

current incoming message.

(Not stored in any slot)

1: The CAN module stores the

current incoming message in

a slot of which ID matches.

0: ID (to which the received message

corresponds) match is handled as

"Don’t care".

1: ID (to which the received message

corresponds) match is checked.

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.10 Acceptance Filter Support Unit (ASU)

The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search.

The IDs to receive are registered in the data table; a received ID is stored in the CiAFS register ( i = 0, 1),

and table search is performed with a decoded received ID. The acceptance filter support unit can be used

for the IDs of the standard frame only.

The acceptance filter support unit is valid in the following cases.

•When the ID to receive cannot be masked by the acceptance filter.

(Example) IDs to receive: 078h, 087h, 111h

•When there are too many IDs to receive; it would take too much time to filter them by software.

Figure 19.18 shows the Write/Read of CiAFS Register in Word Access.

Figure 19.18 Write/read of CiAFS Register in Word Access

b15 b0

b8 b7

When read

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3

SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

When write

3/8 decoder

242h

Addresses

CAN0

244h

CAN1

b15 b0

b8 b7

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M16C/6N Group (M16C/6N4) 19. CAN Module

19.11 Basic CAN Mode

When the BasicCAN bit in the CiCTLR register (i = 0, 1) is set to 1 (Basic CAN mode enabled), slots 14 and

15 correspond to Basic CAN mode. In normal operation mode, each slot can handle only one type message

at a time, either a data frame or a remote frame by setting CiMCTLj regisrer (j = 0 to 15). However, in Basic

CAN mode, slots 14 and 15 can receive both types of message at the same time.

When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in

slots 14 and 15 alternately.

Which type of message has been received can be checked by the RemActive bit in the CiMCTLj register.

Figure 19.19 shows the Slots 14 and 15 Operation in Basic CAN Mode.

Figure 19.19 Slots 14 and 15 Operation in Basic CAN Mode

When using Basic CAN mode, note the following points.

(1) Setting of Basic CAN mode has to be done in CAN reset/initialization mode.

(2) Select the same ID for slots 14 and 15. Also, setting of registers CiLMAR and CiLMBR has to be the

same.

(3) Define slots 14 and 15 as reception slot only.

(4) There is no protection available against message overwrite. A message can be overwritten by a new

message.

(5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode.

Slot 14

Slot 15

Msg n Msg n+1 Msg n+2

Empty

Locked (empty) Locked (empty)

Msg n Locked

Msg n + 1

Msg n+2 (Msg n lost)

Locked (Msg n+1)

(Msg n)

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M16C/6N Group (M16C/6N4) 19. CAN Module

19.12 Return from Bus Off Function

When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by

setting the RetBusOff bit in the CiCTLR register (i = 0, 1) to 1 (force return from bus off). At this time, the

error state changes from bus off state to error active state. If the RetBusOff bit is set to 1, registers CiRECR

and CiTECR are initialized and the State_BusOff bit in the CiSTR register is set to 0 (CAN module is not in

error bus off state). However, registers of the CAN module such as CiCONR register and the content of

each slot are not initialized.

19.13 Time Stamp Counter and Time Stamp Function

When the CiTSR register ( i = 0, 1) is read, the value of the time stamp counter at the moment is read. The

period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the

CiCONR register. The time stamp counter functions as a free run counter.

The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference

clock. Use the TSPreScale bit in the CiCTLR register to select the divide-by-n value.

The time stamp counter is equipped with a register that captures the counter value when the protocol

controller regards it as a successful reception. The captured value is stored when a time stamp value is

stored in a reception slot.

19.14 Listen-Only Mode

When the RXOnly bit in the CiCTLR register ( i = 0, 1) is set to 1, the module enters Listen-only mode.

In Listen-only mode, no transmission, such as data frames, error frames, and ACK response, is performed

to bus.

When Listen-only mode is selected, do not request the transmission.

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M16C/6N Group (M16C/6N4) 19. CAN Module

19.15 Reception and Transmission

Table 19.3 lists the CAN Reception and Transmission Mode Configuration.

Table 19.3 CAN Reception and Transmission Mode Configuration

TrmReq, RecReq, Remote, RspLock, RemActive, RspLock: Bits in CiMCTLj register (i = 0, 1, j = 0 to 15)

When configuring a slot as a reception slot, note the following points.

(1) Before configuring a slot as a reception slot, be sure to set the CiMCTLj register to 00h.

(2) A received message is stored in a slot that matches the condition first according to the result of reception

mode configuration and acceptance filtering operation. Upon deciding in which slot to store, the smaller

the number of the slot is, the higher priority it has.

(3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches, the

CAN module never receives the transmitted data. In loop back mode, however, the CAN module

receives back the transmitted data. In this case, the module does not return ACK.

When configuring a slot as a transmission slot, note the following points.

(1) Before configuring a slot as a transmission slot, be sure to set the CiMCTLj registers to 00h.

(2) Set the TrmReq bit in the CiMCTLj register to 0 (not transmission slot) before rewriting a transmission slot.

(3) A transmission slot should not be rewritten when the TrmActive bit in the CiMCTLj register is 1

(transmitting).

If it is rewritten, an undefined data will be transmitted.

TrmReq RecReq Remote RspLock Communication Mode of Slot

0 0 - - Communication environment configuration mode:

configure the communication mode of the slot.

0 1 0 0 Configured as a reception slot for a data frame.

1 0 1 0 Configured as a transmission slot for a remote frame.

(At this time the RemActive = 1.)

After completion of transmission, this functions as a reception

slot for a data frame. (At this time the RemActive = 0.)

However, when an ID that matches on the CAN bus is detected

before remote frame transmission, this immediately functions

as a reception slot for a data frame.

1 0 0 0 Configured as a transmission slot for a data frame.

0 1 1 1/0 Configured as a reception slot for a remote frame.

(At this time the RemActive = 1.)

After completion of reception, this functions as a transmission

slot for a data frame. (At this time the RemActive = 0.)

However, transmission does not start as long as RspLock bit

remains 1; thus no automatic response.

Response (transmission) starts when the RspLock bit is set to 0.

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M16C/6N Group (M16C/6N4) 19. CAN Module

19.15.1 Reception

Figure 19.20 shows the Timing of Receive Data Frame Sequence. Figure 19.20 shows the behavior of

the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj

CAN bus

RecReq bit

InvalData bit

CANi successful

reception interrupt

RecState bit

RecSucc bit

MBOX bit

NewData bit

SOF ACK EOF EOFIFS IFS

SOF

Receive slot No.

MsgLost bit

CiMCTLj register

CiSTR register

(1)

(2)

(3)

(4)

(5)

i = 0, 1

j = 0 to 15

ACK

Figure 19.20 Timing of Receive Data Frame Sequence

(1) On monitoring a SOF on the CAN bus the RecState bit in the CiSTR register becomes 1 (CAN module

is receiver) immediately, given the module has no transmission pending.

(2) After successful reception of the message, the NewData bit in the CiMCTLj register of the receiving

slot becomes 1 (stored new data in slot). The InvalData bit in the CiMCTLj register becomes 1

(message is being updated) at the same time and the InvalData bit becomes 0 (message is valid) again

after the complete message was transferred to the slot.

(3) When the interrupt enable bit in the CiICR register of the receiving slot = 1 (interrupt enabled), the

CANi successful reception interrupt request is generated and the MBOX bit in the CiSTR register is

changed. It shows the slot number where the message was stored and the RecSucc bit in the CiSTR

(4) Read the message out of the slot after setting the New Data bit to 0 (the content of the slot is read or

still under processing by the CPU) by a program.

(5) When next CAN message is received before the NewData bit is set to 0 by a program or a receive

request to a slot is canceled, the MsgLost bit in the CiMCTLj register is set to 1 (message has been

overwritten). The new received message is transferred to the slot. Generating of an interrupt request

and change of the CiSTR register are same as in 3).

Rev.2.40 Apr 14, 2006 page 236 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 19. CAN Module

19.15.2 Transmission

Figure 19.21 shows the Timing of Transmit Sequence.

CTX

TrmReq bit

TrmActive bit

CANi successful

transmission interrupt

TrmState bit

TrmSucc bit

MBOX bit

SentData bit

Transmission slot No.

CiMCTLj register

CiSTR register

(1)

(2)

(1)

(3)

(4)

(3)

i = 0, 1

j = 0 to 15

SOF SOFEOF IFSACK

Figure 19.21 Timing of Transmit Sequence

(1) If the TrmReq bit in the CiMCTLj register (i = 0, 1, j = 0 to 15) is set to 1 (transmission slot) in the bus

idle state, the TrmActive bit in the CiMCTLj register and the TrmState bit in the CiSTR register are set

to 1 (transmitting/transmitter), and CAN module starts the transmission.

(2) If the arbitration is lost after the CAN module starts the transmission, bits TrmActive and TrmState are

set to 0.

(3) If the transmission has been successful without lost in arbitration, the SentData bit in the CiMCTLj

bus idle or completion of arbitration). And when the interrupt enable bits in the CiICR register = 1

(interrupt enabled), CANi successful transmission interrupt request is generated and the MBOX (the

slot number which transmitted the message) and TrmSucc bit in the CiSTR register are changed.

(4) When starting the next transmission, set bits SentData and TrmReq to 0. And set the TrmReq bit to 1

after checking that bits SentData and TrmReq are set to 0.

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M16C/6N Group (M16C/6N4) 19. CAN Module

19.16 CAN Interrupt

The CAN module provides the following CAN interrupts.

• CANi successful reception interrupt ( i = 0, 1)

• CANi successful transmission interrupt

• CAN0/1 error Interrupt: Error passive state

Error bus off state

Bus error (this feature can be disabled separately)

• CAN0/1 wake-up interrupt

When the CPU detects the CANi successful reception/transmission interrupt request, the MBOX bit in the

CiSTR register must be read to determine which slot has generated the interrupt request.

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M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

20. Programmable I/O Ports

The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10

(except P8_5). Each port can be set for input or output every line by using a direction register, and can also

be chosen to be or not be pulled high every 4 lines. P8_5 is an input-only port and does not have a pull-up

_______ ______

resistor. Port P8_5 shares the pin with NMI, so that the NMI input level can be read from the P8_5 bit in the

P8 register.

Figures 20.1 to 20.5 show the I/O Ports. Figure 20.6 shows the I/O Pins.

Each pin functions as an I/O port, a peripheral function input/output pin or a bus control pin.

For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is

used as a peripheral function input or D/A converter output pin, set the direction bit for that pin to 0 (input

mode). Any pin used as an output pin for peripheral functions other than the D/A converter is directed for

output no matter how the corresponding direction bit is set.

When using any pin as a bus control pin, refer to 7.2 Bus Control.

20.1 PDi Register (i = 0 to 10)

Figure 20.7 shows the PDi Register.

This register selects whether the I/O port is to be used for input or output. The bits in this register correspond

one for one to each port.

During memory expansion and microprocessor modes, the PDi registers for the pins functioning as bus

_______ _______ _____ ________ ______ _________ ________ ________ __________ __________

control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and

BCLK) cannot be modified.

No direction register bit for P8_5 is available.

20.2 Pi Register (i = 0 to 10)

Figure 20.8 shows the Pi Register.

Data input/output to and from external devices are accomplished by reading and writing to the Pi register.

The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For

ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and

data can be written to the port latch by writing to the Pi register.

For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data

can be written to the port latch by writing to the Pi register. The data written to the port latch is output from

the pin. The bits in the Pi register correspond one for one to each port.

During memory expansion and microprocessor modes, the Pi registers for the pins functioning as bus

_______ _______ _____ ________ ______ _________ ________ ________ __________ __________

control pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and

BCLK) cannot be modified.

20.3 PURj Register (j = 0 to 2)

Figure 20.9 shows the PURj Register.

The PURj register bits can be used to select whether or not to pull the corresponding port high in 4-bit unit.

The port selected to be pulled high has a pull-up resistor connected to it when the direction bit is set for input

mode.

However, the pull-up control register has no effect on P0 to P3, P4_0 to P4_3, and P5 during memory

expansion and microprocessor modes. Although the register contents can be modified, no pull-up resistors are

connected.

Rev.2.40 Apr 14, 2006 page 239 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

20.4 PCR Register

Figure 20.10 shows the PCR Register.

When the P1 register is read after setting the PCR0 bit in the PCR register to 1, the corresponding port latch

can be read no matter how the PD1 register is set.

Tables 20.1 lists the Unassigned Pin Handling in Single-chip Mode and 20.2 lists the Unassigned Pin Handling

in Memory Expansion Mode and Microprocessor Mode. Figure 20.11 shows the Unassigned Pin Handling.

Rev.2.40 Apr 14, 2006 page 240 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.1 I/O Ports (1)

NOTE:

1. Symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.

Data bus

Analog input

Pull-up selection

Direction register

Port latch

Data bus

Direction register

Port latch

Pull-up selection

Port P1 control register

Data bus

Direction register

Port latch

Pull-up selection

Port P1 control register

Input to individual peripheral function

Output

Data bus

Direction

Port latch

Pull-up selection

Input to individual peripheral function

(inside dotted-line

included)

(inside dotted-line

not included)

P0_0 to P0 _7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0 to P5_4, P5_6

P1_0 to P1 _4

P1_5 to P1 _7

P5_7

P6_0, P6_4,

P7_3 to P7_6

P8_0, P8_1

P9_0, P9_2

(NOTE 1)

Rev.2.40 Apr 14, 2006 page 241 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.2 I/O Ports (2)

Output

Data bus

Direction

Port latch

Pull-up selection

(NOTE 1)

Input to individual peripheral function

Switching

between

CMOS and

Nch

(NOTE 1)

Data bus

Pull-up selection

Direction register

Port latch

Input to individual peripheral function

Data bus

Pull-up selection

Direction register

Port latch

Input to individual peripheral function

(NOTE 1)

NOTE:

1. Symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.

P6_1, P6_5

P7_2

P8_2 to P8_4

P5_5

P7_7

P9_7

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M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.3 I/O Ports (3)

Data bus

Pull-up selection

Direction register

Port latch

Input to individual peripheral function

Switching

between

CMOS and Nch

Output

Data bus

Pull-up selection

Direction register

Port latch

Switching between CMOS and Nch

Data bus

NMI interrupt input

Data bus

Direction register

Port latch

Input to individual peripheral function

Output

NOTES:

1. Symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.

2. Symbolizes a parasitic diode.

P6_2, P6_6

P6_3, P6_7

P7_0

P7_1, P9_1

P8_5

(NOTE 1)

(NOTE 2)

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Data bus

Direction register

Pull-up selection

Port latch

(NOTE 1)

D/A output enabled

Analog output

Direction register

Data bus Port latch

Pull-up selection

Input to individual peripheral function

D/A output enabled

(NOTE 1)

Output

Direction register

Data bus Port latch

Analog input

Pull-up selection

(NOTE 1)

Direction register

Data bus Port latch

Pull-up selection

(NOTE 1)

Output

(inside dotted-line

included)

(inside dotted-line

not included)

NOTE:

1. Symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.

P10_0 to P10_3

P10_4 to P10_7

P9_3, P9_4

P9_6

P9_5

Analog input

Input to individual peripheral function

Analog input

Input to individual peripheral function

Figure 20.4 I/O Ports (4)

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M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.5 I/O Ports (5)

Figure 20.6 I/O Pins

Data bus

Direction register

Pull-up selection

Port latch

Output

Direction register

Pull-up selection

Port latch

Data bus

(NOTE 1)

P8_7

P8_6

NOTE:

1. Symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.

BYTE

BYTE signal input

CNVSS

CNVSS signal input

RESET

RESET signal input

(NOTE 1)

NOTE:

1. Symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed VCC.

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.7 Registers PD0 to PD10

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

Port Pi Direction Register (i = 0 to 7, 9, 10) (1) (2)

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0 PD0 to PD3

PD4 to PD7

PD9, PD10

03E2h, 03E3h, 03E6h, 03E7h

03EAh, 03EBh, 03EEh, 03EFh

03F3h, 03F6h

00h

Symbol Address After Reset

NOTES:

1. Make sure registers PD7 and PD9 are written to by the next instruction after setting the PRC2 bit in the PRCR

2. During memory expansion and microprocessor modes, the PDi register for the pins functioning as bus control

pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK)

cannot be modified.

PDi_0

PDi_1

PDi_2

PDi_3

PDi_4

PDi_5

PDi_6

PDi_7

Port Pi_0 direction bit

Port Pi_1 direction bit

Port Pi_2 direction bit

Port Pi_3 direction bit

Port Pi_4 direction bit

Port Pi_5 direction bit

Port Pi_6 direction bit

Port Pi_7 direction bit

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

Function

Port P8 Direction Register

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PD8 03F2h 00X00000b

PD8_0

PD8_1

PD8_2

PD8_3

PD8_4

(b5)

PD8_6

PD8_7

Port P8_0 direction bit

Port P8_1 direction bit

Port P8_2 direction bit

Port P8_3 direction bit

Port P8_4 direction bit

Port P8_6 direction bit

Port P8_7 direction bit

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

Function

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M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.8 Registers P0 to P10

Port P8 Register

Bit nameBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

P8 03F0h Undefined

Symbol Address After Reset

P8_0

P8_1

P8_2

P8_3

P8_4

P8_5

P8_6

P8_7

Port P8 _0 bit

Port P8 _1 bit

Port P8 _2 bit

Port P8 _3 bit

Port P8 _4 bit

Port P8 _5 bit

Port P8 _6 bit

Port P8 _7 bit

The pin level on any I/O port which is set

for input mode can be read by reading

the corresponding bit in this register.

The pin level on any I/O port which is

set for output mode can be controlled

by writing to the corresponding bit in

this register (except for P8_5).

0 : "L" level

1 : "H" level

Function

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

NOTES:

1. During memory expansion and microprocessor modes, the Pi register for the pins functioning as bus control

pins (A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK)

cannot be modified.

2. Since P7_1 and P9_1 are N channel open-drain ports, the data is high-impedance.

Pi_0

Pi_1

Pi_2

Pi_3

Pi_4

Pi_5

Pi_6

Pi_7

Port Pi_0 bit

Port Pi_1 bit

Port Pi_2 bit

Port Pi_3 bit

Port Pi_4 bit

Port Pi_5 bit

Port Pi_6 bit

Port Pi_7 bit

The pin level on any I/O port which is set

for input mode can be read by reading

the corresponding bit in this register.

The pin level on any I/O port which is

set for output mode can be controlled

by writing to the corresponding bit in

this register.

0 : "L" level

1 : "H" level (2)

Function

Port Pi Register (i = 0 to 7, 9, 10) (1)

P0 to P3

P4 to P7

P9, P10

03E0h, 03E1h, 03E4h, 03E5h

03E8h, 03E9h, 03ECh, 03EDh

03F1h, 03F4h

Undefined

Symbol Address After Reset

Rev.2.40 Apr 14, 2006 page 247 of 376

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M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Pull-up Control Register 0

(1)

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PUR0 03FCh 00h

Symbol Address After Reset

NOTES:

1. During memory expansion and microprocessor modes, the pins are not pulled high although their corresponding

2. The pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high.

PU00

PU01

PU02

PU03

PU04

PU05

PU06

PU07

P0_0 to P0_3 pull-up

P0_4 to P0_7 pull-up

P1_0 to P1_3 pull-up

P1_4 to P1_7 pull-up

P2_0 to P2_3 pull-up

P2_4 to P2_7 pull-up

P3_0 to P3_3 pull-up

P3_4 to P3_7 pull-up

0 : Not pulled high

1 : Pulled high (2)

Function

Pull-up Control Register 2

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PUR2 03FEh

00h

Symbol Address After Reset

NOTES:

1. The P8_5 pin does not have pull-up.

2. The P9_1 pin does not have pull-up.

3. The pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high.

PU20

PU21

PU22

PU23

PU24

PU25

(b7-b6)

P8_0 to P8_3 pull-up

P8_4, P8_6, and P8_7 pull-up (1)

P9_0, P9_2, and P9_3 pull-up (2)

P9_4 to P9_7 pull-up

P10_0 to P10_3 pull-up

P10_4 to P10_7 pull-up

0 : Not pulled high

1 : Pulled high (3)

Function

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Pull-up Control Register 1

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PUR1 03FDh 00000000b

00000010b

Symbol Address After Reset (1)

NOTES:

1. The values after hardware reset is as follows:

00000000b when input on CNVSS pin is "L".

00000010b when input on CNVSS pin is "H".

The values after software reset, watchdog timer reset and oscillation stop detection reset are as follows:

00000000b when bits PM 01 to PM00 in the PM0 register are 00b (single-chip mode).

00000010b when bits PM 01 to PM00 are 01b (memory expansion mode) or 11b (microprocessor mode).

2. During memory expansion and microprocessor modes, the pins are not pulled high although the contents of

these bits can be modified.

3. If bits PM01 to PM00 are set to 01b (memory expansion mode) or 11b (microprocessor mode) in a program

during single-chip mode, the PU11 bit becomes 1.

4. The P7_1 pin does not have pull-up.

5. The pin for which this bit is 1 (pulled high) and the direction bit is 0 (input mode) is pulled high.

PU10

PU11

PU12

PU13

PU14

PU15

PU16

PU17

P4_0 to P4_3 pull-up (2)

P4_4 to P4_7 pull-up (3)

P5_0 to P5_3 pull-up (2)

P5_4 to P5_7 pull-up (2)

P6_0 to P6_3 pull-up

P6_4 to P6_7 pull-up

P7_0, P7_2, and P7_3 pull-up (4)

P7_4 to P7_7 pull-up

0 : Not pulled high

1 : Pulled high (5)

Function

Figure 20.9 Registers PUR0, PUR1, and PUR2

Rev.2.40 Apr 14, 2006 page 248 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.10 PCR Register

Port Control Register

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PCR 03FFh 00h

Symbol Address After Reset

PCR0

(b7-b1)

Port P1 control bit

Operation performed when the P1

0 : When the port is set for input, the

input levels of pins P1_0 to P1_7

are read. When set for output, the

port latch is read.

1 : The port latch is read regardless of

whether the port is set for input or

output.

Function

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

Rev.2.40 Apr 14, 2006 page 249 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Table 20.1 Unassigned Pin Handling in Single-chip Mode

Pin Name Connection

Ports P0 to P7, P8_0 to P8_4,

P8_6, P8_7, P9, P10

XOUT (4)

_______

NMI(P8_5)

AVCC

AVSS, VREF, BYTE

After setting for input mode, connect every pin to VSS via a resistor (pull-down);

or after setting for output mode, leave these pins open. (1) (2) (3)

Open

Connect via resistor to VCC (pull-up)

Connect to VCC

Connect to VSS

NOTES:

1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until

it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes

undefined, causing the power supply current to increase while the port remains in input mode.

Furthermore, by considering a possibility that the contents of the direction registers may change due to noise

or program runaway caused by noise, it is recommended that the contents of the direction registers be

periodically reset in software, for the increased reliability of the program.

2. Make sure the unused pins are processed with the shortest possible wiring from the MCU pins (2 cm or less).

3. When the ports P7_1 and P9_1 are set for output mode, make sure a low-level signal is output from the pins.

The ports P7_1 and P9_1 are N-channel open-drain outputs.

4. With external clock input to XIN pin.

Table 20.2 Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode

Pin Name Connection

Ports P6, P7, P8_0 to P8_4,

P8_6, P8_7, P9, P10

_______ _______

P4_5/CS1 to P4_7/CS3

________ __________

BHE, ALE, HLDA, XOUT (5),

BCLK (6)

___________ ________ _______

HOLD, RDY, NMI(P8_5)

AVCC

AVSS, VREF

After setting for input mode, connect every pin to VSS via a resistor (pull-down);

or after setting for output mode, leave these pins open. (1) (2) (3) (4)

Connect to VCC via a resistor (pulled high) by setting the corresponding

_____

direction bit in the PD4 register for CSi (i = 1 to 3) to 0 (input mode) and

_____

the CSi bit in the CSR register to 0 (chip select disabled).

Open

Connect via resistor to VCC (pull-up)

Connect to VCC

Connect to VSS

NOTES:

1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until

it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes

undefined, causing the power supply current to increase while the port remains in input mode.

Furthermore, by considering a possibility that the contents of the direction registers may change due to noise

or program runaway caused by noise, it is recommended that the contents of the direction registers be

periodically reset in software, for the increased reliability of the program.

2. Make sure the unused pins are processed with the shortest possible wiring from the MCU pins (2 cm or less).

3. If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode

is switched over in a program after reset. For this reason, the voltage levels on these pins become undefined,

causing the power supply current to increase while they remain set for input ports.

4. When the ports P7_1 and P9_1 are set for output mode, make sure a low-level signal is output from the pins.

The ports P7_1 and P9_1 are N-channel open-drain outputs.

5. With external clock input to XIN pin.

6. If the PM07 bit in the PM0 register is set to 1 (BCLK not output), connect this pin to VCC via a resistor (pulled

high).

Rev.2.40 Apr 14, 2006 page 250 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 20. Programmable I/O Ports

Figure 20.11 Unassigned Pins Handling

NOTE:

1.If the PM07 bit in the PM0 register is set to 1 (BCLK not output), connect this pin to VCC via a resistor (pulled high).

MCU

In single-chip mode

Port P0 to P10 (Input mode)

(except for P8_5)

(Input mode)

(Output mode)

NMI

XOUT

AVCC

BYTE

AVSS

VREF

Open VCC

VCC

VSS

MCU

Port P4_5/CS1

to P4_7/CS3

In memory expansion mode or

in microprocessor mode

Port P6 to P10 (Input mode)

(except for P8_5)

(Input mode)

(Output mode)

NMI

BHE

HLDA

ALE

XOUT

BCLK

(

HOLD

RDY

AVCC

AVSS

VREF

Open VCC

VCC

VSS

Open

Rev.2.40 Apr 14, 2006 page 251 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21. Flash Memory Version

Aside from the on-chip flash memory, the flash memory version MCU has the same functions as the masked

ROM version.

In the flash memory version, the flash memory can perform in four rewrite mode: CPU rewrite mode, standard

serial I/O mode, parallel I/O mode, and CAN I/O mode.

Table 21.1 lists the Flash Memory Version Specifications. See Table 1.1 Functions and Specifications,

for the items not listed in Table 21.1. Table 21.2 shows the Flash Memory Rewrite Modes Overview.

Table 21.1 Flash Memory Version Specifications

Item Specifications

Flash memory rewrite mode 4 modes (CPU rewrite, standard serial I/O, parallel I/O, CAN I/O)

Erase block User ROM area See Figure 21.1 Flash Memory Block Diagram

Boot ROM area 1 block (4 Kbytes) (1)

Program method In units of word, in units of byte (2)

Erase method Collective erase, block erase

Program and erase control method Program and erase controlled by software command

Protect method Lock bit protects each block

Number of commands 8 commands

Programming and erasure endurance

(3) 100 times

ROM code protection Parallel I/O, standard serial I/O, and CAN I/O modes are supported.

NOTES:

1. The boot ROM area contains standard serial I/O mode and CAN I/O mode rewrite control program which is stored in

it when shipped from the factory. This area can only be rewritten in parallel I/O mode.

2. Can be programmed in byte units in only parallel I/O mode.

3. Definition of programming and erasure endurance

The programming and erasure endurance is defined to be per-block erasure endurance. For example, assume a case where

a 4K-byte block A is programmed in 2,048 operations by writing one word at a time and erased thereafter.

In this case, the block is reckoned as having been programmed and erased once.

If a product is 100 times of programming and erasure endurance, each block in it can be erased up to 100 times.

Table 21.2 Flash Memory Rewrite Modes Overview

Flash Memory CPU Rewrite Mode (1)

Standard Serial I/O Mode

Parallel I/O Mode CAN I/O Mode

Rewrite Mode

Function

Areas which User ROM area User ROM area User ROM area User ROM area

can be rewritten

Boot ROM area

Operating Single-chip mode Boot mode Parallel I/O mode Boot mode

mode Memory expansion mode

(EW0 mode)

Boot mode (EW0 mode)

ROM programmer

None Serial programmer Parallel programmer CAN programmer

The user ROM area is

rewritten when the CPU

executes software

commands.

EW0 mode:

Rewrite in areas other

than flash memory (2)

EW1 mode:

Can be rewritten in the

flash memory

The user ROM area is

rewritten using a

dedicated serial

programmer.

Standard serial I/O mode 1:

Clock synchronous

serial I/O

Standard serial I/O mode 2:

UART (3)

The boot ROM and user

ROM areas are rewritten

using a dedicated parallel

programmer.

The user ROM area is

rewritten busing a dedicated

CAN programmer.

NOTES:

1. The PM13 bit remains set to 1 while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The PM13 bit

is reverted to its original value by setting the FMR01 bit to 0 (CPU rewrite mode disabled). However, if the PM13 bit is

changed during CPU rewrite mode, its changed value is not reflected until after the FMR01 bit is set to 0.

2. When in CPU rewrite mode, bits PM10 and PM13 in the PM1 register are set to 1. The rewrite control program can only be

executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1.

3. When using standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 5 MHz, 10 MHz, or 16

MHz.

Rev.2.40 Apr 14, 2006 page 252 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.1 Memory Map

The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to

store the MCU operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte

space as the block A.

Figure 21.1 shows the Flash Memory Block Diagram.

The user ROM area is divided into several blocks, each of which can be protected (locked) against

programming or erasure. The user ROM area can be rewritten in CPU rewrite, standard serial I/O mode,

parallel I/O mode, and CAN I/O mode. Block A is enabled for use by setting the PM10 bit in the PM1 register

_______

to 1 (block A enabled. CS2 area at addresses 10000h to 26FFFh).

The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in

parallel I/O mode (refer to 21.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware

reset occurs while an “H ” signal is applied to pins CNVSS and P5_0 and an “L” signal is applied to the P5_5

pin (refer to 21.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs

while an “L” signal is applied to the CNVSS pin. However, the boot ROM area cannot be read.

Figure 21.1 Flash Memory Block Diagram

21.1.1 Boot Mode

The MCU enters boot mode when a hardware reset occurs while an “H ” signal is applied to pins CNVSS

and P5_0 and an “L ” signal is applied to the P5_5 pin. A program in the boot ROM area is executed.

In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area.

The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment.

The boot ROM area can be rewritten in parallel I/O mode only. If given rewrite control program using

erase-write mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten

according to the system implemented.

Boot ROM area

(2)

4 Kbytes

* Shown here is a block diagram during single-chip mode.

NOTES:

1. Block A can be made usable by setting the PM10 bit in the PM1 register to 1 (block A enabled, addresses

10000h to 26FFFh for CS2 area).

Block A cannot be erased by the erase all unlocked block command. Use the block erase command to

erase it.

2. The boot ROM area can only be rewritten in parallel I/O mode.

3. To specify a block, use an even address in that block.

0FF000h

0FFFFFh

Block 5: 32 Kbytes

Block 4: 8 Kbytes

Block 3: 8 Kbytes

Block 2: 8 Kbytes

Block 1: 4 Kbytes

Block 0: 4 Kbytes

0F0000h

0F7FFFh

0F8000h

0F9FFFh

0FA000h

0FBFFFh

0FC000h

0FDFFFh

0FE000h

0FEFFFh

0FF000h

0FFFFFh

Block 8: 64 Kbytes

Block 7: 64 Kbytes

Block 6: 64 Kbytes

Block 5 to 0

(32+8+8+8+4+4) Kbytes

0C0000h

0CFFFFh

0D0000h

0DFFFFh

0E0000h

0EFFFFh

0F0000h

0FFFFFh

User ROM area

Block A: 4 Kbytes

(1)

00F000h

00FFFFh

Rev.2.40 Apr 14, 2006 page 253 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.2 Functions to Prevent Flash Memory from Rewriting

The flash memory has the ROM code protect function for parallel I/O mode and the ID code check function

for standard serial I/O mode and CAN I/O mode to prevent the flash memory from reading or rewriting.

21.2.1 ROM Code Protect Function

The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I/O

mode. Figure 21.2 shows the ROMCP Register. The ROMCP register is located in the user ROM area.

The ROM code protect function is enabled when the ROMCR bits are set to other than 11b. In this case,

set the bit 5 to bit 0 to 111111b.

When exiting ROM code protect, erase the block including the ROMCP register by CPU rewrite mode,

standard serial I/O mode, or CAN I/O mode.

21.2.2 ID Code Check Function

Use the ID code check function in standard serial I/O mode and CAN I/O mode. The ID code sent from the

serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes

do not match, commands sent from the serial programmer are not accepted. However, if the four bytes of

the reset vector are FFFFFFFFh, ID codes are not compared, allowing all commands to be accepted.

The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh,

0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a

program with the ID codes set in these addresses.

Figure 21.3 shows the Addresses for ID Code Stored.

Rev.2.40 Apr 14, 2006 page 254 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.2 ROMCP Register

Figure 21.3 Address for ID Code Stored

ROM Code Protect Control Address

(5)

Symbol Address Value when Shipped

ROMCP 0FFFFFh FFh

(1)

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol Bit Name Function

Reserved bits

ROM code protect level 1

set bit

(1) (2) (3) (4)

Set to 1 RW

(b5-b0)

ROMCP1

111 11

b7 b6

0 0 : ROM code protection

0 1 : active

1 0 :

1 1 :

ROM code protection inactive

NOTES:

1. The ROMCP address is set to FFh when a block, including the ROMCP address, is erased.

2. When the ROM code protection is active by the ROMCP1 bit setting, the flash memory is protected against

reading or rewriting in parallel I/O mode.

3. Set bits 5 to 0 to 111111b when the ROMCP1 bit is set to a value other than 11b.

If bits 5 to 0 are set to values other than 111111b, the ROM code protection may not become active by

setting the ROMCP1 bit to a value other than 11b.

4. To make the ROM code protection inactive, erase a block including the ROMCP address in CPU rewrite

mode, standard serial I/O mode, or CAN I/O mode.

5. When a value of the ROMCP address is 00h or FFh, the ROM code protect function is disabled.

0FFFDFh to 0FFFDCh

0FFFE3h to 0FFFE0h

0FFFE7h to 0FFFE4h

0FFFEBh to 0FFFE8h

0FFFEFh to 0FFFECh

0FFFF3h to 0FFFF0h

0FFFF7h to 0FFFF4h

0FFFFBh to 0FFFF8h

0FFFFFh to 0FFFFCh Reset vector

Oscillation stop and re-oscillation detection/Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

NMI vector

DBC vector

ID7

ROMCP

ID6

ID5

ID4

ID3

ID2

ID1

Address

4 bytes

Rev.2.40 Apr 14, 2006 page 255 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Item EW0 Mode EW1 Mode

Operating mode • Single-chip mode Single-chip mode

• Memory expansion mode

• Boot mode

Space where rewrite • User ROM area User ROM area

control program can be • Boot ROM area

placed

Space where rewrite The rewrite control program must be The rewrite control program can be

control program can be transferred to any space other than the executed in the user ROM area

executed flash memory (e.g., RAM) before being

executed (2)

Space which can be User ROM area User ROM area

rewritten However, this excludes blocks with the

rewrite control program

Software command None •Program and block erase commands

restriction cannot be executed in a block having

the rewrite control program.

•Erase all unlocked block command

cannot be executed when the lock bit in

a block having the rewrite control program

is set to 1 (unlocked) or when the FMR02

bit in the FMR0 register is set to 1 (lock

bit disabled).

•Read status register command cannot

be used.

Modes after program or Read status register mode Read array mode

erasing

CPU status during Operating Maintains hold state (I/O ports maintains

auto-programming and the state before the command was

auto-erasure executed) (1)

Flash memory status •Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07

detection in the FMR0 register by program in the FMR0 register by program

•Execute the read status register

command to read bits SR7, SR5, and

SR4 in the status register

21.3 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.

The user ROM area can be rewritten with the MCU is mounted on a board without using a parallel, serial or

CAN programmer.

In CPU rewrite mode, only the user ROM area shown in Figure 21.1 can be rewritten. The boot ROM area

cannot be rewritten. Program and the block erase command are executed only in the user ROM area.

Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode.

Table 21.3 lists the differences between EW0 and EW1 Modes.

Table 21.3 EW0 Mode and EW1 Mode

NOTES:

_______

Do not generate an interrupts (except NMI interrupt) and DMA transfer.

2. When in CPU rewrite mode, bits PM10 and PM13 in the PM1 register are set to 1. The rewrite control

program can only be executed in the internal RAM or in an external area that is enabled for use when

the PM13 bit = 1.

Rev.2.40 Apr 14, 2006 page 256 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.1 EW0 Mode

The MCU enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode

enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1

The software commands control programming and erasing. The FMR0 register or the status register

indicates whether a program or erase operation is completed as expected or not.

21.3.2 EW1 Mode

EW1 mode is selected by setting FMR11 bit to 1 (by writing 0 and then 1 in succession) after setting the

FMR01 bit to 1 (by writing 0 and then 1 in succession). (Both bits must be set to 0 first before setting to 1.)

The FMR0 register indicates whether or not a program or erase operation has been completed as

expected. The status register cannot be read in EW1 mode.

When an erase/program operation is initiated the CPU halts all program execution until the operation is

completed or erase-suspend is requested.

Rev.2.40 Apr 14, 2006 page 257 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.4 Registers FMR0 and FMR1

Flash Memory Control Register 0

Symbol Address After Reset

FMR0 01B7h 00000001b

b7 b6 b5 b4 b3 b2 b1 b0

RY/BY status flag

FMR00 0 : Busy (being written or erased) (1)

1 : Ready

CPU rewrite mode

select bit (2)

0 : CPU rewrite mode disabled

1 : CPU rewrite mode enabled

FMR01

0 : Boot ROM area is accessed

1 : User ROM area is accessed

Lock bit disable select

bit (3)

0: Lock bit enabled

1: Lock bit disabled

Flash memory stop

bit (4) (5)

0 Flash memory operation enabled

1: Flash memory operation stops

(placed in low power dissipation mode,

flash memory initialized)

User ROM area select

bit (4)

(Effective in only boot mode)

FMR02

FMSTP

FMR05

Set to 0Reserved bit

Program status flag (6)

FMR06

Erase status flag (6)

FMR07 0 : Terminated normally

1 : Terminated in error

0 : Terminated normally

1 : Terminated in error

(b4)

NOTES:

1.This status includes writing or reading with the lock bit program or read lock bit status command.

2. To set this bit to 1, write 0 and then 1 in succession. Make sure no interrupts or no DMA transfers will occur before

writing 1 after writing 0.

Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, write to this bit from a program in

other than the flash memory.

Enter read array mode and set this bit to 0.

3. To set this bit to 1, write 0 and then 1 in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA

transfers will occur before writing 1 after writing 0.

4. Write to this bit from a program in other than the flash memory.

5. Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit can be set to

1 by writing 1 in a program, the flash memory is neither placed in low power dissipation state nor initialized.

6. This bit is set to 0 by executing the clear status command.

Bit Symbol Bit Name Function

Flash Memory Control Register 1

Symbol Address After Reset

FMR1 01B5h 0X00XX0Xb

b7 b6 b5 b4 b3 b2 b1 b0

000

EW1 mode select bit (1) 0 : EW0 mode

1 : EW1 mode

FMR11

Lock bit status flag

FMR16 0 : Lock

1 : Unlock

Set to 0Reserved bit RW

(b7)

Set to 0Reserved bits RW

(b5-b4)

When read, the content is undefined.

Reserved bits RO

(b3-b2)

When read, the content is undefined.Reserved bit

(b0)

NOTE:

1. To set this bit to 1, write 0 and then 1 in succession when the FMR01 bit in the FMR0 register = 1. Make sure no

interrupts or no DMA transfers will occur before writing 1 after writing 0.

Write to this bit when the NMI pin is in the high state.

Both the FMR01 and FMR11 bits are set to 0 by setting the FMR01 bit to 0.

Bit Symbol Bit Name Function

21.3.3 Registers FMR0 and FMR1

Figure 21.4 shows Registers FMR0 and FMR1.

Rev.2.40 Apr 14, 2006 page 258 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.3.1 FMR00 Bit

This bit indicates the operating status of the flash memory. It is set to 0 while the program, block erase,

erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise,

it is set to 1.

21.3.3.2 FMR01 Bit

The MCU can accept commands when the FMR01 bit is set to 1 (CPU rewrite mode). Set the FMR05 bit

to 1 (user ROM area access) as well if in boot mode.

21.3.3.3 FMR02 Bit

The lock bit is disabled by setting the FMR02 bit to 1 (lock bit disabled). (Refer to 21.3.6 Data Protect

Function.) The lock bit is enabled by setting the FMR02 bit to 0 (lock bit enabled).

The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase or

erase all unlocked block command is executed when the FMR02 bit is set to 1, the lock bit status

changes 0 (locked) to 1 (unlocked) after command execution is completed.

21.3.3.4 FMSTP Bit

The FMSTP bit resets the flash memory control circuits and minimizes power consumption in the flash

memory. Access to the flash memory is disabled when the FMSTP bit is set to 1 (flash memory operation

stops). Set the FMSTP bit by program in a space other than the flash memory.

Set the FMSTP bit to 1 if one of the followings occurs:

•A flash memory access error occurs while erasing or programming in EW0 mode (FMR00 bit does not

switch back to 1 (ready))

•Low power dissipation mode or on-chip oscillator low power dissipation mode is entered

Use the following the procedure to change the FMSTP bit setting.

(1) Set the FMSTP bit to 1

(2) Set tps (the wait time to stabilize flash memory circuit)

(3) Set the FMSTP bit to 0

(4) Set tps (the wait time to stabilize flash memory circuit)

Figure 21.7 shows the Processing Before and After Low Power Dissipation Mode or On-chip Oscillator

Low Power Dissipation Mode. Follow the procedure on this flow chart.

When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait

mode, the flash memory is turned back on. The FMR0 register does not need to be set.

21.3.3.5 FMR05 Bit

This bit selects the boot ROM or user ROM area in boot mode. Set to 0 to access (read) the boot ROM

area or to 1 (user ROM access) to access (read, write or erase) the user ROM area.

21.3.3.6 FMR06 Bit

This is a read-only bit indicating the status of an auto-program operation. The FMR06 bit is set to 1 when

a program error occurs; otherwise, it is set to 0. Refer to 21.3.8 Full Status Check.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.3.7 FMR07 Bit

This is a read-only bit indicating the status of an auto-erase operation. The FMR07 bit is set to 1 when an

erase error occurs; otherwise, it is set to 0. For details, refer to 21.3.8 Full Status Check.

21.3.3.8 FMR11 Bit

EW0 mode is entered by setting the FMR11 bit to 0 (EW0 mode).

EW1 mode is entered by setting the FMR11 bit to 1 (EW1 mode).

21.3.3.9 FMR16 Bit

This is a read-only bit indicating the execution result of the read lock bit status command. When the

block, where the read lock bit status command is executed, is locked, the FMR16 bit is set to 0.

When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is set

to 1.

Figure 21.5 shows the Setting and Resetting of EW0 Mode. Figure 21.6 show the Setting and Resetting

of EW1 Mode.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.6 Setting and Resetting of EW1 Mode

Figure 21.5 Setting and Resetting of EW0 Mode

Procedure to enter EW0 mode

Set registers CM0, CM1, and PM1 (1)

Transfer the rewrite control program in CPU rewrite

mode to a space other than the flash memory (5)

Single-chip mode, memory expansion mode

or boot mode

Execute the software commands

Set the FMR01 bit to 0

(CPU rewrite mode disabled)

Jump to the rewrite control program transferred to

a space other than the flash memory.

(In the following steps, use the rewrite control

program in a space other than the flash memory.)

Rewrite control program

NOTES:

1.In CPU rewrite mode, set the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register to CPU

clock frequency of 10 MHz or less. Set the PM17 bit in the PM1 register to 1 (with wait state).

2.Set the FMR01 bit to 1 immediately after setting it to 0. Do not generate an interrupts or DMA transfer between

setting the bit to 0 and setting it to 1.

Set the bit to 0 if setting to 0. Set this bit in a space other than the flash memory while the NMI pin is held "H".

3.Exit CPU rewrite mode after executing the read array command.

4.When CPU rewrite mode is exited while the FMR05 bit is set to 1, the user ROM area can be accessed.

5.When in CPU rewrite mode, bits PM10 and PM13 in the PM1 register are set to 1. The rewrite control program

can only be executed in the internal RAM or in an external area that is enabled for use when the PM13 bit = 1.

In boot mode only

set the FMR05 bit to 1 (user ROM area access)

Set the FMR01 bit to 1 (CPU rewrite mode

enabled) after writing 0 (2)

Execute the read array command (3)

In boot mode only

Set the FMR05 bit to 0 (Boot ROM area

accessed) (4)

Jump to a given address in the flash memory

Procedure to enter EW1 mode

Set registers CM0, CM1, and PM1

(2)

Set the FMR01 bit to 1 (CPU rewrite mode

enabled) after writing 0

Set the FMR11 bit to 1 (EW1 mode) after

writing 0 (EW1 mode)

(3)

Single-chip mode

(1)

Execute the software commands

Set the FMR01 bit to 0

(CPU rewrite mode disabled)

NOTES:

1.In EW1 mode, do not enter the memory expansion mode or boot mode.

2.In CPU rewrite mode, set the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register to

CPU clock frequency of 10 MHz or less. Set the PM17 bit in the PM1 register to 1 (with wait state).

3. Set the FMR01 bit to 1 immediately after setting it to 0. Do not generate an interrupt or a DMA transfer between

setting the bit to 0 and setting it to 1.

Set the FMR11 bit to 1 immediately after setting it to 0 while the FMR01 bit is set to 1.

Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and setting it to 1.

Set bits FMR01 and FMR11 while "H" is applied to the NMI pin.

Program in the ROM

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.7 Processing Before and After Low Power Dissipation Mode or On-chip Oscillator Low

Power Dissipation Mode

Transfer a low power dissipation mode or on-chip

oscillator low power dissipation mode program to

a space other the flash memory

Set the FMSTP bit to 1 (the flash memory stops

operating. It is in a low power dissipation state)

(1)

Set the FMR01 bit to 1 after setting it to 0

(CPU rewrite mode enabled)

Switch the clock source of the CPU clock.

The main clock stops.

(2)

Process in low power dissipation mode or

on-chip oscillator low power dissipation mode

(4)

Start Wait Switch

main clock

until oscillation

clock source of

oscillation stabilizes the CPU clock

(2)

Set the FMSTP bit to 0 (flash memory operation)

Set the FMR01 bit to 0

(CPU rewrite mode disabled)

Wait until the flash memory circuit

stabilizes (tps µs)

(3)

Jump to a given address in the flash memory

Jump to the low power dissipation mode or on-chip

oscillator low power dissipation mode program

transferred to a space other than the flash memory

(In the following steps, use the low power dissipation

mode in a space other than the flash memory.)

Low power dissipation mode

or on-chip oscillator low power

dissipation mode program

NOTES:

1.Set the FMSTP bit in the FMR0 register to 1 after setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite

mode enabled).

2.Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock.

3.Add tps µs wait time by program. Do not access the flash memory during this wait time.

4.Before entering wait mode or stop mode, be sure to set the FMR01 bit to 0 (CPU rewrite mode disabled).

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.4 Notes on CPU Rewrite Mode

21.3.4.1 Operating Speed

Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to 0 (main

clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and bits CM17 to

CM16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state).

21.3.4.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash

memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

21.3.4.3 Interrupts (EW0 Mode)

• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM

area.

_______

• The NMI and watchdog timer interrupts are available since registers FMR0 and FMR1 are forcibly reset

when either interrupt request is generated. Allocate the jump addresses for each interrupt service

_______

routines to the fixed vector table. Flash memory rewrite operation is suspended when the NMI or

watchdog timer interrupt request is generated. Execute the rewrite program again after exiting the

interrupt routine.

• The address match interrupt is not available since the CPU tries to read data in the flash memory.

21.3.4.4 Interrupts (EW1 Mode)

• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt

during auto-programming or auto-erasure.

• Do not use the watchdog timer interrupt.

_______

• The NMI interrupt is available since registers FMR0 and FMR1 are forcibly reset when the interrupt

request is generated. Allocate the jump address for the interrupt service routine to the fixed vector table.

_______

Flash memory rewrite operation is suspended when the NMI interrupt request is generated. Execute the

rewrite program again after exiting the interrupt service routine.

21.3.4.5 How to Access

To set the FMR01, FMR02 or FMR11 bit to 1, write 1 after first setting the bit to 0. Do not generate an

interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to

_______

1. Set the bit while an “H” signal is applied to the NMI pin.

21.3.4.6 Rewriting in User ROM Area (EW0 Mode)

If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash

memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error

occurs, rewrite the user ROM area while in standard serial I/O mode, parallel I/O mode, or CAN I/O

mode.

21.3.4.7 Rewriting in User ROM Area (EW1 Mode)

Avoid rewriting any block in which the rewrite control program is stored.

21.3.4.8 DMA Transfer

In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to 0 (auto-

programming or auto-erasure).

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.4.9 Writing Command and Data

Write commands and data to even addresses in the user ROM area.

21.3.4.10 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled)

before executing the WAIT instruction.

21.3.4.11 Stop Mode

When entering stop mode, execute the instruction which sets the CM10 bit to 1 (stop mode) after setting

the FMR01 bit to 0 (CPU rewrite mode disabled) and disabling the DMA transfer.

21.3.4.12 Low Power Dissipation Mode and On-chip Oscillator Low Power Dissipation Mode

If the CM05 bit is set to 1 (main clock stopped), do not execute the following commands:

• Program

• Block erase

• Erase all unlocked blocks

• Lock bit program

• Read lock bit status

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.5 Software Commands

Software commands are described below. The command code and data must be read and written in 16-bit

unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8

bits (D15 to D8) are ignored.

Table 21.4 lists the Software Commands.

Table 21.4 Software Commands

Read array

Read status register

Clear status register

Program

Block erase

Erase all unlocked block (1)

Lock bit program

Read lock bit status

Write

xxFFh

xx70h

xx50h

xx40h

xx20h

xxA7h

xx77h

xx71h

Read

Write

SRD

xxD0h

Mode Address Data

(D15 to D0) Mode Address

First Bus Cycle Second Bus Cycle

Software Command Data

(D15 to D0)

SRD:data in the SRD register (D7 to D0)

WA: Address to be written (The address specified in the first bus cycle is the same even address as the

address specified in the second bus cycle.)

WD: 16-bit write data

BA: Highest-order block address (must be an even address)

✕: Given even address in the user ROM area

xx: High-order 8 bits of command code (ignored)

NOTE:

1. Blocks 0 to 8 can be erased by the erase all unlocked block command.

Block A cannot be erased. The block erase command must be used to erase the block A.

21.3.5.1 Read Array Command (FFh)

The read array command reads the flash memory.

By writing command code xxFFh in the first bus cycle, read array mode is entered. Content of a speci-

fied address can be read in 16-bit unit after the next bus cycle.

The MCU remains in read array mode until another command is written. Therefore, contents from multiple

addresses can be read consecutively.

21.3.5.2 Read Status Register Command (70h)

The read status register command reads the status register (refer to 21.3.7 Status Register (SRD

By writing command code xx70h in the first bus cycle, the status register can be read in the second bus

cycle. Read an even address in the user ROM area.

Do not execute this command in EW1 mode.

21.3.5.3 Clear Status Register Command (50h)

The clear status register command clears the status register.

By writing xx50h in the first bus cycle, bits FMR07 to FMR06 in the FMR0 register are set to 00b and bits

SR5 to SR4 in the status register are set to 00b.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.8 Program Command

21.3.5.4 Program Command (40h)

The program command writes 2-byte data to the flash memory.

By writing xx40h in the first bus cycle and data to the write address in the second bus cycle, an

auto-program operation (data program and verify) will start. The address value specified in the first bus

cycle must be the same even address as the write address specified in the second bus cycle.

The FMR00 bit in the FMR0 register indicates whether an auto-program operation has been completed.

The FMR00 bit is set to 0 (busy) during auto-programming and to 1 (ready) when an auto-program

operation is completed.

After the completion of an auto-program operation, the FMR06 bit in the FMR0 register indicates

whether or not the auto-program operation has been completed as expected. (Refer to 21.3.8 Full

Status Check.)

An address that is already written cannot be altered or rewritten.

Figure 21.8 shows a flow chart of the Program Command.

The lock bit protects each block from being programmed inadvertently. (Refer to 21.3.6 Data Protect

Function.)

In EW1 mode, do not execute this command on the block where the rewrite control program is allocated.

In EW0 mode, the MCU enters read status register mode as soon as an auto-program operation starts.

The status register can be read. The SR7 bit in the status register is set to 0 at the same time an

auto-program operation starts. It is set to 1 when auto-program operation is completed. The MCU remains in

read status register mode until the read array command is written. After completion of an auto-program

operation, the status register indicates whether or not the auto-program operation has been completed

as expected.

Start

YES

Write the command code xx40h

to an address to be the written

FMR00=1?

Program operation is

completed

NOTE:

1.Write the command code and data to even addresses.

Full status check

Write data to an address

to be written

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.9 Block Erase Command

21.3.5.5 Block Erase Command

The block erase command erases each block.

By writing xx20h in the first bus cycle and xxD0h to the highest-order even address of a block in the

second bus cycle, an auto-erase operation (erase and verify) will start in the specified block.

The FMR00 bit in the FMR0 register indicates whether an auto-erase operation has been completed.

The FMR00 bit is set to 0 (busy) during auto-erasure and to 1 (ready) when the auto-erase operation is

completed.

After the completion of an auto-erase operation, the FMR07 bit in the FMR0 register indicates whether

or not the auto-erase operation has been completed as expected. (Refer to 21.3.8 Full Status Check.)

Figure 21.9 shows a flow chart of the Block Erase Command.

The lock bit protects each block from being programmed inadvertently. (Refer to 21.3.6 Data Protect

Function.)

In EW1 mode, do not execute this command on the block where the rewrite control program is allocated.

In EW0 mode, the MCU enters read status register mode as soon as an auto-erase operation starts. The

status register can be read. The SR7 bit in the status register is set to 0 at the same time an auto-erase

operation starts. It is set to 1 when an auto-erase operation is completed. The MCU remains in read status

clear status register command and block erase command at least 3 times until an erase error is not

generated when an erase error is generated.

Write xxD0h to the highest-order

block address

Start

YES

FMR00=1?

Full status check

(2) (3)

Block erase operation is

completed

Write the command code xx20h

NOTES:

1.Write the command code and data to even addresses.

2.Refer to Figure 21.12 Full Status Check and Handling Procedure for Each Error.

3.Execute the clear status register command and block erase command at least 3 times

until an erase error is not generated when an erase error is generated.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.5.6 Erase All Unlocked Block

The erase all unlocked block command erases all blocks except the block A.

By writing xxA7h in the first bus cycle and xxD0h in the second bus cycle, an auto-erase (erase and

verify) operation will run continuously in all blocks except the block A.

The FMR00 bit in the FMR0 register indicates whether an auto-erase operation has been completed.

After the completion of an auto-erase operation, the FMR07 bit in the FMR0 register indicates whether

or not the auto-erase operation has been completed as expected.

The lock bit can protect each block from being programmed inadvertently. (Refer to 21.3.6 Data Protect

Function.)

In EW1 mode, do not execute this command when the lock bit for any block storing the rewrite control

program is set to 1 (unlocked) or when the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled).

In EW0 mode, the MCU enters read status register mode as soon as an auto-erase operation starts. The

status register can be read. The SR7 bit in the status register is set to 0 (busy) at the same time an

auto-erase operation starts. It is set to 1 (ready) when an auto-erase operation is completed. The MCU

remains in read status register mode until the read array command or read lock bit status command is

written.

Only blocks 0 to 8 can be erased by the erase all unlocked block command. The block A cannot be

erased. Use the block erase command to erase the block A.

21.3.5.7 Lock Bit Program Command

The lock bit program command sets the lock bit for a specified block to 0 (locked).

By writing xx77h in the first bus cycle and xxD0h to the highest-order even address of a block in the second

bus cycle, the lock bit for the specified block is set to 0. The address value specified in the first bus cycle

must be the same highest-order even address of a block specified in the second bus cycle.

Figure 21.10 shows a flow chart of the Lock Bit Program Command. Execute read lock bit status

command to read lock bit state (lock bit data).

The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed.

Refer to 21.3.6 Data Protect Function for details on lock bit functions and how to set it to 1 (unlocked).

Start

YES

FMR00=1?

Full status check

Write xxD0h to the highest-order

block address

Write command code xx77h to

the highest-order block address

Lock bit program operation

is completed

NOTE:

1.Write the command code and data to even addresses.

Figure 21.10 Lock Bit Program Command

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.5.8 Read Lock Bit Status Command (71h)

The read lock bit status command reads the lock bit state of a specified block.

By writing xx71h in the first bus cycle and xxD0h to the highest-order even address of a block in the

second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit

of a specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to 1

(ready).

Figure 21.11 shows a flow chart of the Read Lock Bit Status Command.

Start

YES

FMR00=1?

YES

FMR16=0?

Write the command code xx71h

Write xxD0h to the highest-order

block address

Block is not locked

Block is locked

NOTE:

1.Write the command code and data to even addresses.

Figure 21.11 Read Lock Bit Status Command

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.3.6 Data Protect Function

Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit

in the FMR0 register to 0 (lock bit enabled). The lock bit allows each block to be individually protected

(locked) against program and erase. This helps prevent data from being inadvertently written to or erased

from the flash memory.

• When the lock bit status is set to 0, the block is locked (block is protected against program and erase).

• When the lock bit status is set to 1, the block is not locked (block can be programmed or erased).

The lock bit status is set to 0 (locked) by executing the lock bit program command and to 1 (unlocked) by

erasing the block. The lock bit status cannot be set to 1 by any commands.

The lock bit status can be read by the read lock bit status command.

The lock bit function is disabled by setting the FMR02 bit to 1 (lock bit disabled). All blocks are unlocked.

However, individual lock bit status remains unchanged. The lock bit function is enabled by setting the

FMR02 bit to 0. Lock bit status is retained.

If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to 1, the

target block or all blocks are erased regardless of lock bit status. The lock bit status of each block are set

to 1 after an erase operation is completed.

Refer to 21.3.5 Software Commands for details on each command.

21.3.7 Status Register (SRD Register)

The status register indicates the operating status of the flash memory and whether or not an erase or

program operation is completed as expected. Bits FMR00, FMR06, and FMR07 in the FMR0 register

indicate status register states.

Table 21.5 shows the Status Register.

In EW0 mode, the status register can be read when the followings occur.

•Given even address in the user ROM area is read after writing the read status register command.

•Given even address in the user ROM area is read from when the program, block erase, erase all

unlocked block, or lock bit program command is executed until when the read array command is

executed.

21.3.7.1 Sequencer Status (Bits SR7 and FMR00)

The sequencer status indicates the operating status of the flash memory. It is set to 0 while the program,

block erase, erase all unlocked block, lock bit program, or read lock bit status command is being

executed; otherwise, it is set to 1.

21.3.7.2 Erase Status (Bits SR5 and FMR07)

Refer to 21.3.8 Full Status Check.

21.3.7.3 Program Status (Bits SR4 and FMR06)

Refer to 21.3.8 Full Status Check.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Table 21.5 Status Register

SR0 (D0)

SR1 (D1)

SR2 (D2)

SR3 (D3)

SR4 (D4)

SR5 (D5)

SR6 (D6)

SR7 (D7)

Reserved

Program status

Erase status

Reserved

Sequencer status

Terminated normally

Busy

Terminated in error

Ready

Status Name Contents

Bits in Status

FMR06

FMR07

FMR00

Bits in FMR0

Value after

Reset

D0 to D7: These data bus are read when the read status register command is executed.

NOTE:

1. Bits FMR06 (SR4) and FMR07 (SR5) are set to 0 by executing the clear status register command.

When the FMR06 bit (SR4) or FMR07 bit (SR5) is set to 1, the program, block erase, erase all

unlocked block and lock bit program commands are not accepted.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

FRM00 Register

(Status Register)

Status Error Error Occurrence Conditions

FMR07 Bit FMR06 Bit

(SR5) (SR4)

1 1 Command •Command is written incorrectly

Sequence •A value other than xxD0h or xxFFh is written in the second bus

error cycle of the lock bit program, block erase or erase all unlocked

block command (1)

1 0 Erase error •The block erase command is executed on a locked block (2)

•The block erase or erase all unlocked block command is

executed on an unlock block and auto-erase operation is not

completed as expected

0 1 Program error •The program command is executed on locked blocks (2)

•The program command is executed on unlocked blocks and

auto-program operation is not completed as expected

• The lock bit program command is executed but program

operation is not completed as expected

21.3.8 Full Status Check

If an error occurs when a program or erase operation is completed, the FMR06, FMR07 bits in the FMR0

these bits (full status check).

Table 21.6 lists the Errors and FMR0 Register Status. Figure 21.12 shows a flow chart of the Full Status

Check and Handling Procedure for Each Error.

Table 21.6 Errors and FMR0 Register Status

NOTES:

1. The flash memory enters read array mode by writing command code xxFFh in the second bus cycle of

these commands. The command code written in the first bus cycle becomes invalid.

2. When the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled), no error occurs even under the

conditions above.

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.12 Full Status Check and Handling Procedure for Each Error

Full status check

FMR06 =1

and

FMR07=1?

YES

FMR07=0?

YES

FMR06=0?

YES

FMR06, FMR07: Bits in FMR0 register

NOTE:

1. When either FMR06 or FMR07 bit is set to 1 (terminated by error), the program, block erase, erase all unlocked block, lock bit program

and read lock bit status commands cannot be accepted.

Execute the clear status register command before each command.

(1) Execute the clear status register command and set the SR5 bit to 0.

(2) Execute the lock bit read status command. Set the FMR02 bit in the

FMR0 register to 1 (lock bit disabled) if the lock bit in the block where

the error occurred is set to 0 (locked).

(3) Execute the block erase or erase all unlocked block command again.

(4) Execute (1), (2), and (3) at least 3 times until an erase error is not

generated.

NOTE: If similar error occurs, that block cannot be used.

If the lock bit is set to 1 (unlocked) in (2) above, that block cannot

be used.

[When a program operation is executed]

(1) Execute the clear status register command and set the SR4 bit to 0

(completed as expected).

(2) Execute the read lock bit status command and set the FMR02 bit to 1

if the lock bit in the block where the error occurred is set to 0.

(3) Execute the program command again.

NOTE: When a similar error occurs, that block cannot be used.

If the lock bit is set to 1 in (2) above, that block cannot be used.

[When a lock bit program operation is executed]

(1) Execute the clear status register command and set the SR4 bit to 0.

(2) Set the FMR02 bit to 1.

(3) Execute the block erase command to erase the block where the error

occurred.

(4) Execute the lock bit program command again.

NOTE: If similar error occurs, that block cannot be used.

(1) Execute the clear status register command and set bits SR4 and SR5

to 0 (completed as expected).

(2) Rewrite command and execute again.

Command

sequence error

Erase error

Program error

Full status check completed

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.4 Standard Serial I/O Mode

In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6N4) can be used

to rewrite the flash memory user ROM area in the MCU mounted on a board. For more information about the

serial programmer, contact your serial programmer manufacturer. Refer to the user's manual included with

your serial programmer for instructions.

Table 21.7 lists the Pin Functions in Standard Serial I/O Mode. Figures 21.13 and 21.14 show the Pin

Connections in Standard Serial I/O Mode.

21.4.1 ID Code Check Function

The ID code check function determines whether the ID codes sent from the serial programmer matches

those written in the flash memory. (Refer to 21.2 Functions to Prevent Flash Memory from Rewriting.)

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M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Table 21.7 Pin Functions in Standard Serial I/O Mode

NOTES:

____________

1. When using standard serial I/O mode, It is necessary to input “H” to the TXD1(P6_7) pin while the RESET pin is

____________

“L”. Therefore, the internal pull-up is enabled for the TXD1(P6_7) pin while the RESET pin is “L”.

2. When using standard serial I/O mode, pins P0_0 to P0_7, P1_0 to P1_7 may become undefined while the P8_4

____________

pin is “H” and the RESET pin is “L”. If this causes a problem, apply “L” to the P8_4 pin.

Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2 to

VCC2 pin. The VCC apply condition is that VCC2 = VCC1.

Apply 0 V to VSS pin.

Connect to VCC1 pin. _____________

Reset input pin. While RESET pin is "L" level, input 20 cycles or

longer clock to XIN pin.

Connect a ceramic resonator or crystal oscillator between XIN and

XOUT pins. To input an externally generated clock, input it to XIN

pin and open XOUT pin.

Connect this pin to VCC1 or VSS.

Connect AVCC to VCC1 and AVSS to VSS, respectively.

Enter the reference voltage for A/D and D/A converters from this

pin.

Input “H” or “L” level signal or open.

Input “H” level signal.

Input “H” or “L” level signal or open.

Input “L” level signal.

Input “H” or “L” level signal or open.

Standard serial I/O mode 1: BUSY signal output pin

Standard serial I/O mode 2: Monitors the boot program operation

check signal output pin.

Standard serial I/O mode 1: Serial clock input pin.

Standard serial I/O mode 2: Input “L”.

Serial data input pin

Serial data output pin (1)

Input “H” or “L” level signal or open.

Input “L” level signal. (2)

Connect this pin to VCC1.

Input “H” or “L” level signal or open.

Input “H” or “L” level signal or connect to a CAN transceiver.

Input “H” level signal, open or connect to a CAN transceiver.

Input “H” or “L” level signal or open.

VCC1, VCC2, VSS

CNVSS

_____________

RESET

XIN

XOUT

BYTE

AVCC, AVSS

VREF

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0

P5_1 to P5_4,

P5_6, P5_7

P5_5

P6_0 to P6_3

_________

P6_4/RTS1

P6_5/CLK1

P6_6/RXD1

P6_7/TXD1

P7_0 to P7_7

P8_0 to P8_3,

P8_6, P8_7

P8_4 _______

P8_5/NMI

P9_0 to P9_4, P9_7

P9_5/CRX0

P9_6/CTX0

P10_0 to P10_7

Pin Name I/O Description

Power supply

input

CNVSS

Reset input

Clock input

Clock output

BYTE

Analog power

supply input

Reference

voltage input

Input port P0

Input port P1

Input port P2

Input port P3

Input port P4

_____

CE input

Input port P5

________

EPM input

Input port P6

BUSY output

SCLK input

RXD input

TXD output

Input port P7

Input port P8

P8_4 input

________

NMI input

Input port P9

CRX input

CTX output

Input port P10

Rev.2.40 Apr 14, 2006 page 275 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.13 Pin Connections in Standard Serial I/O Mode (1)

100

CNVSS

RESET

VSS

VCC1

VCC2

TXD

SCLK

EPM

RXD

BUSY

Connect

oscillation

circuit

Mode setup method

Package: PRQP0100JB-A

(100P6S-A)

M16C/6N Group (M16C/6N4)

(Flash memory version)

CNVSS

EPM

RESET

Signal Value

VCC1

VSS

VSS to VCC1

VCC2

Rev.2.40 Apr 14, 2006 page 276 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.14 Pin Connections in Standard Serial I/O Mode (2)

CNVSS

RESET

VSS

VCC1

VCC2

TXD

SCLK

EPM

RXD

BUSY

M16C/6N Group (M16C/6N4)

(Flash memory version)

Connect

oscillation

circuit

CNVSS

EPM

RESET

Signal

Mode setup method

Value

VCC1

VSS

VSS to VCC1

VCC2

Package: PLQP0100KB-A

(100P6Q-A)

100

Rev.2.40 Apr 14, 2006 page 277 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.4.2 Example of Circuit Application in Standard Serial I/O Mode

Figures 21.15 and 21.16 show the Circuit Application in Standard Serial I/O Mode 1 and Mode 2. Refer to

the user’s manual of your serial programmer to handle pins controlled by a serial programmer.

Note that when using standard serial I/O mode 2, make sure a main clock input oscillation frequency is

set to 5 MHz, 10 MHz, or 16 MHz.

Figure 21.15 Circuit Application in Standard Serial I/O Mode 1

Figure 21.16 Circuit Application in Standard Serial I/O Mode 2

MCU

NOTES:

1.Control pins and external circuitry will vary according to programmer.

For more information, refer to the programmer manual.

2. In this example, modes are switched between single-chip mode and standard serial

I/O mode by controlling the CNVSS input with a switch.

3.If in standard standard serial I/O mode 1 there is a possibility that the user reset

signal will go low during standard serial I/O mode, break the connection between

the user reset signal and RESET pin by using, for example, a jumper switch.

SCLK input

BUSY output

TXD output

RXD input

Reset input

P6_4/RTS1

P6_6/CLK1

P6_7/TXD1

RESET

P6_6/RXD1 CNVSS

P5_0(CE)

P5_5(EPM)

P8_5/NMI

User reset

signal

VCC1

VCC2

VCC1

MCU

P6_4/RTS1

P6_5/CLK1

P6_7/TXD1

P6_6/RXD1 CNVSS

P5_0(CE)

P5_5(EPM)

P8_5/NMI

Monitor output

TXD output

RXD input

NOTE:

1.In this example, modes are switched between single-chip mode and standard serial I/O

mode by controlling the CNVSS input with a switch.

Reset input RESET

User reset

signal

VCC1

VCC2

VCC1

Rev.2.40 Apr 14, 2006 page 278 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.5 Parallel I/O Mode

In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer

supporting the M16C/6N Group (M16C/6N4). Contact your parallel programmer manufacturer for more

information on the parallel programmer. Refer to the user's manual included with your parallel programmer

for instructions.

21.5.1 User ROM and Boot ROM Areas

An erase block operation in the boot ROM area is applied to only one 4-Kbyte block. The rewrite control

program in standard serial I/O and CAN I/O modes are written in the boot ROM area before shipment. Do

not rewrite the boot ROM area if using the serial programmer.

In parallel I/O mode, the boot ROM area is located in addresses 0FF000h to 0FFFFFh. Rewrite this

address range only if rewriting the boot ROM area. (Do not access addresses other than addresses

0FF000h to 0FFFFFh.)

21.5.2 ROM Code Protect Function

The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O

mode. (Refer to 21.2 Functions to Prevent Flash Memory from Rewriting.)

Rev.2.40 Apr 14, 2006 page 279 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.6 CAN I/O Mode

In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6N4) can be used to

rewrite the flash memory user ROM area in the MCU mounted on a board. For more information about the

CAN programmer, contact your CAN programmer manufacturer. Refer to the user's manual included with

your CAN programmer for instructions.

Table 21.8 lists pin functions in CAN I/O mode. Figures 21.17 and 21.18 show pin connections in CAN I/O

mode.

21.6.1 ID Code Check Function

The ID code check function determines whether the ID codes sent from the CAN programmer matches

those written in the flash memory. (Refer to 21.2 Functions to Prevent Flash Memory from Rewriting.)

Table 21.8 Pin Functions in CAN I/O Mode

Apply the Flash Program, Erase Voltage to VCC1 pin and VCC2

to VCC2 pin. The VCC apply condition is that VCC2 = VCC1.

Apply 0 V to VSS pin.

Connect to VCC1 pin. ____________

Reset input pin. While RESET pin is “L” level, input 20 cycles or

longer clock to XIN pin.

Connect a ceramic resonator or crystal oscillator between XIN and

XOUT pins. To input an externally generated clock, input it to XIN

pin and open XOUT pin.

Connect this pin to VCC1 or VSS.

Connect AVCC to VCC1 and AVSS to VSS, respectively.

Enter the reference voltage for A/D and D/A converters from this

pin.

Input “H” or “L” level signal or open.

Input “H” level signal.

Input “H” or “L” level signal or open.

Input “L” level signal.

Input “H” or “L” level signal or open.

Input “L” level signal.

Input “H” level signal.

Input “H” or “L” level signal or open.

Input “L” level signal. (1)

Connect this pin to VCC1.

Input “H” or “L” level signal or open.

Connect to a CAN transceiver.

Input “H” or “L” level signal or open

VCC1, VCC2, VSS

CNVSS

_____________

RESET

XIN

XOUT

BYTE

AVCC, AVSS

VREF

P0_0 to P0_7

P1_0 to P1_7

P2_0 to P2_7

P3_0 to P3_7

P4_0 to P4_7

P5_0

P5_1 to P5_4,

P5_6, P5_7

P5_5

P6_0 to P6_4, P6_6

P6_5/CLK1

P6_7/TXD1

P7_0 to P7_7

P8_0 to P8_3,

P8_6, P8_7

P8_4 _______

P8_5/NMI

P9_0 to P9_4, P9_7

P9_5/CRX0

P9_6/CTX0

P10_0 to P10_7

Pin Name I/O Description

Power supply

input

CNVSS

Reset input

Clock input

Clock output

BYTE

Analog power

supply input

Reference

voltage input

Input port P0

Input port P1

Input port P2

Input port P3

Input port P4

_____

CE input

Input port P5

________

EPM input

Input port P6

SCLK input

TXD output

Input port P7

Input port P8

P8_4 Input

________

NMI input

Input port P9

CRX input

CTX output

Input port P10

NOTE:

1. When using CAN I/O mode, pins P0_0 to P0_7, P1_0 to P1_7 may become undefined while the P8_4 pin is “H”

____________

and the RESET pin is “L”. If this causes a problem, apply “L” to the P8_4 pin.

Rev.2.40 Apr 14, 2006 page 280 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.17 Pin Connections in CAN I/O Mode (1)

100

CNVSS

RESET

VSS

VCC1

VCC2

TXD

SCLK

EPM

Connect

oscillation

circuit

CTX

CRX

M16C/6N Group (M16C/6N4)

(Flash memory version)

CNVSS

EPM

RESET

SCLK

TXD

Signal

Mode setup method

Value

VCC1

VSS

VSS to VCC1

VCC2

VSS

VCC1

Package: PRQP0100JB-A

(100P6S-A)

Rev.2.40 Apr 14, 2006 page 281 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

Figure 21.18 Pin Connections in CAN I/O Mode (2)

CNVSS

RESET

CTX

CRX

VSS

VCC1

VCC2

SCLK

EPM

TXD

Connect

oscillation

circuit

CNVSS

EPM

RESET

SCLK

TXD

Signal

Mode setup method

Value

VCC1

VSS

VSS to VCC1

VCC2

VSS

VCC1

Package: PLQP0100KB-A

(100P6Q-A)

100

M16C/6N Group (M16C/6N4)

(Flash memory version)

Rev.2.40 Apr 14, 2006 page 282 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

21.6.2 Example of Circuit Application in CAN I/O Mode

Figure 21.19 shows the Circuit Application in CAN I/O Mode. Refer to the user’s manual of your CAN

programmer to handle pins controlled by a CAN programmer.

CNVSS

MCU

CAN_L

CAN_H

CAN_L

CAN_H

CAN transceiver

P6_7/TXD1

P9_6/CTX0

P9_5/CRX0

P6_5/CLK1

RESET P8_5/NMI

P5_0(CE)

P5_5(EPM)

NOTES:

1.Control pins and external circuitry will vary according to programmer.

For more information, refer to the programmer manual.

2. In this example, modes are switched between single-chip mode and CAN I/O mode

by controlling the CNVSS input with a switch.

VCC1

VCC2

VCC1

Figure 21.19 Circuit Application in CAN I/O Mode

Rev.2.40 Apr 14, 2006 page 283 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

NOTES:

1. Referenced to VCC = 4.5 to 5.5 V, Topr = 0 to 60°C unless otherwise specified.

2. Programming and erasure endurance refers to the number of times a block erase can be performed.

If the programming and erasure endurance is n (n = 100), each block can be erased n times.

For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different

address, this counts as one programming and erasure endurance. Data cannot be written to the same

address more than once without erasing the block (rewrite prohibited).

3. n denotes the number of block erases.

Table 21.10 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics

(at Topr = 0 to 60 °C)

21.7 Electrical Characteristics

21.7.1 Electrical Characteristics (T/V-ver.)

Table 21.9 lists the Flash Memory Electrical Characteristics. Table 21.10 lists the Flash Memory Version

Program/Erase Voltage and Read Operation Voltage Characteristics.

Table 21.9 Flash Memory Version Electrical Characteristics (1)

VCC = 5.0 ± 0.5 V

Flash Read Operation VoltageFlash Program, Erase Voltage

VCC = 4.2 to 5.5 V

200

4 ✕ n (3)

cycle

µs

Programming and erasure endurance (2)

Word program time (VCC = 5.0 V)

Lock bit program time

Block erase time 4-Kbyte block

(VCC = 5.0 V) 8-Kbyte block

32-Kbyte block

64-Kbyte block

Erase all unlocked blocks time

Flash memory circuit stabilization wait time

Parameter Min.

Standard Unit

Max.Typ.

0.3

0.5

0.8

Symbol

tps

100

Rev.2.40 Apr 14, 2006 page 284 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 21. Flash Memory Version

NOTES:

1. Referenced to VCC = 4.5 to 5.5 V, 3.0 to 3.6 V, Topr = 0 to 60°C unless otherwise specified.

2. Programming and erasure endurance refers to the number of times a block erase can be performed.

If the programming and erasure endurance is n (n = 100), each block can be erased n times.

For example, if a 4-Kbyte block A is erased after writing 1 word data 2,048 times, each to a different

address, this counts as one programming and erasure endurance. Data cannot be written to the same

address more than once without erasing the block (rewrite prohibited).

3. n denotes the number of block erases.

Table 21.12 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics

(at Topr = 0 to 60 °C)

21.7.2 Electrical Characteristics (Normal-ver.)

Table 21.11 lists the Flash Memory Electrical Characteristics. Table 21.12 lists the Flash Memory Version

Program/Erase Voltage and Read Operation Voltage Characteristics.

Table 21.11 Flash Memory Version Electrical Characteristics (1)

VCC = 3.3 ± 0.3 V or 5.0 ± 0.5 V

Flash Read Operation VoltageFlash Program, Erase Voltage

VCC = 3.0 to 5.5 V

200

4 ✕ n (3)

cycle

µs

Programming and erasure endurance (2)

Word program time (VCC = 5.0 V)

Lock bit program time

Block erase time 4-Kbyte block

(VCC = 5.0 V) 8-Kbyte block

32-Kbyte block

64-Kbyte block

Erase all unlocked blocks time

Flash memory circuit stabilization wait time

Parameter Min.

Standard Unit

Max.Typ.

0.3

0.5

0.8

Symbol

tps

100

Rev.2.40 Apr 14, 2006 page 285 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

22. Electrical Characteristics

22.1 Electrical Characteristics (T/V-ver.)

Table 22.1 Absolute Maximum Ratings

option: All options are on request basis.

VCC

AVCC

Topr

Tstg

°C

Unit

Supply voltage (VCC1 = VCC2)

Analog supply voltage

Input

voltage

Output

voltage

Power dissipation

Operating ambient During MCU operation

temperature

During flash memory program and

erase operation

Storage temperature

Symbol Parameter

_____________

RESET, CNVSS, BYTE,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,

P9_0, P9_2 to P9_7, P10_0 to P10_7,

VREF, XIN

P7_1, P9_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7, XOUT

P7_1, P9_1

Rated Value

–0.3 to 6.5

–0.3 to VCC+0.3

–0.3 to 6.5

–0.3 to VCC+0.3

–0.3 to 6.5

700

T version: –40 to 85

V version: –40 to 125

(option)

0 to 60

–65 to 150

Condition

VCC = AVCC

Topr = 25°C

Rev.2.40 Apr 14, 2006 page 286 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Table 22.2 Recommended Operating Conditions (1) (1)

Supply voltage (VCC1 = VCC2)

Analog supply voltage

Supply voltage

Analog supply voltage

HIGH input

voltage

LOW input

voltage

HIGH peak

output current

HIGH average

output current

LOW peak

output current

LOW average

output current

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,

P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,

_____________

P10_0 to P10_7, XIN, RESET, CNVSS, BYTE

P7_1, P9_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(During single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(Data input during memory expansion and microprocessor modes)

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,

P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

_____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(During single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(Data input during memory expansion and microprocessor modes)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,

P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,

P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

5.0

VCC

4.2

0.8 VCC

0.5 VCC

5.5

VCC

6.5

VCC

0.2 VCC

0.16 VCC

–10.0

–5.0

10.0

5.0

VCC

AVCC

VSS

AVSS

VIH

VIL

IOH(peak)

IOH(avg)

IOL(peak)

IOL(avg)

ParameterSymbol Typ.Min.

Standard Unit

Max.

NOTES:

1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.

2. Average output current values during 100 ms period.

3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max.

The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max.

The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.

The total IOH(peak) for ports P3, P4, and P5 must be –40 mA max.

The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.

The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be –40 mA max.

Rev.2.40 Apr 14, 2006 page 287 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Table 22.3 Recommended Operating Conditions (2) (1)

Main clock input oscillation No wait Mask ROM version VCC = 4.2 to 5.5 V

frequency (2) (3) (4)

Flash memory version

Sub clock oscillation frequency

On-chip oscillation frequency

PLL clock oscillation frequency

CPU operation clock

VCC = 4.2 to 5.5 V

PLL frequency synthesizer stabilization wait time

Power supply ripple allowable frequency (VCC)

Power supply ripple allowable amplitude voltage VCC = 5 V

Power supply ripple rising/falling gradient VCC = 5 V

32.768

MHz

kHz

MHz

kHz

V/ms

0.5

0.3

f(XIN)

f(XCIN)

f(Ring)

f(PLL)

f(BCLK)

tsu(PLL)

f(ripple)

VP-P(ripple)

VCC(|∆V/∆T|)

ParameterSymbol Typ.Min.

Standard Unit

Max.

NOTES:

1. Referenced to VCC = 4.2 to 5.5 V at Topr = –40 to 85°C unless

otherwise specified.

2. Relationship between main clock oscillation frequency and supply

voltage is shown right.

3. Execute program/erase of flash memory by VCC = 5.0 ± 0.5 V.

4. When using over 16 MHz, use PLL clock. PLL clock oscillation

frequency which can be used is 16 MHz or 20 MHz.

0.0

16.0

5.54.2

VCC [V] (main clock: no division)

f(XIN) operating maximum frequency [MHz]

Main clock input oscillation frequency

(Mask ROM version / Flash memory

version: no wait)

f(ripple)

Power supply ripple allowable

frequency (VCC)

VP-P(ripple)

Power supply ripple allowable

amplitude voltage

Figure 22.1 Voltage Fluctuation Timing

(ripple)

P-P(ripple)

VCC

Rev.2.40 Apr 14, 2006 page 288 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Table 22.4 Electrical Characteristics (1) (1)

-2.0

-0.3

3.0

0.2

2.0

2.5

1.6

1.5

HIGH output

voltage

HIGH output

voltage

HIGH output

voltage

HIGH output

voltage

LOW output

voltage

LOW output

voltage

LOW output

voltage

LOW output

voltage

Hysteresis

HIGH input

current

LOW input

current

Pull-up

resistance

Feedback resistance

RAM retention voltage

VOH

VOL

VT+-VT-

IIH

IIL

RPULLUP

RfXIN

RfXCIN

VRAM

IOH = –5 mA

IOH = –200 µA

IOH = –1 mA

IOH = –0.5 mA

With no load applied

IOL = 5 mA

IOL = 200 µA

IOL = 1 mA

IOL = 0.5 mA

With no load applied

VI = 5 V

VI = 0 V

At stop mode

µA

kΩ

MΩ

Measuring Condition

Standard

Min. Unit

VCC

2.0

0.45

2.0

1.0

2.5

5.0

–5.0

170

Parameter

Symbol

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

_________ _______

HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,

________ ________ _______ _____________ _________ _________

INT0 to INT5, NMI, ADTRG, CTS0 to CTS2,

SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,

_____ _____

TA0OUT to TA4OUT, KI0 to KI3,

RXD0 to RXD2, SIN3

_____________

RESET

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to

P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7

XIN

XCIN

Typ. Max.

NOTES:

1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.

Rev.2.40 Apr 14, 2006 page 289 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Table 22.5 Electrical Characteristics (2) (1)

Mask ROM f(BCLK) = 20 MHz,

PLL operation,

No division

On-chip oscillation,

No division

Flash memory f(BCLK) = 20 MHz,

PLL operation,

No division

On-chip oscillation,

No division

Flash memory f(BCLK) = 10 MHz,

program VCC = 5 V

Flash memory f(BCLK) = 10 MHz,

erase VCC = 5 V

Mask ROM f(BCLK) = 32kHz,

Low power dissipation

mode, ROM (2)

Flash memory f(BCLK) = 32 kHz,

Low power dissipation

mode, RAM (2)

f(BCLK) = 32 kHz,

Low power dissipation

mode,

Flash memory (2)

Mask ROM On-chip oscillation,

Flash memory Wait mode

f(BCLK) = 32 kHz,

Wait mode (3),

Oscillation capacity High

f(BCLK) = 32 kHz,

Wait mode (3),

Oscillation capacity Low

Stop mode,

Topr = 25°C

NOTES:

1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 20 MHz unless otherwise specified.

2. This indicates the memory in which the program to be executed exists.

3. With one timer operated using fC32.

1.8

420

8.5

3.0

0.8

Power supply

current

(VCC

= 4.2 to 5.5 V)

ICC mA

µA

Measuring Condition Standard

Min. Unit

3.0

ParameterSymbol

In single-chip mode,

the output pins are

open and other pins

are VSS.

Typ. Max.

Rev.2.40 Apr 14, 2006 page 290 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Table 22.6 A/D Conversion Characteristics (1)

(NOTE 2)

1.0

1.5

Bits

µs

kΩ

Resolution

Absolute accuracy

Setup time

Output resistance

Reference power supply input current

–

tsu

IVREF

Symbol Parameter Min.

Standard Unit

Measuring condition

Max.

Typ.

NOTES:

1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.

2. φAD frequency must be 10 MHz or less.

3. When sample & hold is disabled, φAD frequency must be 250kHz or more in addition to a limit of NOTE 2.

When sample & hold is enabled, φAD frequency must be 1MHz or more in addition to a limit of NOTE 2.

Table 22.7 D/A conversion Characteristics (1)

NOTES:

1. Referenced to VCC = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.

2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.

The resistor ladder of the A/D converter is not included. Also, the IVREF will flow even if VREF is disconnected by the

ADCON1 register.

±3

±7

±2

±3

±7

±2

±1

±3

VCC

VREF

Bit

LSB

kΩ

µs

3.3

2.8

0.3

2.0

VREF = VCC

VREF

= VCC

= 5 V

VREF = AVCC = VCC = 5 V

VREF

= VCC

= 5 V

VREF = AVCC = VCC = 5 V

VREF = VCC

VREF = VCC = 5 V, φAD = 10 MHz

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

Resolution

Integral 10 bits

nonlinearity

error

8 bits

Absolute 10 bits

accuracy

8 bits

Differential nonlinearity error

Offset error

Gain error

Resistor ladder

10-bit conversion time,

sample & hold available

8-bit conversion time,

sample & hold available

Sampling time

Reference voltage

Analog input voltage

–

INL

–

DNL

–

RLADDER

tCONV

tSAMP

VREF

VIA

Symbol Parameter Min.

Standard Unit

Measuring Condition Max.

Typ.

Rev.2.40 Apr 14, 2006 page 291 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

150

µs

Time for internal power supply stabilization during powering-on

STOP release time

Low power dissipation mode wait mode release time

td(P-R)

td(R-S)

td(W-S)

Symbol Parameter Min.

Standard Unit

Measuring

Condition Max.

Typ.

VCC = 4.2 to 5.5 V

Table 22.8 Power Supply Circuit Timing Characteristics

CPU clock

VCC

td(P-R)

Time for internal power supply

stabilization during powering-on

td(R-S)

STOP release time

td(W-S)

Low power dissipation mode

wait mode release time

CPU clock

td(W-S)

td(R-S)

(b)

(a)

Interrupt for

(a) Stop mode release

(b) Wait mode release

Figure 22.2 Power Supply Circuit Timing Diagram

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

External clock rise time

External clock fall time

Symbol Parameter Min.

Standard Unit

Max.

62.5

tw(H)

tw(L)

Timing Requirements

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.9 External Clock Input (XIN Input)

Table 22.10 Memory Expansion Mode and Microprocessor Mode

(NOTE 1)

(NOTE 2)

(NOTE 3)

Data input access time (for setting with no wait)

Data input access time (for setting with wait)

Data input access time (when accessing multiplexed bus area)

Data input setup time

________

RDY input setup time

__________

HOLD input setup time

Data input hold time

________

RDY input hold time

__________

HOLD input hold time

Symbol Parameter Min.

Standard Unit

Max.

tac1(RD-DB)

tac2(RD-DB)

tac3(RD-DB)

tsu(DB-RD)

tsu(RDY-BCLK)

tsu(HOLD-BCLK)

th(RD-DB)

th(BCLK-RDY)

th(BCLK-HOLD)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 45 [ns]

2. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 45 [ns]

n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 45 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 293 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Timing Requirements

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.11 Timer A Input (Counter Input in Event Counter Mode)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

100

Table 22.12 Timer A Input (Gating Input in Timer Mode)

tc(TA)

tw(TAH)

tw(TAL)

Table 22.13 Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 22.14 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 22.15 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

200

100

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

100

tw(TAH)

tw(TAL)

TAiOUT input cycle time

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup time

TAiOUT input hold time

Symbol Parameter Min.

Standard Unit

Max.

2000

1000

400

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

Table 22.16 Timer A Input (Two-phase Pulse Input in Event Counter Mode)

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

Symbol Parameter Min.

Standard Unit

Max.

800

200

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

VCC = 5 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

TBiIN input cycle time (counted on one edge)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

Symbol Parameter Min.

Standard Unit

Max.

100

200

Table 22.18 Timer B Input (Pulse Period Measurement Mode)

tc(TB)

tw(TBH)

tw(TBL)

tc(TB)

tw(TBH)

tw(TBL)

Timing Requirements

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.17 Timer B Input (Counter Input in Event Counter Mode)

Table 22.19 Timer B Input (Pulse Width Measurement Mode)

Table 22.20 A/D Trigger Input

Table 22.21 Serial Interface

TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TB)

tw(TBH)

tw(TBL)

TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TB)

tw(TBH)

tw(TBL)

_____________

ADTRG input cycle time (trigger able minimum)

_____________

ADTRG input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

1000

125

tC(AD)

tw(ADL)

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

TXDi output delay time

TXDi hold time

RXDi input setup time

RXDi input hold time

Symbol Parameter Min.

Standard Unit

Max.

200

100

tc(CK)

tw(CKH)

tw(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

_______

Table 22.22 External Interrupt INTi Input

_______

INTi input HIGH pulse width

_______

INTi input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

250

tw(INH)

tw(INL)

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 295 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) (3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR) (3)

__________

HLDA output delay time

Symbol Parameter Min.

Standard Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 40 [ns]

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 kΩ, hold time of output “L” level is

t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

Figure 22.3 Port P0 to P10 Measurement Circuit

DBi

30 pF

P10

Measuring

Condition

Figure 22.3

f(BCLK) is 12.5 MHz or less.

VCC = 5 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) (3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR) (3)

__________

HLDA output delay time

Symbol Parameter Min.

Standard Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.24

Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.

f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 kΩ, hold time of output “L” level is

t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

DBi

Measuring

Condition

Figure 22.3

VCC = 5 V

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

(NOTE 1)

(NOTE 2)

(NOTE 1)

–4

(NOTE 3)

(NOTE 4)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

th(RD-CS)

th(WR-CS)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

td(BCLK-ALE)

th(BCLK-ALE)

td(AD-ALE)

th(ALE-AD)

td(AD-RD)

td(AD-WR)

tdZ(RD-AD)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

__________

HLDA output delay time

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of Address

WR signal output delay from the end of Address

Address output floating start time

Symbol Parameter Min.

Standard Unit

Max.

Switching Characteristics

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.25 Memory Expansion Mode and Microprocessor Mode

(for 2- to 3-wait setting, external area access and multiplexed bus selection)

Measuring

Condition

Figure 22.3

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 40 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 25 [ns]

4. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 15 [ns]

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 298 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.4 Timing Diagram (1)

tsu(D—C)

CLKi

TXDi

RXDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C—Q) th(C—D)

th(C—Q)

INTi input

tc(TB)

tw(TBH)

tw(TBL)

tc(AD)

tw(ADL)

ADTRG input

TBiIN input

Two-phase pulse input in event counter mode

tsu(TAOUT—TAIN)

tsu(TAIN—TAOUT)

tC(TA)

tsu(TAIN—TAOUT)

TAiIN input

TAiOUT input

tc(TA)

tw(TAH)

tw(TAL)

tc(UP)

tw(UPH)

tw(UPL)

TAiIN input

TAiOUT input

During event counter mode

TAiIN input

(When count on falling edge

is selected)

TAiIN input

(When count on rising edge

is selected)

TAiOUT input

(Up/down input)

h(TIN—UP)

su(UP—TIN)

trtr

tw(H) tw(L)

XIN input

VCC = 5 V

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.5 Timing Diagram (2)

Measuring conditions :

VCC = 5 V

Input timing voltage : Determined with V

= 1.0 V, V

= 4.0 V

Output timing voltage: Determined with V

= 2.5 V, V

= 2.5 V

BCLK

HOLD input

HLDA output

P0, P1, P2,

P3, P4,

P5_0 to P5_2

(1)

NOTE:

The above pins are set to high-impedance regardless of the input level of the BYTE pin,

the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.

Hi–Z

RDY input

BCLK

(Multiplexed bus)

WR, WRL, WRH

(Separate bus)

td(BCLK–HLDA)td(BCLK–HLDA)

th(BCLK–HOLD)tsu(HOLD–BCLK)

tsu(RDY–BCLK) th(BCLK–RDY)

Memory Expansion Mode and Microprocessor Mode

(Effective for setting with wait)

(Common to setting with wait and setting without wait)

VCC = 5 V

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.6 Timing Diagram (3)

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

25ns.max

ALE

25ns.max -4ns.min

25ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

Hi-Z

DBi

h(RD-DB)

0ns.min

h(RD-AD)

BHE

tcyc

Read timing

d(BCLK-AD)

d(BCLK-ALE)

h(BCLK-ALE)

SU(DB-RD)

d(BCLK-RD)

40ns.min

ac1(RD-DB)

Memory Expansion Mode and Microprocessor Mode

(For setting with no wait)

WR,WRL,

WRH

25ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

d(BCLK-ALE)

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

40ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

(0.5 ✕ tcyc-40)ns.min

h(WR-DB)

DBi

Write timing

d(BCLK-WR)

Hi-Z

(0.5 ✕ tcyc-45)ns.max

(0.5 ✕ tcyc-10)ns.min

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : V

= 0.8 V, V

= 2.0 V

Output timing voltage : V

= 0.4 V, V

= 2.4 V

(0.5 ✕ tcyc-10)ns.min

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 301 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.7 Timing Diagram (4)

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

h(BCLK-ALE)

-4ns.min

25ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

Hi-Z

DBi

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

tcyc

BHE

Read timing

WR,WRL,

WRH

25ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

d(BCLK-ALE)

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

40ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min

h(WR-DB)

DBi

Write timing

d(BCLK-ALE)

d(BCLK-RD)

d(BCLK-WR)

0ns.min

h(RD-AD)

ac2(RD-DB)

Hi-Z

Memory Expansion Mode and Microprocessor Mode

(For 1-wait setting and external area access)

(1.5 ✕ tcyc-45)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : VIL = 0.8 V, VIH = 2.0 V

Output timing voltage : VOL = 0.4 V, VOH = 2.4 V

(0.5 ✕ tcyc-10)ns.min

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 302 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.8 Timing Diagram (5)

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

Memory Expansion Mode and Microprocessor Mode

(For 2-wait setting and external area access)

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

25ns.max

Hi-Z

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

h(BCLK-RD)

0ns.min

h(RD-AD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

Hi-Z

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-WR)

25ns.max

h(BCLK-CS)

4ns.min

h(BCLK-AD)

4ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-WR)

0ns.min

d(BCLK-DB)

40ns.max

d(DB-WR)

(1.5 ✕ tcyc-40)ns.min

h(BCLK-DB)

4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

ac2(RD-DB)

(2.5 ✕ tcyc-45)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : V

= 0.8 V, V

= 2.0 V

Output timing voltage : V

= 0.4 V, V

= 2.4 V

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 303 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.9 Timing Diagram (6)

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

Memory Expansion Mode and Microprocessor Mode

(For 3-wait setting and external area access)

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

25ns.max

Hi-Z

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

h(BCLK-RD)

0ns.min

h(RD-AD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

Hi-Z

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-WR)

25ns.max

h(BCLK-CS)

4ns.min

h(BCLK-AD)

4ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-WR)

0ns.min

d(BCLK-DB)

40ns.max

d(DB-WR)

(2.5 ✕ tcyc-40)ns.min

h(BCLK-DB)

4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

ac2(RD-DB)

(3.5 ✕ tcyc-45)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : VIL = 0.8 V, VIH = 2.0 V

Output timing voltage : VOL = 0.4 V, VOH = 2.4 V

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 304 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.10 Timing Diagram (7)

Memory Expansion Mode and Microprocessor Mode

(For 1- or 2-wait setting, external area access and multiplexed bus selection)

BCLK

CSi

td(BCLK-CS)

25ns.max

ADi

td(BCLK-AD)

25ns.max

ALE

th(BCLK-ALE)

-4ns.min

25ns.max

th(BCLK-RD)

0ns.min

th(BCLK-AD)

4ns.min

th(BCLK-CS)

4ns.min

tcyc th(RD-CS)

th(RD-AD)

BHE

ADi

/DBi th(RD-DB)

0ns.min

td(AD-ALE)

Read timing

td(BCLK-WR)

25ns.max

th(BCLK-WR)

0ns.min

BCLK

CSi

td(BCLK-CS)

25ns.max

ADi

td(BCLK-AD)

25ns.max

ALE

25ns.max

th(BCLK-ALE)

-4ns.min

th(BCLK-AD)

4ns.min

th(BCLK-CS)

4ns.min

tcyc

th(WR-AD)

BHE

td(BCLK-DB)

40ns.max 4ns.min

th(BCLK-DB)

td(DB-WR) th(WR-DB)

ADi

/DBi

Data output

WR,WRL,

WRH

Write timing

Address

Data input

40ns.min

(0.5 ✕ tcyc-10)ns.min

td(BCLK-ALE)

td(BCLK-RD)

th(WR-CS)

Address

td(AD-ALE)

(0.5 ✕ tcyc-25)ns.min (1.5 ✕ tcyc-40)ns.min

(0.5 ✕ tcyc-10)ns.min

td(BCLK-ALE)

(0.5 ✕ tcyc-25)ns.min

Address

25ns.max

tSU(DB-RD)

tac3(RD-DB)

(0.5 ✕ tcyc-10)ns.min

td(AD-RD)

0ns.min

tdZ(RD-AD)

8ns.max

td(AD-WR)

0ns.min

th(ALE-AD)

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : V

= 0.8 V, V

= 2.0 V

Output timing voltage : V

= 0.4 V, V

= 2.4 V

(1.5 ✕ tcyc-45)ns.max

(0.5 ✕ tcyc-10)ns.min

(0.5 ✕ tcyc-15)ns.min

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 305 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (T/V-ver.)

Figure 22.11 Timing Diagram (8)

Read timing

Write timing

Memory Expansion Mode and Microprocessor Mode

(For 3-wait setting, external area access and multiplexed bus selection)

BCLK

CSi

ALE

ADi

/DBi

ADi

BHE

BCLK

CSi

ALE

ADi

/DBi

tcyc

d(BCLK-AD)

25ns.max

tcyc

Data output

h(BCLK-CS)

4ns.min

d(BCLK-CS)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

25ns.max

h(BCLK-RD)

0ns.min

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

h(RD-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-AD)

4ns.min

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

h(BCLK-DB)

4ns.min

h(BCLK-WR)

0ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

d(BCLK-ALE)

25ns.max

d(BCLK-WR)

25ns.max

-4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

Data input

Address

ADi

BHE

WR, WRL

WRH

d(AD-ALE)

(0.5 ✕ tcyc-25)ns.min

d(AD-RD)

0ns.min

dZ(RD-AD)

8ns.max

ac3(RD-DB)

d(BCLK-DB)

40ns.max

(0.5 ✕ tcyc-10)ns.min

h(WR-CS)

d(AD-WR)

0ns.min

h(RD-CS)

(0.5 ✕ tcyc-10)ns.min

d(AD-ALE)

(0.5 ✕ tcyc-25)ns.min

(2.5 ✕ tcyc-45)ns.max

(no multiplex)

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : V

= 0.8 V, V

= 2.0 V

Output timing voltage : V

= 0.4 V, V

= 2.4 V

td(DB-WR)

(2.5 ✕ tcyc-40)ns.min

h(BCLK-ALE)

(0.5 ✕ tcyc-15)ns.min

th(ALE-AD)

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 306 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

22.2 Electrical Characteristics (Normal-ver.)

Table 22.26 Absolute Maximum Ratings

VCC

AVCC

Topr

Tstg

°C

Unit

Supply voltage (VCC1 = VCC2)

Analog supply voltage

Input

voltage

Output

voltage

Power dissipation

Operating ambient During MCU operation

temperature During flash memory program and

erase operation

Storage temperature

Symbol Parameter

_____________

RESET, CNVSS, BYTE,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,

P9_0, P9_2 to P9_7, P10_0 to P10_7,

VREF, XIN

P7_1, P9_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7, XOUT

P7_1, P9_1

Rated Value

–0.3 to 6.5

–0.3 to VCC+0.3

–0.3 to 6.5

–0.3 to VCC+0.3

–0.3 to 6.5

700

–40 to 85

0 to 60

–65 to 150

Condition

VCC = AVCC

Topr = 25°C

Rev.2.40 Apr 14, 2006 page 307 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Table 22.27 Recommended Operating Conditions (1) (1)

Supply voltage (VCC1 = VCC2)

Analog supply voltage

Supply voltage

Analog supply voltage

HIGH input

voltage

LOW input

voltage

HIGH peak

output current

HIGH average

output current

LOW peak

output current

LOW average

output current

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,

P7_0, P7_2 to P7_7, P8_0 to P8_7, P9_0, P9_2 to P9_7,

_____________

P10_0 to P10_7, XIN, RESET, CNVSS, BYTE

P7_1, P9_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(During single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(Data input during memory expansion and microprocessor modes)

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7,

P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

_____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(During single-chip mode)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(Data input during memory expansion and microprocessor modes)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,

P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0,

P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

5.0

VCC

3.0

0.8 VCC

0.5 VCC

5.5

VCC

6.5

VCC

0.2 VCC

0.16 VCC

–10.0

–5.0

10.0

5.0

VCC

AVCC

VSS

AVSS

VIH

VIL

IOH(peak)

IOH(avg)

IOL(peak)

IOL(avg)

ParameterSymbol Typ.Min.

Standard Unit

Max.

NOTES:

1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless otherwise specified.

2. Average output current values during 100 ms period.

3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, and P10 must be 80 mA max.

The total IOL(peak) for ports P3, P4, P5, P6, P7, and P8_0 to P8_4 must be 80 mA max.

The total IOH(peak) for ports P0, P1, and P2 must be –40 mA max.

The total IOH(peak) for ports P3, P4, and P5 must be –40 mA max.

The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be –40 mA max.

The total IOH(peak) for ports P8_6, P8_7, P9, and P10 must be –40 mA max.

Rev.2.40 Apr 14, 2006 page 308 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Table 22.28 Recommended Operating Conditions (2) (1)

Main clock input oscillation No wait Mask ROM version VCC = 3.0 to 5.5 V

frequency (2) (3) (4)

Flash memory version

Sub clock oscillation frequency

On-chip oscillation frequency

PLL clock oscillation frequency

CPU operation clock

VCC = 3.0 to 5.5 V

PLL frequency synthesizer stabilization wait time

Power supply ripple allowable frequency (VCC)

Power supply ripple allowable amplitude voltage VCC = 5 V

VCC = 3.3 V

Power supply ripple rising/falling gradient VCC = 5 V

VCC = 3.3 V

32.768

MHz

kHz

MHz

kHz

V/ms

0.5

0.3

f(XIN)

f(XCIN)

f(Ring)

f(PLL)

f(BCLK)

tsu(PLL)

f(ripple)

VP-P(ripple)

VCC(|∆V/∆T|)

ParameterSymbol Typ.Min.

Standard Unit

Max.

NOTES:

1. Referenced to VCC = 3.0 to 5.5 V at Topr = –40 to 85°C unless

otherwise specified.

2. Relationship between main clock oscillation frequency and supply

voltage is shown right.

3. Execute program/erase of flash memory by VCC = 3.3 ± 0.3 V or

VCC = 5.0 ± 0.5 V.

4. When using over 16 MHz, use PLL clock. PLL clock oscillation

frequency which can be used is 16 MHz, 20 MHz or 24 MHz.

0.0

16.0

5.53.0

VCC [V] (main clock: no division)

f(XIN) operating maximum frequency [MHz]

Main clock input oscillation frequency

(Mask ROM version / Flash memory

version: no wait)

f(ripple)

Power supply ripple allowable

frequency (VCC)

VP-P(ripple)

Power supply ripple allowable

amplitude voltage

Figure 22.12 Voltage Fluctuation Timing

(ripple)

P-P(ripple)

VCC

Rev.2.40 Apr 14, 2006 page 309 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Table 22.29 A/D Conversion Characteristics (1)

(NOTE 2)

1.0

1.5

Bits

µs

kΩ

Resolution

Absolute accuracy

Setup time

Output resistance

Reference power supply input current

–

tsu

IVREF

Symbol Parameter Min.

Standard Unit

Measuring Condition

Max.

Typ.

NOTES:

1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.

2. φAD frequency must be 10 MHz or less.

3. When sample & hold is disabled, φAD frequency must be 250 kHz or more in addition to a limit of NOTE 2.

When sample & hold is enabled, φAD frequency must be 1 MHz or more in addition to a limit of NOTE 2.

Table 22.30 D/A conversion Characteristics (1)

NOTES:

1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5 V, VSS = AVSS = 0 V, –40 to 85°C unless otherwise specified.

2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to 00h.

The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF

may have been set to be unconnected by the ADCON1 register.

±3

±7

±5

±7

±2

±3

±7

±5

±7

±2

±1

±3

VCC

VREF

Bit

LSB

kΩ

µs

3.3

2.8

0.3

2.0

VREF = VCC

VREF

= VCC

= 5 V

VREF

= VCC

= 3.3 V

VREF = AVCC = VCC = 5.0 V, 3.3 V

VREF

= VCC

= 5 V

VREF

= VCC

= 3.3 V

VREF = AVCC = VCC = 5.0 V, 3.3 V

VREF = VCC

VREF = VCC = 5 V, φAD = 10 MHz

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

ANEX0, ANEX1 input, AN0 to AN7 input,

AN0_0 to AN0_7 input, AN2_0 to AN2_7 input

External operation amp connection mode

Resolution

Integral 10 bits

nonlinearity

error

8 bits

Absolute 10 bits

accuracy

8 bits

Differential nonlinearity error

Offset error

Gain error

Resistor ladder

10-bit conversion time,

sample & hold available

8-bit conversion time,

sample & hold available

Sampling time

Reference voltage

Analog input voltage

–

INL

–

DNL

–

RLADDER

tCONV

tSAMP

VREF

VIA

Symbol Parameter Min.

Standard Unit

Measuring Condition Max.

Typ.

Rev.2.40 Apr 14, 2006 page 310 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

150

µs

Time for internal power supply stabilization during powering-on

STOP release time

Low power dissipation mode wait mode release time

td(P-R)

td(R-S)

td(W-S)

Symbol Parameter Min.

Standard Unit

Measuring

Condition Max.

Typ.

VCC = 3.0 to 5.5 V

Table 22.31 Power Supply Circuit Timing Characteristics

CPU clock

VCC

td(P-R)

Time for internal power supply

stabilization during powering-on

td(R-S)

STOP release time

td(W-S)

Low power dissipation mode

wait mode release time

CPU clock

td(W-S)

td(R-S)

(b)

(a)

Interrupt for

(a) Stop mode release

(b) Wait mode release

Figure 22.13 Power Supply Circuit Timing Diagram

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Table 22.32 Electrical Characteristics (1) (1)

-2.0

-0.3

3.0

0.2

2.0

2.5

1.6

1.5

HIGH output

voltage

HIGH output

voltage

HIGH output

voltage

HIGH output

voltage

LOW output

voltage

LOW output

voltage

LOW output

voltage

LOW output

voltage

Hysteresis

HIGH input

current

LOW input

current

Pull-up

resistance

Feedback resistance

RAM retention voltage

VOH

VOL

VT+-VT-

IIH

IIL

RPULLUP

RfXIN

RfXCIN

VRAM

IOH = –5 mA

IOH = –200 µA

IOH = –1 mA

IOH = –0.5 mA

With no load applied

IOL = 5 mA

IOL = 200 µA

IOL = 1 mA

IOL = 0.5 mA

With no load applied

VI = 5 V

VI = 0 V

At stop mode

µA

kΩ

MΩ

Measuring Condition

Standard

Min. Unit

VCC

2.0

0.45

2.0

1.0

2.5

5.0

–5.0

170

Parameter

Symbol

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

_________ _______

HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,

________ ________ _______ _____________ _________ _________

INT0 to INT5, NMI, ADTRG, CTS0 to CTS2,

SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,

_____ _____

TA0OUT to TA4OUT, KI0 to KI3,

RXD0 to RXD2, SIN3

_____________

RESET

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to

P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7

XIN

XCIN

Typ. Max.

NOTES:

1. Referenced to VCC = 4.2 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 312 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Table 22.33 Electrical Characteristics (2) (1)

Mask ROM f(BCLK) = 24 MHz,

PLL operation,

No division

On-chip oscillation,

No division

Flash memory f(BCLK) = 24 MHz,

PLL operation,

No division

On-chip oscillation,

No division

Flash memory f(BCLK) = 10 MHz,

program VCC = 5 V

Flash memory f(BCLK) = 10 MHz,

erase VCC = 5 V

Mask ROM f(BCLK) = 32 kHz,

Low power dissipation

mode, ROM (2)

Flash memory f(BCLK) = 32 kHz,

Low power dissipation

mode, RAM (2)

f(BCLK) = 32 kHz,

Low power dissipation

mode,

Flash memory (2)

Mask ROM On-chip oscillation,

Flash memory Wait mode

f(BCLK) = 32 kHz,

Wait mode (3),

Oscillation capacity High

f(BCLK) = 32 kHz,

Wait mode (3),

Oscillation capacity Low

Stop mode,

Topr = 25°C

NOTES:

1. Referenced to VCC = 3.0 to 5.5 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.

2. This indicates the memory in which the program to be executed exists.

3. With one timer operated using fC32.

1.8

420

8.5

3.0

0.8

Power supply

current

(VCC

= 3.0 to 5.5 V)

ICC mA

µA

Measuring Condition Standard

Min. Unit

3.0

ParameterSymbol

In single-chip mode,

the output pins are

open and other pins

are VSS.

Typ. Max.

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

External clock rise time

External clock fall time

Symbol Parameter Min.

Standard Unit

Max.

62.5

tw(H)

tw(L)

Timing Requirements

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.34 External Clock Input (XIN Input)

Table 22.35 Memory Expansion Mode and Microprocessor Mode

(NOTE 1)

(NOTE 2)

(NOTE 3)

Data input access time (for setting with no wait)

Data input access time (for setting with wait)

Data input access time (when accessing multiplexed bus area)

Data input setup time

________

RDY input setup time

__________

HOLD input setup time

Data input hold time

________

RDY input hold time

__________

HOLD input hold time

Symbol Parameter Min.

Standard Unit

Max.

tac1(RD-DB)

tac2(RD-DB)

tac3(RD-DB)

tsu(DB-RD)

tsu(RDY-BCLK)

tsu(HOLD-BCLK)

th(RD-DB)

th(BCLK-RDY)

th(BCLK-HOLD)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 45 [ns]

2. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 45 [ns]

n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 45 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 314 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Timing Requirements

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.36 Timer A Input (Counter Input in Event Counter Mode)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

100

Table 22.37 Timer A Input (Gating Input in Timer Mode)

tc(TA)

tw(TAH)

tw(TAL)

Table 22.38 Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 22.39 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 22.40 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

200

100

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

100

tw(TAH)

tw(TAL)

TAiOUT input cycle time

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup time

TAiOUT input hold time

Symbol Parameter Min.

Standard Unit

Max.

2000

1000

400

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

Table 22.41 Timer A Input (Two-phase Pulse Input in Event Counter Mode)

TAiIN input cycle rime

TAiOUT input setup time

TAiIN input setup time

Symbol Parameter Min.

Standard Unit

Max.

800

200

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

VCC = 5 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

TBiIN input cycle time (counted on one edge)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

Symbol Parameter Min.

Standard Unit

Max.

100

200

Table 22.43 Timer B Input (Pulse Period Measurement Mode)

tc(TB)

tw(TBH)

tw(TBL)

tc(TB)

tw(TBH)

tw(TBL)

Timing Requirements

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.42 Timer B Input (Counter Input in Event Counter Mode)

Table 22.44 Timer B Input (Pulse Width Measurement Mode)

Table 22.45 A/D Trigger Input

Table 22.46 Serial Interface

TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TB)

tw(TBH)

tw(TBL)

TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

400

200

tc(TB)

tw(TBH)

tw(TBL)

_____________

ADTRG input cycle time (trigger able minimum)

_____________

ADTRG input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

1000

125

tC(AD)

tw(ADL)

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

TXDi output delay time

TXDi hold time

RXDi input setup time

RXDi input hold time

Symbol Parameter Min.

Standard Unit

Max.

200

100

tc(CK)

tw(CKH)

tw(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

_______

Table 22.47 External Interrupt INTi Input

_______

INTi input HIGH pulse width

_______

INTi input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

250

tw(INH)

tw(INL)

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 316 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) (3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR) (3)

__________

HLDA output delay time

Symbol Parameter Min.

Standard Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.48 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 40 [ns]

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 kΩ, hold time of output “L” level is

t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

Figure 22.14 Port P0 to P10 Measurement Circuit

DBi

30 pF

P10

Measuring

Condition

Figure 22.14

f(BCLK) is 12.5 MHz or less.

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 317 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) (3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR) (3)

__________

HLDA output delay time

Symbol Parameter Min.

Standard Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.49

Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.

f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 kΩ, hold time of output “L” level is

t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

DBi

Measuring

Condition

Figure 22.14

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 318 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

(NOTE 1)

(NOTE 2)

(NOTE 1)

–4

(NOTE 3)

(NOTE 4)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

th(RD-CS)

th(WR-CS)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

td(BCLK-ALE)

th(BCLK-ALE)

td(AD-ALE)

th(ALE-AD)

td(AD-RD)

td(AD-WR)

tdZ(RD-AD)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

__________

HLDA output delay time

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of Address

WR signal output delay from the end of Address

Address output floating start time

Symbol Parameter Min.

Standard Unit

Max.

Switching Characteristics

(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.50 Memory Expansion Mode and Microprocessor Mode

(for 2- to 3-wait setting, external area access and multiplexed bus selection)

Measuring

Condition

Figure 22.14

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 40 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 25 [ns]

4. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 15 [ns]

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 319 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.15 Timing Diagram (1)

tsu(D—C)

CLKi

TXDi

RXDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C—Q) th(C—D)

th(C—Q)

INTi input

tc(TB)

tw(TBH)

tw(TBL)

tc(AD)

tw(ADL)

ADTRG input

TBiIN input

Two-phase pulse input in event counter mode

tsu(TAOUT—TAIN)

tsu(TAIN—TAOUT)

tC(TA)

tsu(TAIN—TAOUT)

TAiIN input

TAiOUT input

tc(TA)

tw(TAH)

tw(TAL)

tc(UP)

tw(UPH)

tw(UPL)

TAiIN input

TAiOUT input

During event counter mode

TAiIN input

(When count on falling edge

is selected)

TAiIN input

(When count on rising edge

is selected)

TAiOUT input

(Up/down input)

h(TIN—UP)

su(UP—TIN)

trtr

tw(H) tw(L)

XIN input

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 320 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.16 Timing Diagram (2)

Measuring conditions :

VCC = 5 V

Input timing voltage : Determined with VIL = 1.0 V, VIH = 4.0 V

Output timing voltage: Determined with VOL = 2.5 V, VOH = 2.5 V

BCLK

HOLD input

HLDA output

P0, P1, P2,

P3, P4,

P5_0 to P5_2 (1)

NOTE:

The above pins are set to high-impedance regardless of the input level of the BYTE pin,

the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.

Hi–Z

RDY input

BCLK

(Multiplexed bus)

WR, WRL, WRH

(Separate bus)

d(BCLK–HLDA)

h(BCLK–HOLD)

su(HOLD–BCLK)

tsu(RDY–BCLK) th(BCLK–RDY)

Memory Expansion Mode and Microprocessor Mode

(Effective for setting with wait)

(Common to setting with wait and setting without wait)

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 321 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.17 Timing Diagram (3)

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

25ns.max

ALE

25ns.max -4ns.min

25ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

Hi-Z

DBi

h(RD-DB)

0ns.min

h(RD-AD)

BHE

tcyc

Read timing

d(BCLK-AD)

d(BCLK-ALE)

h(BCLK-ALE)

SU(DB-RD)

d(BCLK-RD)

40ns.min

ac1(RD-DB)

Memory Expansion Mode and Microprocessor Mode

(For setting with no wait)

WR,WRL,

WRH

25ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

d(BCLK-ALE)

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

40ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

(0.5 ✕ tcyc-40)ns.min

h(WR-DB)

DBi

Write timing

d(BCLK-WR)

Hi-Z

(0.5 ✕ tcyc-45)ns.max

(0.5 ✕ tcyc-10)ns.min

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : V

= 0.8 V, V

= 2.0 V

Output timing voltage : V

= 0.4 V, V

= 2.4 V

(0.5 ✕ tcyc-10)ns.min

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 322 of 376

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M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.18 Timing Diagram (4)

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

h(BCLK-ALE)

-4ns.min

25ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

Hi-Z

DBi

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

tcyc

BHE

Read timing

WR,WRL,

WRH

25ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

d(BCLK-ALE)

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

40ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min

h(WR-DB)

DBi

Write timing

d(BCLK-ALE)

d(BCLK-RD)

d(BCLK-WR)

0ns.min

h(RD-AD)

ac2(RD-DB)

Hi-Z

Memory Expansion Mode and Microprocessor Mode

(For 1-wait setting and external area access)

(1.5 ✕ tcyc-45)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : VIL = 0.8 V, VIH = 2.0 V

Output timing voltage : VOL = 0.4 V, VOH = 2.4 V

(0.5 ✕ tcyc-10)ns.min

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 323 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.19 Timing Diagram (5)

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

Memory Expansion Mode and Microprocessor Mode

(For 2-wait setting and external area access)

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

25ns.max

Hi-Z

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

h(BCLK-RD)

0ns.min

h(RD-AD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

Hi-Z

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-WR)

25ns.max

h(BCLK-CS)

4ns.min

h(BCLK-AD)

4ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-WR)

0ns.min

d(BCLK-DB)

40ns.max

d(DB-WR)

(1.5 ✕ tcyc-40)ns.min

h(BCLK-DB)

4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

ac2(RD-DB)

(2.5 ✕ tcyc-45)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : V

= 0.8 V, V

= 2.0 V

Output timing voltage : V

= 0.4 V, V

= 2.4 V

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 324 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.20 Timing Diagram (6)

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

Memory Expansion Mode and Microprocessor Mode

(For 3-wait setting and external area access)

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

25ns.max

Hi-Z

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

h(BCLK-RD)

0ns.min

h(RD-AD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

Hi-Z

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-WR)

25ns.max

h(BCLK-CS)

4ns.min

h(BCLK-AD)

4ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-WR)

0ns.min

d(BCLK-DB)

40ns.max

d(DB-WR)

(2.5 ✕ tcyc-40)ns.min

h(BCLK-DB)

4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

ac2(RD-DB)

(3.5 ✕ tcyc-45)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : VIL = 0.8 V, VIH = 2.0 V

Output timing voltage : VOL = 0.4 V, VOH = 2.4 V

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 325 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.21 Timing Diagram (7)

Memory Expansion Mode and Microprocessor Mode

(For 1- or 2-wait setting, external area access and multiplexed bus selection)

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

h(BCLK-ALE)

-4ns.min

25ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(RD-CS)

h(RD-AD)

BHE

ADi

/DBi t

h(RD-DB)

0ns.min

d(AD-ALE)

Read timing

d(BCLK-WR)

25ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

25ns.max

ADi

d(BCLK-AD)

25ns.max

ALE

25ns.max

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

40ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

h(WR-DB)

ADi

/DBi

Data output

WR,WRL,

WRH

Write timing

Address

Data input

40ns.min

(0.5 ✕ tcyc-10)ns.min

d(BCLK-ALE)

d(BCLK-RD)

h(WR-CS)

Address

d(AD-ALE)

(0.5 ✕ tcyc-25)ns.min (1.5 ✕ tcyc-40)ns.min

(0.5 ✕ tcyc-10)ns.min

d(BCLK-ALE)

(0.5 ✕ tcyc-25)ns.min

Address

25ns.max

SU(DB-RD)

ac3(RD-DB)

(0.5 ✕ tcyc-10)ns.min

d(AD-RD)

0ns.min

dZ(RD-AD)

8ns.max

d(AD-WR)

0ns.min

h(ALE-AD)

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : VIL = 0.8 V, VIH = 2.0 V

Output timing voltage : VOL = 0.4 V, VOH = 2.4 V

(1.5 ✕ tcyc-45)ns.max

(0.5 ✕ tcyc-10)ns.min

(0.5 ✕ tcyc-15)ns.min

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 326 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.22 Timing Diagram (8)

Read timing

Write timing

Memory Expansion Mode and Microprocessor Mode

(For 3-wait setting, external area access and multiplexed bus selection)

BCLK

CSi

ALE

ADi

/DBi

ADi

BHE

BCLK

CSi

ALE

ADi

/DBi

tcyc

d(BCLK-AD)

25ns.max

tcyc

Data output

h(BCLK-CS)

4ns.min

d(BCLK-CS)

25ns.max

d(BCLK-ALE)

25ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

25ns.max

h(BCLK-RD)

0ns.min

SU(DB-RD)

40ns.min

h(RD-DB)

0ns.min

h(RD-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-AD)

4ns.min

d(BCLK-CS)

25ns.max

d(BCLK-AD)

25ns.max

h(BCLK-DB)

4ns.min

h(BCLK-WR)

0ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

d(BCLK-ALE)

25ns.max

d(BCLK-WR)

25ns.max

-4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

Data input

Address

ADi

BHE

WR, WRL

WRH

d(AD-ALE)

(0.5 ✕ tcyc-25)ns.min

d(AD-RD)

0ns.min

dZ(RD-AD)

8ns.max

ac3(RD-DB)

d(BCLK-DB)

40ns.max

(0.5 ✕ tcyc-10)ns.min

h(WR-CS)

d(AD-WR)

0ns.min

h(RD-CS)

(0.5 ✕ tcyc-10)ns.min

d(AD-ALE)

(0.5 ✕ tcyc-25)ns.min

(2.5 ✕ tcyc-45)ns.max

(no multiplex)

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 5 V

Input timing voltage : VIL = 0.8 V, VIH = 2.0 V

Output timing voltage : VOL = 0.4 V, VOH = 2.4 V

d(DB-WR)

(2.5 ✕ tcyc-40)ns.min

h(BCLK-ALE)

(0.5 ✕ tcyc-15)ns.min

h(ALE-AD)

VCC = 5 V

Rev.2.40 Apr 14, 2006 page 327 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Table 22.51 Electrical Characteristics (1)

-0.5

0.2

2.0

2.5

1.6

100

3.0

HIGH output

voltage

HIGH output

voltage

HIGH output

voltage

LOW output

voltage

LOW output

voltage

LOW output

voltage

Hysteresis

HIGH input

current

LOW input

current

Pull-up

resistance

Feedback resistance

RAM retention voltage

VOH

VOL

VT+-VT-

IIH

IIL

RPULLUP

RfXIN

RfXCIN

VRAM

IOH = –1 mA

IOH = –0.1 mA

IOH = –50 µA

With no load applied

IOL = 1 mA

IOL = 0.1 mA

IOL = 50 µA

With no load applied

VI = 3.3 V

VI = 0 V

At stop mode

µA

kΩ

MΩ

Measuring Condition

Standard

Min. Unit

VCC

0.5

0.8

1.8

4.0

–4.0

500

Parameter

Symbol

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0,

P9_2 to P9_7, P10_0 to P10_7

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7

XOUT HIGHPOWER

LOWPOWER

XCOUT HIGHPOWER

LOWPOWER

_________ _______

HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,

________ ________ _______ _____________ _________ _________

INT0 to INT5, NMI, ADTRG, CTS0 to CTS2,

SCL0 to SCL2, SDA0 to SDA2, CLK0 to CLK3,

_____ _____

TA0OUT to TA4OUT, KI0 to KI3,

RXD0 to RXD2, SIN3

_____________

RESET

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

____________

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to

P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,

P10_0 to P10_7

XIN

XCIN

Typ. Max.

NOTES:

1. Referenced to VCC = 3.0 to 3.6 V, VSS = 0 V at Topr = –40 to 85°C, f(BCLK) = 24 MHz unless otherwise specified.

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 328 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

External clock rise time

External clock fall time

Symbol Parameter Min.

Standard Unit

Max.

62.5

tw(H)

tw(L)

Timing Requirements

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.52 External Clock Input (XIN Input)

Table 22.53 Memory Expansion Mode and Microprocessor Mode

(NOTE 1)

(NOTE 2)

(NOTE 3)

Data input access time (for setting with no wait)

Data input access time (for setting with wait)

Data input access time (when accessing multiplexed bus area)

Data input setup time

________

RDY input setup time

__________

HOLD input setup time

Data input hold time

________

RDY input hold time

__________

HOLD input hold time

Symbol Parameter Min.

Standard Unit

Max.

tac1(RD-DB)

tac2(RD-DB)

tac3(RD-DB)

tsu(DB-RD)

tsu(RDY-BCLK)

tsu(HOLD-BCLK)

th(RD-DB)

th(BCLK-RDY)

th(BCLK-HOLD)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 60 [ns]

2. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 60 [ns]

n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 60 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 329 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Timing Requirements

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.54 Timer A Input (Counter Input in Event Counter Mode)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

150

Table 22.55 Timer A Input (Gating Input in Timer Mode)

tc(TA)

tw(TAH)

tw(TAL)

Table 22.56 Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 22.57 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 22.58 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

600

300

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

300

150

tc(TA)

tw(TAH)

tw(TAL)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

150

tw(TAH)

tw(TAL)

TAiOUT input cycle time

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup time

TAiOUT input hold time

Symbol Parameter Min.

Standard Unit

Max.

3000

1500

600

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

Table 22.59 Timer A Input (Two-phase Pulse Input in Event Counter Mode)

µs

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

Symbol Parameter Min.

Standard Unit

Max.

500

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 330 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

TBiIN input cycle time (counted on one edge)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

Symbol Parameter Min.

Standard Unit

Max.

150

300

120

Table 22.61 Timer B Input (Pulse Period Measurement Mode)

tc(TB)

tw(TBH)

tw(TBL)

tc(TB)

tw(TBH)

tw(TBL)

Timing Requirements

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85°C unless otherwise specified)

Table 22.60 Timer B Input (Counter Input in Event Counter Mode)

Table 22.62 Timer B Input (Pulse Width Measurement Mode)

Table 22.63 A/D Trigger Input

Table 22.64 Serial Interface

TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

600

300

tc(TB)

tw(TBH)

tw(TBL)

TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

600

300

tc(TB)

tw(TBH)

tw(TBL)

_____________

ADTRG input cycle time (trigger able minimum)

_____________

ADTRG input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

1500

200

tC(AD)

tw(ADL)

160

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

TXDi output delay time

TXDi hold time

RXDi input setup time

RXDi input hold time

Symbol Parameter Min.

Standard Unit

Max.

300

150

100

tc(CK)

tw(CKH)

tw(CKL)

td(C-Q)

th(C-Q)

tsu(D-C)

th(C-D)

_______

Table 22.65 External Interrupt INTi Input

_______

INTi input HIGH pulse width

_______

INTi input LOW pulse width

Symbol Parameter Min.

Standard Unit

Max.

380

tw(INH)

tw(INL)

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 331 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) (3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR) (3)

__________

HLDA output delay time

Symbol Parameter Min.

Standard Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.66 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 40 [ns]

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 kΩ, hold time of output “L” level is

t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

Figure 22.23 Port P0 to P10 Measurement Circuit

DBi

30 pF

P10

Measuring

Condition

Figure 22.23

f(BCLK) is 12.5 MHz or less.

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 332 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

td(BCLK-ALE)

th(BCLK-ALE)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

ALE signal output delay time

ALE signal output hold time

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK) (3)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR) (3)

__________

HLDA output delay time

Symbol Parameter Min.

Standard Unit

Max.

(NOTE 1)

–4

(NOTE 2)

(NOTE 1)

Switching Characteristics

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.67

Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

(n – 0.5) ✕ 109n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.

f(BCLK) – 40 [ns] When n = 1, f(BCLK) is 12.5 MHz or less.

3. This standard value shows the timing when the

output is off, and does not show hold time of

data bus.

Hold time of data bus varies with capacitor volume

and pull-up (pull-down) resistance value.

Hold time of data bus is expressed in

t = – CR ✕ ln (1 – VOL / VCC)

by a circuit of the right figure.

For example, when VOL = 0.2 VCC, C = 30 pF,

R =1 kΩ, hold time of output “L” level is

t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns.

DBi

Measuring

Condition

Figure 22.23

VCC = 3.3 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

(NOTE 1)

(NOTE 2)

(NOTE 1)

–4

(NOTE 3)

(NOTE 4)

td(BCLK-AD)

th(BCLK-AD)

th(RD-AD)

th(WR-AD)

td(BCLK-CS)

th(BCLK-CS)

th(RD-CS)

th(WR-CS)

td(BCLK-RD)

th(BCLK-RD)

td(BCLK-WR)

th(BCLK-WR)

td(BCLK-DB)

th(BCLK-DB)

td(DB-WR)

th(WR-DB)

td(BCLK-HLDA)

td(BCLK-ALE)

th(BCLK-ALE)

td(AD-ALE)

th(ALE-AD)

td(AD-RD)

td(AD-WR)

tdZ(RD-AD)

Address output delay time

Address output hold time (in relation to BCLK)

Address output hold time (in relation to RD)

Address output hold time (in relation to WR)

Chip select output delay time

Chip select output hold time (in relation to BCLK)

Chip select output hold time (in relation to RD)

Chip select output hold time (in relation to WR)

RD signal output delay time

RD signal output hold time

WR signal output delay time

WR signal output hold time

Data output delay time (in relation to BCLK)

Data output hold time (in relation to BCLK)

Data output delay time (in relation to WR)

Data output hold time (in relation to WR)

__________

HLDA output delay time

ALE signal output delay time (in relation to BCLK)

ALE signal output hold time (in relation to BCLK)

ALE signal output delay time (in relation to Address)

ALE signal output hold time (in relation to Address)

RD signal output delay from the end of Address

WR signal output delay from the end of Address

Address output floating start time

Symbol Parameter Min.

Standard Unit

Max.

Switching Characteristics

(Referenced to VCC = 3.3 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)

Table 22.68 Memory Expansion Mode and Microprocessor Mode

(for 2- to 3-wait setting, external area access and multiplexed bus selection)

Measuring

Condition

Figure 22.23

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 10 [ns]

2. Calculated according to the BCLK frequency as follows:

(n –0.5) ✕ 109

f(BCLK) – 50 [ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 40 [ns]

4. Calculated according to the BCLK frequency as follows:

0.5 ✕ 109

f(BCLK) – 15 [ns]

VCC = 3.3 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.24 Timing Diagram (1)

tsu(D—C)

CLKi

TXDi

RXDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C—Q) th(C—D)

th(C—Q)

INTi input

tc(TB)

tw(TBH)

tw(TBL)

tc(AD)

tw(ADL)

ADTRG input

TBiIN input

Two-phase pulse input in event counter mode

su(TAOUT—TAIN)

su(TAIN—TAOUT)

C(TA)

su(TAIN—TAOUT)

TAiIN input

TAiOUT input

tc(TA)

tw(TAH)

tw(TAL)

tc(UP)

tw(UPH)

tw(UPL)

TAiIN input

TAiOUT input

During event counter mode

TAiIN input

(When count on falling edge

is selected)

TAiIN input

(When count on rising edge

is selected)

TAiOUT input

(Up/down input)

h(TIN—UP)

su(UP—TIN)

trtr

tw(H) tw(L)

XIN input

VCC = 3.3 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.25 Timing Diagram (2)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : Determined with VIL = 0.6 V, VIH = 2.7 V

Output timing voltage: Determined with VOL = 1.65 V, VOH = 1.65 V

BCLK

HOLD input

HLDA output

P0, P1, P2,

P3, P4,

P5_0 to P5_2 (1)

NOTE:

The above pins are set to high-impedance regardless of the input level of the BYTE pin,

the PM06 bit in the PM0 register, and the PM11 bit in the PM1 register.

Hi–Z

RDY input

BCLK

(Multiplexed bus)

WR, WRL, WRH

(Separate bus)

d(BCLK–HLDA)

h(BCLK–HOLD)

su(HOLD–BCLK)

tsu(RDY–BCLK) th(BCLK–RDY)

Memory Expansion Mode and Microprocessor Mode

(Effective for setting with wait)

(Common to setting with wait and setting without wait)

VCC = 3.3 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.26 Timing Diagram (3)

BCLK

CSi

d(BCLK-CS)

30ns.max

ADi

30ns.max

ALE

30ns.max -4ns.min

30ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

Hi-Z

DBi

h(RD-DB)

0ns.min

h(RD-AD)

BHE

tcyc

Read timing

d(BCLK-AD)

d(BCLK-ALE)

h(BCLK-ALE)

SU(DB-RD)

d(BCLK-RD)

50ns.min

ac1(RD-DB)

Memory Expansion Mode and Microprocessor Mode

(For setting with no wait)

WR,WRL,

WRH

30ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

30ns.max

ADi

d(BCLK-AD)

30ns.max

ALE

30ns.max

d(BCLK-ALE)

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

40ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

(0.5 ✕ tcyc-40)ns.min

h(WR-DB)

DBi

Write timing

d(BCLK-WR)

Hi-Z

(0.5 ✕ tcyc-60)ns.max

(0.5 ✕ tcyc-10)ns.min

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : VIL = 0.6 V, VIH = 2.7 V

Output timing voltage : VOL = 1.65 V, VOH = 1.65 V

(0.5 ✕ tcyc-10)ns.min

VCC = 3.3 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.27 Timing Diagram (4)

BCLK

CSi

td(BCLK-CS)

30ns.max

ADi

td(BCLK-AD)

30ns.max

ALE

30ns.max

th(BCLK-ALE)

-4ns.min

30ns.max

th(BCLK-RD)

0ns.min

th(BCLK-AD)

4ns.min

th(BCLK-CS)

4ns.min

Hi-Z

DBi

tSU(DB-RD)

50ns.min

th(RD-DB)

0ns.min

tcyc

BHE

Read timing

WR,WRL,

WRH

30ns.max

th(BCLK-WR)

0ns.min

BCLK

CSi

td(BCLK-CS)

30ns.max

ADi

td(BCLK-AD)

30ns.max

ALE

30ns.max

td(BCLK-ALE) th(BCLK-ALE)

-4ns.min

th(BCLK-AD)

4ns.min

th(BCLK-CS)

4ns.min

tcyc

th(WR-AD)

BHE

td(BCLK-DB)

40ns.max 4ns.min

th(BCLK-DB)

td(DB-WR)

(0.5 ✕ tcyc-40)ns.min (0.5 ✕ tcyc-10)ns.min

th(WR-DB)

DBi

Write timing

td(BCLK-ALE)

td(BCLK-RD)

td(BCLK-WR)

0ns.min

th(RD-AD)

tac2(RD-DB)

Hi-Z

Memory Expansion Mode and Microprocessor Mode

(For 1-wait setting and external area access)

(1.5 ✕ tcyc-60)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : V

IL = 0.6 V, VIH = 2.7 V

Output timing voltage : VOL = 1.65 V, VOH = 1.65 V

(0.5 ✕ tcyc-10)ns.min

VCC = 3.3 V

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.28 Timing Diagram (5)

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

Memory Expansion Mode and Microprocessor Mode

(For 2-wait setting and external area access)

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

d(BCLK-CS)

30ns.max

d(BCLK-AD)

30ns.max

d(BCLK-ALE)

30ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

30ns.max

Hi-Z

SU(DB-RD)

50ns.min

h(RD-DB)

0ns.min

h(BCLK-RD)

0ns.min

h(RD-AD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

Hi-Z

d(BCLK-CS)

30ns.max

d(BCLK-AD)

30ns.max

d(BCLK-ALE)

30ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-WR)

30ns.max

h(BCLK-CS)

4ns.min

h(BCLK-AD)

4ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-WR)

0ns.min

d(BCLK-DB)

40ns.max

d(DB-WR)

(1.5 ✕ tcyc-40)ns.min

h(BCLK-DB)

4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

ac2(RD-DB)

(2.5 ✕ tcyc-60)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : VIL = 0.6 V, VIH = 2.7 V

Output timing voltage : VOL = 1.65 V, VOH = 1.65 V

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 339 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.29 Timing Diagram (6)

Read timing

Write timing

BCLK

CSi

ALE

DBi

ADi

BHE

WR, WRL

WRH

Memory Expansion Mode and Microprocessor Mode

(For 3-wait setting and external area access)

BCLK

CSi

ALE

DBi

ADi

BHE

tcyc

d(BCLK-CS)

30ns.max

d(BCLK-AD)

30ns.max

d(BCLK-ALE)

30ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-RD)

30ns.max

Hi-Z

SU(DB-RD)

50ns.min

h(RD-DB)

0ns.min

h(BCLK-RD)

0ns.min

h(RD-AD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

Hi-Z

d(BCLK-CS)

30ns.max

d(BCLK-AD)

30ns.max

d(BCLK-ALE)

30ns.max

h(BCLK-ALE)

-4ns.min

d(BCLK-WR)

30ns.max

h(BCLK-CS)

4ns.min

h(BCLK-AD)

4ns.min

h(WR-AD)

(0.5 ✕ tcyc-10)ns.min

h(BCLK-WR)

0ns.min

d(BCLK-DB)

40ns.max

d(DB-WR)

(2.5 ✕ tcyc-40)ns.min

h(BCLK-DB)

4ns.min

h(WR-DB)

(0.5 ✕ tcyc-10)ns.min

ac2(RD-DB)

(3.5 ✕ tcyc-60)ns.max

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : V

= 0.6 V, V

= 2.7 V

Output timing voltage : V

= 1.65 V, V

= 1.65 V

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 340 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.30 Timing Diagram (7)

Memory Expansion Mode and Microprocessor Mode

(For 2-wait setting, external area access and multiplexed bus selection)

BCLK

CSi

d(BCLK-CS)

40ns.max

ADi

d(BCLK-AD)

40ns.max

ALE

h(BCLK-ALE)

-4ns.min

40ns.max

h(BCLK-RD)

0ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(RD-CS)

h(RD-AD)

BHE

ADi

/DBi t

h(RD-DB)

0ns.min

d(AD-ALE)

Read timing

d(BCLK-WR)

40ns.max

h(BCLK-WR)

0ns.min

BCLK

CSi

d(BCLK-CS)

40ns.max

ADi

d(BCLK-AD)

40ns.max

ALE

40ns.max

h(BCLK-ALE)

-4ns.min

h(BCLK-AD)

4ns.min

h(BCLK-CS)

4ns.min

tcyc

h(WR-AD)

BHE

d(BCLK-DB)

50ns.max 4ns.min

h(BCLK-DB)

d(DB-WR)

h(WR-DB)

ADi

/DBi

Data output

WR,WRL,

WRH

Write timing

Address

Data input

50ns.min

(0.5 ✕ tcyc-10)ns.min

d(BCLK-ALE)

d(BCLK-RD)

h(WR-CS)

Address

d(AD-ALE)

(0.5 ✕ tcyc-40)ns.min (1.5 ✕ tcyc-50)ns.min

(0.5 ✕ tcyc-10)ns.min

d(BCLK-ALE)

(0.5 ✕ tcyc-40)ns.min

Address

40ns.max

SU(DB-RD)

ac3(RD-DB)

(0.5 ✕ tcyc-10)ns.min

d(AD-RD)

0ns.min

dZ(RD-AD)

8ns.max

d(AD-WR)

0ns.min

h(ALE-AD)

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : VIL = 0.6 V, VIH = 2.7 V

Output timing voltage : VOL = 1.65 V, VOH = 1.65 V

(1.5 ✕ tcyc-60)ns.max

(0.5 ✕ tcyc-10)ns.min

(0.5 ✕ tcyc-15)ns.min

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 341 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 22. Electric Characteristics (Normal-ver.)

Figure 22.31 Timing Diagram (8)

Read timing

Write timing

Memory Expansion Mode and Microprocessor Mode

(For 3-wait setting, external area access and multiplexed bus selection)

BCLK

CSi

ALE

ADi

/DBi

ADi

BHE

BCLK

CSi

ALE

ADi

/DBi

tcyc

td(BCLK-AD)

40ns.max

tcyc

Data output

th(BCLK-CS)

6ns.min

td(BCLK-CS)

40ns.max

td(BCLK-ALE)

40ns.max th(BCLK-ALE)

-4ns.min

td(BCLK-RD)

40ns.max

th(BCLK-RD)

0ns.min

tSU(DB-RD)

50ns.min

th(RD-DB)

0ns.min

th(RD-AD)

(0.5 ✕ tcyc-10)ns.min

th(BCLK-AD)

4ns.min

td(BCLK-CS)

40ns.max

td(BCLK-AD)

40ns.max

th(BCLK-DB)

4ns.min

th(BCLK-WR)

0ns.min

th(WR-AD)

(0.5 ✕ tcyc-10)ns.min

th(BCLK-AD)

4ns.min

th(BCLK-CS)

4ns.min

td(BCLK-ALE)

40ns.max

td(BCLK-WR)

40ns.max

-4ns.min

th(WR-DB)

(0.5 ✕ tcyc-10)ns.min

Data input

Address

ADi

BHE

WR, WRL

WRH

td(AD-ALE)

(0.5 ✕ tcyc-40)ns.min

td(AD-RD)

0ns.min

tdZ(RD-AD)

8ns.max tac3(RD-DB)

td(BCLK-DB)

50ns.max

(0.5 ✕ tcyc-10)ns.min

th(WR-CS)

td(AD-WR)

0ns.min

th(RD-CS)

(0.5 ✕ tcyc-10)ns.min

td(AD-ALE)

(0.5 ✕ tcyc-40)ns.min

(2.5 ✕ tcyc-60)ns.max

(no multiplex)

tcyc = 1

f(BCLK)

Measuring conditions :

VCC = 3.3 V

Input timing voltage : VIL = 0.6 V, VIH = 2.7 V

Output timing voltage : VOL = 1.65 V, VOH = 1.65 V

td(DB-WR)

(2.5 ✕ tcyc-50)ns.min

h(BCLK-ALE)

(0.5 ✕ tcyc-15)ns.min

th(ALE-AD)

VCC = 3.3 V

Rev.2.40 Apr 14, 2006 page 342 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23. Usage Notes

23.1 SFRs

There are the SFRs with write-only bits which can only be written to. Set these registers with undefined

values. When establishing the next value by altering the present value, write the present value to the RAM

as well as to the register. Transfer the next value to the register after making changes in the RAM.

Table 23.1 lists Registers with Write-only Bits.

Table 23.1 Registers with Write-only Bits

Watchdog Timer Start Register WDTS 000Eh

Timer A1-1 Register TA11 01C3h, 01C2h

Timer A2-1 Register TA21 01C5h, 01C4h

Timer A4-1 Register TA41 01C7h, 01C6h

Dead Time Timer DTT 01CCh

Timer B2 Interrupt Generation Frequency Set Counter

ICTB2 01CDh

SI/O3 Bit Rate Register S3BRG 01E3h

UART2 Bit Rate Register U2BRG 01F9h

UART2 Transmit Buffer Register U2TB 01FBh, 01FAh

Up-Down Flag UDF 0384h

Timer A0 Register TA0 0387h, 0386h

Timer A1 Register TA1 0389h, 0388h

Timer A2 Register TA2 038Bh, 038Ah

Timer A3 Register TA3 038Dh, 038Ch

Timer A4 Register TA4 038Fh, 038Eh

UART0 Bit Rate Register U0BRG 03A1h

UART0 Transmit Buffer Register U0TB 03A3h, 03A2h

UART1 Bit Rate Register U1BRG 03A9h

UART1 Transmit Buffer Register U1TB 03ABh, 03AAh

Rev.2.40 Apr 14, 2006 page 343 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.2 External Bus

When resetting CNVSS pin with “H” input, contents of internal ROM cannot be read out.

Rev.2.40 Apr 14, 2006 page 344 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.3 PLL Frequency Synthesizer

Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 22. Electrical

Characteristics.)

Rev.2.40 Apr 14, 2006 page 345 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.4 Power Control

•

____________

When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized.

• Set the MR0 bit in the TAiMR register (i = 0 to 4) to 0 (pulse is not output) to use the timer A to exit stop

mode.

• When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not execute any

instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the

DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT

instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue roadstead

the instructions following WAIT, and depending on timing, some of these may execute before the

MCU enters wait mode.

Program example when entering wait mode

Program Example: JMP.B L1 ; Insert JMP.B instruction before WAIT instruction

L1:

FSET I ;

WAIT ; Enter wait mode

NOP ; More than 4 NOP instructions

NOP

• When entering stop mode, describe as follows.

(1) To use the BSET instruction for entering stop mode:

Write the BSET instruction (BSET bit, base:16) as described below.

When entering stop mode, DMA transfer must be disabled.

BSET 0,CM1 ; Stop mode setting [bit, base:16]

JMP.B L1 ;

L1:

NOP ; Countermeasure to avoid the program from

NOP ; stopping by reading instruction ahead

NOP ; (insert 4 or more NOPs)

NOP ;

(2) To use the MOV instruction for entering stop mode:

Write the MOV instruction (MOV.B #IMM8, abs16) as described below.

When entering stop mode, DMA transfer must be disabled.

Change the

src

value (marked as “#21”), depending on your usage condition.

MOV.B #21H,CM1 ; Stop mode setting [#IMM8, abs16]

JMP.B L1 ;

L1:

NOP ; Countermeasure to avoid the program from

NOP ; stopping by reading instruction ahead

NOP ; (insert 4 or more NOPs)

NOP ;

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REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

•When entering medium-speed mode after transferring to stop mode from low-speed mode and low

power dissipation mode, write the MOV instruction (MOV.W #IMM16, abs16) as described below.

When entering stop mode and exiting from stop mode, DMA transfer must be disabled.

Change the

src

value (marked as “#2118”) depending on your usage condition.

MOV.W #2118H,CM0 ; Stop mode setting [#IMM16, abs16]

JMP.S L1 ;

L1:

NOP ; Countermeasure to avoid the program from

NOP ; stopping by reading instruction ahead

NOP ; (insert 4 or more NOPs)

NOP ;

•Wait until the main clock oscillation stabilizes, before switching the clock source for CPU clock to the main

clock.

Similarly, wait until the sub clock oscillation stabilizes, before switching the clock source for CPU clock to

the sub clock.

•Suggestions to reduce power consumption.

Ports

The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.

A current flows in active I/O ports. A pass current flows in input ports that high-impedance state.

When entering wait mode or stop mode, set non-used ports to input and stabilize the potential.

A/D converter

When A/D conversion is not performed, set the VCUT bit in the ADCON1 register to 0 (VREF not connection).

When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after setting the VCUT

bit to 1 (VREF connection).

D/A converter

When not performing D/A conversion, set the DAiE bit (i = 0, 1) in the DACON register to 0 (input

disabled) and DAi register to 00h.

Stopping peripheral functions

Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions during wait mode.

However, because the peripheral function clock (fC32) generated from the sub-clock does not stop, this

measure is not conducive to reducing the power consumption of the chip. If low speed mode or low power

dissipation mode is to be changed to wait mode, set the CM02 bit to 0 (do not peripheral function clock

stopped when in wait mode), before changing wait mode.

Switching the oscillation-driving capacity

Set the driving capacity to “LOW” when oscillation is stable.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.5 Protection

Set the PRC2 bit in the PRCR register to 1 (write enabled) and then write to given address, and the PRC2

bit will be set to 0 (write protected). The registers protected by the PRC2 bit should be changed in the next

instruction after setting the PRC2 bit to 1. Make sure no interrupts or no DMA transfers will occur between the

instruction in which the PRC2 bit is set to 1 and the next instruction.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.6 Interrupts

23.6.1 Reading Address 00000h

Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU

reads interrupt information (interrupt number and interrupt request priority level) from the address

00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to 0.

If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among

the enabled interrupts is set to 0. This causes a problem that the interrupt is canceled, or an unexpected

interrupt request is generated.

23.6.2 Setting SP

Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to 0000h after

reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the program

may go out of control. _______

Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first

_______

and only the first instruction after reset, all interrupts including NMI interrupt are disabled.

_______

23.6.3 NMI Interrupt

•

_______ _______

The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a

resistor (pull-up).

•

_______

The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the

_______

P8_5 bit can only be read when determining the pin level in NMI interrupt routine.

•

_______

Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the

_______

NMI pin is low the CM10 bit in the CM1 register is fixed to 0.

•

_______ _______

Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin

goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip

does not drop. In this case, normal condition is restored by an interrupt generated thereafter.

•

_______

The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +

300 ns or more.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.6.4 Changing Interrupt Source

If the interrupt source is changed, the IR bit in the interrupt control register for the changed interrupt may

inadvertently be set to 1 (interrupt requested). If you changed the interrupt source for an interrupt that

needs to be used, be sure to set the IR bit for that interrupt to 0 (interrupt not requested).

Changing the interrupt source referred to here means any act of changing the source, polarity or timing of

the interrupt assigned to each software interrupt number. Therefore, if a mode change of any peripheral

function involves changing the source, polarity or timing of an interrupt, be sure to set the IR bit for that

interrupt to 0 (interrupt not requested) after making such changes. Refer to the description of each peripheral

function for details about the interrupts from peripheral functions.

Figure 23.1 shows the Procedure for Changing Interrupt Source.

Figure 23.1 Procedure for Changing Interrupt Source

_____

23.6.5 INT Interrupt

•Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal

________ ________

input to pins INT0 to INT5 regardless of the CPU operation clock.

•If the POL bit in registers INT0IC to INT5IC or bits IFSR10 to IFSR17 in the IFSR1 register are changed,

the IR bit may inadvertently set to 1 (interrupt requested). Be sure to set the IR bit to 0 (interrupt not

requested) after changing any of those register bits.

Changing the interrupt source

Disable interrupt

(2) (3)

Use the MOV instruction to set the IR bit to 0

(interrupt not requested)

(3)

Change the interrupt source

(including a mode change of peripheral function)

Enable interrupt

(2) (3)

End of change

IR bit: A bit in the interrupt control register for the interrupt whose interrupt source is to be

changed

NOTES:

1.The above settings must be executed individually. Do not execute two or more settings

simultaneously (using one instruction).

2.Use the I flag for the INTi interrupt (i = 0 to 5).

For the interrupts from peripheral functions other than the INTi interrupt, turn off the

peripheral function that is the interrupt source in order not to generate an interrupt request

before changing the interrupt source. In this case, if the maskable interrupts can all be

disabled without causing a problem, use the I flag. Otherwise, if it is not possible to disable

all maskable interrupts, use bits ILVL2 to ILVL0 of the interrupt whose source is changed.

3.Refer to 23.6.6 Rewrite Interrupt Control Register for details about the instructions to

use and the notes to be taken for instruction execution.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.6.6 Rewrite Interrupt Control Register

(a) The interrupt control register for any interrupt should be modified in places where no requests for that

interrupt may be generated. Otherwise, disable the interrupt before rewriting the interrupt control register.

(b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, care must be

taken when selecting the instructions.

Changing any bit other than IR bit

If while executing an instruction, an interrupt request controlled by the register being modified is

generated, the IR bit of the register may not be set to 1 (interrupt requested), with the result that the

interrupt request is ignored. If such a situation presents a problem, use the instructions shown

below to modify the register.

Usable instructions: AND, OR, BCLR, BSET

Changing IR bit

Depending on the instruction used, the IR bit may not always be set to 0 (interrupt not requested).

Therefore, be sure to use the MOV instruction to set the IR bit to 0.

as you set the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the

sample program fragments.)

Examples 1 through 3 show how to prevent the I flag from being set to 1 (interrupt enabled) before the

interrupt control register is rewritten, owing to the effects of the internal bus and the instruction queue

buffer.

Example 1: Using the NOP instruction to keep the program waiting until the interrupt control register is modified

INT_SWITCH1:

FCLR I ; Disable interrupts.

AND.B #00h, 0055h ; Set the TA0IC register to 00h.

NOP ;

NOP

FSET I ; Enable interrupts.

The number of the NOP instruction is as follows.

• The PM20 bit in the PM2 register = 1 (1 wait) : 2

• The PM20 bit = 0 (2 waits) : 3

• When using HOLD function : 4

Example 2: Using the dummy read to the FSET instruction delay

INT_SWITCH2:

FCLR I ; Disable interrupts.

AND.B #00h, 0055h ; Set the TA0IC register to 00h.

MOV.W MEM, R0 ; Dummy read.

FSET I ; Enable interrupts.

Example 3: Using the POPC instruction to changing the I flag

INT_SWITCH3:

PUSHC FLG

FCLR I ; Disable interrupts.

AND.B #00h, 0055h ; Set the TA0IC register to 00h.

POPC FLG ; Enable interrupts.

23.6.7 Watchdog Timer Interrupt

Initialize the watchdog timer after the watchdog timer interrupt request is generated.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.7 DMAC

23.7.1 Write to DMAE Bit in DMiCON Register (i = 0, 1)

When both of the conditions below are met, follow the steps below.

Conditions

• The DMAE bit is set to 1 again while it remains set (DMAi is in an active state).

• A DMA request may occur simultaneously when the DMAE bit is being written.

Step 1: Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1).

Step 2: Make sure that the DMAi is in an initial state (2) in a program.

If the DMAi is not in an initial state, the above steps should be repeated.

NOTES:

1. The DMAS bit remains unchanged even if 1 is written. However, if 0 is written to this bit, it is set to 0

(DMA not requested). In order to prevent the DMAS bit from being modified to 0, 1 should be written

to the DMAS bit when 1 is written to the DMAE bit. In this way the state of the DMAS bit immediately

before being written can be maintained.

Similarly, when writing to the DMAE bit with a read-modify-write instruction, 1 should be written to

the DMAS bit in order to maintain a DMA request which is generated while the instruction is being

executing.

2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to

a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial

state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register

is 1.) If the read value is a value in the middle of transfer, the DMAi is not in an initial state.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.8 Timers

23.8.1 Timer A

23.8.1.1 Timer A (Timer Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i =

0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to 1 (count starts).

Always make sure the TAiMR register is modified while the TAiS bit remains 0 (count stops) regardless

whether after reset or not.

While counting is in progress, the counter value can be read out at any time by reading the TAi register.

However, if the counter is read at the same time it is reloaded, the value FFFFh is read. Also, if the

counter is read before it starts counting after a value is set in the TAi register while not counting, the set

value is read.

______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

______

output forcible cutoff by input on NMI pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to a

high-impedance state.

23.8.1.2 Timer A (Event Counter Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH in the ONSF

Always make sure the TAiMR register, the UDF register, bits TAZIE, TA0TGL, and TA0TGH, and the

TRGSR register are modified while the TAiS bit remains 0 (count stops) regardless whether after reset or

not.

While counting is in progress, the counter value can be read out at any time by reading the TAi register.

However, FFFFh can be read in underflow, while reloading, and 0000h in overflow. When setting the TAi

Also, if the counter is read before it starts counting after a value is set in the TAi register while not

counting, the set value is read.

______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

______

output forcible cutoff by input on NMI pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to a

high-impedance state.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.8.1.3 Timer A (One-shot Timer Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, and the TRGSR

Always make sure the TAiMR register, bits TA0TGL and TA0TGH, and the TRGSR register are modified

while the TAiS bit remains 0 (count stops) regardless whether after reset or not.

When setting the TAiS bit to 0 (count stops), the followings occur:

• A counter stops counting and a content of reload register is reloaded.

• TAiOUT pin outputs “L”.

• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to 1 (interrupt request).

Output in one-shot timer mode synchronizes with a count source internally generated. When an external

trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger

input to TAiIN pin and output in one-shot timer mode.

The IR bit is set to 1 when timer operating mode is set with any of the following procedures:

• Select one-shot timer mode after reset.

•Change an operating mode from timer mode to one-shot timer mode.

• Change an operating mode from event counter mode to one-shot timer mode.

To use the timer Ai interrupt (the IR bit), set the IR bit to 0 after the changes listed above have been

made.

When a trigger occurs, while counting, a counter reloads the reload register to continue counting after

generating a re-trigger and counting down once. To generate a trigger while counting, generate a second

trigger between occurring the previous trigger and operating longer than one cycle of a timer count

source.

______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

______

output forcible cutoff by input on NMI pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to a

high-impedance state.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.8.1.4 Timer A (Pulse Width Modulation (PWM) Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, bits TA0TGL and TA0TGH in the ONSF register, and the TRGSR

Always make sure the TAiMR register, bits TA0TGL and TA0TGH, and the TRGSR register are modified

while the TAiS bit remains 0 (count stops) regardless whether after reset or not.

The IR bit is set to 1 when setting a timer operating mode with any of the following procedures:

• Select the PWM mode after reset.

•Change an operating mode from timer mode to PWM mode.

•Change an operating mode from event counter mode to PWM mode.

To use the timer Ai interrupt (the IR bit), set the IR bit to 0 by program after the above listed changes

have been made.

When setting TAiS bit to 0 (count stops) during PWM pulse output, the following action occurs:

• Stop counting.

• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to 1.

• When TAiOUT pin is output “L”, both output level and the IR bit remain unchanged.

______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

______

output forcible cutoff by input on NMI pin enabled), pins TA1OUT, TA2OUT, and TA4OUT go to a

high-impedance state.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.8.2 Timer B

23.8.2.1 Timer B (Timer Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR

(i = 0 to 5) register and TBi register before setting the TBiS bit (1) in the TABSR or the TBSR register to

1 (count starts).

Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regardless

whether after reset or not.

NOTE:

1. Bits TB0S to TB2S are the bits 5 to 7 in the TABSR register, bits TB3S to TB5S are the bits 5 to 7

in the TBSR register.

A value of a counter, while counting, can be read in the TBi register at any time. FFFFh is read while

reloading. Setting value is read between setting values in the TBi register at count stop and starting a

counter.

23.8.2.2 Timer B (Event Counter Mode)

The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR

(i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to 1

(count starts).

Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regardless

whether after reset or not.

The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this

read value is the one that has been set in the register.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.8.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)

The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register

before setting the TBiS bit in the TABSR or TBSR register to 1 (count starts).

Always make sure the TBiMR register is modified while the TBiS bit remains 0 (count stops) regardless

whether after reset or not. To set the MR3 bit to 0 by writing to the TBiMR register while the TBiS bit = 1

(count starts), be sure to write the same value as previously written to bits TM0D0, TM0D1, MR0, MR1,

TCK0, and TCK1 and, a 0 to the MR2 bit.

The IR bit in the TBiIC register goes to 1 (interrupt request), when an effective edge of a measurement

pulse is input or timer Bi is overflowed. The interrupt source can be determined by use of the MR3 bit in

the TBiMR register within the interrupt routine.

If the interrupt source cannot be identified by the MR3 bit such as when the measurement pulse input

and a timer overflow occur at the same time, use another timer to count the number of times timer B has

overflowed.

To set the MR3 bit to 0 (no overflow), set the TBiMR register with setting the TBiS bit to 1 and counting

the next count source after setting the MR3 bit to 1 (overflow).

Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the

interrupt source.

When a count is started and the first effective edge is input, an undefined value is transferred to the

reload register. At this time, timer Bi interrupt request is not generated.

A value of the counter is undefined at the beginning of a count. The MR3 bit may be set to 1 and timer Bi

interrupt request may be generated between a count start and an effective edge input.

For pulse width measurement, pulse widths are successively measured. Use program to check whether

the measurement result is an “H” level width or an “L” level width.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.9 Serial Interface

23.9.1 Clock Synchronous Serial I/O Mode

23.9.1.1 Transmission/reception _______ ________

With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to

“L” when the data-receivable status becomes ready, which informs the transmission side that the reception

________ ________

has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi pin

________

is connected to the CTSi pin on the transmission side, the circuit can transmission and reception data

_______

with consistent timing. With the internal clock, the RTS function has no effect.

_______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

_______ _________

output forcible cutoff by input on NMI pin enabled), pins RTS2 and CLK2 go to a high-impedance state.

23.9.1.2 Transmission

When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0

transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the

rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in

the low state.

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in UiTB register)

_______ ________

• If CTS function is selected, input on the CTSi pin = L

23.9.1.3 Reception

In operating the clock synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings

for transmission even when using the device only for reception. Dummy data is output to the outside

from the TXDi (i = 0 to 2) pin when receiving data.

When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission

enabled) and write dummy data to the UiTB register, and the shift clock will thereby be generated. When

an external clock is selected, set the TE bit to 1 and write dummy data to the UiTB register, and the shift

clock will be generated when the external clock is fed to the CLKi input pin.

When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive

occurs and the OER bit in the UiRB register is set to 1 (overrun error occurred). In this case, because the

content of the UiRB register is undefined, a corrective measure must be taken by programs on the

transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted.

Note that when an overrun error occurred, the IR bit in the SiRIC register does not change state.

To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time

reception is made.

When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external

clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.

• The RE bit in the UiC1 register = 1 (reception enabled)

• The TE bit in the UiC1 register = 1 (transmission enabled)

• The TI bit in the UiC1 register = 0 (data present in the UiTB register)

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.9.2 Special Modes

23.9.2.1 Special Mode 1 (I2C Mode)

When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to 0

(start and stop conditions not output) and wait for more than half cycle of the transfer clock before setting

each condition generate bit (bits STAREQ, RSTAREQ, and STPREQ) from 0 (clear) to 1 (start).

23.9.2.2 Special Mode 2 _______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

_______ _________

output forcible cutoff by input on NMI pin enabled), pins RTS2 and CLK2 go to a high-impedance state.

23.9.2.3 Special Mode 4 (SIM Mode)

A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 (transmission

completed) and U2ERE bit in the U2C1 register to 1 (error signal output) after reset. Therefore, when

using SIM mode, be sure to set the IR bit to 0 (no interrupt request) after setting these bits.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.9.3 SI/O3

The SOUT3 default value which is set to the SOUT3 pin by the SM37 in the S3C register bit approximately

10 ns may be output when changing the SM33 bit in the S3C register from 0 (I/O port) to 1 (SOUT3 output

and CLK3 function) while the SM32 bit in the S3C register to 0 (SOUT3 output) and the SM36 bit is set to

1 (internal clock). And then the SOUT3 pin is held high-impedance.

If the level which is output from the SOUT3 pin is a problem when changing the SM33 bit from 0 to 1, set

the default value of the SOUT3 pin by the SM37 bit.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.10 A/D Converter

Set the ADCON0 (except bit 6), registers ADCON1 and ADCON2 when A/D conversion is stopped (before

a trigger occurs). After stopping A/D conversion, the VCUT bit in the ADCON1 register is changed from 1

(VREF connected) to 0 (VREF not connected),

When the VCUT bit is changed from 0 to 1, start A/D conversion after passing 1 µs or longer.

To prevent noise-induced device malfunction or latch-up, as well as to reduce conversion errors, insert

capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0_i, and AN2_i) each and

the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin.

Figure 23.2 shows the Use of Capacitors to Reduce Noise.

Make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode).

Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the

__________

ADTRG pin is set to 0 (input mode).

When using key input interrupt, do not use any of four pins AN4 to AN7 as analog inputs. (A key input

interrupt request is generated when the A/D input voltage goes low.)

The φAD frequency must be 10 MHz or less. Without sample and hold, limit the φAD frequency to 250 kHz

or more. With the sample and hold, limit the φAD frequency to 1 MHz or more.

When changing an A/D operating mode, select analog input pin again in bits CH2 to CH0 in the ADCON0

Figure 23.2 Use of Capacitors to Reduce Noise

VCC

VSS

C1 C2

MCU

ANi: ANi, AN0_i, and AN2_i (i =0 to 7)

NOTES:

1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference).

2. Use thick and shortest possible wiring to connect capacitors.

AVCC

AVSS

VREF

ANi

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M16C/6N Group (M16C/6N4) 23. Usage Notes

If the CPU reads the ADi register (i = 0, 1) at the same time the conversion result is stored in the ADi register

after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem

occurs when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock.

•When operating in one-shot or single-sweep mode

Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit in

the ADIC register to see if A/D conversion is completed.)

•When operating in repeat mode or repeat sweep mode 0 or 1

Use the main clock for CPU clock directly without dividing it.

If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to

0 (A/D conversion halted), the conversion result of the A/D converter is undefined. The contents of ADi

ADST bit is set to 0 in a program, ignore the values of all ADi registers.

When setting the ADST bit to 0 in single sweep mode during A/D conversion and A/D conversion is aborted,

disable the interrupt before setting the ADST bit to 0.

The applied intermediate potential may cause more increase in power consumption than other analog input

______

pins (AN0 to AN3, AN0_0 to AN0_7, and AN2_0 to AN2_7), since the AN4 to AN7 are used with the KI0 to

______

KI3.

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M16C/6N Group (M16C/6N4) 23. Usage Notes

23.11 CAN Module

23.11.1 Reading CiSTR Register (i = 0, 1)

The CAN module on the M16C/6N Group (M16C/6N4) updates the status of the CiSTR register in a

certain period. When the CPU and the CAN module access to the CiSTR register at the same time, the

CPU has the access priority; the access from the CAN module is disabled. Consequently, when the

updating period of the CAN module matches the access period from the CPU, the status of the CAN

module cannot be updated. (See Figure 23.3 When Updating Period of CAN Module Matches Access

Period from CPU.)

Accordingly, be careful about the following points so that the access period from the CPU should not

match the updating period of the CAN module:

(a) There should be a wait time of 3fCAN or longer (see Table 23.2 CAN Module Status Updating

Period) before the CPU reads the CiSTR register. (See Figure 23.4 With Wait Time of 3 fCAN

before CPU Read.)

(b) When the CPU polls the CiSTR register, the polling period must be 3 fCAN or longer. (See Figure 23.5

When Polling Period of CPU is 3 fCAN or Longer.)

Table 23.2 CAN Module Status Updating Period

3fCAN Period = 3 ✕ XIN (Original Oscillation Period) ✕ Division Value of CAN Clock (CCLK)

(Example 1) Condition XIN 16 MHz CCLK: Divide-by-1 3 fCAN period = 3 ✕ 62.5 ns ✕ 1 = 187.5 ns

(Example 2) Condition XIN 16 MHz CCLK: Divide-by-2 3 fCAN period = 3 ✕ 62.5 ns ✕ 2 = 375 ns

(Example 3) Condition XIN 16 MHz CCLK: Divide-by-4 3 fCAN period = 3 ✕ 62.5 ns ✕ 4 = 750 ns

(Example 4) Condition XIN 16 MHz CCLK: Divide-by-8 3 fCAN period = 3 ✕ 62.5 ns ✕ 8 = 1.5 µs

(Example 5) Condition XIN 16 MHz CCLK: Divide-by-16 3 fCAN period = 3 ✕ 62.5 ns ✕ 16 = 3 µs

Rev.2.40 Apr 14, 2006 page 363 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

Figure 23.3 When Updating Period of CAN Module Matches Access Period from CPU

fCAN

✕✕✕ ✕✕

CPU read signal

CPU reset signal

Updating period of

CAN module

CiSTR register

b8: State_Reset bit

i = 0, 1

0: CAN operation

mode

1: CAN reset/initial-

ization mode

✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read

period, it does not enter reset mode, for the CPU read has the higher priority.

Figure 23.4 With Wait Time of 3 fCAN before CPU Read

Figure 23.5 When Polling Period of CPU is 3 fCAN or Longer

: Updated without fail in period of 3 fCAN

CPU read signal

CPU reset signal

Updating period of

the CAN module

CiSTR register

b8: Reset state flag

Wait time

i = 0, 1

0: CAN operation

mode

1: CAN reset/initial-

ization mode

: Updated without fail in period of 4 fCAN

CPU read signal

CPU reset signal

Updating period of

the CAN module

CiSTR register

b8: State_Reset bit

4 f

CAN

i = 0, 1

0: CAN operation

mode

1: CAN reset/initial-

ization mode

✕: When the CAN module's State_Reset bit updating period matches the CPU's read

period, it does not enter reset mode, for the CPU read has the higher priority.

Rev.2.40 Apr 14, 2006 page 364 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.11.2 Performing CAN Configuration

If the Reset bit in the CiCTLR register (i = 0, 1) is changed from 0 (operation mode) to 1 (reset/initialization

mode) in order to place the CAN module from CAN operation mode into CAN reset/initialization mode,

always be sure to check that the State_Reset bit in the CiSTR register is set to 1 (reset mode).

Similarly, if the Reset bit is changed from 1 to 0 in order to place the CAN module from CAN reset/

initialization mode into CAN operation mode, always be sure to check that the State_Reset bit is set to 0

(operation mode).

The procedure is described below.

To Place CAN Module from CAN Operation Mode into CAN Reset/Initialization Mode

• Change the Reset bit from 0 to 1

• Check that the State_Reset bit is set to 1

To Place CAN Module from CAN Reset/Initialization Mode into CAN Operation Mode

• Change the Reset bit from 1 to 0

• Check that the State_Reset bit is set to 0

Rev.2.40 Apr 14, 2006 page 365 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.11.3 Suggestions to Reduce Power Consumption

When not performing CAN communication, the operation mode of CAN transceiver should be set to

“standby mode” or “sleep mode”.

When performing CAN communication, the power consumption in CAN transceiver in not performing

CAN communication can be substantially reduced by controlling the operation mode pins of CAN

transceiver.

Tables 23.3 and 23.4 show the Recommended Pin Connections.

Table 23.3 Recommended Pin Connections (In case of PCA82C250: Philips product)

Standby Mode High-speed Mode

Rs pin (1) “H”“L”

Power consumption in

less than 170 µA less than 70 mA

CAN transceiver (2)

CAN communication

impossible possible

Connection

i = 0, 1

NOTES:

1. The pin which controls the operation mode of CAN transceiver.

2. In case of Ta = 25 °C

3. Connect to enabled port to control CAN transceiver.

Table 23.4 Recommended Pin Connections (In case of PCA82C252: Philips product)

M16C/6N4 PCA82C250

CTXi

CRXi

Port

(3)

TXD

RXD

CANH

CANL

"H" output

PCA82C250

CTXi

CRXi

TXD

RXD

CANH

CANL

M16C/6N4

Port

(3)

"L" output

Sleep Mode Normal Operation Mode

_______

STB pin (1) “L”“H”

EN pin (1) “L”“H”

Power consumption in

less than 50 µA less than 35 mA

CAN transceiver (2)

CAN communication

impossible possible

Connection

i = 0, 1

NOTES:

1. The pin which controls the operation mode of CAN transceiver.

2. Ta = 25 °C

3. Connect to enabled port to control CAN transceiver.

PCA82C252

CTXi

CRXi

TXD

RXD

STB

CANH

CANL

M16C/6N4

Por

t (3)

Por

t (3)

"L" output

PCA82C252

CTXi

CRXi

TXD

RXD

STB

CANH

CANL

M16C/6N4

Por

(3)

Por

(3)

"H" output

Rev.2.40 Apr 14, 2006 page 366 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.11.4 CAN Transceiver in Boot Mode

When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver

should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by

the MCU, CAN transceiver must be set the operation mode to “high-speed mode” or “normal operation

mode” before programming the flash memory by changing the switch etc.

Tables 23.5 and 23.6 show the Pin Connections of CAN Transceiver.

Table 23.5 Pin Connections of CAN Transceiver (In case of PCA82C250: Philips product)

Standby Mode High-speed Mode

Rs pin (1) “H”“L”

CAN communication

impossible possible

Connection

i = 0, 1

NOTES:

1. The pin which controls the operation mode of CAN transceiver.

2. Connect to enabled port to control CAN transceiver.

Table 23.6 Pin Connections of CAN Transceiver (In case of PCA82C252: Philips product)

M16C/6N4 PCA82C250

CTXi

CRXi

Port

(2)

TXD

RXD

CANH

CANL

Switch OFF

M16C/6N4 PCA82C250

CTXi

CRXi

TXD

RXD

CANH

CANL

Port

(2)

Switch ON

Sleep Mode Normal Operation Mode

_______

STB pin (1) “L”“H”

EN pin (1) “L”“H”

CAN communication

impossible possible

Connection

i = 0, 1

NOTES:

1. The pin which controls the operation mode of CAN transceiver.

2. Connect to enabled port to control CAN transceiver.

M16C/6N4 PCA82C252

CTXi

CRXi

TXD

RXD

STB

CANH

CANL

Switch OFF

Por

t (2)

Por

t (2)

M16C/6N4 PCA82C252

CTXi

CRXi

TXD

RXD

STB

CANH

CANL

Por

(2)

Por

(2)

Switch ON

Rev.2.40 Apr 14, 2006 page 367 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.12 Programmable I/O Ports

_______

If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase

_______

output forcible cutoff by input on NMI pin enabled), pins P7_2 to P7_5, P8_0, and P8_1 go to a

high-impedance state.

Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to a high-impedance state.

The input threshold voltage of pins differs between programmable I/O ports and peripheral functions.

Therefore, if any pin is shared by a programmable I/O port and a peripheral function and the input level at

this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor “low”),

the input level may be determined differently depending on which side—the programmable I/O port or the

peripheral function—is currently selected.

Undefined values are read from bits P3_7 to P3_4, and PD3_7 to PD3_4 by reading registers P3 and PD3

when bits PM01 to PM00 in the PM0 register are set to 01b (memory expansion mode) or 11b (microprocessor

mode) and setting the PM11 bit to 1.

Use the MOV instruction when rewriting registers P3 and PD3 (including the case that the size specifier is

“.W” and registers P2 and PD2 are rewritten).

When bits PM01 to PM00 are rewritten, “L” is output from pins P3_7 to P3_4 during 0.5 cycles of the BCLK

by setting bits PM01 to PM00 in the PM0 register to 01b (memory expansion mode) or 11b (microprocessor

mode) from 00b (single-chip mode) after setting the PM11 bit to 1.

Rev.2.40 Apr 14, 2006 page 368 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.13 Electrical Characteristic Differences between Mask ROM and Flash Memory

Version MCUs

Flash memory version and mask ROM version may have different characteristics, operating margin, noise

tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,

etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests

conducted in the flash memory version.

Rev.2.40 Apr 14, 2006 page 369 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.14 Mask ROM Version

When using the masked ROM version, write nothing to internal ROM area.

Rev.2.40 Apr 14, 2006 page 370 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.15 Flash Memory Version

23.15.1 Functions to Prevent Flash Memory from Rewriting

ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and

0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in

standard serial I/O mode and CAN I/O mode.

The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash

memory cannot be read or written in parallel I/O mode.

In the flash memory version of MCU, these addresses are allocated to the vector addresses (H) of fixed

vectors.

23.15.2 Stop Mode

When entering stop mode, execute the instruction which sets the CM10 bit to 1 (stop mode) after setting

the FMR01 bit to 0 (CPU rewrite mode disabled) and disabling the DMA transfer.

23.15.3 Wait Mode

When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled)

before executing the WAIT instruction.

23.15.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode

If the CM05 bit is set to 1 (main clock stopped), do not execute the following commands:

• Program

• Block erase

• Erase all unlocked blocks

• Lock bit program

• Read lock bit status

23.15.5 Writing Command and Data

Write commands and data to even addresses in the user ROM area.

23.15.6 Program Command

By writing xx40h in the first bus cycle and data to the write address in the second bus cycle, an

auto-program operation (data program and verify) will start. The address value specified in the first bus

cycle must be the same even address as the write address specified in the second bus cycle.

23.15.7 Lock Bit Program Command

By writing xx77h in the first bus cycle and xxD0h to the highest-order even address of a block in the

second bus cycle, the lock bit for the specified block is set to 0. The address value specified in the first bus

cycle must be the same highest-order even address of a block specified in the second bus cycle.

23.15.8 Operating Speed

Before entering CPU rewrite mode (EW0 or EW1 mode), set the CM11 bit in the CM1 register to 0 (main

clock), select 10 MHz or less for CPU clock using the CM06 bit in the CM0 register and bits CM17 to

CM16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state).

Rev.2.40 Apr 14, 2006 page 371 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.15.9 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash

memory: the UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

23.15.10 Interrupts

EW0 Mode

To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM

area.

_______

• The NMI and watchdog timer interrupts are available since registers FMR0 and FMR1 are forcibly reset

when either interrupt request is generated. Allocate the jump addresses for each interrupt service

_______

routines to the fixed vector table. Flash memory rewrite operation is suspended when the NMI or

watchdog timer interrupt request is generated. Execute the rewrite program again after exiting the

interrupt routine.

• The address match interrupt is not available since the CPU tries to read data in the flash memory.

EW1 Mode

• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt

during auto-programming or auto-erasure.

• Do not use the watchdog timer interrupt.

_______

• The NMI interrupt is available since registers FMR0 and FMR1 are forcibly reset when the interrupt

request is generated. Allocate the jump address for the interrupt service routine to the fixed vector table.

_______

Flash memory rewrite operation is suspended when the NMI interrupt request is generated. Execute the

rewrite program again after exiting the interrupt service routine.

23.15.11 How to Access

To set the FMR01, FMR02, or FMR11 bit to 1, write 1 after first setting the bit to 0. Do not generate an

interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set the bit to 1.

_______

Set the bit while an “H” signal is applied to the NMI pin.

23.15.12 Rewriting in User ROM Area

EW0 Mode

If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash

memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error

occurs, rewrite the user ROM area while in standard serial I/O mode, parallel I/O mode, or CAN I/O

mode.

EW1 Mode

Avoid rewriting any block in which the rewrite control program is stored.

23.15.13 DMA Transfer

In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to 0 (auto-

programming or auto-erasure).

Rev.2.40 Apr 14, 2006 page 372 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.16 Flash Memory Programming Using Boot Program

When programming the on-chip flash memory using boot program, be careful about the pins state and

connection as follows.

23.16.1 Programming Using Serial I/O Mode

CTX0 pin : This pin automatically outputs “H” level.

CRX0 pin : Connect to CAN transceiver or connect via resister to VCC (pull-up)

Figure 23.6 shows the Pin Connection for Programming Using Serial I/O Mode.

Figure 23.6 Pin Connection for Programming Using Serial I/O Mode

23.16.2 Programming Using CAN I/O Mode

_________

RTS1 pin : This pin automatically outputs “H” and “L” level.

Figure 23.7 shows the Pin Connection for Programming Using CAN I/O Mode.

Figure 23.7 Pin Connection for Programming Using CAN I/O Mode

CLK1(P6_5)

RXD1(P6_6)

TXD1(P6_7)

RTS1(P6_4)

EPM(P5_5)

CE(P5_0)

CNVSS

RESET

NMI(P8_5)

CRX0(P9_5)

CTX0(P9_6)

Power

supply

VCC

GND

VCC monitor input

10-pin connector

PC card-type

flash programmer

user reset signal

M16C/6N4

CTX0(P9_6)

CRX0(P9_5)

EPM(P5_5)

CE(P5_0)

CNVSS

RESET

NMI(P8_5)

RTS1(P6_4)

VCC

GND

PCA

82C250

CAN_H

CAN_L

Power

supply

VCC monitor input

10-pin connector

PC card-type

CAN programmer

user reset signal

M16C/6N4

Rev.2.40 Apr 14, 2006 page 373 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) 23. Usage Notes

23.17 Noise

Connect a bypass capacitor (approximately 0.1 µF) across pins VCC1 and VSS, and pins VCC2 and VSS

using the shortest and thicker possible wiring.

Figure 23.8 shows the Bypass Capacitor Connection.

Figure 23.8 Bypass Capacitor Connection

Bypass capacitor

Connecting patternConnecting pattern

Bypass capacitor

Connecting patternConnecting pattern

VSS VCC2

VSS VCC1

M16C/6N Group

(M16C/6N4)

Rev.2.40 Apr 14, 2006 page 374 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) Appendix 1. Package Dimensions

Appendix 1. Package Dimensions

Terminal cross section

1. DIMENSIONS "*1" AND "*2"

DO NOT INCLUDE MOLD FLASH.

NOTE)

DIMENSION "*3" DOES NOT

INCLUDE TRIM OFFSET.

Index mark

125

100

Detail F

y0.08

e0.5

0° 8°

L0.35 0.5 0.65

0.05 0.1 0.15

A1.7

15.8 16.0 16.2

1.4

E13.9 14.0 14.1

D13.9 14.0 14.1

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.15 0.20 0.25

0.09 0.145 0.20

0.08

1.0

0.18

0.125

1.0

Previous CodeJEITA Package Code RENESAS Code

PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV

MASS[Typ.]

0.6gP-LQFP100-14x14-0.50

0.80.5

0.825

0.575

y0.10

e0.65

0°10°

L0.4 0.6 0.8

00.1 0.2

A3.05

16.5 16.8 17.1

22.5 22.8 23.1

2.8

E13.8 14.0 14.2

D19.8 20.0 20.2

Reference

Symbol

Dimension in Millimeters

Min Nom Max

0.25 0.3 0.4

0.13 0.15 0.2

P-QFP100-14x20-0.65 1.6g

MASS[Typ.]

100P6S-APRQP0100JB-A

RENESAS CodeJEITA Package Code Previous Code

Index mark

100

80 51

Detail F

INCLUDE TRIM OFFSET.

DIMENSION "*3" DOES NOT

NOTE)

DO NOT INCLUDE MOLD FLASH.

DIMENSIONS "*1" AND "*2"1.

Rev.2.40 Apr 14, 2006 page 375 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) Register Index

AD0 to AD7 ................................... 196

ADCON0 .... 195,198,200,202,204,206

ADCON1 .... 195,198,200,202,204,206

ADCON2 ....................................... 196

ADIC................................................ 80

AIER ................................................ 92

AIER2 .............................................. 92

C01ERRIC ...................................... 80

C01WKIC ........................................ 80

C0AFS, C1AFS ............................. 224

C0CONR, C1CONR ...................... 223

C0CTLR, C1CTLR ........................ 220

C0GMR, C1GMR .......................... 218

C0ICR, C1ICR............................... 222

C0IDR, C1IDR............................... 222

C0LMAR, C1LMAR ....................... 218

C0LMBR, C1LMBR ....................... 218

C0MCTL0 to C0MCTL15 .............. 219

C0RECIC ........................................ 80

C0RECR, C1RECR....................... 224

C0SSTR, C1SSTR ........................ 225

C0STR, C1STR............................. 221

C0TECR, C1TECR ....................... 224

C0TRMIC ........................................ 80

C0TSR, C1TSR............................. 224

C1MCTL0 to C1MCTL15 .............. 219

C1RECIC ........................................ 81

C1TRMIC ........................................ 81

CAN0/1 Slot 0 to 15

: Time Stamp ....................... 216,217

: Data Field .......................... 216,217

: Message Box .................... 216,217

CCLKR ............................................ 56

CM0................................................. 53

CM1................................................. 54

CM2................................................. 55

CPSRF .................................... 110,124

CRCD ............................................ 212

CRCIN ........................................... 212

CSE ................................................. 47

CSR................................................. 41

DA0, DA1 ....................................... 211

DACON .......................................... 211

DAR0, DAR1 ................................... 99

DM0CON, DM1CON ....................... 98

DM0IC, DM1IC ................................ 80

DM0SL ............................................ 97

DM1SL ............................................ 98

DTT ............................................... 134

FMR0 ............................................ 257

FMR1 ............................................ 257

ICTB2 ............................................ 136

IDB0, IDB1 .................................... 134

IFSR0 .............................................. 89

IFSR1 .............................................. 89

INT0IC to INT5IC ............................ 81

INVC0............................................ 132

INVC1............................................ 133

KUPIC ............................................. 80

ONSF ............................................. 110

P0 to P10 ...................................... 246

PCLKR ............................................ 56

PCR............................................... 248

PD0 to PD10 ................................. 245

PLC0 ............................................... 57

PM0 ................................................. 35

PM1 ................................................. 36

PM2 ................................................. 57

PRCR .............................................. 74

PUR0 to PUR2 .............................. 247

RMAD0 to RMAD3 .......................... 92

ROMCP ......................................... 254

S0RIC to S2RIC .............................. 80

S0TIC to S2TIC ............................... 80

S3BRG .......................................... 189

S3C ............................................... 189

S3IC ................................................ 81

S3TRR .......................................... 189

SAR0, SAR1 ................................... 99

TA0 ................................................ 108

TA0IC .............................................. 80

TA0MR ............... 108,111,113,118,120

TA1 ......................................... 108,135

TA11 .............................................. 135

TA1IC .............................................. 80

TA1MR ........ 108,111,113,118,120,138

TA2 ......................................... 108,135

TA21 .............................................. 135

TA2IC .............................................. 80

TA2MR .... 108,111,113,115,118,120,138

TA3 ................................................ 108

TA3IC .............................................. 80

TA3MR ......... 108,111,113,115,118,120

TA4 ......................................... 108,135

TA41 .............................................. 135

TA4IC .............................................. 80

TA4MR .... 108,111,113,115,118,120,138

TABSR ............................ 109,124,137

TB0................................................ 123

TB0IC .............................................. 80

TB0MR ..................... 123,125,126,128

TB1................................................ 123

TB1IC .............................................. 80

TB1MR ..................... 123,125,126,128

TB2......................................... 123,135

TB2IC .............................................. 80

TB2MR .............. 123,125,126,128,138

TB2SC........................................... 136

TB3................................................ 123

TB3IC .............................................. 80

TB3MR ..................... 123,125,126,128

TB4................................................ 123

TB4IC .............................................. 80

TB4MR ..................... 123,125,126,128

TB5................................................ 123

TB5IC .............................................. 80

TB5MR ..................... 123,125,126,128

TBSR............................................. 124

TCR0, TCR1 ................................... 99

TRGSR.................................... 110,137

U0BCNIC to U2BCNIC.................... 80

U0BRG to U2BRG ........................ 145

U0C0 to U2C0 ............................... 146

U0C1 to U2C1 ............................... 147

Rev.2.40 Apr 14, 2006 page 376 of 376

REJ09B0009-0240

M16C/6N Group (M16C/6N4) Register Index

U0MR to U2MR ............................. 146

U0RB to U2RB .............................. 145

U0SMR to U2SMR ........................ 148

U0SMR2 to U2SMR2 .................... 149

U0SMR3 to U2SMR3 .................... 149

U0SMR4 to U2SMR4 .................... 150

U0TB to U2TB ............................... 145

UCON............................................ 148

UDF ............................................... 109

WDC................................................ 94

WDTS.............................................. 94

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-1

1.00

May. 30, 2003

2.00

Nov. 10, 2004

– First edition issued

– Revised edition issued

* Words standardizes (on-chip oscillator)

* 100P6Q-A (100-pin version) is added.

* Usage Notes Reference Book is added to Chapter 23 Usage Precaution.

* Revised parts and revised contents are as follows (except for change of chapter composition,

change of a layout, and an expressional change).

1 1. Overview 3rd line: "and LQFP" is added.

2 Table 1.1 Performance outline of M16C/6N Group (M16C/6N4)

• Operation Mode is added.

• Address Space is added.

• Power Consumption is revised.

• "LQFP" is added to Package.

4 Table 1.2 Product List is revised.

Figure 1.2 Type No., Memory Size, and Package:

• "GP: Package 100P6Q-A" is added to Package type.

5 Figure 1.3 Pin Configuration (Top View) (1): "ZP" is added.

6 Figure 1.4 Pin Configuration (Top View) (2) is added. (100P6Q-A)

8 Table 1.4 Pin Description (2): "ZP" is added to Timer A.

12 3. Memory

• 5th to 6th lines: The description about the flash memory version (block A) is added.

Figure 3.1 Memory Map:

• Internal ROM (data area) is added.

• NOTES 3, 4 are added and NOTE 5 is revised.

13 Table 4.1 SFR Information (1)

• The value of After Reset in PM1 register is revised.

• The value of After Reset in CM2 register is revised.

19 Table 4.7 SFR Information (7)

• The value of After Reset in FMR0 register is revised.

27 Table 4.15 SFR Information (15)

• The value of After Reset in U0C1 register is revised.

• The value of After Reset in U1C1 register is revised.

• NOTE 1 is added.

28 Table 4.16 SFR Information (16)

• The value of After Reset in DA0, DA1 registers are revised.

30 Figure 5.1 Example Reset Circuit: NOTE 1 is added.

34 Figure 6.2 PM1 Register

• The value of After Reset is revised.

• NOTES 2, 6 are revised.

_____

Figure 6.6 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (3)

• NOTE 2 is added.

_____

Figure 6.7 Memory Map and CS Area in Memory Expansion Mode and Microprocessor Mode (4)

• NOTE 1 is added.

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-2

38 Table 7.1 Difference between Separate Bus and Multiplexed Bus is added.

39 Figure 7.1 CSR Register: NOTE 2 is revised.

46 Table 7.8 Software Wait Related Bits and Bus Cycles

• Bus Cycle of SFR (PM20 = 0) is revised from "2 BCLK cycles" to "3 BCLK cycles".

• Bus Cycle of SFR (PM20 = 1) is revised from "3 BCLK cycles" to "2 BCLK cycles".

• From bottom to 5th item in CSR Register: The value is revised from "1" to "0".

• NOTE 5 is added.

49 Table 8.1 Clock Generating Circuit Specifications

• Clock Frequency in PLL Frequency Synthesizer: 16 MHz is added.

50 Figure 8.1 Clock Generating Circuit: Block diagram (upper) is revised.

51 Figure 8.2 CM0 Register

• Bit name of CM02 is revised.

• NOTE 6 (2) and NOTE 8 are revised.

52 Figure 8.3 CM1 Register: NOTE 3 of CM11 bit is deleted.

54 Figure 8.6 CCLKR Register: Location of NOTE 2 is changed and NOTE 3 is added.

55 Figure 8.7 PM2 Register: NOTE 2 is revised.

Figure 8.8 PLC0 Register: Function of 011b and 100b in PLC02 to PLC00 bits are revised

from "Multiply by 6 and Multiply by 8" to "Do not set a value".

58 8.1.4 PLL Clock 11th line: 16 MHz is added to PLL clock frequency.

Table 8.2 Example for Setting PLL Clock Frequencies

• PLL clock = 16 MHz is added. (8✕2, 4✕4)

• 16 MHz is added to NOTE 1.

59 Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source

• 4th frame: “(To select a 16 MHz or higher PLL clock)” is revised to “(When PLL clock

>16 MHz)”.

61 8.4.1.2 PLL Operation Mode: 1st line

• The main clock multiplied is revised from "by 2, 4, 6 or 8" to "by 2 or 4".

62 Table 8.3 Setting Clock Related Bit and Modes

• CM21 bit in Low Power Dissipation Mode: Value is revised from "-" to "0".

• CM11 bit in Low-Speed Mode, Low Power Dissipation Mode, On-chip Oscillator Mode

and On-chip Oscillator Low Power Dissipation Mode: Value is revised from "-" to "0".

63 8.4.2 Wait Mode 4th line: "PLL clock" is deleted.

Table 8.4 Pin Status During Wait Mode

• Memory Expansion Mode, Microprocessor Mode in ALE: Value is revised from

"H" to "L".

64 Table 8.5 Interrupts to Exit Wait Mode

• CAN0/1 Wake-up Interrupt: "in CAN sleep mode" is added.

65 8.4.3 Stop Mode

• CAN0/1 Wake-up interrupt: "(when CAN sleep mode is selected)" is added.

Table 8.6 Pin Status in Stop Mode

• Memory Expansion Mode, Microprocessor Mode in ALE: Value is revised from

" H" to "indeterminate".

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REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-3

67 Figure 8.12 State Transition to Stop Mode and Wait Mode

• Figure is revised.

• NOTE 3 is revised.

68 Figure 8.13 State Transition in Normal Operation Mode

• Low-Speed and Low Power Dissipation Mode: "CM7 = 1” is revised to "CM7 = 0" (3 places).

• NOTES 2, 6 are revised.

71 Figure 8.14 Procedure to Switch Clock Source from On-chip Oscillator to Main Clock

is revised.

77 Table 10.2 Relocatable Vector Tables

• Interrupt Source: "Software interrupt" is revised to "INT Instruction Interrupt"

• NOTES 10, 11 are added.

78 Figure 10.3 Interrupt Control Registers (1): NOTES 5, 6, 7 are added.

79 Figure 10.4 Interrupt Control Registers (2)

• NOTE 2 is added to C1RECIC/INT5IC, C1TRMIC/S3IC/INT4IC

• NOTES 6, 7 are added.

87 Figure 10.11 (upper) IFSR0 Register: NOTE 3 is added.

88 10.9 CAN0/1 Wake-up Interrupt is revised.

Figure 10.13 CAN0/1 Wake-up Interrupt Block Diagram is revised.

____________

Figure 11.1 Watchdog Timer Block Diagram: "RESET" is revised to "Internal RESET signal".

108 Figure 13.6 (upper and middle) ONSF Register, TRGSR Register: NOTE 2 is added.

109 Table 13.1 Specifications in Timer Mode

• Specification of Divide Ratio: "TAiMR register" is revised to "TAi register".

• Specification of Select Function: "When not counting, the pin outputs a low" is

revised to "When TAiS bit is set to "0" (stop counting), the pin outputs a low".

110 Table 13.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal)

• Specification in Select Function: "When not counting, the pin outputs a low" is

revised to "When TAiS bit is set to "0" (stop counting), the pin outputs a low".

114 13.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing 4th line

•

________

"the INT2 pin" is revised to "the ZP pin".

Figure 13.10 Two-phase Pulse (A phase and B phase) and Z Phase

•

________

"INT2 (Z phase)" is revised to "ZP".

118 Figure 13.12 TA0MR to TA4MR Registers in PWM Mode

• Bit name and Function in MR0 bit is revised from "Set to "1" in PWM mode" to "Pulse

Output Function Select Bit (3)".

• NOTE 3 is added.

123 Table 13.6 Specifications in Timer Mode

• Specification in Divide Ratio: "TBiMR register" is revised to "TBi register".

129 Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.

130 Figure 14.2 INVC0 Register is revised.

131 Figure 14.3 INVC1 Register: Function of INV13 bit is revised.

132 Figure 14.4 (upper) IDB0 and IDB1 Registers: (b7-b6) is revised.

Figure 14.4 (lower) DTT Register: NOTE 2 is revised.

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Nov. 10, 2004

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-4

134 Figure 14.6 (upper) ICTB2 Register

• (b7-b4) is revised.

• NOTE 3 is added.

135 Figure 14.7 (upper) TRGSR Register: NOTE 2 is added.

136 Figure 14.8 (upper) TA1MR, TA2MR and TA4MR Registers

• Function of MR1 bit: "Has no effect" is revised to "Set to "0" ".

137 Figure 14.9 Triangular Wave Modulation Operation is revised.

139 15.1 UARTi: "UART0, UART1" in Special mode 3 is deleted.

140, 141 Figures 15.1 to 15.3 UART0 to 2 Block Diagram are revised.

142 Figure 15.4 UARTi Transmit/Receive Unit is revised.

144 Figure 15.6 (lower) U0C0 to U2C0 Registers: NOTES 3, 4 are revised.

145 Figure 15.7 (upper) U0C1, U1C1 Registers

• The value of After Reset is revised.

• (b5-b4) is revised from "When read, their contents are "0" " to "When read, their

contents are indeterminate".

• NOTE 1 is added.

Figure 15.7 (lower) U2C1 Register: NOTE 1 is added.

153 15.1.1.1 Counter Measure for Communication Error Occurs is added.

154 15.1.1.4 Continuous Receive Mode: first to 4th lines are added.

156

_______ _______

15.1.1.7 CTS/RTS Function is added.

157 Table 15.5 UART Mode Specifications: NOTE 3 is added.

159 Table 15.7 I/O Pin Functions

• Method of Selection in TXDi: "Output dummy data" is revised to "Output "H" ".

161 15.1.2.1 Bit Rates and Table 15.9 Example of Bit Rates and Settings are added.

162 15.1.2.2 Counter Measure for Communication Error Occurs is added.

164

_______ _______

15.1.2.6 CTS/RTS Function is added.

176 Table 15.15 Registers to Be Used and Settings in Special Mode 2

• "U2LCH" in UiC1 register is revised to "UiLCH".

179 Table 15.16 Registers to Be Used and Settings in IE Mode

• "UiRRM" in UiC1 register is revised to "U2RRM".

181 Table 15.17 SIM Mode Specifications: NOTE 3 is added.

189 Figure 15.39 Polarity of Transfer Clock is revised.

205 16.2.4 External Operation Amplifier (Op-Amp) Connection Mode: 6th line

• "Note that the ANEX0 and ANEX1 pins cannot be directly connected to each other."

is deleted.

206 16.2.6 Output Impedance of Sensor under A/D Conversion is added.

209 Figure 17.2 (lower) DA0 and DA1 Registers: The value of After Reset are revised.

216 Figure 19.4 Bit Mapping of Mask Registers in Byte Access: NOTES 1, 2 are added.

Figure 19.5 Bit Mapping of Mask Registers in Word Access: NOTES 1, 2 are added.

217 Figure 19.6 C0MCTLj and C1MCTLj Registers: NOTE 2 is revised.

218 Figure 19.7 C0CTLR and C1CTLR Registers (upper)

• NOTE 1 (Rev.1.00) is deleted and NOTES 1, 2, 3 are added.

Figure 19.7 C0CTLR and C1CTLR Registers (lower): NOTES 3, 4 are added.

2.00

Nov. 10, 2004

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-5

219 Figure 19.8 C0STR and C1STR Registers (upper): NOTE 2 is added.

223 19.5 Operational Modes

• 1st line: "three operational modes" is revised to "four operational modes".

• 5th line: "CAN Interface Sleep Mode" is added.

Figure 19.12 Transition Between Operational Modes is revised.

19.5.1 CAN Reset/Initialization Mode is revised.

224 19.5.2 CAN Operation Mode is revised.

19.5.3 CAN Sleep Mode is revised.

19.5.4 CAN Interface Sleep Mode is added.

225 19.5.5 Bus Off State is revised.

231 19.12 Return from Bus Off Function is revised.

19.14 Listen-Only Mode

• last line: "When listen-only mode is selected, do not request the transmission." is added.

233 Figure 19.20 Timing of Receive Data Frame Sequence: Waveform of RecState bit is revised.

19.15.1 Reception: (4) (5) are revised.

234 Figure 19.21 Timing of Transmit Sequence

• The position of the number corresponding to the text is revised.

19.15.2 Transmission: (1) to (4) are revised.

251 21.2.1 ROM Code Protect Function is revised.

21.2.2 ID Code Check Function is revised.

252 Figure 21.2 ROMCP Register is revised.

255 Figure 21.4 (upper) FMR0 Register: The value of After Reset is revised.

256 21.3.3.1 FMR00 Bit is revised.

21.3.3.8 FMR11 Bit is revised.

21.3.3.9 FMR16 Bit is revised.

257 Figure 21.5 Setting and Resetting of EW0 Mode is revised.

Figure 21.6 Setting and Resetting of EW1 Mode: NOTE 3 is revised.

258 Figure 21.7 Processing Before and After Low Power Dissipation Mode: NOTE 4 is added.

260 21.3.4.12 Low Power Dissipation Mode and On-chip Oscillator Low Power Dissipation

Mode is revised.

261 Table 21.4 Software Commands: NOTE 2 is deleted.

262 21.3.5.4 Program Command (40h)

• From bottom to 3rd line: "read command" is revised to "read array command".

265 Figure 21.11 Read Lock Bit Status Command

• "Locked", "Not locked" are revised to "Block is locked", "Block is not locked".

266 21.3.7.1 Sequencer Status (SR7 and FMR00 Bits) is revised.

271 Table 21.7 Pin Functions for Standard Serial I/O Mode

• "VCC" is revised to "VCC1", and "VCC2" is added.

• VCC1, VCC2, VSS: VCC apply condition is added.

273 Figure 21.14 Pin Connections for Standard Serial I/O Mode (2) is added.

274

____________

Figure 21.16 Circuit Application in Standard Serial I/O Mode 2: "RESET" is added.

276 Table 21.8 Pin Functions for CAN I/O Mode

• "VCC" is revised to "VCC1", and "VCC2" is added.

• VCC1, VCC2, VSS: VCC apply condition is added.

2.00

Nov. 10, 2004

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-6

278 Figure 21.18 Pin Connections for CAN I/O Mode (2) is added.

280 Table 21.9 Flash Memory Version Electrical Characteristics

• Parameter is added and the value of some item is revised.

281 Table 22.1 Absolute Maximum Ratings

• "Flash Program Erase" in Operating Ambient Temperature is added.

283 Table 22.3 Recommended Operating Conditions (2)

• Parameters of Power Supply Ripple are added.

• NOTE 4 is revised.

Figure 22.1 Timing of Voltage Fluctuation is added.

284 Table 22.4 Electrical Characteristics (1): Hysteresis

• "CLK4" is revised to "CLK3", and "TA2OUT" is revised to "TA0OUT".

•

____________

Max. of Standard in RESET is revised from "2.2" to "2.5".

• XIN is added.

286 Table 22.6 A/D Conversion Characteristics: "Tolerance Level Impedance" is added.

287 Table 22.8 Power Supply Circuit Timing Characteristics: "td(M-L)" is deleted.

Figure 22.2 Power Supply Circuit Timing Diagram is added.

288 Table 22.10 Memory Expansion Mode and Microprocessor Mode: "td(BCLK-HLDA)" is deleted.

290 Table 22.21 Serial I/O: Min. of standard in tsu(D-C) is revised from "30" to "70".

291 Table 22.23 Memory Expansion Mode and Microprocessor Mode (for setting with no wait)

• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".

• td(BCLK-HLDA) is added.

292 Table 22.24 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting

and external area access)

• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".

• td(BCLK-HLDA) is added.

293 Table 22.25 Memory Expansion Mode and Microprocessor Mode (for 2- to 3-wait setting,

external area access and multiplexed bus selection)

• td(BCLK-HLDA) is added.

• Max. of Standard in td(BCLK-ALE) is revised from "25" to "15".

294 Figure 22.4 Timing Diagram (1): "XIN input" is added.

296, 297 Figures 22.6 and 22.7 Timing Diagram (3) (4): "DB" in Read timing is revised to "DBi".

298, 299 Figures 22.8 and 22.9 Timing Diagram (5) (6): "DB" in Write timing is revised to "DBi".

301 Figure 22.11 Timing Diagram (8)

• "ADi/DB" in Read/Write timing is revised to "ADi/DBi".

302 23.1 External Bus: The description of the external ROM version is deleted.

303 23.2 PLL Frequency Synthesizer is revised.

304 23.3 Power Control

• 2nd item is added. (Set the MR0 bit in the TAiMR register to •••)

• 4th item is revised. (Wait for main clock oscillation •••)

• Section of "External clock" is deleted.

316 23.8.2.1 Special Mode 1 (I2C Mode) is added.

317 23.8.3 SI/O3 is added.

2.00

Nov. 10, 2004

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-7

319 23.9 A/D Converter: last item is added. (When setting the ADST bit to •••)

322 23.10.2 Performing CAN Configuration is added.

323 23.10.3 Suggestions to Reduce Power Consumption is added.

327 23.13 Mask ROM Version is added.

328 23.14.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation

Mode is revised.

330 23.15 Flash Memory Programming Using Boot Program is added.

331 23.16 Noise is added.

332 Appendix 1. Package Dimensions: 100P6Q-A is added.

– Revised edition issued

* The contents of product are revised. (Normal-ver. is added.)

* Revised parts and revised contents are as follows (except for expressional change).

2 Table 1.1 Performance outline of M16C/6N Group (M16C/6N4)

• Performance outline of Normal-ver. is added.

4 Table 1.2 Product List is revised. (Normal-ver. is added.)

Figure 1.2 Type No., Memory Size, and Package:

• "(no): Normal-ver." is added to Characteristics.

19 Figure 4.7 SFR Information (7): NOTE 1 is revised.

53 Figure 8.4 CM2 Register: The value of After Reset is revised.

68 Figure 8.13 State Transition in Normal Operation Mode: NOTE 7 is revised.

217 Figure 19.6 C0MCTLj and C1MCTLj Registers

• RemActive bit: Function is revised.

• RspLock bit: Bit Name is revised.

• NOTE 2 is revised.

218 Figure 19.7 C0CTLR and C1CTLR Registers (upper)

• LoopBack bit: The expression of Function is revised.

• BasicCAN bit: The expression of Function is revised.

Figure 19.7 C0CTLR and C1CTLR Registers (lower)

• TSPreScale bit: Bit Symbol is revised. (“Bit1, Bit0” is deleted.)

• TSReset bit: The expression of Function is revised.

• RetBusOff bit: The expression of Function is revised.

• RXOnly bit: The expression of Function is revised.

219 Figure 19.8 C0STR and C1STR Registers (upper): NOTE 1 is deleted.

Figure 19.8 C0STR and C1STR Registers (lower)

• State_LoopBack bit: The expression of Function is revised.

• State_BasicCAN bit: The expression of Function is revised.

222 Figure 19.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR,

C1TSR Registers, and C0AFS, C1AFS Registers

• C0RECR, C1RECR Registers: NOTE 2 is deleted.

• C0TECR, C1TECR Registers: NOTE 1 is deleted.

• C0TSR, C1TSR Registers: NOTE 1 is deleted.

233 19.15.1 Reception (1): “(refer to 19.15.2 Transmission)” is deleted.

2.00

Nov. 10, 2004

2.10

Jun. 24, 2005

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-8

238 Figure 20.1 I/O Ports (1): “P7_0” in 4th figure is deleted.

240 Figure 20.3 I/O Ports (3): “P7_0” is added to middle figure.

242 Figure 20.6 I/O Pins: NOTE 1 is deleted.

284 Table 22.4 Electrical Characteristics (1)

• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.

285 Table 22.5 Electrical Characteristics (2): Mask ROM (5th item)

• “f(XCIN)” is changed to “(f(BCLK)).

286 Table 22.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.

– Revised edition issued

* Electric Characteristics of Normal-ver. is added.

* Revised parts and revised contents are as follows (except for expressional change).

1 1.1 Applications: Comment of Normal-ver. is added.

4 Table 1.2 Product List: NOTE 1 is added.

7, 8 Tables 1.3 and 1.4 Pin Characteristics (1)(2) are added.

9 Table 1.5 Pin Description (1)

• 3.0 to 3.6 V (Normal-ver.) is added to Description of Power supply input.

31 to 33 5. Reset: Layout is changed.

33 5.5 Internal Space is added.

44 7.2.6 RDY Signal: Last sentence is revised.

51 Table 8.1 Clock Generating Circuit Specifications

• Clock Frequency in PLL Frequency Synthesizer: 24 MHz (1) is added.

• NOTE 1 is added.

57 Figure 8.8 PLC0 Register

• PLC02 to PLC00 bits: Function of 011b is revised.

• NOTE 4 is added.

58 Figure 8.9 Examples of Main Clock Connection Circuit is revised.

59 Figure 8.10 Examples of Sub Clock Connection Circuit is revised.

60 8.1.4 PLL Clock

• 9th line: The sentence (When the PLL ... to) is added.

• 12th line: 24 MHz and NOTE 1 is added to PLL clock frequency.

• NOTE 1 is added.

Table 8.2 Example for Setting PLL Clock Frequencies

• 24 MHz is added to PLL clock.

• 24 MHz is added to NOTE 1.

• NOTES 2 and 3 are added.

63 8.4.1.2 PLL Operation Mode

• 1st line: The main clock multiplied by “6” and NOTE 1 is added.

64 8.4.1.6 On-chip Oscillator Mode: Last sentence (When the operation mode is ...) is added.

8.4.1.7 On-chip Oscillator Low Power Dissipation Mode: Last sentence (When the

operation mode is ...) is deleted.

67 Table 8.6 Interrupts to Stop Mode and Use Conditions is added.

70 Figure 8.13 State Transition in Normal Operation Mode: NOTE 7 is deleted.

2.10

Jun. 24, 2005

2.30

Oct. 24, 2005

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-9

86 10.5.8 Returning from an Interrupt Routine: Last sentence (Register bank ...) is added.

10.5.9 Interrupt Priority: First sentence (If two or more...) is revised.

10.5.10 Interrupt Priority Resolution Circuit: First sentence (The interrupt priority level ...)

is revised.

89 Figure 10.11 IFSR1 Register (upper)

• IFSR17: NOTE 2 is added to Bit Name.

• NOTE 2 is revised.

96 Table 12.1 DMAC Specifications: DMA transfer Cycles is added.

100 12.1.3 Effect of Software Wait: 3rd to 9th lines is moved from next section of 12.1.4.

120 Figure 13.12 TA0MR to TA4MR Registers in PWM Mode: b2 is revised from “1” to “(blank)”.

131 Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram is revised.

132 Figure 14.2 INVC0 Register: NOTES 5 and 6 are revised.

145 Figure 15.5 U0BRG to U2BRG Registers (lower): NOTE 3 is added.

146 Figure 15.6 U0C0 to U2C0 Registers (lower): NOTE 5 is added.

163 Table 15.9 Example of Bit Rates and Settings: 24 MHz and NOTE 1 is added.

189 Figure 15.37 S3C Register (upper): NOTE 5 is added.

Figure 15.37 S3BRG Register (middle): NOTE 3 is added.

193 Table 16.1 A/D Converter Performance

• Performance of Integral Nonlinearity Error: “When AVCC = VREF = 3.3 V” is added.

194 Figure 16.1 A/D Converter Block Diagram

• ADGSEL1 to ADGSEL0 (right/lower) is revised from “10b” to “11b”.

208 16.2.6 Output Impedance of Sensor under A/D Conversion

• 10th line: f(XIN) is revised to f(φAD).

209 Figure 16.10 Analog Input Pin and External Sensor Equivalent Circuit

• fAD is revised to φAD.

210 Figure 17.1 D/A Converter Block Diagram is revised.

211 Figure 17.2 DA0 and DA1 Registers: Setting Range is added.

Figure 17.3 D/A Converter Equivalent Circuit: NOTE 2 is added.

213 Figure 18.3 CRC Calculation: Details of CRC operation is revised.

224 Figure 19.11 C0TECR, C1TECR Registers (2nd register): NOTE 1 is added.

229 Table 19.2 Examples of Bit-rate: 24 MHz and NOTE 2 is added.

247 Figure 20.9 PUR1 Register (middle): Value of After Reset is revised.

252 Figure 21.1 Flash Memory Block Diagram is revised.

254 Figure 21.2 ROMCP Register is revised.

255 Table 21.3 EW0 Mode and EW1 Mode: NOTE 1 is revised.

256 21.3.2 EW1 Mode: Last sentence (When an erase/program ...) is added.

258 21.3.3.4 FMSTP Bit

• 8th line: Procedure to change the FMSTP bit setting (1) to (4) are added.

261 Figure 21.7 Processing Before and After Low Power Dissipation Mode or On-chip Oscillator

Low Power Dissipation Mode

• Title, First and second frames (left) and top of right: “on-chip oscillator low power

dissipation mode” is added.

2.30

Oct. 24, 2005

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-10

263 21.3.4.11 Stop Mode is revised.

21.3.4.12 Low Power Dissipation Mode and On-chip Oscillator Low Power Dissipation

Mode is partly revised.

266 21.3.5.5 Block Erase Command: Last sentence (Also execute ...) is added.

Figure 21.9 Block Erase Command: NOTES 2 and 3 are added.

272 Figure 21.12 Full Status Check and Handling Procedure for Each Error

• Erase error: (4) is added.

274 Table 21.7 Pin Functions for Standard Serial I/O Mode

• Description of VCC1, VCC2, VSS is revised.

• Description of P8_4 is revised.

• NOTE 1 is revised.

• NOTE 2 is added.

277 Figures 21.15 and 21.16 Circuit Application in Serial I/O Mode 1/2

• “VCC1” and “VCC2” are added.

279 Table 21.8 Pin Functions for CAN I/O Mode

• Description of VCC1, VCC2, VSS is revised.

• Description of P8_4 is revised.

• NOTE 1 is added.

282 Figure 21.19 Circuit Application in CAN I/O Mode: “VCC1” and “VCC2” are added.

283 Table 21.9 Flash Memory Version Electrical Characteristics

• Measuring condition is revised in word program time and block erase time.

284 21.7.2 Electrical Characteristics (Normal-ver.) is added.

306 to 341 22.2 Electrical Characteristics (Normal-ver.) is added.

344 23.3 Power Control: 3rd and 4th items (When entering wait mode ... / When entering

stop mode ...) are revised.

359 Figure 23.2 Use of Capacitors to Reduce Noise is partly revised.

360 23.9 A/D Converter: Last item (The applied intermediate ...) is added.

366 23.11 Programmable I/O Ports: 4th and 5th items (Indeterminate values ... / When the

PM01 ...) are added.

369 23.14.2 Stop Mode is revised.

23.14.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation

Mode is partly revised.

23.14.8 Operation Speed is revised.

– Revised edition issued

* Revised parts and revised contents are as follows (except for expressional change).

4 Table 1.2 Product Information: Note 2 is added.

22 Table 4.8 SFR Information (8)

• The value of After Reset in IDB0 register is revised.

• The value of After Reset in IDB1 register is revised.

69 Figure 8.12 State Transition to Stop Mode and wait Mode is revised.

100 12.1.3 Effect of Software Wait: 3rd to 9th lines (Figure 12.5 shows ... required.) is moved

to next section of 12.1.4.

2.30

Oct. 24, 2005

2.40

Apr.14, 2006

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-11

2.40

Apr.14, 2006

111 Figure 13.7 Registers TA0MR to TA4MR in Timer Mode: Note 2 is added.

118 Figure 13.11 Registers TA0MR to TA4MR in One-shot Timer Mode: Note 3 is added.

120 Figure 13.12 Registers TA0MR to TA4MR in PWM Mode: Note 4 is added.

125 Figure 13.18 Registers TB0MR to TB5MR in Timer Mode: Note 1 is added.

128 Figure 13.20 Registers TA0MR to TA4MR in Pulse Period and Pulse Width Measurement

Mode: Note 2 is added.

133 Figure 14.3 INVC1 Register: Note 6 is added.

134 Figure 14.4 Registers IDB0 and IDB1 (upper): The value of After Reset is revised.

138 Figure 14.8 Registers TA1MR, TA2MR, TA4MR (upper): Note 1 is added.

Figure 14.8 TB2MR Register (lower): Note 1 is added.

142, 143 Figures 15.1 to 15.3 are revised.

145 Figure 15.5 Registers U0RB to U2RB (middle): Note 3 is added.

146 Figure 15.6 Registers U0C0 to U2C0 (lower): Note 6 is added.

151 Table 15.1 Clock Synchronous Serial I/O Mode Specifications

• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.

• Note 3 is revised.

154 Figure 15.11 Transmit and Receive Operation is revised.

159 Table 15.5 UART Mode Specifications

• Transfer clock: “fj/16(n+1)” is revised to “fj/(16(n+1))” and “fEXT/16(n+1)” is revised

to “fEXT/(16(n+1))” .

• Note 2 is revised.

162 Figure 15.17 Transmit Operation is revised.

163 Table 15.9 Example of Bit Rates and Settings: “Actual Time” is revised to “Bit Rate”.

167 Table 15.10 I2C Mode Specifications

• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.

169 Table 15.11 Registers to Be Used and Settings in I2C Mode: Note 3 is added.

176 Table 15.14 Special Mode 2 Specifications

• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.

183 Table 15.17 SIM Mode Specifications

• Transfer clock: “fj/16(n+1)” is revised to “fj/(16(n+1))” and “fEXT/16(n+1)” is revised

to “fEXT/(16(n+1))”.

185 Figure 15.32 Transmit and Receive Timing in SIM Mode is revised.

187 15.1.6.2 Format is revised.

189 Figure 15.37 S3C Register (upper): Note 6 is added.

190 Table 15.19 SI/O3 Specifications

• Transfer clock: “fj/2(n+1)” is revised to “fj/(2(n+1))”.

191 Figure 15.38 SI/O3 Operation Timing: Cycle and Note 1 is revised. (1.5 -> 0.5 to 1.0)

192 15.2.3 Functions for Setting SOUT3 Initial Value: 2nd item (However...) is added.

211 Figure 17.3 D/A Converter Equivalent Circuit is revised.

220 Figure 19.7 Registers C0CTLR and C1CTLR (upper): NOTE 4 is added.

224 Figure 19.11 Registers C0TSR and C1TSR (3rd register): Note 1 is added.

225 Figure 19.12 Transition between Operational Modes is revised.

REVISION HISTORY M16C/6N Group (M16C/6N4) Hardware Manual

Rev. Date Description

Page Summary

C-12

226 19.5.3 CAN Sleep Mode

• 1st item: “and Reset bit to 0” is deleted.

229 Table 19.2 Examples of Bit-rate is revised.

249 Table 20.2 Unassigned Pin Handling in Memory expansion Mode and Microprocessor Mode

• Pin Name: “P0 to P7” is revised to “P6, P7”.

288 Table 22.4 Electrical Characteristics (1): Hysteresis XIN is deleted.

311 Table 22.32 Electrical Characteristics (1): Hysteresis XIN is deleted.

327 Table 22.51 Electrical Characteristics: Hysteresis XIN is deleted.

342 23.1 SFR is added.

345 23.4 Power Control

• 4th item: Notes when entering stop mode is revised.

346 • 5th item: Notes is added.

360 23.10 A/D Converter

• 1st item: “After stopping ...” is added.

2.40

Apr.14, 2006

M16C/6N Group (M16C/6N4) Hardware Manual

Publication Data : Rev.1.00 May 30, 2003

Rev.2.40 Apr 14, 2006

Published by : Sales Strategic Planning Div.

Renesas Technology Corp.

M16C/6N Group (M16C/6N4)

Hardware Manual

REJ09B0009-0240