CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM (With ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-97888 Rev. *E Revised July 1, 2016
18-Mbit (512 K × 36/1M × 1 8) Flow-Through SRAM (With ECC)
Features
■Supports 133 MHz bus operations
■512K × 36 and 1M × 18 common I/O
■3.3 V core power supply (VDD)
■2.5 V or 3.3 V I/O supply (VDDQ)
■Fast clock-to-output time
❐6.5 ns (133 MHz version)
■Provides high performance 2-1-1-1 access rate
■User selectable burst counter supporting interleaved or linear
burst sequences
■Separate processor and controller address strobes
■Synchronous self-timed write
■Asynchronous output enable
■CY7C1381KV33/CY7C1381KVE33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball
FBGA package. CY7C1383KV33/CY7C1383KVE33 available
in JEDEC-standard Pb-free 100-pin TQFP.
■IEEE 1149.1 JTAG-Compatible Boundary Scan
■ZZ sleep mode option.
■On-chip error correction code (ECC) to reduce soft error rate
(SER)
Functional Description
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 are a 3.3 V, 512K × 36 and 1M × 18
synchronous flow through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
chip enable (CE1), depth-expansion chip enables (CE2 and
CE3), burst control inputs (ADSC, ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an interleaved
burst sequence, while a LOW selects a linear burst sequence.
Burst accesses can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC)
inputs. Address advancement is controlled by the address
advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 operates from a +3.3 V core power supply
while all outputs operate with a +2.5 V or +3.3 V supply. All inputs
and outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description 133 MHz 100 MHz Unit
Maximum access time 6.5 8.5 ns
Maximum operating current × 18 129 114 mA
× 36 149 134 mA
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 2 of 34
Logic Block Diagram – CY7C1381KV33
(512K × 36)
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A
[1:0]
DQs
DQP
A
DQP
B
DQP
C
DQP
D
A0, A1, A
ADV
CLK
ADSP
ADSC
BW
D
BW
C
BW
B
BW
A
BWE
CE1
CE2
CE3
OE
GW
SLEEP
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
WRITE REGISTER
DQ
C
,
DQP
C
WRITE REGISTER
BYTE
WRITE REGISTER
DQ D
,
DQP
D
BYTE
WRITE REGISTER
DQ D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
WRITE REGISTER
DQ
B
,
DQP
B
WRITE REGISTER
DQ
A
,
DQP
BYTE
WRITE REGISTER
Logic Block Diagram – CY7C1381KVE33
(512K × 36)
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A[1:0]
ZZ
DQs
DQPA
DQPB
DQPC
DQPD
A0, A1, A
ADV
CLK
ADSP
ADSC
BWD
BWC
BWB
BWA
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQA
,
DQPA
BYTE
WRITE REGISTER
DQB
,
DQPB
BYTE
WRITE REGISTER
DQC
,
DQPC
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQC
,
DQPC
BYTE
WRITE REGISTER
DQB
,
DQPB
BYTE
WRITE REGISTER
DQA
,
DQPA
BYTE
WRITE REGISTER
ECC
DECODER
ECC
ENCODER
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 3 of 34
Logic Block Diagram – CY7C1383KV33
(1M × 18)
ADDRESS
REGISTER
ADV BURST
COUNTER AND
Q1
Q0
CE
1
OE
SENSE
AMPS
MEMORY
ARRAY
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE
2
CE
3
GW
BWE
A0,A1,A
BW
B
BW
A
DQ
B
,DQP
B
DQ
A
,DQP
A
ENABLE
A[1:0]
DQs
DQP
A
DQP
B
DQ
B
,DQP
B
WRITE DRIVER
DQ
A
,DQP
A
WRITE DRIVER
SLEEP
CONTROL
Logic Block Diagram – CY7C1383KVE33
(1M × 18)
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 4 of 34
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................9
Single Read Accesses ................................................9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ...................9
Burst Sequences .........................................................9
Sleep Mode .................................................................9
Interleaved Burst Address Table ...............................10
Linear Burst Address Table .......................................10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ......................................................................11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 17
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent .........................18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent .........................18
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Timing Diagrams ............................................................ 25
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC®Solutions ....................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 5 of 34
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)
CY7C1381KV33/CY7C1381KVE33 (512K × 36) CY7C1383KV33/CY7C1383KVE33 (1M × 18)
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 6 of 34
Figure 2. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3-Chip Enable)
CY7C1381KV33 (512K × 36)
Pin Configurations (continued)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
DQPC
DQC
DQPD
NC
DQD
CE1BWB CE3
BWCBWE
ACE2
DQC
DQD
DQD
MODE
NC
DQC
DQC
DQD
DQD
DQD
NC/36M
NC/72M
VDDQ
BWDBWACLK GW
VSS VSS VSS VSS
VDDQ VSS
VDD VSS
VSS
VSS
A
VSS
VSS
VSS
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
A
VDD VSS
VDD VSS VSS
VDDQ VDD
VSS
VDD
VSS
VDD VSS VSS
VSS
VDD
VDD VSS
VDD VSS VSS
NC
TCK
VSS
TDI
A
A
DQCVSS
DQCVSS
DQC
DQC
NC
VSS
VSS
VSS
VSS
NC
VSS
A1
DQD
DQD
NC
NC
VDDQ
VSS
TMS
891011
A
ADV A
ADSC NC
OE ADSP ANC/576M
VSS VDDQ NC/1G DQPB
VDDQ
VDD DQB
DQB
DQB
NC
DQB
NC
DQA
DQA
VDD VDDQ
VDD VDDQ DQB
VDD
NC
VDD
DQA
VDD VDDQ DQA
VDDQ
VDD
VDD VDDQ
VDD VDDQ DQA
VDDQ
AA
VSS
A
A
A
DQB
DQB
DQB
ZZ
DQA
DQA
DQPA
DQA
A
VDDQ
A
A0
A
VSS
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 7 of 34
Pin Definitions
Name I/O Description
A0, A1, AInput
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB,
BWC, BWD
Input
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
GW Input
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is
conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).
CLK Input
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1Input
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2Input
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3Input
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE Input
Asynchronou
s
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV Input
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments
the address in a burst cycle.
ADSP Input
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC Input
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWE Input
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
LOW to conduct a byte write.
ZZ Input
Asynchronou
s
ZZ sleep input. This active HIGH input places the device in a non time critical sleep condition with data
integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal
pull down.
DQsI/O
Synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.The outputs are automatically tristated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQPXI/O
Synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQPX is controlled by BWX correspondingly.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 8 of 34
MODE Input Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull-up.
VDD Power Supply Power supply inputs to the core of the device.
VDDQ I/O Power
Supply
Power supply for the I/O circuitry.
VSS Ground Ground for the core of the device.
VSSQ I/O Ground Ground for the I/O circuitry.
TDO JTAG Serial
Output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
not being used, this pin can be left unconnected. This pin is not available on TQFP packages.
TDI JTAG Serial
Input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
used, this pin can be left floating or connected to VDD through a pull-up resistor. This pin is not available
on TQFP packages.
TMS JTAG Serial
Input
Synchronous
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
TCK JTAG
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
NC – No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
VSS/DNU Ground/DNU This pin can be connected to ground or can be left floating.
Pin Definitions (continued)
Name I/O Description
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 9 of 34
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCDV) is 6.5 ns (133 MHz device).
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C138
3KVE33 supports secondary cache in systems using a linear or
interleaved burst sequence. The linear burst sequence is suited
for processors that use a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with the processor address
strobe (ADSP) or the controller address strobe (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically
increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter and/or
control logic, and later presented to the memory core. If the OE
input is asserted LOW, the requested data is available at the data
outputs with a maximum to tCDV after clock rise. ADSP is ignored
if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BWX) are ignored during this first clock cycle. If the write
inputs are asserted active (see Truth Table for Read/Write on
page 12 for appropriate states that indicate a write) on the next
clock rise, the appropriate data is latched and written into the
device. Byte writes are allowed. All I/O are tristated during a byte
write. As this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWX)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered to
the memory core The information presented to DQ[A:D] is written
into the specified address location. Byte writes are allowed. All
I/O are tristated when a write is detected, even a byte write.
Because this is a common I/O device, the asynchronous OE
input signal must be deasserted and the I/O must be tristated
prior to the presentation of data to DQs. As a safety precaution,
the data lines are tristated when a write cycle is detected,
regardless of the state of OE.
Burst Sequences
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C138
3KVE33 provides an on-chip two-bit wraparound burst counter
inside the SRAM. The burst counter is fed by A[1:0], and can
follow either a linear or interleaved burst order. The burst order
is determined by the state of the MODE input. A LOW on MODE
selects a linear burst sequence. A HIGH on MODE selects an
interleaved burst order. Leaving MODE unconnected causes the
device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE1, CE2, CE3,
ADSP
, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 10 of 34
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 65 mA
tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns
tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns
tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 11 of 34
Truth Table
The truth table for CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33 follows. [1, 2, 3, 4, 5]
Cycle Description Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power Down None H X X L X L X X X L–H Tri-State
Deselected Cycle, Power Down None L L X L L X X X X L–H Tri-State
Deselected Cycle, Power Down None L X H L L X X X X L–H Tri-State
Deselected Cycle, Power Down None L L X L H L X X X L–H Tri-State
Deselected Cycle, Power Down None X X H L H L X X X L–H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L–H Q
Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L–H D
Read Cycle, Begin Burst External L H L L H L X H L L–H Q
Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L–H Q
Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L–H Q
Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L–H D
Write Cycle, Continue Burst Next H X X L X H L L X L–H D
Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L–H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L–H D
Write Cycle, Suspend Burst Current H X X L X H H L X L–H D
Notes
1. X = Don't Care, H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for the
remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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Document Number: 001-97888 Rev. *E Page 12 of 34
Truth Table for Read/Write
The truth table for CY7C1381KV33/CY7C1381KVE33 read/write follows. [6, 7]
Function (CY7C1381KV33/CY7C1381KVE33) GW BWE BWDBWCBWBBWA
Read H H X X X X
Read HLHHHH
Write Byte A (DQA, DQPA)HLHHHL
Write Byte B(DQB, DQPB)HLHHLH
Write Bytes A, B (DQA, DQB, DQPA, DQPB)HLHHLL
Write Byte C (DQC, DQPC)HLHLHH
Write Bytes C, A (DQC, DQA, DQPC, DQPA)HLHLHL
Write Bytes C, B (DQC, DQB, DQPC, DQPB)HLHLLH
Write Bytes C, B, A (DQC, DQB, DQA, DQPC, DQPB,
DQPA)
HLHLLL
Write Byte D (DQD, DQPD)HLLHHH
Write Bytes D, A (DQD, DQA, DQPD, DQPA)HLLHHL
Write Bytes D, B (DQD, DQA, DQPD, DQPA)HLLHLH
Write Bytes D, B, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
HLLHLL
Write Bytes D, B (DQD, DQB, DQPD, DQPB) HLLLHH
Write Bytes D, B, A (DQD, DQC, DQA, DQPD, DQPC,
DQPA)
HLLLHL
Truth Table for Read/Write
The truth table for CY7C1383KV33/CY7C1383KVE33 read/write follows. [6, 7]
Function (CY7C1383KV33/CY7C1383KVE33) GW BWE BWBBWA
Write Bytes D, C, A (DQD, DQB, DQA, DQPD, DQPB,
DQPA)
HL L L
Write All Bytes H L L L
Write All Bytes L X X X
Read H H X X
Read H L H H
Write Byte A – (DQA and DQPA)HLHL
Write Byte B – (DQB and DQPB)HLLH
Write All Bytes H L L L
Write All Bytes L X X X
Notes
6. X=Don't Care, H = Logic HIGH, L = Logic LOW.
7. The table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is done based on which byte write is active.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 13 of 34
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1381KV33 incorporates a serial boundary scan test
access port (TAP). This part is fully compliant with 1149.1. The
TAP operates using JEDEC-standard 3.3 V or 2.5 V I/O logic
levels.
CY7C1381KV33 contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
may be left unconnected. At power up, the device comes up in a
reset state, which does not interfere with the operation of the
device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 20 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 19.
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Document Number: 001-97888 Rev. *E Page 14 of 34
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Instruction
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state, when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction when it is shifted in, the TAP controller needs to
be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the Shift-DR controller state.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command places
all SRAM outputs into a high Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required; that is, while data captured is
shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST Output Bus Tri-State
IEEE standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #89
(for 165-ball FBGA package). When this scan cell, called the
“extest output bus tristate,” is latched into the preload register
during the Update-DR state in the TAP controller, it directly
controls the state of the output (Q-bus) pins, when the EXTEST
is entered as the current instruction. When HIGH, it enables the
output buffers to drive the output bus. When LOW, this bit places
the output bus into a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 15 of 34
TAP Controller State Diagram
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1 1
0 0
1 1
1
0
0
0
0 0
0
0
0 0
1
0
1
1
0
1
0
1
1
1
1 0
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 16 of 34
TAP Controller Block Diagram
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 17 of 34
TAP Timing
Figure 3. TAP Timing
tTL
Test Clock
(TCK)
123456
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter [8, 9] Description Min Max Unit
Clock
tTCYC TCK Clock Cycle Time 50 –ns
tTF TCK Clock Frequency –20 MHz
tTH TCK Clock HIGH Time 20 –ns
tTL TCK Clock LOW Time 20 –ns
Output Times
tTDOV TCK Clock LOW to TDO Valid –10 ns
tTDOX TCK Clock LOW to TDO Invalid 0 – ns
Setup Times
tTMSS TMS Setup to TCK Clock Rise 5 – ns
tTDIS TDI Setup to TCK Clock Rise 5 – ns
tCS Capture Setup to TCK Rise 5 – ns
Hold Times
tTMSH TMS Hold after TCK Clock Rise 5 – ns
tTDIH TDI Hold after Clock Rise 5 – ns
tCH Capture Hold after Clock Rise 5 – ns
Notes
8. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 18 of 34
3.3 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times (Slew Rate) ........................... 2 V/ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time (Slew Rate) ............................. 2 V/ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
2.5 V TAP AC Output Load Equivalent
TDO
1.5V
20pF
Z = 50 Ω
O
50Ω
TDO
1.25V
20pF
Z = 50 Ω
O
50Ω
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [10] Description Test Conditions Min Max Unit
VOH1 Output HIGH Voltage IOH = –4.0 mA VDDQ = 3.3 V 2.4 – V
IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V
VOH2 Output HIGH Voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V
VDDQ = 2.5 V 2.1 – V
VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V
IOL = 8.0 mA VDDQ = 2.5 V – 0.4 V
VOL2 Output LOW Voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V
VDDQ = 2.5 V – 0.2 V
VIH Input HIGH Voltage VDDQ = 3.3 V 2.0 VDD + 0.3 V
VDDQ = 2.5 V 1.7 VDD + 0.3 V
VIL Input LOW Voltage VDDQ = 3.3 V –0.3 0.8 V
VDDQ = 2.5 V –0.3 0.7 V
IXInput Load Current GND < VIN < VDDQ –5 5 µA
Note
10. All voltages referenced to VSS (GND).
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 19 of 34
Identification Register Definitions
Instruction Field CY7C1381KV33
(512K × 36) Description
Revision Number (31:29) 000 Describes the version number.
Device Depth (28:24) [11] 01011 Reserved for internal use.
Device Width (23:18)
165-ball FBGA
000001 Defines the memory type and architecture.
Cypress Device ID (17:12) 100101 Defines the width and density.
Cypress JEDEC ID Code
(11:1)
00000110100 Allows unique identification of SRAM vendor.
ID Register Presence
Indicator (0)
1 Indicates the presence of an ID register.
Scan Register Sizes
Register Name Bit Size (× 36)
Instruction Bypass 3
Bypass 1
ID 32
Boundary Scan Order (165-ball FBGA package) 89
Instruction Codes
Instruction Code Description
EXTEST 000 Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to high Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z 010 Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
RESERVED 101 Do Not Use. This instruction is reserved for future use.
RESERVED 110 Do Not Use. This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
11. Bit #24 is “1” in the register definitions for both 2.5 V and 3.3 V versions of this device.
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 20 of 34
Boundary Scan Order
165-ball FBGA [12, 13]
Bit # Ball ID Bit # Ball ID Bit # Ball ID
1N6 31D10 61G1
2N7 32C11 62D2
3N10 33A11 63E2
4P11 34B11 64F2
5P8 35A10 65G2
6R8 36B10 66H1
7R9 37A9 67H3
8P938B968J1
9P10 39C10 69K1
10 R10 40 A8 70 L1
11 R11 41 B8 71 M1
12 H11 42 A7 72 J2
13N11 43B7 73K2
14 M11 44 B6 74 L2
15 L11 45 A6 75 M2
16 K11 46 B5 76 N1
17 J11 47 A5 77 N2
18M10 48A4 78P1
19 L10 49 B4 79 R1
20 K10 50 B3 80 R2
21J10 51A3 81P3
22 H9 52 A2 82 R3
23H10 53B2 83P2
24 G11 54 C2 84 R4
25F11 55B1 85P4
26 E11 56 A1 86 N5
27 D11 57 C1 87 P6
28 G10 58 D1 88 R6
29 F10 59 E1 89 Internal
30 E10 60 F1
Notes
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 89 is pre-set HIGH.
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CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 21 of 34
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. For user guidelines, not tested.
Storage Temperature ............................... –65 °C to +150 °C
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Supply Voltage on VDD Relative to GND .....–0.3 V to +4.6 V
Supply Voltage on VDDQ Relative to GND .... –0.3 V to +VDD
DC Voltage Applied to Outputs
in Tri-State ........................................–0.5 V to VDDQ + 0.5 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature VDD VDDQ
Commercial 0 °C to +70 °C 3.3 V– 5% /
+ 10%
2.5 V – 5% to
VDD
Industrial –40 °C to +85 °C
Neutron Soft Error Immunity
Parameter Description Test
Conditions Typ Max* Unit
LSBU
(Device
without
ECC)
Logical
Single-Bit
Upsets
25 °C <5 5 FIT/
Mb
LSBU
(Device with
ECC)
0 0.01 FIT/
Mb
LMBU Logical
Multi-Bit
Upsets
25 °C 0 0.01 FIT/
Mb
SEL Single Event
Latch up
85 °C 0 0.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [14, 15] Description Test Conditions Min Max Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ I/O Supply Voltage for 3.3 V I/O 3.135 VDD V
for 2.5 V I/O 2.375 2.625 V
VOH Output HIGH Voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V
for 2.5 V I/O, IOH = –1.0 mA 2.0 – V
VOL Output LOW Voltage for 3.3 V I/O, IOL = 8.0 mA – 0.4 V
for 2.5 V I/O, IOL = 1.0 mA – 0.4 V
VIH Input HIGH Voltage[14] for 3.3 V I/O 2.0 VDD + 0.3 V V
for 2.5 V I/O 1.7 VDD + 0.3 V V
VIL Input LOW Voltage[14] for 3.3 V I/O –0.3 0.8 V
for 2.5 V I/O –0.3 0.7 V
Notes
14. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) of at least 200 ms. During this time VIH < VDD and VDDQ <VDD.
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Document Number: 001-97888 Rev. *E Page 22 of 34
IXInput Leakage Current except ZZ
and MODE
GND VI VDDQ –5 5 A
Input Current of MODE Input = VSS –30 –
Input = VDD – 5
Input Current of ZZ Input = VSS –5 –
Input = VDD –30
IOZ Output Leakage Current GND VI VDDQ, Output Disabled –5 5A
IDD VDD Operating Supply VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
100 MHz × 18 – 114 mA
× 36 – 134
133 MHz × 18 – 129
× 36 – 149
ISB1 Automatic CE Power-down
Current – TTL Inputs
Max. VDD,
Device Deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
100 MHz × 18 – 75 mA
× 36 – 80
133 MHz × 18 – 75
× 36 – 80
ISB2 Automatic CE Power-down
Current – CMOS Inputs
Max. VDD,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = 0
All speed
grades
× 18 – 65 mA
× 36 – 70
ISB3 Automatic CE Power-down
Current – CMOS Inputs
Max. VDD,
Device Deselected,
VIN 0.3 V or
VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
100 MHz × 18 – 75 mA
× 36 – 80
133 MHz × 18 – 75
× 36 – 80
ISB4 Automatic CE Power-down
Current – TTL Inputs
Max. VDD,
Device Deselected,
VIN VIH or VIN VIL,
f = 0
All speed
grades
× 18 –65mA
× 36 –70
Electrical Characteristics (continued)
Over the Operating Range
Parameter [14, 15] Description Test Conditions Min Max Unit
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Document Number: 001-97888 Rev. *E Page 23 of 34
Capacitance
Parameter Description Test Conditions 100-pin TQFP
Package
165-ball FBGA
Package Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 2.5 V
55pF
CCLK Clock input capacitance 5 5 pF
CIO Input/Output capacitance 5 5 pF
Thermal Resistance
Parameter Description Test Conditions 100-pin TQFP
Package
165-ball FBGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow
standard test
methods and
procedures for
measuring thermal
impedance, per
EIA/JESD51.
With Still Air (0 m/s) 37.95 17.34 C/W
With Air Flow (1 m/s) 33.19 14.33 C/W
With Air Flow (3 m/s) 30.44 12.63 C/W
JB Thermal resistance
(junction to board)
-- 24.07 8.95 C/W
JC Thermal resistance
(junction to case)
8.36 3.50 C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
V
T
= 1.5 V
3.3 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
OUTPUT
R = 1667
R = 1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
3.3 V I/O Test Load
2.5 V I/O Test Load
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 24 of 34
Switching Characteristics
Over the Operating Range
Parameter [16, 17] Description 133 MHz 100 MHz Unit
Min Max Min Max
tPOWER VDD(typical) to the first access [18] 1–1–ms
Clock
tCYC Clock cycle time 7.5 –10–ns
tCH Clock HIGH 2.1 –2.5–ns
tCL Clock LOW 2.1 –2.5–ns
Output Times
tCDV Data output valid after CLK rise –6.5 – 8.5 ns
tDOH Data output hold after CLK rise 2.0 –2.0–ns
tCLZ Clock to low Z [19, 20, 21] 2.0 –2.0 –ns
tCHZ Clock to high Z [19, 20, 21] 04.0 05.0 ns
tOEV OE LOW to output valid –3.2 –3.8 ns
tOELZ OE LOW to output low Z [19, 20, 21] 0 – 0 – ns
tOEHZ OE HIGH to output high Z [19, 20, 21] –4.0 –5.0 ns
Setup Times
tAS Address setup before CLK rise 1.5 –1.5–ns
tADS ADSP, ADSC setup before CLK rise 1.5 –1.5–ns
tADVS ADV setup before CLK rise 1.5 –1.5–ns
tWES GW, BWE, BW[A:D] setup before CLK rise 1.5 –1.5–ns
tDS Data input setup before CLK rise 1.5 –1.5–ns
tCES Chip enable setup 1.5 –1.5–ns
Hold Times
tAH Address hold after CLK rise 0.5 –0.5–ns
tADH ADSP, ADSC hold after CLK rise 0.5 –0.5–ns
tWEH GW, BWE, BW[A:D] hold after CLK rise 0.5 –0.5–ns
tADVH ADV hold after CLK rise 0.5 –0.5–ns
tDH Data input hold after CLK rise 0.5 –0.5–ns
tCEH Chip enable hold after CLK rise 0.5 –0.5–ns
Notes
16. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
17. Test conditions shown in (a) of Figure 4 on page 23 unless otherwise noted.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be
initiated.
19. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 23. Transition is measured ±200 mV from steady-state voltage
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system condition.
21. This parameter is sampled and not 100% tested.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 25 of 34
Timing Diagrams
Figure 5. Read Cycle Timing [22]
.
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
Data Out (Q) High-Z
tCLZ
tDOH
tCDV
tOEHZ
tCDV
Single READ
BURST
READ
tOEV tOELZ tCHZ
Burst wraps around
to its initial state
tADVH
tADVS
tWEH
tWES
tADH
tADS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1) Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
A2
ADV suspends burst
Deselect Cycle
DON’T CARE UNDEFINED
ADSP
ADSC
G
W, BWE,BW
X
CE
ADV
OE
Note
22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 26 of 34
Figure 6. Write Cycle Timing [23, 24]
.
Timing Diagrams (continued)
tCYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A1
tCEH
tCES
High-Z
BURST READ BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A1) D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2 A3
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH
tADS
tADH
tADS
tOEHZ
tADVH
tADVS
tWEH
tWES
tDH
tDS
tWEH
tWES
Byte write signals are ignored for rst cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
ADSP
ADSC
BWE,
BW
X
GW
CE
ADV
OE
Data in (D)
D
ata Out (Q)
Notes
23. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 27 of 34
Figure 7. Read/Write Cycle Timing [25, 26, 27]
.
Timing Diagrams (continued)
t
CYC
tCL
CLK
tADH
tADS
ADDRESS
tCH
tAH
tAS
A2
tCEH
tCES
Single WRITE
D(A3)
A3 A4
BURST READ
Back-to-Back READs
High-Z
Q(A2) Q(A4) Q(A4+1)
Q(A4+2)
Q(A4+3)
tWEH
tWES
tOEHZ
tDH
tDS
tCDV
tOELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW X
CE
ADV
OE
Data In (D)
D
ata Out (Q)
Notes
25. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC.
27. GW is HIGH.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 28 of 34
Figure 8. ZZ Mode Timing [28, 29]
Timing Diagrams (continued)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
28. Device must be deselected when entering ZZ mode. See Truth Table on page 11 for all possible signal conditions to deselect the device.
29. DQs are in high Z when exiting ZZ sleep mode.
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 29 of 34
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a
worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit
us at t http://www.cypress.com/go/datasheet/offices.
Ordering Code Definitions
Speed
(MHz) Ordering Code Package
Diagram Part and Package Type Operating
Range
133 CY7C1381KV33-133AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
CY7C1383KV33-133AXC
CY7C1381KVE33-133AXI lndustrial
CY7C1381KV33-133AXI
CY7C1383KVE33-133AXI
CY7C1383KV33-133AXI
100 CY7C1381KV33-100AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
CY7C1381KV33-100BZXI 51-85180 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free lndustrial
Temperature range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = -40 °C to +85 °C
X = Pb-free; X Absent = Leaded
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 100 MHz or 133 MHz
33 = 3.3 V VDD
E = Device with ECC; E Absent = Device without ECC
Process Technology: K =65 nm
Part Identifier: 13XX = 1381 or 1383
1381 = FT, 512Kb × 36 (18Mb)
1383 = FT, 1Mb × 18 (18Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
C 13XX -XXX X
XX
33 X
CY 7KV E
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 30 of 34
Package Diagrams
Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *E
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 31 of 34
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
Package Diagrams (continued)
51-85180 *G
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 32 of 34
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
FBGA Fine-Pitch Ball Grid Array
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
JTAG Joint Test Action Group
LMBU Logical Multi-Bit Upsets
LSB Least Significant Bit
LSBU Logical Single-Bit Upsets
MSB Most Significant Bit
OE Output Enable
SEL Single Event Latch Up
SRAM Static Random Access Memory
TAP Test Access Port
TCK Test Clock
TDI Test Data-In
TDO Test Data-Out
TMS Test Mode Select
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
ms millisecond
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Document Number: 001-97888 Rev. *E Page 33 of 34
Document History Page
Document Title: CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/CY7C1383KVE33, 18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM (With ECC)
Document Number: 001-97888
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*C 4983482 DEVM 10/26/2015 Changed status from Preliminary to Final.
*D 5085859 DEVM 01/14/2016 Post to external web.
*E 5333612 PRIT 07/01/2016 Updated Truth Table.
Updated Neutron Soft Error Immunity:
Updated values in “Typ” and “Max” columns corresponding to LSBU (Device
without ECC) parameter.
Updated to new template.
Document Number: 001-97888 Rev. *E Revised July 1, 2016 Page 34 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
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