APRIL 2012
DSC-5313/10
1
©2012 Integrated Device Technology, Inc.
A
0
-A
19
Address Inputs Input Synchronous
CE
1
, CE
2
, CE
2
Chip Enables Input Synchronous
OE Output Enable Input Asynchronous
R/WRead/Write Signal Input Synchronous
CEN Clock Enable Input Synchronous
BW
1
, BW
2
, BW
3
, BW
4
Individual Byte Write Selects Input Synchronous
CLK Clock Input N/A
ADV/LD A dvance burst address / Load new address Input Synchronous
LBO Linear / Interleaved Burst Order Input Static
TMS Test Mode Select Input N/A
TDI Test Data Input Input N/A
TCK Test Clock Input N/A
TDO Test Data Input Output N/A
TRST JTAG Reset (Optional) Input Asynchronous
ZZ Sleep Mode Input Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output I/O Synchronous
V
DD
, V
DDQ
Core Power, I/O Power Supply Static
V
SS
Ground Supply Static
5313 tbl 01
Pin Description Summary
Features
• 512K x 36, 1M x 18 memory configurations
• Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
• ZBTTM Feature - No dead cycles between write and read
cycles
• Internally synchronized output buffer enable eliminates the
need to control OE
• Single R/W (READ/WRITE) control pin
• Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
• 4-word burst capability (interleaved or linear)
• Individual byte write (BW1 - BW4) control (May tie active)
• Three chip enables for simple depth expansion
• 2.5V power supply (±5%)
• 2.5V I/O Supply (VDDQ)
• Power down controlled by ZZ input
• Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
• Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
IDT71T75602
IDT71T75802
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Description
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or Zero
Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71T75602/802 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable CEN pin allows operation of the IDT71T75602/802
to be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
6.42
2
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
19
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,
any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.
R/WRead / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
BW
1
-BW
4
Individual Byte
Write Enables
I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW
4
) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled
high. The appropriate byte(s) of data are written into the device two cycles later. BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
CE
1
, CE
2
Chip Enables I LOW Synchronous active low chip enable. CE
1
and CE
2
are used with CE
2
to enable the IDT71T75602/802 (CE
1
or CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
CE
2
Chip Enable I HIGH Synchronous active high chip enable. CE
2
is used with CE
1
and CE
2
to enable the chip. CE
2
has inverted polarity
but otherwise identical to CE
1
and CE
2
.
CLK Clock I N/A This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered
by the rising edge of CLK.
LBO Linear Burst Order I LOW Burst order selection i nput. When LBO is high the Interleaved burst sequence is selected. When LBO is low the
Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
OE Output Enable I LOW Asynchronous output enable . OE must be low to read data from the 71T75602/802. Whe n OE is high the I/O pins
are in a high-imped ance state.OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Test Data Input I N/A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
TDO Test Data Output O N/A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
TRST JTAG Reset
(Optional) ILOW
Optio nal asynchronous JTAG reset. Can be used to reset the TAP controller, b ut not required. JTAG reset occurs
automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left
floating. This pin has an internal pullup. Only available in BGA package.
ZZ Sleep Mode I HIGH Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
V
DD
Power Supply N/A N/A 2.5V core power supply.
V
DDQ
Power Supply N/A N/A 2.5V I/O Supply.
V
SS
Ground N/A N/A Ground.
5313 tbl 02
Description (cont.)
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
The IDT71T75602/802 have an on-chip burst counter. In the burst
mode, the IDT71T75602/802 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
used to load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA).
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
Clk
DQ
DQ
DQ
Address A [0:18]
Control Logic
Address
Control
DI DO
Input Register
5313 drw 01
Clock
Data I/O [0:31],
I/O P[1:4]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 512Kx36 BIT
MEMORY ARRAY
JTAG
TMS
TDI
TCK TDO
TRST
(optional)
Clk
DQ
DQ
DQ
Address A [0:19]
Control Logic
Address
Control
DI DO
Input Register
5313 drw 01b
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Clk
Output Register
Mux Sel
Gate
OE
CE1, CE2, CE2
R/W
CEN
ADV/LD
BWx
LBO 1Mx18 BIT
MEMORY ARRAY
JTAG
TMS
TDI
TCK TDO
TRST
(optional)
6.42
4
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Pin Configuration — 512K x 36
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with
normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left
unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG
circuit will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
Top View
100 TQFP
Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
DD
Core Supply Voltage 2.375 2.5 2.625 V
V
DDQ
I/O Supply Voltage 2.375 2.5 2.625 V
V
SS
Ground 000V
V
IH
Input High Voltage - Inputs 1.7
____
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 1.7
____
V
DDQ
+0.3 V
V
IL
Input Low Voltage -0.3
(1)
____
0.7 V
5313 tbl 03
Grade Ambient
Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial 0° C to +70° C OV 2.5V ± 5% 2.5V ± 5%
Industrial -40° C to +85° C OV 2.5V ± 5% 2.5V ± 5%
5313 tbl 05
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A6
A7
CE1
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
A
18
A8
A9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC / TCK
(2,3)
NC / TDO
(2)
NC / TDI
(2)
NC / TMS
(2)
LBO
A14
A13
A12
A11
A10
VDD
VSS
A0
A1
A2
A3
A4
A5
I/O31
I/O30
VDDQ
VSS
I/O29
I/O28
I/O27
I/O26
VSS
VDDQ
I/O25
I/O24
VSS
VDD
I/O23
I/O22
VDDQ
VSS
I/O21
I/O20
I/O19
I/O18
VSS
VDDQ
I/O17
I/O16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VDD
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
5313 drw 02
VDD
(1)
I/O15
I/OP3
VDD
(1)
I/OP4
A15
A16
I/OP1
VDD
(1)
I/OP2
ZZ
A17
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
Absolute Maximum Ratings(1)
Pin Configuration — 1Mx 18
100-Pin TQFP Capacitance
(TA = +25°C, f = 1.0MHz)
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the
input voltage is ≥ VIH.
2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42
should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38,
39 and 43 could be left unconnected “NC” and the JTAG circuit will remain
disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary; however,
the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp
up.
7. During production testing, the case temperature equals TA.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Commercial Industrial Unit
V
TE RM
(2)
Terminal Voltage with
Respect to GND -0.5 to +3.6 -0.5 to +3.6 V
V
TE RM
(3,6)
Terminal Voltage with
Respect to GND -0.5 to V
DD
-0.5 to V
DD
V
V
TE RM
(4,6)
Terminal Voltage with
Respect to GND -0.5 to V
DD
+0.5 -0.5 to V
DD
+0.5 V
V
TE RM
(5,6)
Terminal Voltage with
Respect to GND -0.5 to V
DDQ
+0.5 -0.5 to V
DDQ
+0.5 V
T
A
(7)
Operating Ambient
Temperature 0 to +70 -40 to +85
o
C
T
BIAS
Temperature Under Bias -55 to +125 -55 to +125
o
C
T
STG
Storage Temperature -55 to +125 -55 to +125
o
C
P
T
Power Dissipation 2.0 2.0 W
I
OUT
DC Output Current 50 50 mA
53 13 tb l 06
Symbol Parameter
(1)
Conditions Max. Unit
CIN Input Capacitance VIN = 3dV 5 pF
CI/O I/O Cap acitance VOUT = 3dV 7 pF
5313 tbl 07
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
19
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5313 drw 02a
V
DD(1)
NC
NC
V
DD(1)
NC
A
16
A
17
NC
V
DD(1)
A
10
ZZ
A
18
,
NC / TCK
(2,3)
NC / TDO
(2)
NC / TDI
(2)
NC / TMS
(2)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
5313 tbl 07a
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
5313 tbl 07b
165 fBGA Capacitance
(TA = +25°C, f = 1.0MHz)
119 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
6.42
6
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. J3, R5, and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are
possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3, U4 and U6
could be left unconnected “NC” and the JTAG circuit will remain disabled from power up.
3. The 36M address will be ball T6 (for the 512K x 36 device) and ball T4 (for the 1M x 18 device).
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
Top View
Pin Configuration — 1M X 18, 119 BGA(1,2)
Top View
Pin Configuration — 512K X 36, 119 BGA(1,2)
12345 6 7
AV
DDQ
A
6
A
4
A
18
A
8
A
16
V
DDQ
BNCCE
2
A
3
ADV/LD A
9
CE
2
NC
CNCA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
CE
1
V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
A
17
BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
R/WV
SS
I/O
9
I/O
8
JV
DDQ
V
DD
V
DD
(1)
V
DD
V
DD
(1)
V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
CEN V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
P1
I/O
0
RNCA
5
LBO V
DD
V
DD
(1)
A
13
NC
TNCNCA
10
A
11
A
14
NC
(3)
ZZ
UV
DDQ NC/TMS
(2)
NC/TDI
(2)
NC/TCK(2) NC/TDO(2)
NC/TRST
(2, 4 )
V
DDQ
53 13 tbl 25
1234567
AV
DDQ
A
6
A
4
A
19
A
8
A
16
V
DDQ
BNCCE
2
A
3
ADV/LD A
9
CE
2
NC
CNCA
7
A
2
V
DD
A
13
A
17
NC
DI/O
8
NC V
SS
NC V
SS
I/O
P1
NC
ENCI/O
9
V
SS
CE
1
V
SS
NC I/O
7
FV
DDQ
NC V
SS
OE V
SS
I/O
6
V
DDQ
GNCI/O
10
BW
2
A
18
V
SS
NC I/O
5
HI/O
11
NC V
SS
R/WV
SS
I/O
4
NC
JV
DDQ
V
DD
V
DD
(1)
V
DD
V
DD
(1)
V
DD
V
DDQ
KNCI/O
12
V
SS
CLK V
SS
NC I/O
3
LI/O
13
NC V
SS
NC BW
1
I/O
2
NC
MV
DDQ
I/O
14
V
SS
CEN V
SS
NC V
DDQ
NI/O
15
NC V
SS
A
1
V
SS
I/O
1
NC
PNCI/O
P2
V
SS
A
0
V
SS
NC I/O
0
RNCA
5
LBO V
DD
V
DD
(1)
A
12
NC
TNCA
10
A
15
NC
(3)
A
14
A
11
ZZ
UV
DDQ NC/TMS
(2)
NC/TDI
(2)
NC/TCK
(2)
NC/TDO
(2)
NC/TRST(2, 4 )
V
DDQ
531 3 tb l 25a
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
7
Synchronous Truth Table(1)
Partial Truth Table for Writes(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst
cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state
two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
CEN R/WChip
(5)
Enable
ADV/LD BWxADDRESS
USED
PREVIOUS CYCLE CURRENT CYCLE I/O
(2 cycles later)
L L Select L Valid External X LOAD WRITE D
(7)
L H Select L X External X LOAD READ Q
(7)
L X X H Valid Internal LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)
(2)
D
(7)
L X X H X Internal LOAD READ /
BURST READ
BURST READ
(Advance burst counter)
(2)
Q
(7)
L X Deselect L X X X DESELECT or STOP
(3)
HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUSPEND
(4)
Previous Value
53 13 tbl 08
OPERATION R/WBW
1
BW
2
BW
3(3)
BW
4(3)
READ H X X X X
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O[0:7], I/O
P1
)
(2)
L L HHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)
(2)
LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)
(2,3)
LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)
(2,3)
LHHHL
NO WRITE LHHHH
5313 tbl 09
6.42
8
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Interleaved Burst Sequence Table (LBO=VDD)
Functional Timing Diagram(1)
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay
from the rising edge of clock.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 000110 11
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
53 13 tbl 10
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 000110 11
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
5313 tbl 11
n+29
A29
C29
D/Q27
ADDRESS(2)
(A
0
- A
18
)
CONTROL(2)
(R/W, ADV/LD, BWx)
DATA(2)
I/O
[0:31]
, I/O P
[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q28
n+31
A31
C31
D/Q29
n+32
A32
C32
D/Q30
n+33
A33
C33
D/Q31
n+34
A34
C34
D/Q32
n+35
A35
C35
D/Q33
n+36
A36
C36
D/Q34
n+37
A37
C37
D/Q35
5313drw 03
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
9
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Read Operation(1)
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Cycle Address R/WADV/LD CE
(1)
CEN BWxOE I/O Comments
nA
0
HL LLXXXLoad read
n+1 X X H X L X X X Burst read
n+2 A
1
HL LLXLQ
0
Load read
n+3 X X L H L X L Q
0+1
Deselect or STOP
n+4 X X H XLXLQ
1
NOOP
n+5 A
2
HL LLXXZLoad read
n+6 X X H X L X X Z Burst read
n+7 X X L H L X L Q
2
Deselect or STOP
n+8 A
3
L L LLLLQ
2+1
Load write
n+9 X X H X L L X Z Burst write
n+10 A
4
L L LLLXD
3
Load write
n+11 X X L H L X X D
3+1
Deselect or STOP
n+12 X X H X L X X D
4
NOOP
n+13 A
5
L L L L L X Z Load write
n+14 A
6
HL LLXXZLoad read
n+15 A
7
L L LLLXD
5
Load write
n+16 X X H XLLLQ
6
Burst write
n+17 A
8
HL LLXXD
7
Load read
n+18 X X H X L X X D
7+1
Burst read
n+19 A
9
L L LLLLQ
8
Load write
53 13 tbl 12
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X L X X X Clock Setup Valid
n+2 X X X XXXLQ
0
Contents of Address A
0
Read Out
53 13 tbl 13
6.42
10
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Burst Write Operation(1)
Burst Read Operation(1)
Write Operation(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0H L L L X X X Address and Control meet setup
n+1 X X H X L X X X Clock Setup Valid, Advance Counter
n+2 X X H XLXLQ
0Address A0 Read Out, Inc. Count
n+3 X X H XLXLQ
0+1 Address A0+1 Read Out, Inc. Count
n+4 X X H XLXLQ
0+2 Address A0+2 Read Out, Inc. Count
n+5 A1HL LLXLQ0+3 Address A0+3 Read Out, Load A1
n+6 X X H XLXLQ0Address A0 Read Out, Inc. Count
n+7 X X H XLXLQ
1Address A1 Read Out, Inc. Count
n+8 A2HL LLXLQ1+1 Address A1+1 Read Out, Load A2
53 13 tbl 14
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X X X L X X X Clock Setup Valid
n+2 X X X X L X X D
0
Write to Address A
0
53 13 tbl 15
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X H X L L X X Clock Setup Valid, Inc. Count
n+2 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+3 X X H X L L X D
0+1
Address A
0+1
Write, Inc. Count
n+4 X X H X L L X D
0+2
Address A
0+2
Write, Inc. Count
n+5 A
1
L L LLLXD
0+3
Address A
0+3
Write, Load A
1
n+6 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+7 X X H X L L X D
1
Address A
1
Write, Inc. Count
n+8 A
2
L L LLLXD
1+1
Address A
1+1
Write, Load A
2
53 13 tbl 16
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
11
Read Operation with Clock Enable Used(1)
Write Operation with Clock Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X H X X X Clock n+1 Ignored
n+2 A
1
HL LLXXXClock Valid
n+3 X X X X H X L Q
0
Clock Ignored. Data Q
0
is on the bus.
n+4 X X X X H X L Q
0
Clock Ignored. Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
0
Address A
0
Read out (bus trans.)
n+6 A
3
HL LLXLQ
1
Address A
1
Read out (bus trans.)
n+7 A
4
HL LLXLQ
2
Address A
2
Read out (bus trans.)
53 13 tbl 17
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
nA
0
L L L L L X X Address and Control meet setup.
n+1 X X X X H X X X Clock n+1 Ignored.
n+2 A
1
L L LLLXXClock Valid.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
2
L L LLLXD
0
Write Data D
0
n+6 A
3
L L LLLXD
1
Write Data D
1
n+7 A
4
L L LLLXD
2
Write Data D
2
53 13 tbl 18
6.42
12
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation with Chip Enable Used(1)
Write Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
H L L L X X Z Address and Control meet setup.
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
HL LLXLQ
0
Address A
0
Read out. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X L Q
1
Address A
1
Read out. Deselected.
n+7 A
2
H L L L X X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X L Q
2
Address A
2
Read out. Deselected.
53 13 tbl 19
Cycle Address R/WADV/LD CE
(2)
CEN BWxOE I/O Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X ? Deselected.
n+2 A
0
L L L L L X Z Address and Control meet setup.
n+3 X X L H L X X Z Deselected or STOP.
n+4 A
1
L L LLLXD
0
Address D
0
Write in. Load A
1
.
n+5 X X L H L X X Z Deselected or STOP.
n+6 X X L H L X X D
1
Address D
1
Write in. Deselected.
n+7 A
2
L L L L L X Z Address and control meet setup.
n+8 X X L H L X X Z Deselected or STOP.
n+9 X X L H L X X D
2
Address D
2
Write in. Deselected.
5313 tbl 20
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
13
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
AC Test Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%)
Figure 1. AC Test Load
AC Test Load
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD, and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
Symbol Parameter Test Conditions Min. Max. Unit
|ILI| Input Leakage Current VDD = Max., VIN = 0V to VDD ___ 5µA
|ILI|LBO, JTAG and ZZ Input Leakage Current
(1)
VDD = Max., VIN = 0V to VDD ___ 30 µA
|ILO| Output Leakage Current VOUT = 0V to VDDQ, Device Deselected ___ 5µA
VOL Output Low Voltage IOL = +6mA, VDD = Min. ___ 0.4 V
VOH Output High Voltage IOH = -6mA, VDD = Min. 2.0 ___ V
5313 tbl 21
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 2.5V
2ns
(V
DDQ
/2)
(V
DDQ
/2)
See Figure 1
5313 tbl 23
V
DDQ
/2
50Ω
I/O Z
0
= 50Ω
5313 drw 04
1
2
3
4
20 30 50 100 200
ΔtCD
(Ty pical , ns)
Capaci t ance (pF )
80
5
6
•
•
•
•
•
5313 dr 05
Symbol Parameter Test Conditions
200MHz 166MHz 150MHz 133MHz 100MHz
Unit
Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind
I
DD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX(2)
275 295 245 265 215 235 195 215 175 195 mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0
(2,3)
40 60 40 60 40 60 40 60 40 60 mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = f
MAX(2.3)
80 100 70 90 60 80 50 70 45 65 mA
I
SB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN > V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX(2,3)
60 80 60 80 60 80 60 80 60 80 mA
I
ZZ
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
CEN < V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX(2,3)
,ZZ > V
HD
40 60 40 60 40 60 40 60 40 60 mA
5313 tbl 22
6.42
14
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = 2.5V +/-5%, Commercial and Industrial
Temperature Ranges)
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is faster than tCLZ (device turn-on) at a given temperature and voltage. The specs
as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ, which is a Max.
parameter (worse case at 70 deg. C, 2.375V).
200MHz 166MHz 150MHz 133MHz 100MHz
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit
t
CYC
Clock Cycle Time 5
____
6
____
6.7
____
7.5
____
10
____
ns
t
F
(1)
Clock Frequency
____
200
____
166
____
150
____
133
____
100 MHz
t
CH
(2)
Clock High Pulse Width 1.8
____
1.8
____
2.0
____
2.2
____
3.2
____
ns
t
CL
(2)
Clock Low Pulse Width 1.8
____
1.8
____
2.0
____
2.2
____
3.2
____
ns
Output Parameters
t
CD
Clock High to Valid Data
____
3.2
____
3.5
____
3.8
____
4.2
____
5ns
t
CDC
Clock High to Data Change 1.0
____
1.0
____
1.5
____
1.5
____
1.5
____
ns
t
CLZ
(3,4,5)
Clock High to Output Active 1.0
____
1.0
____
1.5
____
1.5
____
1.5
____
ns
t
CHZ
(3,4,5)
Clock High to Data High-Z 1.0 3 1.0 3 1.5 3 1.5 3 1.5 3.3 ns
t
OE
Output Enable Access Time
____
3.2
____
3.5
____
3.8
____
4.2
____
5ns
t
OLZ
(3,4)
Output Enable Low to Data Active 0
____
0
____
0
____
0
____
0
____
ns
t
OHZ
(3,4)
Output Enable High to Data High-Z
____
3.2
____
3.5
____
3.8
____
4.2
____
5ns
Set Up Times
t
SE
Clock Enable Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SA
Address Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SD
Data In Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SW
Read/Write (R/W) Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SADV
Advance/Load (ADV/LD) Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SC
Chip Enable/Select Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
t
SB
Byte Write Enable (BWx) Setup Time 1.4
____
1.5
____
1.5
____
1.7
____
2.0
____
ns
Hold Times
t
HE
Clock Enable Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HA
Address Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HW
Read/Write (R/W) Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HADV
Advance/Load (ADV/LD) Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HB
Byte Write Enable (BWx) Hold Time 0.4
____
0.5
____
0.5
____
0.5
____
0.5
____
ns
5313 tbl 24
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
15
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control
are loaded into the SRAM.
ADV/LD
(CEN high, eliminates
current L-H clock edge)
tCD
tHADV
Pipeline
Read
(Burst Wraps around
to initial state)
tCDC
tCLZ tCHZ
tCD
tCDC
R/W
CLK
CEN
ADDRESS
OE
DATAOUT
tHE
tSE
A1 A2
tCH tCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst Pipeline Read
Pipeline
Read
BW1 - BW4
5313 drw 06
CE1, CE2
(2)
Q(A2+3)Q(A2)
Q(A2+2)
Q(A2+2)
Q(A2+1)
Q(A2)
Q(A1)
6.42
16
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control
are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Write Cycles(1,2,3,4,5)
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
OE
DATAIN
tHD
tSD
tCH tCL
tCYC
tHADV
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst Pipeline Write
Pipeline
Write
Pipeline
Write
tHB
tSB
(Burst Wraps around
to initial state)
tHD
tSD
(CEN high, eliminates
current L-H clock edge)
(2)
D(A2+2)D(A2+3)
D(A1)D(A2)D(A2)
5313 drw 07
BW1 - BW4
CE1, CE2
D(A2+1)
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
17
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of Combined Read and Write Cycles(1,2,3)
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
CE1, CE2(2)
BW1 - BW4
DATAOUT Q(A3)
Q(A1)Q(A6)Q(A7)
tCD
Read
tCHZ
5313 drw 08
Write
tCLZ
D(A2)D(A4)
tCDC
D(A5)
Write
tCH tCL
tCYC
tHW
tSW
tHA
tSA
A4
A3
tHC
tSC
tSD tHD
tHADV
tSADV
A6A7A8
A5A9
DATAIN
tHB
tSB
OE
Read
Read
6.42
18
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not
occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
Timing Waveform of CEN Operation(1,2,3,4)
tHE
tSE
R/W
A1A2
CLK
CEN
ADV/LD
ADDRESS
BW1 - BW4
OE
DATAOUT Q(A3)
tCD
tCLZ
tCHZ
tCH tCL
tCYC
tHC
tSC
D(A2)
tSD tHD
tCDC
A4A5
tHADV
tSADV
tHW
tSW
tHA
tSA
A3
tHB
tSB
DATAIN
Q(A1)
5313 drw 09
Q(A1)
B(A2)
CE1, CE2(2)
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
19
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3.
2CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not
occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
OE
DATAOUT Q(A1)
tCD
tCLZ
tCHZ
tCDC
tCH tCL
tCYC
tHC
tSC
tSD tHD
A5
A3
tSB
DATAIN
tHE
tSE
A2
tHA
tSA
A4
tHW
tSW
tHB
CEN
tHADV
tSADV
5313 drw 10
Q(A2)Q(A4)
D(A3)
BW1 - BW4
CE1, CE2
(2)
6.42
20
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
JTAG Interface Specification
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(3)
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M5313 drw 01
x
Symbol Parameter Min. Max. Units
tJCYC JTAG Clock Input Period 100
____
ns
tJCH JTAG Clock HIGH 40
____
ns
tJCL JTAG Clock Low 40
____
ns
tJR JTAG Clock Rise Time
____
5
(1)
ns
tJF JTAG Clock Fall Time
____
5
(1)
ns
tJRST JTAG Reset 50
____
ns
tJRSR JTAG Reset Recovery 50
____
ns
tJCD JTAG Data Output
____
20 ns
tJDC JTAG Data Output Hold 0
____
ns
tJS JTAG Setup 25
____
ns
tJH JTAG Hold 25
____
ns
I5313 tbl 01
Register Name Bit Size
Instruction (IR) 4
Bypass (BYR) 1
JTAG Identification (JIDR) 32
Boundary Scan (BSR) Note (1)
I5313 tbl 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JTAG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
21
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instruction Field Value Description
Revision Number (31:28) 0x2 Reserved for version number.
IDT Device ID (27:12) 0x220, 0x222 Define s IDT part number 71T75602 and 71T75802, respectively.
IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register.
I5313 tbl 02
JTAG Identification Register Definitions
Instruction Description OPCODE
EXTEST Forces contents of the boundary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO. 0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
and outputs
(1)
to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO. 0010
HIGHZ Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state. 0011
RESERVED
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
0100
RESERVED 0101
RESERVED 0110
RESERVED 0111
CLAMP Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO. 1000
RESERVED
Same as above.
1001
RESERVED 1010
RESERVED 1011
RESERVED 1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mand ated by the IEEE std. 1149.1 specification.
1101
RESERVED Same as above. 1110
BYPASS The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length. 1111
I5313 tbl 04
Available JTAG Instructions
6.42
22
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATAOUT
tOHZ tOLZ
tOE
Valid
5313 drw 11
100-Pin Plastic Thin Quad Flatpack (TQFP)
TQFP - Green
119 Ball Grid Array (BGA)
BGA - Green
S
Power
XX
Speed
XX
Package
XXXX
*200
166
150
133
100
Clock Frequency in Megahertz
5313 drw 12
Device
Type
71T75602
71T75802
512Kx36 Pipelined ZBT SRAM
1Mx18 Pipelined ZBT SRAM
PF
PFG
BG
BGG
X
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
8
Tube or Tray
Tape and Reel
X
* 200MHz available Only for IDT71T75802
6.42
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
23
Datasheet Document History
Rev Date Pages Description
0 04/20/00 Created New Datasheet
1 05/25/00 Pg.1,14,15,25 Added 166MHz speed grade offering
Pg. 1,2,14 Corrected error in ZZ Sleep Mode
Pg. 23 AddBQ165 Package Diagram Outline
Pg. 24 Corrected 119BGA Package Diagram Outline.
Pg. 25 Corrected topmark on ordering information
2 08/23/01 Pg. 1,2,24 Removed reference of BQ165 Package
Pg. 7 Removed page of the 165 BGA pin configuration
Pg. 23 Removed page of the 165 BGA package diagram outline
3 10/16/01 Pg. 6 Corrected 3.3V to 2.5V in Note 2
10/29/01 Pg. 13 Improved DC Electrical characteristics-parameters improved: Icc, ISB2, ISB3, IZZ.
4 12/21/01 Pg. 4-6 Added clarification to JTAG pins, allow for NC. Added 36M address pin locations.
Pg. 14 Revised 166MHz tCDC(min), tCLZ(min) and tCHZ(min) to 1.0ns
5 06/07/02 Pg. 1-3,6,13,20,21 Added complete JTAG functionality.
Pg. 2,13 Added notes for ZZ pin internal pulldown and ZZ leakage current.
Pg. 13,14,24 Added 200MHz and 225MHz to DC and AC Electrical Characteristics. Updated supply current for
Idd, ISB1, ISB3 and Izz.
6 11/19/02 Pg.1-24 Changed datasheet from Advanced Information to final release.
Pg.13 Updated DC Electrical characteristics temperature and voltage range table.
7 05/23/03 Pg.4,5,13,14,24 Added I-temp to the datasheet.
Pg.5 Updated 165 BGA Capacitance table.
8 04/01/04 Pg. 1 Updated logo with new design.
Pg. 4,5 Clarified ambient and case operating temperatures.
Pg. 6 Updated pin I/O number order for the 119 BGA.
Pg. 23 Updated 119BGA Package Diagram Drawing.
9 10/01/08 Pg. 1,13,14,24 Deleted 225MHz part, added 200MHz Industrial grade and added green packages. Updated the
ordering information by removing the “IDT” notation.
10 04/04/12 Pg. 2,22 Updated text on Page 2 last paragraph. Added Note to ordering information and updated to include
tube or tray and tape & reel.
.
The IDT logo is a registered trademark of Integrated Device Technology, Inc. All brands or products are the trademarks or registered trademarks of their respective owners.
ZBT® and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 800-345-7015 or
www.idt.com 408/284-4555