L6569AD - STMICROELECTRONICS - Datasheet.Directory

1/13

L6569

L6569A

June 2000

This is preliminary information on a new product now in development. Details are subject to change without notice.

■HIGH VOLTAG E RAIL UP TO 600V

■BCD OFF LINE TECHNOLOGY

■INTERNAL BOOTSTRAP DIODE

STRUCTURE

■15.6V ZENER CLAMP ON VS

■DRIVER CURRENT CAPABILITY:

- SINK CURRENT = 270mA

- SOURCE CURRENT = 170mA

■VERY LOW START UP CURRENT: 150µA

■UNDER VOLTAGE LOCKOU T WITH

HYSTERESIS

■PROGRAMM ABLE OSCILLATOR

FREQUENCY

■DEAD TIME 1.25µs

■dV/dt IMMUNITY UP TO ±50V/ns

■ESD PRO TECT ION

DESCRIPTION

The device is a high voltage half bridge driver with

built in oscillator. The frequency of the oscillator can

be programmed using external resistor and capaci-

tor. The internal circuitry of the device allows it to be

driven also by external logic signal.

The output drivers are designed to drive external n-

channel power MOSFET and IGBT. The internal log-

ic assures a dead time [typ. 1.25

s] to avoid cross-

conduction of the power devices.

Two version are available: L6569 and L6569A. They

differ in the l ow voltage gate driver star t up seq uence.

Minidip SO8

ORDER ING NUMB ERS :

L6569 L6569D

L6569A L6569AD

HIGH VOLTAGE HALF BRIDGE

DRIVER WITH OSCILLATOR

BLOCK DIAGRAM

LOGIC

BIAS

REGULATOR

COMP

LEVEL

SHIFTER

BUFFER

GND

HIGH

SIDE

DRIVER

LOW SIDE

DRIVER

HVG

LVG

OUT

BOOTV

BOOT

H.V.

LOAD

D94IN058D

CHARGE

PUMP

Source

L6569 L6569A

2/13

ABSOLUTE MAXIMUM RATINGS

(*) T he dev i ce has an internal zener c l am p betw een GND and V S (typi cal 15.6 V). T heref ore the cir cuit sh oul d not b e dri ven by a DC low im-

pedance power source.

Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)

THERMAL DATA

RECOMMENDED OPERATING CONDITIONS

PIN CONNECTION

Symbol Parameter Value Unit

IS (*) Supply Current 25 mA

VCF Oscillator Resistor Voltage 18 V

VLVG Low Side Switch Gate Output 14.6 V

VOUT High Side Switch Source Output -1 to VBOOT - 18 V

VHVG High Side Switch Gate Output -1 to VBOOT V

VBOOT Floating Supply Voltage 618 V

VBOOT/OUT Floating Supply vs OUT Voltage 18 V

dVBOOT/dt VBOOT Slew Rate (Repetitive) ± 50 V/ns

dVOUT/dt VO UT Slew Rate (Repetitive) ± 50 V/ns

Tstg Storage Temperature -40 to 150 °C

TjJunction Temperature -40 to 150 °C

Tamb Ambient Temperature (Operative) -40 to 125 °C

Symbol Parameter Minidip SO8 Unit

Rth j-amb Thermal Resistance Junction-Ambient Max 100 150 °C/W

Symbol Parameter Min. Max. Unit

VSSupply Voltage 10 VCL V

VBOOT Floating Supply Voltage - 500 V

VOUT High Side Switch Source Output -1 VBOOT -VCL V

fout Oscill ation Frequenc y 200 k Hz

GND

4 LVG

OUT

HVG

BOOT8

D94IN059

3/13

L6569 L6569A

PIN FUNCT ION

ELECTRICAL CHARACTERISTCS

= 12V; V

BOOT

- V

OUT

= 12V; T

= 25°C; unless otherwise specified.)

N° Pin Description

1 VS Supply input voltage with internal clamp [typ. 15.6V]

2 RF Oscillator timing resistor pin.

A buffer set alternatively to VS and GND can provide current to the external resistor RF

connected between pin 2 and 3.

Alternatively, the signal on pin 2 can be used also to drive another IC (i.e. another L6569 to drive

a full H-bridge)

3 CF Oscillator timing capacitor pin.

A capacitor connected between this pin and GND fixes (together with RF) the oscillat ing

frequency

Alternatively an external logic signal can be applied to the pin to drive the IC.

4 GND Ground

5 LVG Low side driver output.

The output stage can deliver 170mA source and 270mA sink [typ.values].

6 OUT Upper driver floating reference

7 HVG High side driver output.

The output stage can deliver 170mA source and 270mA sink [typ.values].

8 BOOT Bootstrap voltage supply.

It is the upper driver floating supply . The bootstrap capacitor connected between this pin and pin

6 can be fed by an internal structure named “bootstrap driver” (a patented structure). This

structure can replace the external bootstrap diode.

Symbol Pin Parameter Test Condition Min. Typ. Max. Unit

VSUVP 1 VS Turn On Threshold 8.3 9 9.7 V

VSUVN VS Turn Off Threshold 7.3 8 8.7 V

VSUVH VS Hysteresis 0.7 1 1.3 V

VCL VS Clamping Voltage IS = 5mA 14.6 15. 6 16.6 V

ISU Start Up Current VS < VSUVN 150 250 µA

IqQuiescent Current VS > VSUVP 500 700 µA

IBOOTLK 8 Leakage Current BOOT pin vs

GND VBOOT = 580V 5 µA

IOUTLK 6 Leakage Current OUT pin vs

GND VOUT = 562V 5 µA

IHVG SO 7 High Side Driver Source Current VHVG = 6V 110 175 mA

IHVG SI High Side Driver Sink Current VHVG = 6V 190 275 mA

ILV G SO 5 Low Side Driver Source Current VLVG = 6V 110 175 mA

ILVG SI Low Side Driver Sink Current VLVG = 6V 190 275 mA

L6569 L6569A

4/13

OSCILLATOR FREQUENCY

The frequency of the internal oscillator can be programmed using external resistor and capacitor.

The nominal oscillator frequency can be calculated using the following equation:

Where R

and C

are the external resistor and capacitor.

The device c an be dr iven i n "shut down" condi tion keeping the C

pin close to GND, but some car es hav e to be

taken:

1. When C

is to GND the high side driver is off and the low side is on

2. The forced discharge of the os cill ator capacitor C

must not be shor ter than 1us: a s imple w ay to do this i s to

limit the current discharge with a resistive path imposing R · C

s (see fig.1)

Figure 1.

VRFON 2 RF High Level Output Voltage IRF = 1mA

-0.05

VS -0.2 V

VRF OFF RF Low Level Output Voltage IRF = -1mA 50 200 mV

VCFU 3 CF Upper Threshold 7.7 8 8.2 V

VCFL CF Lower Threshold 3.80 4 4.3 V

tdInternal Dead Time 0.85 1. 25 1.65 µs

DC Duty Cycle, Ratio Between Dead

Time + Conduction Time of High

Side and Low Side Drivers

0.45 0.5 0.55

RON On resistance of Boostrap

LDMOS 120 Ω

VBC Boostrap Voltage before UVLO VS = 8.2 2.5 3.6 V

IAVE 1 Average Current from Vs No Load, fs = 60KHz 1.2 1.5 mA

fout 6 Oscillation Frequency RT = 12K; CT = 1nF 57 60 63 kHz

Symbol Pin Parameter Test Condition Min. Typ. Max. Unit

fOSC 1

FIn2

⋅⋅⋅

----------------------------------------- 1

1.3863 RFCF

⋅⋅

------------------------------------------==

GNDM

fault si

nal R

ELECTRICAL CHARACTERISTCS

(continued)

5/13

L6569 L6569A

Bootstrap Function

The L65 69 has an i nternal Bootstr ap structure that enables the user to avoid the external di ode needed, in sim-

ilar device s, to perform the char ge of the bootstrap c apacitor that, in tur ns , provide an appropr iate driv ing to the

Upper External Mosfet.

The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS dr iven

by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side

Gate driver (LVG pin), actually working as a synchronous rectifier .

The char ging path for the Bootstr ap capacitor is closed via the Lower External Mosfet that i s driven ON (i.e. LV G

High) for a time interval: T

= R

· C

· In2

→

1.1 · R

· C

starting from the time the Supply Voltage V

has reached the Turn On Voltage (V

SUVP

= 9 V typical value).

After time T

(see waveform Diagram) the LDMOS that charges the Bootstrap Capacitor, is on with a R

=120

Ω

(typical value).

In the L6569A a different star t up procedure is follow ed (see wa veform Diagram). The Lower External Mosfet i s

drive OFF until V

has reached the Turn On Threshold (V

SUVPp

), then again the T

time interval starts as above.

Being the LDMOS used to implement the bootstrap operation a "bi-directional" switch the current flowing into

the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZER O VOLTAGE SWITC HING opera-

tions is not en sured, and then an high v oltage is applied to the BOOT pin. Thi s condition can occur, for exa mple,

when the load is removed and an high resistive value is placed in series with the gate of the external Power

Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided

(fig. 7).

Let's consider the steps that should be taken.

1) Calculate the Turn on delay ( td ) of your Lower Power MOS:

2) Calculate the Fall time ( tf ) of your Lower Power MOS:

where:

= External gate resistor

= 50

Ω

, typical equivalent output resistance of the driving buffer (when sourcing current)

, C

iss

and Q

are Power MOS parameters

= Low Voltage Supply.

3) Sketch the VBOOT wavefor m (using log-log scales ) starti ng from the Drain Voltage of the Lower Power MOS

(remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example

is given where:

= Low Voltage Supply

= High Voltage Supply Rail

The V

BOOT

voltage sw ing must fal l below the cur ve id entified by the actual operating fr equen cy of your appl ica-

tion.

tdRgRid

+()

iss 1

1VTH

-----------–

--------------------

⋅⋅=

VSVTH

–

------------------------ Qgd

⋅=

L6569 L6569A

6/13

DEMO BOARD

To allow an easy evaluation of the device, a P.C. board dedicated to lamp ballast application has been de-

signed.

Fig. 11 shows the electric al schematic of a typical bal last appl ication, w hile th e PC and component l ayout is giv-

en in Fig12. This application has been designed to work with both the 110+/-20%V and the 220 +/- 20%V mains

by means of a v oltage doubler c onfiguration at the bul k capac itor. The ballas t inductance and the oper ating fre-

quen cy are especially designed for a 18 W Sylvania De-luxe T/E type bulb. The PTC for preheat at the start up

and the two back to back synchronization diodes, makes this application easy to implement and safe in opera-

tion.

part value

R1 15ohm 1W

R2, R3 22 ohm

R4 27K

R5 100K 1/2W

R6 47ohm

R7, R9 180K

R8 120K 1/2W

D1 18V zener

D2, D3 BYW100-100

D4,D5,D6,D7 1N4007

D8 1N4148

C1 560pF 50V

C2, C5 47µF 250V

C3 4.7µF 25V

C4 100nF 50V

C6 100nF 250V

C7-C8 8.2nF 630V

C9 470pF 630V

RV1 PTC 150ohm

Q1, Q2 STD2NB50-1

L1 2.4mH

7/13

L6569 L6569A

Figure 2. Waveform s (L656 9)

Figure 3. Waveform s (L656 9A)

4.6V(typ)

τ=Ron*CBOOT

T1 TC

VBOOT-VOUT

VCF

LVG

D95IN250B

VSUVP

4.6V(typ)

τ=Ron*CBOOT

T1 TC

VBOOT-VOUT

VCF

LVG

D95IN251B

VSUVP

L6569 L6569A

8/13

Figure 4. Typical Dead Time vs. Temp eratur e

Dependency

Figure 5. Typic al Frequ ency vs Te m pera ture

Dependency

Figure 6. Typical and Theoretical Oscillator

Frequency vs Resistor Value

Figure 7. Vboot pi n SO A for di f fe ren t Op e ra ti ng

Fre qu e ncy @ Tj = 125°C

Figure 8. Vboot pi n S OA @ Tj = 125°C

Figure 9. Typical Rise and Fall Times vs. Load

Capacitance

-50 0 50 100 150

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

Temperature [C]

Dead time [µsec]

D96IN378A

-50 -25 0 25 50 75 100 125

Temperature

[

]

Frequency [KHz]

D96IN379A

56789101520304050

100

150

Resistor Value (Kohm)

f (KHz)

Theoretical

C=1nF C=560pF C=330pF

D96IN380

20 50 100 200 500 1,000 2,000 5,000 10,000

100

200

300

500

Time

(

)

, from LVG Transition Hi

VBOOT

(V)

20KHz

50KHz

150KHz

110KHz

70KHz

D96IN381

20 50 100 200 500 1,000 2,000 5,000 10,000

100

200

300

500

Time

(

)

, from LVG Transition Hi

VBOOT

(V)

ACTUAL OPERTATING

FREQUENCY

D96IN416

VBOOT

For both hi

h and low side buffers @25˚C Tamb

0123456

100

150

200

250

300

C [nF]

time [nsec]

D96IN417

9/13

L6569 L6569A

Figure 10. Quiescent Current vs. Supply V oltage.

Figure 11. CFL Demoboard 110/220V Inputs.

02468101214V

(V)

Iq (µA)

D96IN418

L1=2.4mH

L1=2.4mH core TH LCC E2006-B4 Ref also VOGH 575 0409200 2.4mH

C7-C8=PS8n2J H3 630-2A TH

D7 D4

D5D6

R1 15 1W

47µF

250V

120K

1/2W

R5 100K

47µF

250V

4.7µF

25V

1N4148

ZPD 18V

27K

1/4W

560pF

50V

220V

110V R6 47 1/4W

R2 22 1/4W 1/4W

R3 22 1/4W

C4100nF 50V

D3 BYW100-100

C9 470pF 630V

STD2NB50-1

180K

1/4W C6

100nF

250V

8.2nF

630V

8.2nF

630V

CFL LAMP

SYLVANIA DELUX T/E 18W

180K

1/4W

L6569

D96IN419B

GND

LVG

OUT

HVG

BOOT

4 x 1N4006

1/2W

BYW100-100

R10 10K

RV1

PTC 150

350V

L6569 L6569A

10/13

Figure 12. PC Board and Components Layout.

Component Side

Copper Side

11/13

L6569 L6569A

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 1.75 0.069

a1 0.1 0.25 0.004 0.010

a2 1.65 0.065

a3 0.65 0.85 0.026 0.033

b 0.35 0.48 0.014 0.019

b1 0.19 0.25 0.007 0.010

C 0.25 0.5 0.010 0.020

c1 45° (typ.)

D (1) 4.8 5.0 0.189 0.197

E 5.8 6.2 0.228 0.244

e 1.27 0.050

e3 3.81 0.150

F (1) 3.8 4.0 0.15 0.157

L 0.4 1.27 0.016 0.050

M 0.6 0.024

S8° (max.)

(1) D and F do not include mold flash or protrusions. Mold flash or

potrusions shall not exceed 0.15mm (.006inch).

SO8

OUTLINE AND

MECHANICAL DATA

L6569 L6569A

12/13

Minidip

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150

Z 1.52 0.060

OUTLINE AND

MECHANICAL DATA

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L6569 L6569A