VNQ810 Quad channel high side driver Features Type RDS(on) IOUT VCC VNQ810 160m(1) 3.5A(1) 36V 1. Per each channel. CMOS compatible inputs Open Drain status outputs On state open load detection Off state open load detection Shorted load protection Undervoltage and overvoltage shutdown Loss of ground protection Very low standby current Reverse battery protection(a) SO-28 (double island) Description The VNQ810 is a quad HSD formed by assembling two VND810 chips in the same SO-28 package. The VND810 is a monolithic device made using| STMicroelectronics VIPower M0-3 Technology. The VNQ830 is intended for driving any type of multiple load with one side connected to ground. The Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects the open load condition in both the on and off state. a. See Application schematic on page 18 Table 1. In the off state the device detects if the output is shorted to VCC. The device automatically turns off in the case where the ground pin becomes disconnected. Device summary Order codes Package SO-28 (double island) December 2008 Tube Tape and reel VNQ810 VNQ81013TR Rev 3 1/28 www.st.com 28 Contents VNQ810 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 4 6 2/28 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 18 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 19 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 21 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 VNQ810 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching (VCC = 13V; Tj = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/28 List of figures VNQ810 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. 4/28 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Openload On state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Openload Off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Openload detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Rthj-amb Vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23 Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal fitting model of a quad channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-28 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VNQ810 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC1,2 Vcc OVERVOLTAGE CLAMP UNDERVOLTAGE GND1,2 CLAMP 1 OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 LOGIC DRIVER 2 OUTPUT2 OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 OPENLOAD ON 2 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 VCC3,4 Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE GND3,4 CLAMP 3 OUTPUT3 INPUT3 DRIVER 3 CLAMP 4 STATUS3 CURRENT LIMITER 3 LOGIC DRIVER 4 OUTPUT4 OVERTEMP. 3 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 OPENLOAD ON 4 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 5/28 Block diagram and pin description Figure 2. VNQ810 Configuration diagram (top view) VCC1,2 1 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 INPUT4 OUTPUT4 14 15 VCC3,4 Suggested connections for unused and not connected pins Connection / pin Status N.C. Output Input Floating X X X X To ground 6/28 VCC1,2 GND 1,2 VCC3,4 Table 2. 28 X Through 10K resistor VNQ810 Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3. Absolute maximum ratings Symbol VCC Parameter DC supply voltage Value Unit 41 V - VCC Reverse DC supply voltage - 0.3 V - IGND DC reverse ground pin current - 200 mA Internally limited A -6 A DC input current +/- 10 mA ISTAT DC Status current +/- 10 mA VESD Electrostatic discharge (human body model: R=1.5K; C = 100pF) - INPUT - STATUS - OUTPUT - VCC 4000 4000 5000 5000 V V V V EMAX Maximum switching energy (L = 2.5mH; RL = 0; Vbat = 13.5V; Tjstart = 150C; IL = 9A) 23 mJ 6.25 W Internally limited C - 55 to 150 C IOUT - IOUT IIN Ptot Tj Tstg DC output current Reverse DC output current Power dissipation (per island) at Tlead = 25C Junction operating temperature Storage temperature 7/28 Electrical specifications 2.2 VNQ810 Thermal data Table 4. Thermal data (per island) Symbol Parameter Value Unit 20 C/W Rthj-lead Thermal resistance junction-lead Rthj-amb Thermal resistance junction-ambient (one chip ON) 60(1) 44(2) C/W Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 31(2) C/W 1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2.3 Electrical characteristics Values specified in this section are for 8V < VCC < 36V; -40C < Tj < 150C, unless otherwise stated. Figure 3. Current and voltage conventions IS3,4 IS1,2 VCC3,4 VCC3,4 VCC1,2 VF1 (*) VCC1,2 IIN1 ISTAT1 VIN1 IIN2 VSTAT1 ISTAT2 VIN2 IIN3 VSTAT2 ISTAT3 VIN3 VSTAT3 IIN4 VIN4 ISTAT4 VSTAT4 INPUT1 STATUS1 IOUT1 OUTPUT1 STATUS2 OUTPUT2 INPUT4 OUTPUT3 IOUT4 OUTPUT4 STATUS4 GND3,4 8/28 VOUT4 GND1,2 IGND3,4 Note: VOUT2 IOUT3 INPUT3 STATUS3 VOUT1 IOUT2 INPUT2 VFn = VCCn - VOUTn during reverse battery condition. IGND1,2 VOUT3 VNQ810 Electrical specifications Table 5. Symbol Parameter VCC Operating supply voltage VUSD Test conditions Min. Typ. Max. Unit 5.5 13 36 V Undervoltage shutdown 3 4 5.5 V VOV Overvoltage shutdown 36 RON On state resistance IS Supply current V IOUT = 1A; Tj = 25C IOUT = 1A; VCC > 8V 160 320 m m Off State; VCC = 13V; VIN = VOUT = 0V 12 40 A Off State; VCC = 13V; VIN = VOUT = 0V; Tj = 25C 12 25 A On State; VCC = 13V; VIN = 5V; IOUT = 0A 5 7 mA 0 50 A -75 0 A IL(off1) Off state output current VIN = VOUT = 0V IL(off2) Off state output current VIN = 0V; VOUT = 3.5V IL(off3) Off state output current VIN = VOUT = 0V; VCC = 13V; Tj = 125C 5 A IL(off4) Off state output current VIN = VOUT = 0V; VCC = 13V; Tj =25C 3 A Table 6. Symbol Protections Min. Typ. Max. Unit Shutdown temperature 150 175 200 C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload conditions Ilim Current limitation TTSD Vdemag Note: Power output Parameter Turn-off output clamp voltage Test conditions C 15 Tj > TTSD VCC = 13V 5.5V < VCC < 36V IOUT = 1A; L = 6mH 3.5 5 C 20 s 7.5 7.5 A A VCC - VCC - VCC 41 48 55 V To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 9/28 Electrical specifications Table 7. VCC - output diode Symbol Parameter Test conditions VF Forward on voltage - IOUT = 0.5A; Tj = 150C Table 8. Symbol Min. Typ. Max. Unit 0.6 V Switching (VCC = 13V; Tj = 25C) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 13 from VIN rising edge to VOUT = 1.3V (see Figure 5) 30 s td(off) Turn-off delay time RL = 13 from VIN falling edge to VOUT = 11.7V (see Figure 5) 30 s dVOUT/dt(on) Turn-on voltage slope RL = 13 from VOUT = 1.3V to VOUT = 10.4V (see Figure 5) See Figure 10 V/s dVOUT/dt(off) Turn-off voltage slope RL = 13 from VOUT = 11.7V to VOUT = 1.3V (see Figure 5) See Figure 12 V/s Table 9. Symbol Logic inputs Parameter VIL Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Table 10. Symbol 10/28 VNQ810 Input clamp voltage Test conditions Min. VIN = 1.25V Typ. Max. Unit 1.25 V 1 A 3.25 V VIN = 3.25V 10 0.5 IIN = 1mA IIN = -1mA A V 6 6.8 - 0.7 8 V V Status pin Parameter Test conditions Min. Typ. Max. Unit VSTAT Status low output voltage ISTAT = 1.6mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5V 10 A CSTAT Status pin Input capacitance Normal operation; VSTAT = 5V 100 pF VSCL Status clamp voltage 8 V V ISTAT = 1mA ISTAT = - 1mA 6 6.8 - 0.7 VNQ810 Electrical specifications Table 11. Openload detection Symbol IOL tDOL(on) Parameter Test conditions Min. Openload On state detection threshold VIN = 5V 20 Openload On state detection delay IOUT = 0A VOL Openload Off state voltage detection threshold tDOL(off) Openload detection delay at turn-off Figure 4. VIN = 0V 1.5 Typ. Max. 40 2.5 80 mA 200 s 3.5 V 1000 s Status timings OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL OVER TEMP STATUS TIMING Tj > TTSD VINn VINn VSTATn VSTATn tSDL tDOL(off) Figure 5. Unit tSDL tDOL(on) Switching characteristics VOUT 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t ISENSE 90% INPUT t tDSENSE td(on) td(off) t 11/28 Electrical specifications Table 12. 12/28 VNQ810 Truth table Conditions Input Output Status Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L VNQ810 Electrical specifications Table 13. Electrical transient requirements ISO T/R Test level 7637/1 Test pulse I II III IV Delays and impedance 1 - 25V - 50V - 75V - 100V 2ms, 10 2 + 25V + 50V + 75V + 100V 0.2ms, 10 3a - 25V - 50V - 100V - 150V 0.1s, 50 3b + 25V + 50V + 75V + 100V 0.1s, 50 4 - 4V - 5V - 6V - 7V 100ms, 0.01 5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2 ISO T/R 7637/1 Test level I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Test pulse Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 13/28 Electrical specifications Figure 6. VNQ810 Waveforms NORMAL OPERATION INPUTn LOAD VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VCC VUSD INPUTn LOAD VOLTAGEn STATUS undefined OVERVOLTAGE VCC<VOV VCC > VOV VCC INPUTn LOAD VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn VOUT > VOL LOAD VOLTAGEn VOL STATUSn OPEN LOAD without external pull-up INPUTn LOAD VOLTAGEn STATUSn Tj INPUTn LOAD CURRENTn STATUSn 14/28 TTSD TR OVERTEMPERATURE VNQ810 Electrical specifications 2.4 Electrical characteristics curves Figure 7. Off state output current Figure 8. IL(off1) (uA) High level input current Iih (uA) 1.6 5 1.44 4.5 Off state Vcc=36V Vin=Vout=0V 1.28 1.12 Vin=3.25V 4 3.5 0.96 3 0.8 2.5 0.64 2 0.48 1.5 0.32 1 0.16 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C ) Figure 9. 50 75 100 125 150 175 150 175 150 175 Tc (C ) Input clamp voltage Figure 10. Turn-on voltage slope dVout/dt(on) (V/ms) Vicl (V) 1000 8 900 7.8 Iin=1mA 7.6 Vcc=13V Rl=13Ohm 800 7.4 700 7.2 600 7 500 6.8 400 6.6 300 6.4 200 6.2 100 0 6 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 Tc (C ) Tc (C ) Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope Vov (V) dVout/dt(off) (V/ms) 50 600 48 550 Ri=6.5Ohm 46 500 44 450 42 40 400 38 350 36 300 34 250 32 30 200 -50 -25 0 25 50 75 Tc (C ) 100 125 150 175 -50 -25 0 25 50 75 100 125 Tc (C ) 15/28 Electrical specifications VNQ810 Figure 13. ILIM vs Tcase Figure 14. On state resistance vs VCC Ilim (A) Ron (mOhm) 20 120 Tc=150C 110 18 Vcc=13V 16 100 90 14 80 12 70 10 60 8 50 Tc=25C 40 6 Tc=- 40C 30 4 20 2 10 0 0 -50 -25 0 25 50 75 100 125 150 Iout=5A 5 175 10 15 20 25 30 35 40 Vcc (V) Tc (C ) Figure 15. Input high level Figure 16. Input hysteresis voltage Vih (V) Vhyst (V) 3.6 1.5 1.4 3.4 1.3 3.2 1.2 3 1.1 2.8 1 0.9 2.6 0.8 2.4 0.7 2.2 0.6 2 0.5 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C ) 75 100 125 150 175 Tc (C ) Figure 17. On state resistance vs Tcase Figure 18. Input low level Ron (mOhm) Vil (V) 400 2.6 350 2.4 Iout=0.5A Vcc=8V; 13V & 36V 300 2.2 250 2 200 1.8 150 1.6 100 1.4 50 1.2 1 0 -50 -25 0 25 50 75 Tc (C ) 16/28 50 100 125 150 175 -50 -25 0 25 50 75 Tc (C ) 100 125 150 175 VNQ810 Electrical specifications Figure 19. Status leakage current Figure 20. Status low output voltage Ilstat (uA) Vstat (V) 0.05 0.8 0.7 Istat=1.6mA 0.04 0.6 Vstat=5V 0.5 0.03 0.4 0.02 0.3 0.2 0.01 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C ) 50 75 100 125 150 175 Tc (C ) Figure 21. Status clamp voltage Figure 22. Openload On state detection threshold Vscl (V) Iol (mA) 8 150 7.8 140 Istat=1mA 7.6 Vcc=13V Vin=5V 130 7.4 120 7.2 110 7 100 6.8 90 6.6 80 6.4 70 6.2 60 6 50 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) -50 -25 0 25 50 75 100 125 150 175 Tc (C ) Figure 23. Openload Off state voltage detection threshold Vol (V) 5 4.5 Vin=0V 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C ) 17/28 Application information 3 VNQ810 Application information Figure 24. Application schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 OUTPUT1 CU OUTPUT2 OUTPUT3 Rprot INPUT3 Rprot STATUS4 OUTPUT4 Rprot INPUT4 GND1,2 GND3,4 RGND +5V +5V VGND DGND Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: a resistor in the ground line (RGND only) This can be used with any type of load. The following show how to dimension the RGND resistor: 18/28 1. RGND 600mV / 2 (IS(on)max) 2. RGND ( - VCC) / ( - IGND) VNQ810 Application information where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = ( - VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND . If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/O pins from latching up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os: - VCCpeak / Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax 19/28 Application information VNQ810 Example For the following conditions: VCCpeak = - 100V Ilatchup 20mA VOHC 4.5V 5k Rprot 65k. Recommended values are: Rprot = 10k 3.4 Open load detection in off state Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL + RPU))RL < VOlmin. 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. Figure 25. Openload detection in Off state V batt. VPU V CC R PU INP UT DRIVER + LOGIC IL(off2) OUT + S TATUS R V OL G ROUND 20/28 RL VNQ810 3.5 Application information Maximum demagnetization energy (VCC = 13.5V) Figure 26. Maximum turn-off current versus load inductance ILMAX (A) 10 A B C 1 0.01 0.1 1 L(mH) 10 100 A = single pulse at TJstart = 150C B= repetitive pulse at TJstart = 100C C= repetitive pulse at TJstart = 125C VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL = 0. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 21/28 Package and PCB thermal data VNQ810 4 Package and PCB thermal data 4.1 SO-28 thermal data Figure 27. SO-28 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB thickness = 2mm, Cu thickness = 35m, Copper areas: 0.5 cm2, 3 cm2, 6 cm2). Table 14. Thermal calculation according to the PCB heatsink area Chip 1 Chip 2 Tjchip1 Tjchip2 Note ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb ON ON RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2 ON ON (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1 Pdchip2 RthA = thermal resistance junction to ambient with one chip ON RthB = thermal resistance junction to ambient with both chips ON and Pdchip1 = Pdchip2 RthC = mutual thermal resistance 22/28 VNQ810 Package and PCB thermal data Figure 28. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (C/W) 70 60 50 RthA 40 RthB 30 RthC 20 10 0 1 2 3 4 5 PCB Cu heats ink area (cm^2)/is land 6 7 Figure 29. Thermal impedance junction ambient single pulse 100 Zth(C/W) 0,5 cm ^2/is land 3 cm ^2/is land 6 cm ^2/is land 10 1 One channel ON Two channels ON on same chip 0.1 0.01 0.0001 0.001 0.01 0.1 1 time(s) 10 100 1000 23/28 Package and PCB thermal data VNQ810 Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Figure 30. Thermal fitting model of a quad channel HSD in SO-28 Tj_1 P d1 T j _2 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 C 10 C 11 C 12 C 13 R 13 P d2 C 14 R 14 R 17 Tj_3 R 18 C7 C8 C9 R7 R8 R9 P d3 T j _4 P d4 C 15 R 15 R 10 R 11 R 12 C 16 R 16 T_amb Table 15. 24/28 Thermal parameters Area / island (cm2) Footprint R1 = R7 = R13 = R15 (C/W) 0.35 R2 = R8 = R14 = R16 (C/W) 1.8 R3 = R9 (C/W) 4.5 R4 = R10 (C/W) 11 R5 = R11 (C/W) 15 R6 = R12 (C/W) 30 C1 = C7 = C13 = C15 (W.s/C) 0.0001 C2 = C8 = C14 = C16 (W.s/C) 7E-04 C3 = C9 (W.s/C) 6E-03 C4 = C10 (W.s/C) 0.2 C5 = C11 (W.s/C) 1.5 C6 = C12 (W.s/C) 5 R17 = R18 (C/W) 150 6 13 8 VNQ810 Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 31. SO-28 package dimensions Table 16. SO-28 mechanical data Millimeters Symbol Min. Typ. A Max. 2.65 a1 0.10 0.30 b 0.35 0.49 b1 0.23 0.32 C 0.50 c1 45 (typ.) D 17.7 18.1 E 10.00 10.65 e 1.27 e3 16.51 F 7.40 7.60 L 0.40 1.27 S 8 (max.) 25/28 Package and packing information 5.2 VNQ810 SO-28 packing information Figure 32. SO-28 tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C B 28 700 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 33. SO-28 tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 12 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components 500mm min Empty components pockets saled with cover tape. User direction of feed 26/28 No components 500mm min VNQ810 6 Revision history Revision history Table 17. Document revision history Date Revision Changes 09-Sep-2004 1 Initial release. 03-May-2006 2 Minor changes Current and voltage convention update (page 3). Configuration diagram (top view) & suggested connections for unused and n.c. pins insertion (page 3). 6 cm2 Cu condition insertion in thermal data table (page 4). VCC - output diode section update (page 4). Protections note insertion (page 5) Revision history table insertion (page 20). Disclaimers update (page 21). 01-Dec-2008 3 Document reformatted and restructured. Added contents, list of tables and figures. Added ECOPACK(R) packages information. 27/28 VNQ810 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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