December 2008 Rev 3 1/28
28
VNQ810
Quad channel high side driver
Features
■CMOS compatible inputs
■Open Drain status outputs
■On state open load detection
■Off state open load detection
■Shorted load protection
■Undervoltage and overvoltage shutdown
■Loss of ground protection
■Very low standby current
■Reverse battery protection(a)
Description
The VNQ810 is a quad HSD formed by
assembling two VND810 chips in the same SO-28
package. The VND810 is a monolithic device
made using| STMicroelectronics VIPower M0-3
Technology. The VNQ830 is intended for driving
any type of multiple load with one side connected
to ground.
The Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table). Active current
limitation combined with thermal shutdown and
automatic restart protects the device against
overload. The device detects the open load
condition in both the on and off state.
In the off state the device detects if the output is
shorted to VCC. The device automatically turns off
in the case where the ground pin becomes
disconnected.
Type RDS(on) IOUT VCC
VNQ810 160mΩ
(1)
1. Per each channel.
3.5A(1) 36V
a. See Application schematic on page 18
SO-28 (double island)
Table 1. Device summary
Package
Order codes
Tube Tape and reel
SO-28 (double island) VNQ810 VNQ81013TR
www.st.com
Contents VNQ810
2/28
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 18
3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 18
3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 19
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 21
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VNQ810 List of tables
3/28
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 11. Openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 14. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of figures VNQ810
4/28
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. On state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. On state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 21. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 22. Openload On state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 23. Openload Off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. Openload detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Maximum turn-off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. Rthj-amb Vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. Thermal fitting model of a quad channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 31. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 32. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 33. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VNQ810 Block diagram and pin description
5/28
1 Block diagram and pin description
Figure 1. Block diagram
OVERTEMP. 1
VCC1,2
GND1,2
INPUT1 OUTPUT1
OVERVOLTAGE
LOGIC
DRIVER 1
STATUS1
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 1
OPENLOAD ON 1
CURRENT LIMITER 1
OPENLOAD OFF 1
OUTPUT2
DRIVER 2
CLAMP 2
OPENLOAD ON 2
OPENLOAD OFF 2
OVERTEMP. 2
INPUT2
STATUS2
CURRENT LIMITER 2
OVERTEMP. 3
VCC3,4
GND3,4
INPUT3 OUTPUT3
OVERVOLTAGE
LOGIC
DRIVER 3
STATUS3
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 3
OPENLOAD ON 3
CURRENT LIMITER 3
OPENLOAD OFF 3
OUTPUT4
DRIVER 4
CLAMP 4
OPENLOAD ON 4
OPENLOAD OFF 4
OVERTEMP. 4
INPUT4
STATUS4
CURRENT LIMITER 4
Block diagram and pin description VNQ810
6/28
Figure 2. Configuration diagram (top view)
Table 2. Suggested connections for unused and not connected pins
Connection / pin Status N.C. Output Input
Floating X X X X
To ground X Through 10KΩ
resistor
VCC1,2
GND 1,2
INPUT1
STATUS1
STATUS2
VCC1,2
VCC3,4
GND 3,4
INPUT3
STATUS3
VCC3,4 VCC3,4
OUTPUT4
OUTPUT4
OUTPUT4
OUTPUT3
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
VCC1,2
OUTPUT3
OUTPUT3
OUTPUT1
OUTPUT1
INPUT2
STATUS4
INPUT4
1
14 15
28
VNQ810 Electrical specifications
7/28
2 Electrical specifications
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage 41 V
- VCC Reverse DC supply voltage - 0.3 V
- IGND DC reverse ground pin current - 200 mA
IOUT DC output current Internally limited A
- IOUT Reverse DC output current - 6 A
IIN DC input current +/- 10 mA
ISTAT DC Status current +/- 10 mA
VESD
Electrostatic discharge (human body model: R=1.5KΩ;
C = 100pF)
- INPUT
- STATUS
- OUTPUT
- VCC
4000
4000
5000
5000
V
V
V
V
EMAX
Maximum switching energy
(L = 2.5mH; RL = 0Ω; Vbat = 13.5V; Tjstart = 150ºC; IL = 9A) 23 mJ
Ptot Power dissipation (per island) at Tlead = 25°C 6.25 W
TjJunction operating temperature Internally limited °C
Tstg Storage temperature - 55 to 150 °C
Electrical specifications VNQ810
8/28
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless
otherwise stated.
Figure 3. Current and voltage conventions
Note: VFn = VCCn - VOUTn during reverse battery condition.
Table 4. Thermal data (per island)
Symbol Parameter Value Unit
Rthj-lead Thermal resistance junction-lead 20 °C/W
Rthj-amb
Thermal resistance junction-ambient
(one chip ON) 60(1)
1. When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35 µm thick) connected
to all VCC pins. Horizontal mounting and no artificial air flow.
44(2)
2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
°C/W
Rthj-amb
Thermal resistance junction-ambient
(two chips ON) 46(1) 31(2) °C/W
I
S1,2
I
GND1,2
OUTPUT3
V
CC1,2
GND
1,2
INPUT2
I
OUT3
V
CC1,2
V
OUT4
OUTPUT2
I
OUT2
V
OUT3
INPUT1
I
IN1
STATUS1
I
STAT1
OUTPUT1
I
OUT1
OUTPUT4
I
OUT4
V
OUT2
V
OUT1
I
IN2
I
STAT2
I
STAT3
I
IN4
I
STAT4
STATUS2
STATUS3
STATUS4
INPUT3
INPUT4
V
STAT4
V
IN4
V
STAT3
V
IN3
V
STAT2
I
IN3
V
IN2
V
STAT1
V
IN1
I
GND3,4
GND
3,4
I
S3,4
V
CC3,4
V
CC3,4
V
F1
(*)
VNQ810 Electrical specifications
9/28
Note: To ensure long term reliability under heavy overload or short circuit conditions, protection
and related diagnostic signals must be used together with a proper software strategy. If the
device is subjected to abnormal conditions, this software must limit the duration and number
of activation cycles.
Table 5. Power output
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCC
Operating supply
voltage 5.5 13 36 V
VUSD Undervoltage shutdown 3 4 5.5 V
VOV Overvoltage shutdown 36 V
RON On state resistance IOUT = 1A; Tj = 25°C
IOUT = 1A; VCC > 8V
160
320
mΩ
mΩ
IS Supply current
Off State; VCC = 13V;
VIN = VOUT = 0V
Off State; VCC = 13V;
VIN = VOUT = 0V;
Tj = 25°C
On State; VCC = 13V; VIN = 5V;
IOUT = 0A
12
12
5
40
25
7
µA
µA
mA
IL(off1) Off state output current VIN = VOUT = 0V 0 50 µA
IL(off2) Off state output current VIN = 0V; VOUT = 3.5V -75 0 µA
IL(off3) Off state output current VIN = VOUT = 0V; VCC = 13V;
Tj = 125°C 5µA
IL(off4) Off state output current VIN = VOUT = 0V; VCC = 13V;
Tj =25°C 3µA
Table 6. Protections
Symbol Parameter Test conditions Min. Typ. Max. Unit
TTSD Shutdown temperature 150 175 200 °C
TRReset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
tSDL
Status delay in overload
conditions Tj > TTSD 20 µs
Ilim Current limitation VCC = 13V
5.5V < VCC < 36V
3.5 5 7.5
7.5
A
A
Vdemag
Turn-off output clamp
voltage IOUT = 1A; L = 6mH VCC -
41
VCC -
48
VCC -
55 V
Electrical specifications VNQ810
10/28
Table 7. VCC - output diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VFForward on voltage - IOUT = 0.5A; Tj = 150°C 0.6 V
Table 8. Switching (VCC = 13V; Tj = 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time RL = 13Ω from VIN rising edge
to VOUT = 1.3V (see Figure 5)30 µs
td(off) Turn-off delay time
RL = 13Ω from VIN falling edge
to VOUT = 11.7V
(see Figure 5)
30 µs
dVOUT/dt(on) Turn-on voltage slope RL = 13Ω from VOUT = 1.3V to
VOUT = 10.4V (see Figure 5)
See
Figure 10 V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 13Ω from VOUT = 11.7V
to VOUT = 1.3V (see Figure 5)
See
Figure 12 V/µs
Table 9. Logic inputs
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input low level 1.25 V
IIL Low level input current VIN = 1.25V 1 µA
VIH Input high level 3.25 V
IIH High level input current VIN = 3.25V 10 µA
VI(hyst) Input hysteresis voltage 0.5 V
VICL Input clamp voltage IIN = 1mA
IIN = -1mA
66.8
- 0.7
8V
V
Table 10. Status pin
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSTAT Status low output voltage ISTAT = 1.6mA 0.5 V
ILSTAT Status leakage current Normal operation; VSTAT = 5V 10 µA
CSTAT Status pin Input capacitance Normal operation; VSTAT = 5V 100 pF
VSCL Status clamp voltage ISTAT = 1mA
ISTAT = - 1mA
66.8
- 0.7
8V
V
VNQ810 Electrical specifications
11/28
Figure 4. Status timings
Figure 5. Switching characteristics
Table 11. Openload detection
Symbol Parameter Test conditions Min. Typ. Max. Unit
IOL Openload On state detection threshold VIN = 5V 20 40 80 mA
tDOL(on) Openload On state detection delay IOUT = 0A 200 µs
VOL
Openload Off state voltage detection
threshold VIN = 0V 1.5 2.5 3.5 V
tDOL(off) Openload detection delay at turn-off 1000 µs
V
INn
V
STATn
t
DOL(off)
OPEN LOAD STATUS TIMING (with external pull-up)
V
INn
V
STATn
OVER TEMP STATUS TIMING
t
SDL
t
SDL
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
T
j
> T
TSD
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10% t
f
dV
OUT
/dt
(off)
I
SENSE
t
t
90%
t
d(off)
INPUT
t
90%
t
d(on)
t
DSENSE
Electrical specifications VNQ810
12/28
Table 12. Truth table
Conditions Input Output Status
Normal operation L
H
L
H
H
H
Current limitation
L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature L
H
L
L
H
L
Undervoltage L
H
L
L
X
X
Overvoltage L
H
L
L
H
H
Output voltage > VOL
L
H
H
H
L
H
Output current < IOL
L
H
L
H
H
L
VNQ810 Electrical specifications
13/28
Table 13. Electrical transient requirements
ISO T/R
7637/1
Test pulse
Test level
I II III IV Delays and impedance
1 - 25V - 50V - 75V - 100V 2ms, 10Ω
2 + 25V + 50V + 75V + 100V 0.2ms, 10Ω
3a - 25V - 50V - 100V - 150V 0.1µs, 50Ω
3b + 25V + 50V + 75V + 100V 0.1µs, 50Ω
4 - 4V - 5V - 6V - 7V 100ms, 0.01Ω
5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2Ω
ISO T/R
7637/1
Test pulse
Test level
IIIIIIIV
1C C C C
2C C C C
3a C C C C
3b C C C C
4C C C C
5C E E E
Class Contents
CAll functions of the device are performed as designed after exposure to
disturbance.
EOne or more functions of the device is not performed as designed after exposure
and cannot be returned to proper operation without replacing the device.
Electrical specifications VNQ810
14/28
Figure 6. Waveforms
OPEN LOAD without external pull-up
STATUSn
INPUTn
NORMAL OPERATION
UNDERVOLTAGE
VCC
VUSD
VUSDhyst
INPUTn
OVERVOLTAGE
VCC
VCC > VOV
STATUS
INPUTn
STATUSn
STATUSn
INPUTn
STATUSn
INPUTn
OPEN LOAD with external pull-up
undefined
OVERTEMPERATURE
INPUTn
STATUSn
TTSD
TR
Tj
LOAD VOLTAGEn
VCC<VOV
LOAD VOLTAGEn
LOAD VOLTAGEn
LOAD VOLTAGEn
LOAD VOLTAGEn
LOAD CURRENTn
VOUT > VOL
VOL
VNQ810 Electrical specifications
15/28
2.4 Electrical characteristics curves
Figure 7. Off state output current Figure 8. High level input current
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
0.16
0.32
0.48
0.64
0.8
0.96
1.12
1.28
1.44
1.6
IL(off1) (uA )
Off state
Vcc=36V
Vin=Vout=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA )
Vin=3.25V
Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Ii n =1 m A
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
100
200
300
400
500
600
700
800
900
1000
dVout/dt(on) (V/ms)
Vcc=13V
Rl=13Ohm
Figure 11. Overvoltage shutdown Figure 12. Turn-off voltage slope
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
200
250
300
350
400
450
500
550
600
dV out/dt(off) (V /ms)
Ri=6.5Ohm
Electrical specifications VNQ810
16/28
Figure 13. ILIM vs Tcase Figure 14. On state resistance vs VCC
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
2
4
6
8
10
12
14
16
18
20
Ili m (A )
Vcc=13V
5 10152025303540
Vcc (V)
0
10
20
30
40
50
60
70
80
90
100
110
120
Ron (mOhm)
Io u t =5 A
Tc = - 40°C
Tc =25°C
Tc =150°C
Figure 15. Input high level Figure 16. Input hysteresis voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vih (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
Figure 17. On state resistance vs Tcase Figure 18. Input low level
-50 -25 0 25 50 75 100 125 150 175
Tc (°C )
0
50
100
150
200
250
300
350
400
Ron (mOhm)
Io u t =0 . 5 A
Vc c =8V; 13V & 36V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vil (V)
VNQ810 Electrical specifications
17/28
Figure 19. Status leakage current Figure 20. Status low output voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.01
0.02
0.03
0.04
0.05
Ils tat (u A )
Vs tat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V stat (V )
Is tat=1.6mA
Figure 21. Status clamp voltage Figure 22. Openload On state detection
threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl (V)
Is tat=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
50
60
70
80
90
100
110
120
130
140
150
Iol (mA )
Vcc=13V
Vin=5V
Figure 23. Openload Off state voltage
detection threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
Application information VNQ810
18/28
3 Application information
Figure 24. Application schematic
Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2.
3.1 GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against
reverse battery.
3.1.1 Solution 1: a resistor in the ground line (RGND only)
This can be used with any type of load.
The following show how to dimension the RGND resistor:
1. RGND ≤ 600mV / 2 (IS(on)max)
2. RGND ≥ ( - VCC) / ( - IGND)
V
CC1,2
OUTPUT2
+5V
R
prot
OUTPUT1
STATUS1
INPUT1
+5V
STATUS2
INPUT2
+5V
D
GND
R
GND
V
GND
GND1,2 GND3,4
OUTPUT3
OUTPUT4
Μ
CU
V
CC3,4
STATUS3
INPUT3
STATUS4
INPUT4
+5V
+5V
R
prot
R
prot
R
prot
R
prot
R
prot
R
prot
R
prot
D
ld
VNQ810 Application information
19/28
where - IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC < 0 during reverse battery situations) is:
PD = ( - VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND .
If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: a diode (DGND) in the ground line
A resistor (RGND = 1kΩ) should be inserted in parallel to DGND if the device will be driving
an inductive load. This small signal diode can be safely shared amongst several different
HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in
the input threshold and the status output values if the microprocessor ground is not common
with the device ground. This shift will not vary if more than one HSD shares the same
diode/resistor network. Series resistor in INPUT and STATUS lines are also required to
prevent that, during battery voltage transient, the current exceeds the Absolute Maximum
Rating. Safest configuration for unused INPUT and STATUS pin is to leave them
unconnected.
3.2 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than those shown in the ISO T/R 7637/1 table.
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
- VCCpeak / Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Application information VNQ810
20/28
Example
For the following conditions:
VCCpeak = - 100V
Ilatchup ≥ 20mA
VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended values are:
Rprot = 10kΩ
3.4 Open load detection in off state
Off state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1) no false open load indication when load is connected: in this case we have to avoid VOUT
to be higher than VOlmin; this results in the following condition
VOUT = (VPU / (RL + RPU))RL < VOlmin.
2) no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2).
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-
up resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
Figure 25. Openload detection in Off state
VOL
V batt. VPU
RPU
RL
R
DRIVER
+
LOGIC
+
-
IN P U T
STATUS
VCC
OUT
GROUND
IL(off2)
VNQ810 Application information
21/28
3.5 Maximum demagnetization energy (VCC = 13.5V)
Figure 26. Maximum turn-off current versus load inductance
Note: Values are generated with RL = 0Ω.
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse
must not exceed the temperature specified above for curves B and C.
VIN, IL
t
Demagnetization Demagnetization Demagnetization
A = single pulse at TJstart = 150ºC
B= repetitive pulse at TJstart = 100ºC
C= repetitive pulse at TJstart = 125ºC
1
10
0.01 0.1 1 10 100
L(mH)
I
LMAX (A)
A
B
C
Package and PCB thermal data VNQ810
22/28
4 Package and PCB thermal data
4.1 SO-28 thermal data
Figure 27. SO-28 PC board
Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB
thickness = 2mm, Cu thickness = 35µm, Copper areas: 0.5 cm2, 3 cm2, 6 cm2).
RthA = thermal resistance junction to ambient with one chip ON
RthB = thermal resistance junction to ambient with both chips ON and Pdchip1 = Pdchip2
RthC = mutual thermal resistance
Table 14. Thermal calculation according to the PCB heatsink area
Chip 1 Chip 2 Tjchip1 Tjchip2 Note
ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb
OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb
ON ON RthB x (Pdchip1 + Pdchip2) +
Tamb
RthB x (Pdchip1 + Pdchip2) +
Tamb
Pdchip1 = Pdchip2
ON ON (RthA x Pdchip1) + RthC x
Pdchip2 + Tamb
(RthA x Pdchip2) + RthC x
Pdchip1 + Tamb
Pdchip1 ≠ Pdchip2
VNQ810 Package and PCB thermal data
23/28
Figure 28. Rthj-amb Vs PCB copper area in open box free air condition
Figure 29. Thermal impedance junction ambient single pulse
10
20
30
40
50
60
70
01234567
PCB Cu heatsink area (cm^2)/is land
RTH
j
_am b
(°C /W)
RthA
RthB
RthC
0.01
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
time(s )
Zth(°C /W)
6 cm ^2/is land
3 cm ^2/is land
0,5 cm ^2/is land
One channel ON
Two channels
ON on same chip
Package and PCB thermal data VNQ810
24/28
Equation 1: pulse calculation formula
Figure 30. Thermal fitting model of a quad channel HSD in SO-28
Table 15. Thermal parameters
Area / island (cm2) Footprint 6
R1 = R7 = R13 = R15 (°C/W) 0.35
R2 = R8 = R14 = R16 (°C/W) 1.8
R3 = R9 (°C/W) 4.5
R4 = R10 (°C/W) 11
R5 = R11 (°C/W) 15
R6 = R12 (°C/W) 30 13
C1 = C7 = C13 = C15 (W.s/°C) 0.0001
C2 = C8 = C14 = C16 (W.s/°C) 7E-04
C3 = C9 (W.s/°C) 6E-03
C4 = C10 (W.s/°C) 0.2
C5 = C11 (W.s/°C) 1.5
C6 = C12 (W.s/°C) 5 8
R17 = R18 (°C/W) 150
ZTHδRTH δZTHtp 1δ–()+⋅=
where
δtpT⁄=
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2
R14
C13 C14
R13
Tj_1
Tj_2
T_amb
Pd3
C7
R10
C9 C10
R9R7 R12R11
R8
C11 C12
C8
Pd4
R16
C15 C16
R15
Tj_3
Tj_4
R17 R18
VNQ810 Package and packing information
25/28
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 31. SO-28 package dimensions
Table 16. SO-28 mechanical data
Symbol
Millimeters
Min. Typ. Max.
A2.65
a1 0.10 0.30
b 0.35 0.49
b1 0.23 0.32
C0.50
c1 45° (typ.)
D 17.7 18.1
E 10.00 10.65
e1.27
e3 16.51
F 7.40 7.60
L 0.40 1.27
S 8° (max.)
Package and packing information VNQ810
26/28
5.2 SO-28 packing information
Figure 32. SO-28 tube shipment (no suffix)
Figure 33. SO-28 tape and reel shipment (suffix “TR”)
All dimensions are in mm.
Base Q.ty 28
Bulk Q.ty 700
Tube length (± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
A
C
B
Base Q.ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
Reel dimensions
VNQ810 Revision history
27/28
6 Revision history
Table 17. Document revision history
Date Revision Changes
09-Sep-2004 1 Initial release.
03-May-2006 2
Minor changes
Current and voltage convention update (page 3).
Configuration diagram (top view) & suggested connections for unused
and n.c. pins insertion (page 3).
6 cm2 Cu condition insertion in thermal data table (page 4).
VCC - output diode section update (page 4).
Protections note insertion (page 5)
Revision history table insertion (page 20).
Disclaimers update (page 21).
01-Dec-2008 3
Document reformatted and restructured.
Added contents, list of tables and figures.
Added ECOPACK® packages information.
VNQ810
28/28
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