1
FEATURES
APPLICATIONS
SYS_IN
L1
SM1
PGND1
PGND2
SM2
L2
AGND0
SM3
FB3
L3
SM3SW
OUT
SIM
OUT
GPIO1
USB
GPIO2
LDO_PM
PWM
AC
RED
BAT
GREEN
BAT
BLUE
TMR
SCLK
ISET1
SDAT
DPPM
INT
TS
RESPWRON
RTC_OUT
TRSTPWON
HOT_RST
LDO1
LDO0
LDO3
LDO35_REF
VIN_LDO35
LDO4
ADC_REF
AGND2
ANLG1
ANLG2
LDO5
GPIO3
GROUNDPAD
AGND1
VIN_LDO02
PGND3
VIN_SM2
VIN_SM1
2
11
8
13
10
12
9
6
7
5
3
4
14
38
41
36
39
37
40
42
34
35
33
32
31
30
27
29
25 282624232219 21201817
LED_PWM
LDO2
48 47 434446 4549505154 5256 5355
1
1615
QFN56-Pin,7x7mmPackage
(TopView-NotToScale)
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
SINGLE-CELL Li-ION BATTERY- AND POWER-MANAGEMENT IC
•HOST INTERFACE•BATTERY CHARGER – Host can set system parameters andaccess system status using I
2
C interface– Complete charge management solution forsingle Li-Ion/Li-Pol cell with thermal – Interrupt function with programmablefoldback, dynamic power management and masking signals system status modifictionpack temperature sensing, supporting up to hostto 1.5-A max charge current
– 3 GPIO ports, programmable as drivers,– Programmable charge parameters for AC integrated A/D trigger or buck convertersadapter and USB port operation standby mode control•INTEGRATED POWER SUPPLIES– A total of 9 LDOs are integrated:
•PDAs– Six adjustable output LDOs (1.25-V to
•Smart Phones3.3-V)
•MP3s– Two fixed-voltage LDOs (3.3-V)
•Internet Appliances– One fixed-voltage, always-on LDO
•Handheld Devices(3.3-V)
– One RTC backup supply with lowleakage (3.1-V)– Two 600-mA output current, 0.6-V to 3.4-Vprogrammable dc/dc buck converters withenable, standby mode operation, andautomatic low-power mode setting•DISPLAY FUNCTIONS
– Two open-drain PWM outputs withprogrammable frequency and duty cycle.Can be used to control keyboard backlight,vibrator, or other external peripheralfunctions
– RGB LED driver with programmableflashing period and individual R/G/Bbrightness control– Constant-current white LED driver, withprogrammable current level, brightnesscontrol, and overvoltage protection candrive up to 6 LEDs in series configuration•SYSTEM MANAGEMENT
– Dual input power path function with inputcurrent limiting and OVP protection– POR function with programmable maskingmonitors all integrated supplies outputs– Software and hardware reset functions– 8-channel integrated A/D samples systemparameters with single conversion, peakdetection, or averaging operating modesspacer1
spacer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
The TPS65820 provides an easy to use, fully integrated solution for handheld devices, integrating chargemanagement, multiple regulated power supplies, system management and display functions, in a smallthermally-enhanced 7-mm ×7-mm package. The high level of integration enables typical board area spacesavings of 70% when compared to equivalent discrete solutions, while implementing a high-performance andflexible solution, portable across multiple platforms. If required, an external host may control the TPS65820 viaI
2
C interface, with access to all integrated systems. The I
2
C enables setting output voltages, current thresholds,and operation modes. Internal registers have a complete set of status information, enabling easy diagnostics,and host-controlled handling of fault conditions. The TPS65820 can operate in stand-alone mode, with noexternal host control, if the internal power-up defaults are compatible with the system requirements
AVAILABLE OPTIONS
(1)
T
J
DEVICES
(2) (3) (4)
MARKING
– 40 °C to 125 °C TPS65820RSH TPS65820
(1) For the most current package and ordering information, see the Package Option Addendum at the endof this document, or see the TI Web site at www.ti.com .(2) The RSH package is available in tape and reel. Add suffix R (TPS65820RSHR) to order quantities of2000 parts per reel. Add suffix T (TPS65820RSHT) to order quantities of 250 parts per reel.(3) This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of totalproduct weight, and is suitable for use in specified lead-free soldering processes. In addition, thisproduct uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb)above 0.1% of total product weight.(4) Other power-up sequences and default power-up states for the supplies can be implemented uponrequest. Consult factory for available options
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FUNCTIONAL BLOCK DIAGRAM
RTC_OUT
AC
BAT
OUT
USB
TMR
ISET1
TS
I2CINTERFACE
ANDINTERRUPT
CONTROLLER
INT
SDAT
SCLK
RESET
CONTROLLER
HOT_RST
RESPWRON
TRSTPWON
L1
PGND1
SM2
L2
L3
SM3
SIM
RED
BLUE
GREEN
SYS_IN
1.25V-3.3V
150 mA
LDO1
1.25V-3.3V
150 mA
LDO2
LDO3 1.224V-4.4V
100 mA
VIN_ LDO35
1.224V-4.4V
100 mA
LDO4
LDO35_REF
ANLG1
ANLG2
GPIO1
GPIO2
3.3V
10 mA
LDO_PM
FB3
BAT
OUT
ADC_REF
GPIO3
AGND2
PGND3
VIN_SM1
VIN_ SM2
PGND2
VIN_LDO12
DPPM
PWM
1.224V-4.4V
100 mA
LDO5
AGND1
LED_PWM
3.3V
150 mA
LDO0
AGND0
LDO3,4,5
LDO0,1,2
CONTROL
LOGIC
PWM
DRIVER
RGB
DRIVER
WHITELED
DRIVER
DISPLAY ANDI /O
GPIO’S
OUT
SM1
8 CHANNEL
MUX
A/D
CONVERTER
6 INTERNAL
CHANNELS
SM3_SW
2.6V/3.1V
8 mA
POWERPATH
CONTROL
LINEAR
CHARGER
0.6-1.8V
600 mA
1.0V-3.4V
600 mA
LDO_PM
CHARGE
MANAGEMENT
DC/DC
HOSTINTERFACE AND
SEQUENCING
ADC
AGND2
REFERENCE
SYSTEM
INTERNAL BIAS OUT
OUT
OUT
TPS65820
SIM,RTCLDOS
SYSTEM
POWER
ON/OFF
OUT
AGND1AGND1
AGND1
OUT
AGND1
AGND1
AGND1
OUT
AGND1
BAT
AGND1
AGND 0, AGND 1 AND AGND 2PINSSHORTEDTOEACHOTHERINSIDETPS 65800. ALL AGNDPINS AREINTERNALLY CONNECTEDTO
THETPS 65800 THERMAL PAD ANDSUBSTRATE .
PGND1, PGND 3 ANDPGND 3PINS ARENOTCONNECTEDTOEACHOTHERORTOTHETPS 65800 SUBSTRATE / POWERPAD
DISPLAY ANDI /O
OUT
1.8V/3V
8mA
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Figure 1. TPS65820 Simplified Block Diagram
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
AC and USB with respect to AGND1 – 0.3 to 18ANLG1, ANLG2 with respect to AGND2 – 0.3 to V(OUT)V(OUT) with respect to AGND1 5VIN_LDO12, VIN_LDO35, LDO3, LDO4, LDO5 with respect to AGND2 – 0.3 to V(OUT)LDO35_REF, ADC_REF with respect to AGND2 – 0.3 to smaller of: 3.6 or V(OUT)SIM, RTC_OUT with respect to AGND1 – 0.3 to smaller of: 3.6 or V(OUT)SM1, L1, VIN_SM1 with respect to PGND1 – 0.3 to V(OUT) VSM2, L2, VIN_SM2 with respect to PGND2 – 0.3 to V(OUT)SM3, L3 with respect to PGND3 – 0.3 to 29SM3SW with respect to PGND3 – 0.3 to V(OUT)FB3 with respect to PGND3 – 0.3 to 0.5All other pins (except AGND and PGND), with respect to AGND1 – 0.3 to V(OUT)AGND2, AGND0, PGND1, PGND2, PGND3 with respect to AGND1 – 0.3 to +0.3Input Current, AC pin 2750Input Current, USB pin 600Output continuous current, OUT pin 3000 mAOutput conitnuous current, BAT pin – 3000Continuous current at L1, PGND1, L2, PGND2 1800T
A
Operating free-air temperature – 40 to 85T
J
Maximum junction temperature 125
°CT
STG
Storage temperature – 65 to 150Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds 260ESD rating, all pins 1.5 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
T
A
≤55 °C DERATING FACTORPACKAGE θ
JA
POWER RATING ABOVE T
A
= 55 °C
RSH
(1) (2)
21.7 °C/W 3.22 W 0.046 W/ °C
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cupad on the board. This is connected to the ground plane by a via matrix.(2) The RSH package MSL Level : HIR3 at 260 °C
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RECOMMENDED OPERATING CONDITIONS
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
MIN MAX UNIT
AC and USB with respect to AGND1 4.35 16.5
(1)
VANLG1,ANLG2 with respect to AGND2 0 2.6 VVIN_LDO35 with respect to AGND2 Greater of : 3.6 V OR minimum input 4.7voltage required for LDO/converterVIN_LDO12 with respect to AGND1 4.7operation outside dropout region
VVIN_SM1 with respect to PGND1 4.7VIN_SM2 with respect to PGND2 4.7SM3 with respect to PGND3 28 VT
A
Operating free-air temperature – 40 85 °CT
J(op)
Junction temperature, functional operation assured – 40 125 °CT
J
Junction temperature, electrical characteristics assured 0 125 °C
(1) Thermal operating restrictions are reduced or avoided if input voltage does not exceed 5 V.
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ELECTRICAL CHARACTERISTICS – I
2
C INTERFACE
tsu(STOP)
t(BUF)
STOP
START
19873
2
19873
2
ACK
ACK
SCL
SCL
SDA
SDA
tsu(STA)
START
tr
STOP
th(STA) th(DAT)
tsu(DAT)
SCL
SDA
tw(H) tw(L)
tf
trtf
th(DAT)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in figure (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
2
C TIMING CHARACTERISTICS
t
R
SCLK/SDATA rise time 300t
F
SCLK/SDATA fall time 300 nst
W(H)
SCLK pulse width high 600t
W(L)
SCLK Pulse Width Low 1.3 µst
SU(STA)
Setup time for START condition 600t
H(STA)
START condition hold time after which first clock pulse is generated 600t
SU(DAT)
Data setup time 100 nst
H(DAT)
Data hold time 0t
SU(STOP)
Setup time for STOP condition 600t
(BUF)
Bus free time between START and STOP condition 1.3 µsFSCL Clock Frequency 400 kHz
I
2
C INTERFACE LOGIC LEVELS
V
IH
High level input voltage 1.3 6
VV
IL
Low level input voltage 0 0.6I
H
Input bias current 0.01 µA
Figure 2. I
2
C Timing
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ELECTRICAL CHARACTERISTICS – SYSTEM SEQUENCING AND OPERATING MODES
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
QUIESCENT CURRENT
BAT pin current, sleepI
BAT(SLEEP)
Input power not detected, V(BAT) = 4.2 V, Sleep mode set 370 µAmode setBAT pin current, charge Charger function enabled by I
2
C, termination detected, inputI
BAT(DONE)
3µAterminated power detected and selectedBAT pin current, charge Charger function disabled by I
2
C, termination not detected,I
BAT(CHGOFF)
3µAfunction OFF input power detected and selectedCharger function disabled by I
2
C, termination not detected,AC or USB pin current,I
INP(CHGOFF)
input power detected and selected. All integrated supplies 200 µAcharge function OFF
and drivers OFF, no load at OUT pin.
UNDER-VOLTAGE LOCKOUT
Internal UVLO detection NO POWER mode set at V(OUT) < V
UVLO
,V
UVLO
– 3% 2.5 3% Vthreshold V(OUT) decreasingUVLO detectionV
UVLO_HYS
V(OUT) increasing 120 mVhysteresis
UVLO detection deglitcht
DGL(UVLO)
Falling voltage only 5 mstime
SYSTEM LOW VOLTAGE THRESHOLD
Minimum system voltage System voltage V(SYS_IN) decreasing, SLEEP mode set ifV
LOW_SYS
0.97 1 1.03 Vdetection threshold V(SYS_IN) < V
LOW_SYS
Minimum system voltageV
HYS(LOWSYS)
V(SYS_IN) increasing 50 mVdetection hysteresisMinimum system voltage
V(SYS_IN) decreasing, valid only for initial power-up, seet
DGL(HOTPLUG)
detection hotplug 650 msstate machine diagramdeglitch timeMinimum system voltaget
DGL(LOWSYS)
V(SYS_IN) decreasing, hotplug deglitch time expired 5 msdetection deglitch time
THERMAL FAULT
T
SHUT
Thermal shutdown Increasing junction temperature 165 °CThermal shudownT
HYS(SHUT)
Decreasing junction temperature 30 °Chysteresis
INTEGRATED SUPPLY POWER FAULT DETECTION
Power good fault Falling output voltage, applies to all integrated supply outputs.V
PGOOD
84% 90% 96%detection threshold Referenced to the programmed output voltage valuePower good fault Rising output voltage, applies to all integrated supply outputs.V
HYS(PGOOD)
3% 5% 7%detection hysteresis Referenced to V
PGOOD
threshold
HOT RESET FUNCTION
V
HRSTON
Low level input voltage RESET mode set at V( HOT_RESET) < V
HRSTON
0.4 VV
HRSTOFF
High level input voltage HOT reset not active at V( HOT_RESET) > V
HRSTOFF
1.3 Vt
DGL(HOTRST)
Hot reset input deglitch 5000 µs
SYSTEM RESET – OPEN DRAIN OUTPUT RESPWRON
V
RSTLO
Low level output voltage I
IL
= 10 mA, V( RESPWRON ) < V
RSTLO
0 0.3 VI
TRSTPWON
Pullup current source Internally connected to TRSTPWRON pin 0.9 1 1.2 µAK
RESET
Reset timer constant T
RESET
= K
RESET
°C
TRSTPWON
1 ms/nF
SEQUENCING DELAYS
t
DLY(D1)
Sequencing delay See sequencing timing diagram 0.24 mst
DLY(D1)
Sequencing delay See sequencing timing diagram 12 ms
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ELECTRICAL CHARACTERISTICS – POWER PATH AND CHARGE MANAGEMENT
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOLTAGE DETECTION THRESHOLDS
Input voltage detection AC detected at V(AC) – V(BAT) > V
IN(DT)
;V
IN(DT)
190 mVthreshold USB detected at V(USB) – V(BAT) > V
IN(DT)
Input Voltage removal AC not detected at V(AC) – V(BAT) < V
IN(NDT)
;V
IN(NDT)
125 mVthreshold USB not detected at V(USB) – V(BAT) < V
IN(NDT)
t
DGL(NDT)
Power not detected deglitch 22.5 ms
Supplement detectionV
SUP(DT)
Battery switch ON at V(BAT) – V(OUT) > V
SUP(DT)
60 mVthreshold
Supplement not detectedV
SUP(NDT)
Battery switch OFF at V(BAT) – V(OUT) < V
SUP(NDT)
20 mVthreshold
POWER PATH INTEGRATED MOSFETs CHARACTERISTICS
AC switch dropout voltage V
ACDO
= V(AC) – V(OUT); V(AC) = 4.75-V AC input current limit set to 2.75 AV
ACDO
350 375 mV(typ), I
O(OUT)
= 1 A
V
USBDO
= V(USB) – V(OUT); V(USB) = 4.6 V I(OUT) + I(BAT)= 0.5 A 175 190 mVV
USBDO
USB switch dropout voltage
USB input current limit set to 2.75 A (typ)
I(OUT) + I(BAT)= 0.1 A 35 45 mV
Battery switch dropoutV
BATDODCH
V(BAT): 3 V →V
CH(REG)
, I(BAT) = – 1 A 60 100 mVvoltage, discharge
Battery switch dropoutV
BATDOCH
Charger on, V(BAT): 3 V →4.2 V, I(BAT) = 1 A 60 100 mVvoltage, charge
POWER PATH INPUT CURRENT LIMIT
Selected Input current limit,
Selected input switch not in dropout, I
2
C settings : ISET2 = LO,I
INP(LIM1)
80 100 mAapplies to USB input only
PSEL = LO
Selected Input current limit,I
INP(LIM2)
400 500 mASelected input switch not in dropout, I
2
C settings: ISET2 = HI, PSEL = LOapplies to USB input only
Selected Input current limit,
Selected input switch not in dropout, I
2
C settings: ISET2 = HI OR LO,I
INP(LIM3)
applies to either AC or USB 2.75 APSEL = HIinput
SYSTEM REGULATION VOLTAGE
V
SYS(REG)
= V(OUT), DPPM loop not active, selected input current limit notV
SYS(REG)
Output regulation voltage 4.6 4.7 Vreached. Selected input voltage (AC or USB) > 5.1 V
POWER PATH PROTECTION AND RECOVERY FUNCTIONS
Input-to-output short-circuitV
INOUTSH
AC and USB switches set to OFF if V(OUT) < V
INOUTSH
0.6 Vdetection threshold
OUT short-circuit recoveryR
SH(USBSH)
V(OUT) < 1 V, internal resistor connected from USB to OUT 500 Ωpullup resistor
OUT short-circuit recoveryR
SH(ACSH)
V(OUT) < 1 V, internal resistor connected from AC to OUT 500 Ωpullup resistor
Overvoltage detection Rising voltage, overvoltage detected when V(AC) > V
OVP
or
6 6.5 6.8 Vthreshold V(USB) > V
OVPV
OVP
Overvoltage detection
Falling voltage, relative to detection threshold 0.1 Vhysteresis
Battery-to-output short-circuitV
BATOUTSH
BAT switch set to OFF if V(BAT) – V(OUT)> V
BATOUTSH
200 mVdetection threshold
Battery-to-ouput short-circuit V
(DPPM)
< 1V, t
BLK(SHBAT)
= K
BLK(SHBAT)
×C
DPPM,
C
DPPM
capacitor is connectedK
BLK(SHBAT)
1 mS/nFblanking time constant from DPPM pin to AGND1
OUT short-circuit recovery V
(BAT)
– V
(OUT)
> V
BATOUTSH
,I
SH(BAT)
10 mApullup current source Internal current source connected between OUT and BAT
BAT short-circuit recovery V
(BAT)
< 1V,R
SHBAT)
1 k Ωresistor Internal resistor connected from OUT to BAT
Internal resistor connected from BAT to AGND1 when battery is not detectedR
DCH(BAT)
BAT pulldown resistor 500 Ωby ANLG1
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ELECTRICAL CHARACTERISTICS – POWER PATH AND CHARGE MANAGEMENT (Continued)
V(OUT)*1.2
500 kW
IO(BAT) +K(SET) V(SET)
RSET
IO(PRECHG) +V(PRECHG) K(SET)
RSET
I(TERM) +V(TERM) K(SET)
RSET
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER PATH TIMING CHARACTERISTICS, DPPM AND THERMAL LOOPS NOT ACTIVE, R
TMR
= 50 k Ω
t
BOOT
Boot-up time Measured from input power detection 120 200 300 ms
No USB: measured from V(AC) – V(BAT) < V
IN(NDT)
, USBt
SW(ACBAT)
Switching from AC to BAT 50 µsdetected: CE = LO (after CE hold-off time)
No AC: measured from V(USB) – V(BAT) < V
IN(NDT)
, USBt
SW(USBBAT)
Switching from USB to BAT 50 µsdetected: CE = LO (after CE hold-off time)
t
SW(PSEL)
Switching from USB to AC 50 µsToggling I
2
C PSEL bit
Switching from AC to USB or USB tot
SW(ACUSB)
AC power removed or USB power removed 100 µsAC
BATTERY REMOVAL DETECTION
V
NOBATID
Battery ID resistor detection ID resistor not detected at V(OUT) – V(ANLG1) < V
NOBATID
0.5 V
Deglitch time for battery removalt
DGL(NOBAT)
0.6 1.2 msdetection
00, V
(OUT)
: 2.5 V to 4.4 V
Set via I
2
C bits (BATID1,
µA01 10BATID2) ADC_WAIT registerI
O(ANLG1)
ANLG1 pullup current
10 50
11 60
Total accuracy 25% 25%
FAST CHARGE CURRENT, V(OUT) > V(BAT) + 0.1 V, V(BAT) > V
LOWV
I
O(BAT)
Charge current range 100 1500 mA
11, 100% scaling 2.475 2.5 2.525
10, 75% scaling 1.875 1.9 1.925V
SET
= V(ISET1),V
SET
Battery charge current set voltage V(ISET1_1, ISET1_0) =
01, 50% scaling 1.225 1.25 1.275
00, 25% scaling 0.575 0.6 0.625
100 mA < I
O(BAT)
≤1 A 350 400 450K
SET
Battery charge current set factor
1 mA < I
O(BAT)
≤100 mA 100 400 1000
PRECHARGE CURRENT, V(OUT) > V(BAT) + 0.1 V, V
BATSH
< V(BAT) < V
LOWV
, t < t
(PRECHG)
I
O(PRECHG)
Precharge current range 10 150 mA
V
PRECHG
Precharge set voltage V
PRECHG
= V(ISET1) 220 250 270 mV
V
LOWV
Precharge to fast-charge transition Fast charge at V(BAT) > V
LOWV
2.8 3 3.2 V
Deglitch time for fast charge tot
DGL(PRE)
Decreasing battery voltage, R
TMR
= 50 k Ω22.5 msprecharge transition
CHARGE REGULATION VOLTAGE, V(OUT) > V
O(BATREG)
+ 0.1V
4.2
VVoltage options, selection via I
2
C
4.356V
O(BATREG)
Battery charge voltage
Accuracy, T
A
= 25 °C – 0.5% 0.5%
Total accuracy – 1% 1%
CHARGE TERMINATION, V(BAT) > V
RCH
, VOLTAGE REGULATION MODE SET
I
TERM
Charge termination current range 10 150 mA
11, 100% scaling 240 260 280
10, 75% scaling 145 160 175Battery termination detection set V
TERM
= V(ISET1),V
TERM
mVvoltage (ISET1_1, SET1_0) =
01, 50% scaling 90 110 130
00, 25% scaling 40 60 75
t
DGL(TERM)
Deglitch time for termination detection V(ISET1) < V
TERM
, R
TMR
= 50 k Ω22.5 ms
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ELECTRICAL CHARACTERISTICS – POWER PATH AND CHARGE MANAGEMENT (Continued)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY RECHARGE DETECTION
V
RCH
New charge cycle starts if V(BAT) < V
O(BATREG)
– V
RCH
, afterRecharge threshold voltage 80 100 130 mVtermination was detected
t
DGL(RCH)
Deglitch time for recharge detection R
TMR
= 50 k Ω22.5 ms
DPPM FUNCTION
V
DPPM
DPPM regulation point range V
(DPPM)
= R
DPPM
×K
DPPMM
x I
O(DPPM)
2.6 4.4 V
I
O(DPPM)
DPPM pin current source AC or USB present 95 100 105 µA
K
DPPM
DPPM scaling factor 1.139 1.15 1.162
Status bit set indicating DPPM loop active after deglitch time,t
DGL(DPPM)
DPPM de-glitch time 500 µsR
TMR
= 50 k Ω
PACK TEMPERATURE SENSING
V
LTF
Low temperture threshold Pack low temperature fault at V(TS) > V
LTF
2.465 2.500 2.535 V
V
HTF
High temperture threshold Pack low temperature fault at V(TS) < V
HTF
0.485 0.500 0.515 V
I
O(TS)
Temperature sense current source Thermistor bias current 18.8 20 21.2 µA
Deglitch time for temperature fault R(TMR) = 50 k Ω,t
DLG(TFAULT)
22.5 msdetection V(TS) > V
LTF
OR V(TS) < V
HTF
CHARGE AND PRECHARGE SAFETY TIMER
Charge safety timer programmed Safety timer range, thermal/DPPM loop not active,t
CHG
3 5 10 hoursvalue t
CHG
= R
TMR
×K
TMR
K
TMR
Charge timer set factor 0.313 0.360 0.414 s/ Ω
Total elapsed time when DPPM or fast charge on, t
CHGADD
is the maximum add-on time added tot
CHGADD
2 t
CHG
hoursthermal loop are active t
CHG
Precharge safety timer programmed Pre charge safety timer range, thermal/DPPM loop not active,t
PRECHG
18 30 60 minvalue t
PRECHG
= K
PRE
×R
TMR
×K
TMR
K
PRE
Precharge timer set factor 0.09 0.1 0.11
Total elapsed time when DPPM or Precharge on, t
PCHGADD
is the maximum add-on time added to 2 ×t
PCHGADD
hoursthermal loop are active t
PRECHG
t
PRECHG
R
TMR
External timer resistor limits 30 100 k Ω
Internal resistor connected from OUT to BAT after safety timerR
TMR(FLT)
Timer fault recovery pullup resistor 1 k Ωtimeout
THERMAL REGULATION LOOP
Charge current decreasesd and timer extended when T
J
>T
THREG
Temperature regulation limit 115 135 °CT
THREG
CHARGER THERMAL SHUTDOWN
T
THCHG
Charger thermal shutdown Charger turned off when T
J
> T
THCHG
150 °C
T
THCHGHYS
Charger thermal shutdown hysteresis 30 °C
10 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
ELECTRICAL CHARACTERISTICS – LINEAR REGULATORS
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SELECTABLE OUTPUT VOLTAGE LDO ’ S : LDO1, LDO2
I
(LDO1,2)
= – 1 mA 15Quiescent current, either LDO1 orI
Q(LDO12)
I
Q(LDO12)
= I(VIN_LDO02) µALDO2 enabled, LDO0 disabled
I
(LDO1,2)
= – 150 mA 160
I
O(LDO1,2)
Output current range 150 mA
Available output voltages:V
O(LDO1,2)
VOutput voltage, selectable via I
2
C.
TYP = 1.25, 1.5, 1.8, 2.5,2.85, 3, 3.2, 3.3
Dropout voltage, 150 mA load 300 mVV
O(LDO1,2)
LDO1, LDO2 output voltage
Total accuracy, V(VIN_LDO02) = 3.65 V – 3% 3%
Line regulation, 100 mA load,
– 1% 1%V(VIN_LDO02): V
(LDO1,2)TYP
+ 0.5 V →4.7 V
Load regulation, load: 10 mA →150 mA
– 1.5% 1.5%V(VIN_LDO02) > V
O(LDO1,2) TYP
+ 0.5V
P
SR(LDO12)
PSRR at 20 kHz 150-mA load at output, V(VIN_LDO02) – V
O(LDO1,2)
= 1 V 40 dB
LDO1 and -2 short-circuit currentI
SC(LDO1,2)
Output grounded 300 mAlimit
R
DCH(LDO1,2)
Discharge resistor 300 ΩLDO disabled by I
2
C command
I
LKG(LDO1,2)
Leakage current LDO off 2 µA
SIM LINEAR REGULATOR
I
Q(SIM)
Quiescent current Internally connected to OUT pin 20 µA
I
O(SIM)
Output current range 8 mA
Available output voltages:
VOutput voltage, selectable via I
2
C.
V
O(SIM)TYP
= 1.8 or 3
Dropout voltage, 8-mA load 0.2 V
Total accuracy, V(OUT): 3.2 V to 4.7 V, 8 mA – 5% 5%V
O(SIM)
SIM LDO output voltage
Load regulation, load: 1 mA →8 mA,
– 3% 3%V(OUT) > V
O(SIM) TYP
+ 0.5 V
Line regulation, 5 mA load, V(OUT):
– 2% 2%V
O(SIM) TYP
+ 0.5 V →4.7 V
I
SC(SIM)
Short-circuit current limit Output grounded 20 mA
I
LKG(SIM)
Leakage current LDO off 1 µA
PROGRAMMABLE OUTPUT VOLTAGE LDO ’ S: LDO3, LDO4, LDO5
Quiescent current, only one ofI
Q(LDO35)
I
Q(LDO35)
= I(VIN_LDO35) 70 µALDO3, LDO4, LDO5 is enabled
I
O(LDO35)
Output current range 100 mA
Available output voltages :V
O(LDO35)TYP
= 1.224 V to VOutput voltage, selectable via I
2
C
4.46 V, 25 mV steps
Dropout voltage, 100-mA load 240 mV
Total accuracy, 100 mA load V
(VIN_LDO35)
= 5 V – 3% 3%V
O(LDO35)
LDO3, LDO4, LDO5 output voltage
Load regulation,
V(VIN_LDO35) > V
O(LDO35)TYP
+ load: 1 mA →50 mA – 1% 1%0.5 V
Line regulation, 10 mA load,
– 1% 1%V(VIN_LDO35): V
O(LDO35)TYP
+ 0.5 V →4.7 V
I
SC(LDO35)
Short-circuit current limit Output grounded 250 mA
PSR
(LDO35)
PSRR at 10 kHz V(VIN_LDO35) > V
O(LDO3,5)
+ 1 V, 50 mA load at output 40 dB
R
DCH(LDO35)
Discharge resistor 400 ΩLDO is disabled by I
2
C command
I
LKG(LDO35)
Leakage current LDO off 1 µA
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS65820
ELECTRICAL CHARACTERISTICS – LINEAR REGULATORS (continued)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RTC_OUT LINEAR REGULATOR
I
Q(RTC_OUT)
Quiescent current for RTC LDO Internally connected to OUT pin 20 µA
I
O(RTC_OUT)
Output current range 8 mA
Available output voltages:
VOutput voltage value, selectable via I
2
C.
2.6 V or 3.1 V
Dropout voltage, I(RTC_OUT) = – 8 mA 200 mV
Total accuracy, V(OUT): 2 V to 4.7 V, 8 mA load,
– 5% 5%V
O(RTC_OUT)
RTC_OUT output voltage sleep mode not set
Load regulation, load: 1 mA →8 mA, 2 V < V(OUT) < 4.7
– 3% 3%V
Line regulation, 5 mA load
– 2% 2%V(OUT): 2 V →4.7 V
I
SH(RTC_OUT)
Short-circuit current limit V(RTC_OUT) = 0 V 20 mA
T
J
= 85 °C 880V(RTC_OUT) = 1.5 V,I
LKG(RTC_OUT)
Leakage current nAV(OUT) = 0 V
T
J
= 25 °C 250
LDO0 LINEAR REGULATOR
I(LDO0) = – 1 mA 15Internally connected to VIN_LDO12I
Q(LDO0)
Quiescent current µApin
I(LDO0) = – 150 mA 160
I
O(LDO0)
Output current range 150 mA
Fixed output voltage value 3.3 V
Dropout voltage, I(LDO0) = – 150 mA 300 mV
Total accuracy – 3% 3%V
O(LDO0)
Output voltage
Line regulation, V(OUT): V
O(LDO0)
+ 0.5 →4.7 V, I(LDO0) =
– 1% 1%– 100 mA
Load regulation, I(LDO0) = – 10 mA →– 150 mA – 1.5% 1.5%
PSR
(LDO0)
PSRR at 20 kHz 150-mA load at output, V(VIN_LDO12) – V
O(LDO1,2)
= 1 V 40 dB
I
SC(LDO0)
Short-circuit current limit V(LDO0) = 0 V 300 mA
I
LKG(LDO0)
Leakage current LDO off 1 µA
LDO_PM LINEAR REGULATOR
I
Q(LD0_PM)
Output current range 20 mA
Fixed output voltage value, V(OUT) > 4 V 3.3 V
V
O(LDO_PM)
Output voltage Dropout voltage, I(LDOPM) = – 12 mA 0.5 0.7 V
Total accuracy – 5% 5%
I
LKG(LDOPM)
Leakage current LDO off 1 µA
12 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
ELECTRICAL CHARACTERISTICS – SWITCHED MODE SM1 STEP-DOWN CONVERTER
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Over recommended operating conditions (typical values at T
J
= 25 °C), V
O(SM1)
= 1.24 V, application circuit as in Figure 3(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
Q(SM1)
= I(VIN_ SM1), no output load Not switching 10I
Q(SM1)
Quiescent current for SM1 µASM1 OFF, set via I
2
C 0.1I
O(SM1)
Output current range 600 mAAvailable outputvoltages: V
O(SM1)TYP
=Output voltage, selectable via I
2
C, standby OFF 0.6 V to 1.8 V,adjustable in 40 mVsteps
VAvailable outputvoltages: V
SBY(SM1)
=V
O(SM1)
= V
SBY(SM1)
, output voltage range, standby ON 0.6 V to 1.8 V,V
O(SM1)
Output voltage, PWM mode
adjustable in 40 mVstepsTotal accuracy, V
O(SM1)TYP
= V
SBY(SM1)
= 1.24 V,
– 3% 3%V(VIN_SM1) = 3 V to 4.7 V; 0 mA ≤I
O(SM1)
≤600 mALine regulation, V(VIN_SM1): 3 V →4.7 V,
0.027 %/VI
O(SM1)
= 10 mALoad regulation, V(VIN_SM1) = 4.7 V,
0.139 %/AI
O(SM1)
: 60 mA →540 mAP-channel MOSFETR
DSON(PSM1)
V(VIN_SM1) = 3.6 V, 100% duty cycle set 310 500 m Ωon-resistanceI
LKG(PSM1)
P-channel leakage current 0.1 µAN-channel MOSFETR
DSON(NSM1)
V(VIN_SM1) = 3.6 V, 0% duty cycle set 220 330 m Ωon-resistanceI
LKG(PSM1)
N-channel leakage current 5 µAI
LIM(SM1)
P- and N-channel current limit 3 V < V(VIN_SM1) < 4.7 V 900 1050 1200 mAf
S(SM1)
Oscillator frequency PWM mode set 1.3 1.5 1.7 MHzV(VIN_SM1) = 4.2 V, PWM mode, I
O(SM1)
= 300 mA,EFF
(SM1)
Efficiency 90%V
O(SM1)
= 3 VConverter OFF →ON, V
O(SM1)
: 5% →95% of targett
SS(SM1)
Soft start ramp time 750 µsvaluet
DLY(SM1)
GPIO1 pin programmed as SM1 converter enableConverter turn-on delay 170 µscontrol. Measured from V(GPIO1): LO →HI
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS65820
ELECTRICAL CHARACTERISTICS – SWITCHED MODE SM2 STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS – GPIOs
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
Over recommended operating conditions (typical values at T
J
= 25 °C), V
O(SM1)
= 1.24 V, application circuit as in Figure 3(unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Not 10I
Q(SM2)
= I(VIN_ SM2), no output load
switchingI
Q(SM2)
Quiescent current for SM2 µASM2 OFF, set via I
2
C 0.1I
O(SM2)
Output current range 600 mAAvailable outputvoltages: V
O(SM2)TYP
=Output voltage, selectable via I
2
C, standby OFF
1 V to 3.4 V, adjustable
in 80 mV steps
VAvailable outputV
O(SM2)
= V
SBY(SM2)
, output voltage range, standby voltages: V
SBY(SM2)
= 1ON V to 3.4 V, adjustable in80 mV stepsV
O(SM2)
Output voltage
Total accuracy, V
O(SM2)TYP
= V
SM2(SBY)
= 1.8 V,V(VIN_SM2) = greater of [3 V or (V
O(SM2)
+ 0.3 V)] – 3% 3%to 4.7 V; 0 mA ≤I
O(SM2)
≤600 mALine regulation, V(VIN_SM2) = greater of %/V[3 V or (V
O(SM2)
+ 0.3 V)] 0.027to 4.7 V; 0 mA ≤I
O(SM2)
≤600 mALoad regulation, V(VIN_SM2) = 4.7 V,
0.139 %/AI
O(SM2)
: 60 mA →540 mAP-channel MOSFETR
DSON(PSM2)
V(VIN_SM2) = 3.6 V, 100% duty cycle set 310 500 m Ωon-resistanceI
LKG(PSM2)
P-channel leakage current 0.1 µAN-channel MOSFETR
DSON(NSM2)
V(VIN_SM2) = 3.6 V, 0% duty cycle set 220 330 m Ωon-resistanceI
LKG(PSM2)
N-channel leakage current 5 µAI
LIM(SM2)
P- and N-channel current limit 3 V < V(VIN_SM2) < 4.7 V, TPS65820 900 1050 1200 mAf
S(SM2)
Oscillator frequency PWM mode set 1.3 1.5 1.7 MHzV(VIN_SM2) = 4.2 V, I
O(SM2)
= 300 mA,EFF
(SM2)
Efficiency 90%V
O(SM2)
= 3 VConverter OFF →ON, V
O(SM2)
: 5% →95% of targett
SS(SM2)
Soft start ramp time 750 µsvaluet
DLY(SM2)
Converter turn-on delay GPIO2 pin programmed as SM2 converter enable 170 µscontrol. Measured from V(GPIO2): LO →HI
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPIO1 – 3
V
OL
Low level output voltage GPIO0 I
OL
= 20 mA 0.5 VI
OGPIO
Low level sink current into GPIO1, 2, 3 V(GPIOn) = V(OUT) 20 mAV
IL
Low level input voltage 0.4 VI
LKG(GPIO)
Input leakage current V(GPIOn) = V(OUT) 1 µA
14 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
ELECTRICAL CHARACTERISTICS – ADC
V(OUT)*1.2
500 kW
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Over recommended operating conditions (typical values at T
J
= 25 °C), V(ADC_REF) =2.535v if external reference voltage isused,application circuit as in Figure 3 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Full scale input range Ch1 to V(ADCV
RNG(CH1_5)
Positive inputs (active clamp), full scale ~ 2.535 V 0 VCh5 _REF)Full scale input range Ch6 to V
INTREFV
RNG(CH6_8)
Positive inputs (active clamp), full scale ~4.7 V 0 VCh8 ×1.854Input capacitance (allC
IN(ADC)
15 pFchannels)R
INADC(CH1_5)
Input resistance (Ch1 to Ch5) 1 M Ω
I
LKGADC(CH1_5)
Leakage current (Ch1 to Ch5) 100 nAR
INADC(CH6_8)
Input resistance (Ch6 to Ch8) 430 540 k Ω
I
LKGADC(CH6_8)
Leakage current (Ch6 to Ch8) 10 µAT
J
= 25 °C, ADC channel 5 input voltage 1.895 VInternal voltage proportional toV
CH5(ADC)
junction temperature
Temperature coefficient 6.5 mV/ °C
DC ACCURACY
RES
(ADC)
Resolution SAR ADC 10 BitsMCD
(ADC)
No missing codes SPECIFIEDINL
(ADC)
Integral linearity error ± 3 LSBDNL
(ADC)
Differential non-linearity error ± 1 LSBDifference between the first code transitionOFF
ZERO(ADC)
Offset error 5 LSB(00...00 to 00...01) from the ideal AGND + 1 LSBOffset error match betweenOFF
CH(ADC)
5 LSBchannels
Deviation in code from the ideal full scale codeGAIN
ADC
Gain error ± 8 LSB(11 … 111) for the full scale voltageGAIN
CH(ADC)
Gain error match Any two channels 2 LSB
THROUGHPUT SPEED
ADC
CLK
Sampling clock 600 750 900 kHzSampling, convertion and setting Rs ≤200 K forADC
TCONV
Conversion time 44 59 68 µsCH1, CH2, CH3; Rs ≤500 Ωfor CH6, CH7, CH8
REFERENCE VOLTAGES
T
A
= 25 °C, V(ADC_REF) = V
INTREF
when internalV
INTREF
Internal ADC reference voltage 2.53 2.535 2.54 VADC reference is selectedInternal reference short-circuit V(ADC_REF) = AGND1, internal referenceI
SHRT(INTREF)
6 mAlimit enabled via I
2
CADC internal referenceV
REF(DRIFT)
50 100 ppm/ °Ctemperature driftADC Internal reference Measured at OUT pin (internal reference) orI
Q(ADC)
40 µAquiescent current ADC_REF pin (external reference)
00 0ADC channel 2 bias current, set via
01 10I
2
C register ADC_WAIT bits µAANLG2 pin internal pullupI
(ANLG2)
10 50(ADC_CH2I_D1_1, ADC_CH2I _D2)current source
11 60Total accuracy, relative to selected value – 25% 25%
00 µAADC channel 1 bias current, set via
01 10I
2
C register ADC_WAIT bitsANLG1 pin internal pullupI
(ANLG1)
(BATIDI_D1, BATIDI _D2)current source
10 5011 60Total accuracy 10% 10%
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS65820
ELECTRICAL CHARACTERISTICS – LED AND PWM DRIVERS
Current range, Vin = 3.3 V,
IO(SM3) +V(SM3REF)
RFB3
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS – ADC (continued)Over recommended operating conditions (typical values at T
J
= 25 °C), V(ADC_REF) =2.535v if external reference voltage isused,application circuit as in Figure 3 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL REFERENCE POWER CONSUMPTION
PD
ACTIVE
Power dissipation Conversion active 2.3 mWPD
ARMED
Power dissipation Not converting 0.43 mW
TRIGGER TIMING CHARACTERISTICS
t
DELAY(TRG)
Trigger delay time accuracy Time range, set via I
2
C register ADC_DELAY 0 750 uSRelative to typical value set via I
2
C – 20% 20%t
WAIT(TRG)
Trigger wait time accuracy Time range, set via I
2
C register ADC_WAIT 0 20.48 mSRelative to typical value set via I
2
C – 20% 20%
Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SM3 BOOST CONVERTER, WHITE LED CONSTANT CURRENT DRIVER
V
VIN(SM3)
Input Voltage range V(OUT) = 3.3 V 3 4.7 VV
OVP3
Output overvoltage trip OVP detected at V(SM3) > V
OVP3
26.5 29 30 VV
HYS(OVP3)
Output overvoltage hysteresis OVP not detected at V(SM3) < V
OVP3
– V
HYS(OVP3)
1.8 VLED current below regulation point atV
SM3REF
LED current sense threshold 244 252 260 mVV(FB3) < V
SM3REF
0 25 mAI
O(SM3)
LED current
Total accuracy, I
O(SM3)
= 10 mA – 10% 10%D
SM3SW
= 0% to 99.6%, setD
SM3SW
LED switch duty cycle Duty cycle range via I
2
C, 256 steps 0.4%minimum stepSM3_LF_OSC = 0 122LED switch duty cycle pattern 256 pulses within repetitionF
REP_SM3
Hzrepetition rate rate time
SM3_LF_OSC = 1 183R
DSON(SM3SW
LED switch MOSFET
V(OUT) = 3.6 V; I(SM3SW) = 20 mA 1 2 Ω)
on-resistanceI
LKG(SM3SW)
LED switch MOSFET leakage 1 µAPower stage MOSFETR
DSON(L3)
V(OUT) = 3.6 V; I(L3) = 200 mA 300 600 m Ωon-resistanceI
LKG(L3)
Power stage MOSFET leakage 1 µAPower stage MOSFET currentI
MAX(L3)
3 V < V(OUT) < 4.7 V 400 500 600 mAlimit
PWM DRIVER, PWM OPEN DRAIN OUTPUT
V
OL(PWM)
Low level output voltage I(PWM)= 150 mA 0.5 VSet via I
2
C, F
PWM
=Frequency range Hz0.5/1/1.5/2/3/4.5/7.8/15.6F
PWM
PWM driver frequency
Total accuracy, relative to selected value -20% 20%D
PWM
= 6.25% to 100%,D
PWM
PWM driver duty cycle Duty cycle range set via I
2
C,6.25% minimum step
LED_PWM DRIVER, LED_PWM OPEN DRAIN OUTPUT
D
LEDPWM
= 0% to 99.6%,D
LEDPWM
LED_PWM driver duty cycle Duty cycle range set via I
2
C, 256 steps0.4% minimum stepSM3_LF_OSC = 0 122LED_PWM driver duty cycle 256 pulses within repetitionF
REP(LEDPWM)
Hzpattern repetition rate rate time
SM3_LF_OSC = 1 180
16 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
PIN ASSIGNMENT
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
ELECTRICAL CHARACTERISTICS – LED AND PWM DRIVERS (continued)Over recommended operating conditions (typical values at T
J
= 25 °C), application circuit as in Figure 3 (unless otherwisenoted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OL(LEDPWM)
Low level output voltage I(LED_PWM) = 150 mA 0.5 VV
OH(LEDPWM)
High level output voltage 6 V
RGB DRIVER, RED/GREEN/BLUE OPEN DRAIN OUTPUTS
t
FLASH(RGB)
= 1 to 8 s, setFlashing period range via I
2
C, 0.5 s minimum st
FLASH(RGB)
Flashing period
step, 8 stepsTotal accuracy -20% 20%Set via I
2
C, t
FLASH(ON)
=Flash on time range, value selectable by I
2
C 0.1/0.15/0.2/0.25/0.3/0.4/ st
FLASH(ON)
Flash on time
0.5/0.6 sTotal accuracy, relative to selected value -20% 20%D
RGB
= 0% to 99.98%, setD
RGB
Duty cycle Duty cycle range, value selectable via I
2
C via I
2
C, 3.23% minimum
step00 (Driver set to OFF)V(RED) = V(GREEN) =
01 2.4 4 5.6I
SINK(RGB)
RGB output sink current V(BLUE) = 2 V, set via I
2
C mA10 4.8 8 11.2RGB_ISET1,0
11 7 12 16.6Output low voltage, 8-mA load, RED/GREEN/BLUEV
OL(RGB)
Low-level output voltage 0.3 VPINS
V(RED)=V(GREEN)=V(BLUE) = 4.7 V, all driversI
LKG(RGB)
Output off leakage current 1 µAdisabled
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS65820
PIN DESCRIPTION, REQUIRED EXTERNAL COMPONENTS
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
NAME PIN I/O DESCRIPTION EXTERNAL REQUIRED COMPONENTS(SEE APPLICATION DIAGRAM)
AC 7 I Adapter charge input voltage, connect to 1- µF (minimum) capacitor to AGND1 pin to minimizeAC_DC adapter positive output terminal overvoltage transients during AC power hot-plug events.(dc voltage)ADC_REF 22 I/O ADC internal reference filter or ADC 4.7- µF (minimum) to 10- µF (maximum) capacitor connected toexternal reference input AGND2 pinAGND0 16 – Analog ground connection Connect to analog ground planeAGND1 48 Analog ground pin Connect to analog ground planeAGND2 25 Analog ground pin Connect to analog ground planeANLG1 24 I Analog input to ADC, programmable Can be used to monitor additional system or pack parameterscurrent source outputANLG2 23 I Analog input to ADC, programmable Can be used to monitor additional system or pack parameterscurrent source outputBAT 17, I/O Battery power Connect to battery positive terminal. Connect 10- µF capacitor18 (minimum) from BAT pin to AGND1 pinBLUE 1 O Programmable blue driver, open drain Connect to BLUE input of RGB LEDoutput, current sink output when active.DPPM 14 I Dynamic power path management External resistor from DPPM pin to AGND1 pin sets the DPPMset-point regulation threshold. 1 nF (minimum) capacitor to from DPPMto AGND1 sets BAT to OUT short-circuit blanking delay whenbattery is hot-plugged into systemFB3 41 I/O White LED duty cycle switch output, LED External resistor from FB3 pin to PGND3 pin sets LED peakcurrent setting current. Connect 100-pF (minimum) filter capacitor to PGND3pin.HOT_RST 15 I/O Hardware reset input, reset generated Connect to an external push-button switchwhen connected to groundGPIO1 43 I/O General purpose programmable I/O Example: External interrupt request to host ( INT: HI →LO)GPIO2 53 I/O General purpose programmable I/O example: Set SM1 and SM2 converters in standby modeGPIO3 54 I/O General purpose programmable I/O Example: ADC conversion start triggerGREEN 56 O Programmable LED driver, open-drain Connect to GREEN input of RGB LEDoutput, current sink output when activeINT 19 O Interruption pin, open-drain output Connect 100-k Ωexternal pullup resistor between INT andOUT. INT pin is LO when interrupt is requested by TPS65820.ISET1 11 I Current set point when charging in auto External resistor from ISET1 pin to AGND1 pin sets chargemode with AC selected. Precharge and current valuecharge termination set point for all chargemodesL1 46 O SM1 synchronous buck converter power 3.3- µH inductor to SM1 pinstage outputL2 51 O SM2 synchronous buck converter power 3.3- µH inductor to SM2 pinstage outputL3 39 O Drain of the integrated boost power stage 4.7- µH inductor to OUT pin, external Schottky diode to SM3 pinswitchLDO_PM 10 O General-purpose LDO output 1- µF (minimum) capacitor to AGND1 pinLDO0 32 O LDO0 output, fixed voltage 1- µF (minimum) capacitor to AGND1LDO1 37 O LDO1 output 1- µF (minimum) capacitor to AGND1LDO2 33 O LDO2 output 1- µF (minimum) capacitor to AGND1LDO3 28 O LDO3 output 2.2- µF (minimum) capacitor to AGND2LDO35_REF 30 I Linear regulators LDO3 – 5 reference filter 100-nF capacitor to AGND2LDO4 27 O LDO4 output 2.2- µF (minimum) capacitor to AGND2LDO5 26 O LDO5 output 2.2- µF (minimum) capacitor to AGND2LED_PWM 36 O PWM driver output, open-drain Can be used to drive a keyboard backlight LEDOUT 8, 9 O Power path output. Connect to system 10- µF capacitor to AGND1 pinmain power rail (system power bus)
18 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
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TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
NAME PIN I/O DESCRIPTION EXTERNAL REQUIRED COMPONENTS(SEE APPLICATION DIAGRAM)
PGND1 45 – SM1 synchronous buck converter power Connect to power ground planegroundPGND2 52 – SM1 synchronous buck converter power Connect to power ground planegroundPGND3 38 – White LED driver power ground input Connect to a power ground planePWM 34 O PWM driver output, open-drain Can be used to drive a vibrator or other external functionsRED 55 O Programmable LED driver, open drain Connect to RED input of RGB LEDoutput, current sink output when active.RESPWRON 21 O System reset, open-drain output 100-k Ωexternal pullup resistor to OUT. RESPWRON pin is LOwhen TPS65820 is resetting the system.RTC_OUT 4 O Low-leakage LDO output. Can be 1- µF (minimum) capacitor to AGND1 pin or supercapconnected to a super-capacitor orsecondary cell, if used as a RTC backupoutput.SCLK 2 I I
2
C interface clock line 2-k Ωpullup resistor to OUT pinSDAT 3 I/O I
2
C interface data line 2-k Ωpullup resistor to OUT pinSIM 5 O General-purpose LDO output 1- µF (minimum) capacitor to AGND1 pinSM1 44 I SM1 synchronous buck converter output LC filter: 10- µF capacitor to PGND1 pinvoltage senseSM2 49 I SM2 synchronous buck converter output LC filter: 10- µF capacitor to PGND2 pinvoltage senseSM3 42 I White LED driver output overvoltage Connect 1- µF capacitor to PGND3 pin. Connect SM3 pin to thedetection positive side of white LED ladder.SM3SW 40 I Integrated white LED duty cycle switch Connect to negative side of external LED ladderinputSYS_IN 31 I System power bus low-voltage detection External resistive divider sets minimum system operationalvoltage. TPS65820 enters sleep mode when voltage belowminimum system voltage threshold is detected. 1-nF filtercapacitor to AGND1 recommended.TMR 13 I Charge safety timer program input External resistor from TMR pin to AGND1 pin sets the chargesafety timer time-out valueTRSTPWON 20 I System reset pulse duration setting 100-nF (minimum) capacitor to AGND1. External capacitorfrom TRSTPWON pin to AGND1 pin sets RESPWRON pulsewidth.TS 12 I/O Temperature sense input, current source Connect to battery pack thermistor to sense battery packoutput temperatureUSB 6 I USB charge input voltage, connect to 1- µF (minimum) capacitor to AGND1 pin, to minimizeUSB port positive power output overvoltage transients during USB power hot-plug events.VIN_LDO35 29 – Input to LDOs 3 to 5 1- µF (minimum) decoupling capacitor to AGND2VIN_LDO02 35 – Positive supply input for LDO0, LDO1, 1- µF (minimum) decoupling capacitor to AGND1LDO2VIN_SM1 47 – SM1 synchronous buck converter positive 10- µF capacitor to PGND1 pinsupply inputVIN_SM2 50 – SM2 synchronous buck converter positive 10- µF capacitor to PGND2 pinsupply inputExposed 57 – There is an internal electrical connection between the exposed thermal pad and AGNDn pins of the IC. Thethermal pad exposed thermal pad must be connected to the same potential as the AGND1 pin on the printed circuitboard. Do not use the thermal pad as the primary ground input for the IC. AGNDn pins must be connectedto a clean ground plane at all times.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS65820
APPLICATION DIAGRAM
SM1
AC
BAT
OUT
USB
TMR
DPPM
TS
HOT_RST
L1
SM2
L2
L3
SM3
SM3SW
BAT
OUT
7
Battery
PGND1
PGND2
PGND3
FB3
VIN_SM2
VIN_SM1
PWM
LED_PWM
RED
BLUE
GREEN
AGND1
VIN_LDO02
LDO1
LDO0
LDO2
TRSTPWON
SYS_IN
TPS65820
INT
SDAT
SCLK
RESPWRON
AGND2
EXTERNAL HOST
GPIO2
GPIO1
ANLG1
GPIO3
ANLG2
ADC_REF
VIN_LDO35
LDO35_REF
LDO4
LDO3
LDO5
1uF
2.2uF
A1
0.1uF
1nF
210K
100K
AC_DC
ADAPTER
OUTPUT
USB
POWER
GND
GND
+
-
2K
100K
100K
A2
A1
VLDO2
VLDO1
VLDO0
VLDO5
VLDO4 VLDO 3
P3
P2
VSM2
VSM1
P1
A1 GND
49.9K
37.4K
100pF
GND A1 A2 A3 P1 P2 P3
SIM
RTC_OUT
AGND0
A0
VRTC_OUT
ISET1 1K
Supercap
LDO_PM
VLDO_PM
VSIM
2K
37
32
35
10
4
5
6
50
45
44
46
47
14
13
12
18
17
11
9
8
48
33
39
40
52
49
51
2
16
31
20
15
25
26
27
28
30
29
42
21
19
3
56
55
36
34
41
38
53
43
1
24
23
54
22
A2
+
-
2.2uF
2.2uF
1uF
4.7uF
4.7uF
4.7uF
0.1uF
1uF
10uF
10uF
2.2uF
1uF
100pF
4.7uH
10uF
10uF
10uF
3.3uH
3.3uH
47nF
10uF
22uF
0.22uF
4.7uF
SYSTEM
POWER
BUS
ADC
EXTERNAL
ANALOG
INPUTS
I2C
CONFIGURABLE
GPIO’S
CLOCK
DATA
ALARM
RESET
10
NOTES:
1) RESISTORVALUESINOHMS
2) THEFOLLOWINGPARAMETERS AREPROGRAMMED :
- RTMR =49. 9K: 6 HOURCHARGESAFETY TIMER ,
30 MINPRE-CHARGESAFETY TIMER
- RSET =1K: 1A CHARGECURRENT (NOSCALING, INPUTLIMIT=2.5A),
100mA TERMINATION ANDPRE -CHARGECURRENTS
- RFB 3=10 OHMS: 25mA WHITELEDCURRENT
- CTRSTPWON =100nF : 100mSECRESETPULSEWIDTH
- RDPPM =37.4K: V(DPPM) =4.3V
3) THECAPACITORVALUESSHOWNINTHE APPLICATIONDIAGRAM
MAY BELARGERTHANTHEMINIMUMREQUIREDVALUESINDICATED
INTHEPINDESCRIPITONTABLE
4) THEVALUESSHOWNINTHE APPLICATIONDIAGRAMMATCHTHE
COMPONENTVALUESUSEDINTHEHPA 129 EVM, SEEDESIGNNOTES
SECTIONFORCOMPONENTSELECTIONDETAILS
VOUT
VOUT
VOUT
VOUT
VOUT
EXTERNAL
PERIPHERALS
VOUT
WHITELEDS
VOUT
VOUT
57
PWRGND
A1
RSET
RTMR
RDPPM
CTRSTPWON
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C28
1uF
C21 C22
C23
C24
C25
C26
R1
R2
R3
R4
R5
R6
RFB3
LSM1
LSM2
LSM3
C27
D1
RGBLED
P3
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Figure 3. TPS65820 Application Diagram, Recommended External Components
20 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS – POWER PATH MANAGEMENT
IBAT
VUSB
VOUT VBAT
USB=5V,
BAT =3.3V
IBAT
VAC
VOUT
VBAT
AC=5V,
BAT =3.3V
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Measured with Application Circuit shown in Figure 3 , unless otherwise noted
SWITCHING FROM AC TO BATTERY SWITCHING FROM USB TO BATTERYON AC REMOVAL ON AC REMOVAL
Figure 4. Figure 5.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
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TYPICAL CHARACTERISTICS – LINEAR REGULATORS 0, 1, 2
0
0.05
0.1
0.15
0.2
0.25
0 20 40 60 80 100 120 140
LineRegulation-%
VIN_LDO02=3.8Vto4.7V,
Load=10mA,
C (LDO02)=1 F
Om
T -JunctionTemperature-°C
J
VIN_LDO02=3.65V,
Load=10mA to150mA,
C (LDO02)=1 F
Om
-0.850
-0.800
-0.750
-0.700
-0.650
-0.600
-0.550
-0.500
0 20 40 60 80 100 120 140
T -JunctionTemperature-°C
J
LoadRegulation-%
VIN_LDO02=3.3V,
Load=150mA,C =1 F
O(LDO02) m
70
80
90
100
110
120
130
140
0 20 40 60 80 100 120 140
DropoutVoltage-mV
T -JunctionTemperature-°C
J
VIN_LDO02=3.65V,Load=10mA,
V =3.3V,
O(LDO 0) V =1.225V
O(LDO 1,2)
1
1.5
2
2.5
3
3.5
0 20 40 60 80 100 120 140
V-OutputVoltage-V
O
LDO0
LDO1 LDO2
T -JunctionTemperature-°C
J
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Measured with Application Circuit shown in Figure 3 , unless otherwise noted
LOAD REGULATION LINE REGULATIONvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 6. Figure 7.
OUTPUT VOLTAGE DROPOUT VOLTAGEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 8. Figure 9.
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TYPICAL CHARACTERISTICS – LINEAR REGULATORS 3, 4, 5
VIN_LDO35=3V,
Load=10mA to150mA,
C =1 F
O(LDO 35) m
-1
-0.95
-0.90
-0.85
-0.80
-0.75
-0.70
-0.65
-0.6
-0.55
-0.5
0 20 40 60 80 100 120 140
LoadRegulation-%
T -JunctionTemperature-°C
J
-0.018
-0.017
-0.016
-0.015
-0.014
-0.013
-0.012
-0.011
-0.010
0 20 40 60 80 100 120 140
LineRegulation-%
VIN_LDO35=3.3Vto4.7V,
Load=100mA,
C (LDO35)=1 F
Om
T -JunctionTemperature-°C
J
1.2285
1.229
1.2295
1.23
1.2305
1.231
1.2315
1.232
1.2325
020 40 60 80 100 120 140
VIN_LDO35=4.7V,
Load=10mA,
V (LDO35)=1.228V,
C (LDO35)=1 F
O
Om
T -JunctionTemperature-°C
J
V -OutputVoltage-V
O
90
100
110
120
130
140
0 20 40 60 80 100 120 140
Dropout-mV
VIN_LDO35=3.3V,
Load=150mA,
C (LDO35)=1 F
Om
T -JunctionTemperature-°C
J
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Measured with Application Circuit shown in Figure 3 , unless otherwise noted
LOAD REGULATION LINE REGULATIONvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 10. Figure 11.
OUTPUT VOLTAGE DROPOUT VOLTAGEvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 12. Figure 13.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
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TYPICAL CHARACTERISTICS – SM1 AND SM2 BUCK CONVERTERS
0
10
20
30
40
50
60
70
80
90
100
0 0.1 0.2 0.3 0.4 0.5 0.6
I -OutputCurrent- A
O
Efficiency-%
VIN_SM1=4V,
V (SM1)=1.24V,
L =3.3 H,
C (SM1)=10 F
O
O
m
m
76
78
80
82
84
86
88
90
92
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
I -OutputCurrent- A
O
Efficiency-%
VIN_SM2=4.6V,
VO(SM2)=1.8V,
L =3.3 H.
C (SM2)=10 F
Om
m
AC=5V,
VIN_SM2=4.6V,
V (SM2=1.8V
O
I (SM2)
L =3.3mF,
C (SM2)=10 F
O
Om
AC=5V,
VIN_SM2=4.6V,
V (SM2=1.8V
O
I (SM2)
L =3.3mF,
C (SM2)=10 F
O
Om
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
Measured with Application Circuit shown in Figure 3 , unless otherwise noted
PWM MODEEFFICIENCY IN AUTOMATIC EFFICIENCYPWM/PFM MODE vs OUTPUT CURRENT
Figure 14. Figure 15.
PFM OPERATION PFM LOW RIPPLE OPERATION
Figure 16. Figure 17.
24 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
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TYPICAL CHARACTERISTICS – DRIVERS
VIN_SM2
VO(SM2)
AC=5V,VIN_SM2=3V(DC)+1V(AC),
V (SM2)=1.8V,I (SM2)=100mA,
L =3.3 F,C (SM1)=10 F,
CH1=VIN_SM2,CH2=V (SM2)
O O
O
O
m m
VO_SM2
I (SM2)
O
AC=5V,
VIN_SM2=4V,
V (SM2)=1.8V,
I (SM2)=0mA to600mA,
L =3.3 F,C (SM1)=10 F,
CH1=VO_SM2,
CH3=I (SM2)
O
O
O
m m
O
SM2Voltage
SM2Current
AC=5V,
VIN_SM2/SM2=4V,
V (SM2)=1.8V,
I (SM2)=600mA,
L =3.3 F,
C (SM1)=10 F
O
O
O
m
m
SM1Voltage
SM1Current
AC=5V,
VIN_SM2/SM2=4V,
V (SM2)=1.8V,
I (SM2)=600mA,
L =3.3 F,
C (SM1)=10 F
O
O
O
m
m
BAT =4V,
DC=0%
L3=4.7 F,
C (SM3)=10 F,
CH1=L3,
CH4=SM3
m
m
O
BAT =4V,DC=0%
L3=4.7 F,C (SM3)=10 F,
CH1=L3,CH4=SM3
m m
O
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Measured with Application Circuit shown in Figure 3 , unless otherwise noted
LINE TRANSIENT LOAD TRANSIENT
Figure 18. Figure 19.
TRANSIENT - SM1 STARTUP TRANSIENT - SM2 STARTUP
Figure 20. Figure 21.
SM3 LED CURRENTSM3 WHITE LED DRIVER vsSOFT START PWM DUTY CYCLE
Figure 22. Figure 23.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
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SERIAL INTERFACE
Overview
Register Default Values
I
2
C Address
Incremental Read
I
2
C Bus Release
Sleep Mode Operation
I
2
C Bus Error Recovery
I
2
C Communication Protocol
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
The TPS65820 is compatible with a host-controlled environment, with internal parameters and status informationaccessible via an I
2
C interface. An I
2
C communication port provides a simple way for an I
2
C compatible host toaccess system status information and reset fault modes, functioning as a SLAVE port enabling I
2
C compatiblehosts to WRITE to or to READ from internal registers. The TPS65820 I
2
C port is a 2-wire bidirectional interfaceusing SCL (clock) and SDA (data) pins; the SDA pin is open drain and requires an external pullup. The I
2
C isdesigned to operate at SCL frequencies up to 400 kHz. The standard 8 bit command is supported, the CMD partof the sequence is the 8 bit register address to READ from or to WRITE to.
The internal TPS65820 registers are loaded during the initial power-up from an internal, non-volatile memorybank. The power-up default values are described in the sections detailing the registers functionality.
The register contents remain intact as long as OUT pin voltage remains above the internal UVLO threshold,V
UVLO
When the OUT pin voltage falls below the VUVLO threshold all register bits are reset to the internal powerup default.
The I
2
C specification contains several global addresses, which the slaves on the bus are required to respond to.The TPS65820 only responds (ACK) to addresses: 0x90 and 0x91 and does not respond (NACK) to any otheraddress.
Table 1. TPS65820 I
2
C Read/Write Address
BYTE BIT
MSB 6 5 4 3 2 1 LSB
TPS65820 I
2
C WRITE ADDRESS 1 0 0 1 0 0 0 0TPS65820 I
2
C READ ADDRESS 1 0 0 1 0 0 0 1I/O DATA BUS B7 B6 B5 B4 B3 B2 B1 B0
The TPS65820 does not support incremental read operations. Each register must be accessed in a single readoperation.
The TPS65820 I
2
C engine does not create START or STOP states on the I
2
C bus during normal operation.
When the sleep mode is set SDAT is held LO by the TPS65820. The overall system operation is not affected, asin sleep mode all TPS65820 integrated supplies are disabled and no power is available for any external devicesconnected to the TPS65820 SDAT pin. When sleep mode ends the SDAT pin is released before the TPS65820integrated regulated supplies are enabled. See section on System Sequencing and TPS65820 Operating Modesfor additional details on sleep mode operation.
The I
2
C bus specification does not define a method to be used when recovering from a host side bus error.During a read operation the SDA pin can be left in a LO state if the host has not sent enough SCL pulses tocomplete a transaction (i.e., host side bus error). The TPS65820 clears any SDA LO condition if 10 SCL pulsesare sent by the host, enabling recovery from host side bus error events.
The following conventions are used when describing the communication protocol:
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STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB BIT 6 BIT0
LSB ACKNOWLEDGE
(hA orbqA)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB BIT 6 BIT 0
LSB
NOT
ACKNOWLEDGE
(hNorbqN)
STOP
CONDITION
(P)
SCL
SDA
STOP
CONDITION
(P)
START
CONDITION
(S)
BIT 7
MSB BIT 6
SCL
SDA
DATA LINE
STABLE
DATA
CHANGE
ALLOWED
BIT 5-1
I
2
C Read and Write Operations
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Table 2. I
2
C Naming Conventions Used
CONDITION CODE
START sent from host SSTOP sent from host PTPS65820 I
2
C slave address sent from host, bus direction set from host to TPS65820 (WRITE) hA0TPS65820 register address sent from TPS65820, bus direction is from TPS65820 to host (READ) hA1Non-valid I
2
C slave address sent from host hA_NValid TPS65820 register address sent from host HCMDNon-valid TPS65820 register address sent from host HCMD_NI/O data byte (8 bits) sent from host to TPS65820 hDATAI/O data byte (8 bits) sent from TPS65820 to host bqDATAAcknowledge (ACK) from host hANot acknowledge (NACK) from host hNAcknowledge (ACK) from TPS65820 bqANot acknowledge (NACK) from TPS65820 bqN
Figure 24. I
2
C operation waveforms
For normal data transfers, SDA is allowed to change only when SCL is low, and one clock pulse is used per bitof data. The SDA line must remain stable whenever the SCL line is high, as SDA changes when SCL is high arereserved for indicating the start and stop conditions. Each data transfer is initiated with a start condition andterminated with a stop condition.
When addressed, the TPS65820 device generates an acknowledge bit after the reception of each byte by pullingthe SDA line Low. The master device (microprocessor) must generate an extra clock pulse that is associatedwith the acknowledge bit. After the acknowledge/not acknowledge bit the TPS65820 leaves the data line high,enabling a STOP condition generation.
The TPS65820 supports the standard I
2
C one-byte write. The basic I
2
C read protocol has the following steps:•Host sends a start and sets TPS65820 I
2
C slave address in write mode•TPS65820 ACKs that this is a valid I
2
C address and that the bus is configured for write•Host sends TPS65820 register address•TPS65820 ACKs that this is a valid register and stores the register address to be read•Host sends a repeated start and TPS65820 I
2
C slave address, reconfiguring the bus for read•TPS65820 ACKs that this is a valid address and that bus is reconfigured•Bus is in read mode, TPS65820 starts sending data from selected register
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SCLK ... ......
SDAT
Slave Address
hA0
Slave Address
hA1
Register
Address
hCMD
....
A6 R0R7R/WA0
000 0
Start
...
.. D0D7R/WA0A6
1Slave
Drives
theData
bqDATA
MasterDrives
ACKandStop
RepeatedStart, canbereplacedbya
STOP andSTART
..
SCLK ... ......
SDAT
Slave Address
hA0
HostSends
Data
hDATA
Register
Address
hCMD
.........
A6 R6 R5 R0 D7 D6 D5 D0R7R/WA0A4A5
0 0 0 0
PStart
bqA bqA bqA hA PS
bqA bqA bqA
ACK
ACK ACK
ACK
ACK
ACK ACK
Valid Write Sequences
One-Byte Write
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The I
2
C write protocol is similar to the read, without the need for a repeated start and bus being set in writemode. In a WRITE it is not necessary to end each 1 byte WRITE command with a STOP, a START has thesame effect (repeated start).
Figure 25. I
2
C read and write operations
The host can complete a READ or a WRITE sequence with either a STOP or a START.
The TPS65820 always ACKs its own address. If the CMD points to an allowable READ or WRITE address, thebq writes the address into its RAM address register and sends an ACK. If the CMD points to a non-allowedaddress, bq does NOT write the address into its RAM address register, and sends an NACK.
S hA0 bqAS hA0 bqA hCMD bqAS hA0 bqA hCMD_N bqN
The data is written to the addressed register when the bq ACK ending the one-byte write sequence is received.The host can cancel a WRITE by sending a STOP or START before the trailing edge of the bq ACK clock pulse.
S hA0 bqA hCMD bqA hDATA bqA
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Valid Read Sequences
Non-Valid Sequences
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The TPS65820 always ACKs its own address.
S hA1 bqA
Upon receiving hA1, TPS65820 starts at wherever the RAM address register is pointing. The START and theSTOP both act as priority interrupts. If the host has been interrupted and is not sure where it left off it can send aSTOP and reset the TPS65820 state machine to the WAIT state; once in WAIT state TPS65820 ignores allactivity on the SCL and SDA lines until it receives a START. A repeated START and START in the I
2
Cspecification are both treated as a START.
S hA0 bqA hCMD bqA PS hA0 bqA hCMD bqA S hA1 bqA bqDATA hN PS hA1 bqA bqDATA hN P
Incremental read sequences
S hA1 bqA bqDATA hA bqDATA hA bqDATA hA bqDATA hA ... bqDATA hA P
START and non-hA0 or non-hA1 Address
A START followed by an address which is not bqA0 or bqA1 is NACKED
S hA_N bqN
Attempt to Specify Non-Allowed READ Address
If the CMD points to a non-allowed READ address (reserved registers), bq sends a NACK back to the host and itdoes not load the address in the RAM address register. Note that TPS65820 NACKS whether a stop is sent ornot.
S hA0 bqA hCMD_N bqN PS hA0 bqA hCMD_N bqN
Attempt to Specify Non-Allowed WRITE Address
If the host attempts to WRITE to a READ-ONLY or non-accessible address TPS65820 ACKS the CMDcontaining the allowed READ address, loads the address into the address register and NACKS after the hostsends the next data byte. After issuing the NACK TPS65820 returns to WAIT state. A subsequent hA1 READcould read this address.
S hA0 bqA hCMD bqA hDATA bN
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TPS65820 INTERNAL REGISTER MAP
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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hex NAME DESCRIPTION ADDITIONAL
DETAILS
0 RESERVED_01 RESERVED FACTORY ONLY1 RESERVED_02 RESERVED FACTORY ONLY2 PGOOD Output voltage status for linear regulators and dc/dc buck converters3 INTMASK1 Interrupt request masking settings4 INTMASK2 Interrupt request masking settings5 INT_ACK1 Masked interrupt request register, latched6 INT_ACK2 Masked interrupt request register, latched7 PGOODFAULT_MASK System reset masking settings8 SOFT_RESET Generates a software reset9 CHG_CONFIG Battery charger configurationA CHG_STAT Battery charger statusB EN_LDO Linear regulator ON/OFF controlC LDO12 LDO1 and LDO2 output voltage settingD LDO3 LDO3 output voltage settingsE LDO4 LDO4 output voltage settingsF LDO5 LDO5 output voltage settings10 SM1_SET1 SM1 buck converter ON/OFF control and output voltage setting, normal mode11 SM1_SET2 SM1 buck converter configuration12 SM1_STANDBY SM1 buck converter standby mode ON/OFF and standby output voltage setting13 SM2_SET1 SM2 buck converter ON/OFF control and output voltage setting, normal mode14 SM2_SET2 SM2 buck converter configuration15 SM2_STANDBY SM2 buck converter standby mode ON/OFF and standby output voltage setting16 SM3_SET SM3 white LED driver ON/OFF control and settings17 RGB_FLASH Overall RGB driver timing settings18 RGB_RED RGB driver: RED duty cycle and output current setting19 RGB_GREEN RGB driver: GREEN duty cycle and output current setting1A RGB_BLUE RGB driver: BLUE duty cycle and output current setting1B GPIO12 GPIO1 and GPIO2 configuration1C GPIO3 GPIO2 and GPIO3 configuration, battery charge voltage selection1D PWM PWM output configuration1E ADC_SET ADC ON/OFF control, ADC configuration1F ADC reading_hi ADC data output20 ADC reading_lo ADC data output21 DHILIM1 ADC maximum threshold setting22 DHILIM2 ADC maximum threshold setting23 DLOLIM1 ADC minimum threshold setting24 DLOLIM2 ADC minimum threshold setting25 ADC_DELAY ADC configuration: conversion delay26 ADC_WAIT ADC configuration: wait and repeat operation27 LED_PWM LED_PWM configuration2E RESERVED_03 RESERVED FACTORY ONLY
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FUNCTIONALITY REFERENCE GUIDE – HOST INTERFACE AND SYSTEM SEQUENCING
INT
SCLK
TRSTPWON
SYS_IN
HOST INTERFACE
ANDSEQUENCING
OUT
A1
HOST
TPS65820
A1
A1
CTRSTPWON
210kW
R6
R1
100kW
C16
100nF
R4100kW
R32kW
R22kW
0.1 Fm
R5100kW
I2CENGINE
INTERRUPT
CONTROLLER
STATEMACHINE
ANDRESET
CONTROLLER
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
INTERRUPT CONTROLLER, OPEN-DRAIN OUTPUT (INT)
System Parameters Monitored by Interrupt Controller Power updefaultSupply Output System
Charger Status Input and OutputPower Good Fault Status ADC status
Transition Power TransitionDetection
(1)
Modification
Charge: Pre ↔FastSM1, ADC conversion endThermal fault or ↔Done AC detected: yes ↔noSM2, ADCGPIO1 ,2 DPPM:on ↔off USB detected: yes ↔noSM3, Input out of rangeconfigured as Charge suspend: on ↔Input OVP: yes ↔no
All interruptLDO1, LDO2, External resistiveexternal interrupt off System power: AC ↔
controllerLDO3, LDO4, load connected torequest Thermal foldback: on USB
inputs set toLDO5 ANLG1
↔off
non-maskedCan be masked Individually
Can be masked as a group via a single I
2
C maskvia I
2
C. Blanked during Can be masked individually via I
2
C
register bitinitial power up
(1) For all supplies (except) for SM3 an output fault is detected if the output voltage is below 90% of the programmed regulation voltage. Inthe SM3 converter an output fault indicates that the output OVP threshold was reached.
EVENTS TRIGGERING TPS65820 OPERATING MODE CHANGES
EVENT POWER GOOD FAULT THERMAL HARDWARE SOFTWAREDETECTION
(1)
FAULT RESET RESET
How transition is Integrated regulator output Internal IC junction Using HOT_RST control I
2
C register control bittriggered voltage below target value: temperature pinSM1, SM2, SM3, LDO1, LDO2,LDO3, LDO4, LDO5Operating mode Sets Sleep mode or starts a Sets sleep mode when Generates external host Generates external hostchange new power-up cycle when thermal fault is detected reset pulse at pin reset pulse at pinpower good fault is detected RESPWON when RESPWON when I
2
C(see state machine diagram). HOT_RST=LO. control bit is set.Power good fault detection Input and Battery power Pulse duration set by Pulse duration set bycomparators are blanked during cycling required to exit external capacitor. external capacitor.initial power-up. sleepControls Can be masked individually via Fixed internal threshold External input Set via I
2
CI
2
C.
(1) For all supplies (except) for SM3 an output fault is detected if the output voltage is below 90% of the programmed regulation voltage. Inthe SM3 converter an output fault indicates that the output OVP threshold was reached.
Figure 26. Required External Components, Recommended Values, External Connections
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INTERRUPT CONTROLLER AND SYSTEM SEQUENCING
Overview
INTERRUPT
CONTROLLER
INT
SDAT
SCLK
SEQUENCING
ANDOPERATING
MODESETTING
HOT _ RST
RESPWRON
TRSTPWON
SYS _IN
HOST INTERFACE ANDSEQUENCING
I2CENGINE I2CREGISTERS
NON-VOLATILE
MEMORY
CONTROL
LOGIC
1V
AC/USB/BAT
(HIGHERVOLTAGE)
VSYS
OUT
HOST
TPS65820
R 1 R 6
A1
C 16
R 5
R 3
R 2
R 4
CTRSTPWON
2.5V
2.5V
A1
AND
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The TPS65820 has two dedicated internal controllers that execute the host interface and system sequencingtasks: a sequencing controller and an interrupt controller.
The sequencing controller monitors internal and system parameters and defines the sequencing of the internalpower supplies during power up and power down / power fault events, and executes specific internal powersupply reset operations under external hardware control or host software commands.
The following parameters are monitored by the sequencing controller :•System power bus voltage (at SYS_IN pin), input supply voltage, battery pack voltage•TPS65820 thermal fault status•Integrated supply status
The interrupt controller monitors multiple system status parameters and signals to the host when one of themonitored parameters toggled, as a result of a system status change. The interrupt controller inputs include allthe parameters monitored by the sequencing controller plus:•Charger status•Battery pack status•ADC status
Internal I
2
C registers enable masking of all the monitored parameters. Using those registers the host can selectwhich parameters trigger an interrupt or a power good fault. Power good faults trigger a change in the TPS65820operating mode, as detailed in the next sections.
A simplified block diagram for the TPS65820 sections that interface to the external host is shown in Figure 27 .
Figure 27. Simplified Block Diagram
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SYSTEM SEQUENCING AND TPS65820 OPERATING MODES
LOADPOWERUP DEFAULTSIN
I2CREGISTERS
CONNECT AC , USBORBAT PIN TO
OUT PIN
DISABLEPOWERGOODFAULT
DETECTION
INT PIN = HIGHIMPEDANCE
POR_FLAG= HI
OFF
ANY
STATE
V(AC) > VUVLO
OR
V(USB) > VUVLO
OR
V(BAT) > VUVLO
V(OUT) < VUVLO
PGOODFAULT : A NON- MASKEDBIT OF THE
POWER _GOODI2CREGISTER TOGGLES
FROMLO TOHI
STANDBY ON : SM1 ANDSM2 SET INSTANDBY
MODEBY GPIOORI 2CCOMMAND
STANDBY OFF : SM1 ANDSM2 EXIT STANDBY
MODEBY GPIOOR
I2CCOMMAND
RESETTIMER : VALUESET BY CAPACITOR
CONNECTED TO TRSTPWONPIN
I2CSOFT_RESETBIT LOCATEDIN
SOFT_RESET REGISTER , BIT B0
POWERUP
SYS_IN INITIAL DEGLITCH
TIMER TINSYS EXPIRED
V < V
THERMAL FAULT
I2C SOFT_RESET REGISTER
BIT SLEEP_MODE = HI
(SELF - CLEARED)
AND
OR
OR
(SYS_IN) (LOW_SYS) FOR 5 msec
PGOOD
FAULT
POWER
CYCLE
AND
SLEEP NOT SET BY
THERMAL FAULT
PROCESSOR
STANDBY STATE
RESPWRON = HI
PGFORSM1&SM2
ismasked
ENABLESTATE
RESPWRON=LO,
RESET I2CENGINE
- UP TIMER
SEQUENCESTATE
START INTEGRATED
SUPPLY START - UP SEQUENCE
RESPWRON
= LO
POWERGOOD
CHECKSTATE
RESPWRON=HI
ENABLEPOWERGOODCOMPARATORS
INT PINMODESET BY INTERRUPT
CONTROLLER
=HI
RESETSTATE
RESPWRON=LO
START SYSTEMRESET PULSE TIMER
WHENHOT_RESET=HI
RESET
TIMEREXPIRES
V(SYS_IN) > AND
V(OUT) > V
NOPGOOD
FAULT STANDBY
ON
STANDBY
OFF
PGOOD
FAULT
RESPWRON=LO
V(HOT_RESET)=LO
OR
I2CSOFT_RESET
REGISTERBIT
SOFT_RST = HI
V(HOT_RESET)=HI OR
I2CSOFT_RESET
REGISTERBIT
SOFT_RESET = LO
(SELFCLEARED)
V(HOT_RESET)=LO
OR
I2CSOFT_RESET
REGISTERBIT
SOFT_RST= HI
UVLO
V(LOW_SYS)
POWERUP DEFAULTSLOADED
IN ALL I2CREGISTERS
(ExceptINT_ACKn)
POWERDOWNRAILS,
WAIT 5msec
START BOOT
SLEEP STATE
ONLY RTC_LDOISON
POWERPATH ACTIVE
RESPWRON = 0
REGISTERCONTENTSNOT RESET
INTERRUPT CLEARED
RESET I2CENGINE
ENABLEI2CENGINE
RESET I2CENGINE
RESET I2CENGINE
RESET I2CENGINE
NORMAL MODE
RESPWRON
HOTPLUGDEGLITCH
START SYS_IN
INITIAL DEGLITCH TIMER
TINSYS
TPS65820
www.ti.com
.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The TPS65820 has a state machine that controls the device power up and power down sequencing. The mainoperating modes are shown in the state diagram below:
Figure 28. TPS65820 State Diagram
POWER-UP – If the AC, USB and BAT pin voltages are below the internal UVLO threshold V
UVLO
(2.5 V typ) allIC blocks are disabled and the TPS65820 is not operational, with all functions OFF. When an external powersource or battery with voltage greater than the V
UVLO
voltage threshold is applied to AC/USB or BAT pins theinternal TPS65820 references are powered up, biasing internal circuits. When all the main internal supply railsare active the TPS65820 I
2
C registers are set to the power-up default values, shown in Table 3 :
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V(OUT) +V(LOW_SYS) ǒ1)R6
R1Ǔ:
where R6 and R1 are external resistors, V(LOW_SYS) +1 V typical
(1)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Table 3. Integrated Supply and Drivers Power-Up Defaults
SUPPLY POWER-UP DEFAULT OTHER BLOCKS POWER-UP DEFAULT
LDO0 OFF, 3.3 V POWER PATH INPUT TO SYSTEMLDO1 2.85V, ON PWM OFFLDO2 3.3 V, ON PWM_LED OFFLDO3 1.25 V, ON GPIO1 INPUTLDO4 2.75 V, ON GPIO2 INPUTLD05 2.81 V, ON GPIO3 INPUTSIM 1.8 V, OFF ADC OFFRTC_OUT ON, 3.1 V SM3 (WHITE LED) OFFLDO_PM 3.3 V, ON @ OUT POWERED RGB DRIVER OFFSM1 ON, 1.24 V INTERRUPT MASK NONE MASKEDSM2 ON, 1.8 V POWER GOOD MASK ALL MASKEDCHARGER ON
After the internal I
2
C register power-up defaults are loaded the power path control logic is enabled, connectingthe external power source to the OUT pin. A status flag (nRAMLOAD) is set to LO in the SOFT_RESET register,indicating that the I
2
C registers were loaded with the power-up defaults, and the TPS65820 enters the HOTPLUGmode.
HOTPLUG: In the HOTPLUG state an independent timer, TDGL(HOTPLUG) is started. The hotplug deglitchtimer, when active (not expired), prevents the TPS65820 from entering the SLEEP mode. This functionalityavoids potential system lockup conditions caused by contact bouncing events, when the TPS65820 is initiallypowered by a battery pack insertion. After the hotplug deglitch timer is started the TPS65820 enters the ENABLEmode.
ENABLE: In the ENABLE mode the R ESPWRON output is set to the LO level, the INT pin mode is set to highimpedance and all the power good comparators that monitor the integrated supply outputs are disabled. TheENABLE mode is used by the TPS65820 to detect when the main system power rail (OUT pin) is powered andready to be used on the internal supply power-up. The OUT pin voltage is sensed by an internal low systemvoltage comparator which holds the IC in the ENABLE mode until the system power bus voltage (OUT pin) hasreached a minimum operating voltage, defined by the user. The internal comparator senses the system voltageat pin SYS_IN, and the threshold for the minimum system operating voltage at the OUT pin is set by the externaldivider connected from OUT pin to SYS_IN pin. The threshold voltage is calculated as follows:
The minimum system operating voltage should always be set above the internal UVLO threshold V
UVLO
. Innormal application conditions the minimum system operating voltage is usually set to a value that assures thatthe TPS65820 integrated regulators are not operating in the dropout region.
When the voltage at the SYS_IN pin exceeds the internal threshold V
(LOW_SYS)
the TPS65820 is ready to start thesystem power sequencing, and the SEQUENCING mode is entered.
SEQUENCING – The sequencing state starts immediately after the enable state. In this mode of operation theintegrated supplies are turned ON, according to the sequencing steps loaded from the internal non-volatilememory during the power-up phase. The TPS65820 sequencing timing diagram shown in figure details theinternal timing delays and supply sequencing. At the end of the sequencing state the user-programmable resettimer is started, and the TPS65820 enters the reset state.
The startup sequence for the TPS65820 device is controlled by an internal (not user-programmable) EEPROMconfiguration byte location that is set at the time of manufacturing. A limited number of variations are possibleaccording to the configuration table below. The TPS65820 configuration is programmed as 0x02 (or bits 00000010). The corresponding startup sequence for the TPS65820 is illustrated in Table 4 ,Table 5 , and Figure 29 .For alternate startup sequences, a new configuration is required (contact TI factory).
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Table 4. Startup Sequence EEPROM Byte (Factory-Programmable Only)
Bit B7 B6 B5 B4 B3 B2 B1 B0Choose 1 of 4 initial delays; Choose 1 of 8 secondary delays; seeFunction Choose 1 of 8 sequences; see Table 5 .
see Table 5 .Table 5 .
Table 5. Startup Conditions
D1 D2B7 B6 B5 Startup Sequence
DelayB4 B3 Delay (ms) B2 B1 B0
(ms)
[LDO1, LDO4, LDO5] {D1} [SM1, LDO3] {D2} [SM2,0 0 0 0 0 0.24 0 0 0 4.8LDO2]
[SM1, LDO3] {D1}[LDO1, LDO4, LDO5] {D2} [SM2,0 0 1 0 1 0.48 0 0 1 9.6LDO2]0 1 0 All together 1 0 0.96 0 1 0 120 1 1 [SM1] {D1} [SM2] {D2} LDOs 1 1 1.2 0 1 1 19.21 0 0 [SM2] {D1} [SM1] {D2} [LDOs] 1 0 0 26.41 0 1 [LDOS] {D1} [SM1] {D2} [SM2] 1 0 1 62.41 1 0 [LDOS] {D1} [SM2] {D2} [SM1] 1 1 0 79.21 1 1 Disabled 1 1 1 100.8
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OUT
SM2
RESPWRON
INT
RESET DELAY
PROGRAMMEDBY EXTERNAL CAPACITOR
CONNECTED TOPIN TRSTPWON
Power Applied
SYS_IN
RTC_OUT
LDO2
LDO5
LDO3
VLOW_SYS
SEQUENCING RESET NORMAL
NOPOWER
LDO1
I CRegistersLoadedFrom
E PROM
2
2
ENABLE
HI-Z
AC,USB,ORBAT
VUVLO
VUVLO
HI-Z
HI-Z
tDLY(D2)
tDLY(D1)
LD04
SM1
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Figure 29. TPS65820 Supply Sequencing Timing
RESET – When the reset state starts the RESPWRON output is LO. The user can program the reset timer valueselecting the value of the external capacitor connected to pin TRSTPWON, as shown below:T
(RESET)
= K
RESET
×C
TRSTPWON
; where K
RESET
is the reset timer constant (1 ms/nF typ)
The TPS65820 RESPWRON pin should be used to reset the external host. During the external host reset( RESPWRON = LO) the I
2
C SDA and SCL pins are not used to access TPS65820 internal registers. If anon-standard configuration is used to reset the system the SDA and SCL lines should not be used tocommunicate with the TPS65820 until RESPWRON = HI. The TPS65820 I
2
C engine is kept in reset as long asRESPWRON = LO, avoiding false detection of start/stop conditions when the SDA and SCL pullup resistors areinitially powered.
The power good comparators are masked during the reset mode. The reset mode ends when the reset timerexpires, and the TPS65820 goes into the power good check mode.
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TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The RESPWRON signal set to a high level is the proper signal to use as an indicator that the device hastransitioned out of the reset state. During the power-up sequence the RESPWRON pin is asserted LOW until theRESET TIMER expires. The RESET TIME (t
reset
= 1ms/nF ×CTRSTPWON) can be programmed via a capacitorbetween the TRSTPWON pin and ground.
When the RESPWRON signal is LO, all internal and external interrupts are ignored. As a result, the open-drainoutput that asserts the INT pin LO during a NORMAL MODE interrupt request is disabled. The INT pin is thenasserted HI via a pullup resistor that is typically connected to VOUT. After the RESPWRON signal goes HI, theinterrupt controller is given control of the INT pin. Finally, the rising edge of the RESPWRON pin should be usedto indicate the PMIC has transitioned from the RESET STATE to the POWER GOOD CHECK STATE. At thatpoint, the interrupt controller asserts an interrupt if necessary.
POWER GOOD CHECK – In the power good check mode the power good comparators are enabled, providingstatus on the integrated supplies output voltages. An output voltage is considered as out of regulation andgenerates a fault condition if the output voltage is below 90% of the target output voltage regulation value. If apower good fault is detected the SLEEP mode is set, if a power good fault is not detected the NORMAL mode isset.
The individual supply power good status can be masked via an I
2
C register PGOODFAULT_MASK. Supplies thathave their power-good fault status masked do not generate a power good fault. However, the status bit for thesupply indicates that the output voltage is out of regulation.
The power good mask register bits default to masked upon power up.
NORMAL MODE – If a power good fault is not present at the end of the power good check mode the NORMALmode starts. In this mode of operation the I
2
C registers define the TPS65820 operation, and the host has fullcontrol on operation modes, parameter settings, etc. The normal state operation ends if a thermal fault, systemlow voltage fault ( V(SYS_IN) < V
LOW_SYS
) or power good fault is detected. A thermal fault or system low voltagefault sets the SLEEP mode operation, a power good fault sets the NO POWER operation mode. From the normalmode the converters SM1 and SM2 can be set in the STANDBY mode, with reduced output voltages. InNORMAL mode either an I
2
C register bit (SOFT_RESET register bit SOFT_RST) or a hardware input (HOT_RESET pin set to LO) can trigger a transition to the RESET state, enabling implementation of a host resetfunction. In NORMAL mode an I
2
C register bit (SOFT_RESET register bit SLEEP_MODE) can trigger a transitionto SLEEP mode.
SLEEP MODE – The SLEEP mode is set when a thermal fault or system low voltage fault is detected, underNORMAL operation mode set. This operation mode is also set when a power good fault is detected during thepower good check state or via the I
2
C bit SLEEP_MODE. In the SLEEP mode the RESPWRON output is set toLO, and the I
2
C registers keep the same contents as in the state preceding SLEEP mode, with the exception ofthe following control bits, which are reset to the default power-up values:
1. LDO1,2,3,4,5 and RTC_OUT are enabled, SIM LDO is disabled: EN_LDO register set to default values2. LDO0 disabled, all GPIOs with no control function assigned: GPIO12, GPIO3 registers set to default values3. White LED driver is set to OFF: SM3_SET register has all bits set to LO4. RGB drivers are set to OFF: RGB_FLASH, RGB_RED, RGB_GREEN, RGB_BLUE registers are set todefault values5. PWM, PWM_LED drivers OFF: PWM, LED_PWM registers are set to default values6. ADC engine reset to power up default: ADC_SET, ADC_DELAY, ADC_WAIT registers are set to defaultvalues
In SLEEP mode, the power path and main internal blocks are still active, but the internal integratedsupply sequencing is disabled. As a result of that, during SLEEP mode ALL integrated supplies (ALLLDO's, ALL Buck Converters) are disabled, with exception of the RTC_LDO. The RTC_LDO is ON duringsleep mode if the RTC_EN bit (register EN_LDO) is set to HI. The RTC_LDO is OFF during sleep mode ifthe RTC_EN bit (register EN_LDO) is set to LO.
At the end of the SLEEP mode, the sequencer block uses the I
2
C control register values (which were reset to thedefault power-up values) to sequence the integrated power supplies. The SLEEP mode ends when one of thethree following events happens:1. If SLEEP was set by thermal fault: The SLEEP mode ends only when all external input supplies and batterypack are removed and a UVLO condition is detected by the TPS65820, setting the NO POWER mode.
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TPS65820 OPERATING MODE CONTROLS
SEQUENCING AND OPERATING MODES – I
2
C REGISTERS
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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2. If SLEEP was set by a system low voltage detection, or I
2
C bit SLEEP_MODE, only with battery present:Input power must be connected, setting the TPS65820 in the ENABLE mode. If no input power is inserted,the battery discharges until the TPS65820 detects a UVLO condition and enters the NO POWER mode.3. If sleep was set by a system low voltage detection, power good fault or SLEEP_MODE, with battery andinput power present: all external input supplies connected to AC and USB pins must be removed, and then atleast one of them reconnected to the system. The input power cycling triggers a transition from SLEEP modeto the ENABLE mode.
PROCESSOR STANDBY STATE – This state is set using a I
2
C register or a GPIO configured as SM1/SM2standby control. In standby mode operation the SM1 and SM2 voltages are set to value distinct than the normalmode output voltage, and SM1/SM2 are set to PFM mode. The standby output voltage is defined in I
2
C registersSM1_STANDBY and SM2_STANDBY.
HARDWARE RESET: A dedicated control pin, HOT_RESET, enables implementation of a hardware resetfunction. The system reset pin RESPWRON is set to LO when HOT_RESET = LO for a period longer than theinternal deglitch (5 ms, typical). The RESET mode is started when the HOT_RESET pin transitions from LO toHI, as shown in the state diagram.
SOFTWARE RESET: The external host can set the TPS65820 in RESET mode using the I
2
C registerSOFT_RESET, bit B0 (SOFT_RST).
SOFTWARE SLEEP: The external host can set the TPS65820 in SLEEP mode using the I
2
C registerSOFT_RESET, bit B6 (SLEEP_MODE).
A hardware or software reset does not affect the contents of the I
2
C registers.
The I
2
C registers that control sequencing-related functions are shown below. The HEX address for each registeris shown by the register name, together with the R or W functionality for the register bits. Shaded values indicatedefault initial power-up values.SOFT_RESET, ADDRESS=08, ALL BITS R/W, BITS B7/B6/B1/B0 APPLY TO SEQUENCING.
B7 B6 B5 B4 B3 B2 B1 B0
Bit name STBY MODE SLEEP MODE NOT USED NOT USED SM3_LF_OSc NOT USED nRAMLOAD SOFT RST
Function SET SM1 AND SET TPS65820 NOT USED NOT USED NOT RELATED NOT USED RAM RESET SOFTWARESM2 IN IN SLEEP TO FLAG RESETSTANDBY MODE SEQUENCING, CONTROLMODE SEE SM3Control LogicWhen 0 NOT ACTIVE NOT ACTIVE NOT USED NOT USED NOT USED RAM NOT ACTIVEOverview
DEFAULTSSECTION
LOADED
When 1 When 1 SET SET SLEEP NOT USED NOT USED NOT USED RAM SET RESETSM1 AND SM2 MODE (reset to DEFAULTS MODE (reset toIN STANDBY LO internally) NOT LOADED LO internally)
Some host algorithms need to identify when the power-up defaults are loaded in the RAM, in order to startroutines that initialize specific RAM registers. If that functionality is required the nRAMLOAD bit should be set toHI by the host when entering hte NORMAL operation mode. The nRAMLOAD bit is reset to LO by the TPS65820when the power-up defaults are loaded in the I
2
C registers (V(OUT)<V
UVLO
OR PGOOD fault detected), enablingthe host algorithm to detect that the RAM registers need to be initialized.
The integrated supplies status is available in a dedicated register, shown below. The host can select whichintegrated supply outputs trigger a power good fault condition using the PGOODFAULT_MASK register.
When a non-masked power good status register bit toggles state, the sequence controller generates a transitionin the TPS65820 state machine, indicated as a PGOOD FAULT in TPS65820 state diagram.
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INTERRUPT CONTROLLER
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The power-good status register and mask register are shown below:SYSTEM STATUS MONITORED BY SEQUENCING CONTROLLER
B7 B6 B5 B4 B3 B2 B1 B0
PGOOD, ADDRESS=02, ALL BITS READ ONLY - POWER UP DEFAULTS SHOW SYSTEM STATUS WHEN EXITING POWER DOWN
Bit name PGOOD SM1 PGOOD SM2 PGOOD SM3 PGOOD LDO1 PGOOD LDO2 PGOOD LDO3 PGOOD LDO4 PGOOD LDO5
Function SM1 OUTPUT SM2 SM3 OVP LDO1 OUTPUT LDO2 OUTPUT LDO3 OUTPUT LDO4 OUTPUT LDO5 OUTPUTSTATUS OUTPUT STATUS STATUS STATUS STATUS STATUS STATUSSTATUS
When 0 OK OK OK OK OK OK OK OK
When 1 FAULT FAULT FAULT FAULT FAULT FAULT FAULT FAULT
PGOODFAULT_MASK, ADDRESS=07, ALL BITS R/W
Bit name MASK_PSM1 MASK_PSM2 MASK_PSM3 MASK_PLDO1 MASK_PLDO2 MASK_PLDO3 MASK_PLDO4 MASK_PLDO5
Function MASK PGOOD MASK MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOODFAULT BY SM1 PGOOD FAULT BY FAULT BY FAULT BY FAULT BY FAULT BY FAULT BYFAULT BY SM3 LDO1 LDO2 LDO3 LDO4 LDO5SM2
When 0 UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED
When 1 MASKED MASKED MASKED MASKED MASKED MASKED MASKED MASKED
The TPS65820 has internal block and overall system status information stored in I
2
C status registers. Thefollowing subsystems and system parameters are monitored :•External power supply status: AC or USB supply detected, AC or USB connected to system, AC/USB OVP•Charger status: on/off/suspend, fast charge/precharge, termination detected, DPPM on, thermal loop ON•Battery pack status: temperature, discharge on/off•TPS65820 Thermal shutdown•ADC status: conversion status, input out of range, ANLG1 high impedance detection•Integrated supplies status: output out of regulation (power good fault)
The GPIO1 and GPIO2 pins can be configured as inputs, generating an interrupt request to the host (INT:HI →LO) at the GPIO rising or falling edge. The host can use internal the INT_MASK I
2
C registers to definewhich of the monitored status variables trigger an interrupt. When a non-masked system status bit toggles state,the interrupt controller issues an interrupt, following the steps below:1. system status bits that caused the interruption are set to HI in registers INT_ACK1 and INT_ACK22. An interrupt is sent to the host ( INT:HI →LO)
Once an interrupt is sent to the host, INT is kept in the LO state and the INT_ACK registers contents are latched,holding the system status that generated the currently issued interrupt request. When an interrupt request isactive ( INT = LO) additional changes in non-masked status registers and control signals are ignored, and theINT_ACK registers are not updated.
The host must write a 0 to the INT_ACK register bit that generated the interrupt in order to set INT = HI andenable new updates to the INT_ACK registers. If the host stops in the middle of a WRITE or READ operation,the INT pin stays at the LO level. The TPS65820 has no reset timeout; it is assumed that the host does not leaveINT = LO and the status registers unread for a long time.
The non-masked I
2
C register bits and internal control signals generate a new interrupt only after INT is set to HI.The non-masked power good fault register bits generate a power good fault when any of the non-masked bitsdetects that the monitored output voltage is out of regulation, independently of the INT pin level.
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SYSTEM STATUS — I
2
C REGISTERS
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The I
2
C registers that have system status data are shown below. The HEX address for each register is shown bythe register name, together with the R or W functionality for the register bits. Those registers are valid, after aninitial power up, when the TPS65820 enters the normal operation mode.SYSTEM STATUS MONITORED BY INTERRUPT CONTROLLER
B7 B6 B5 B4 B3 B2 B1 B0
PGOOD, ADDRESS=02, ALL BITS READ ONLY - POWER UP DEFAULTS SHOW SYSTEM STATUS WHEN EXITING POWER DOWN
Bit name PGOOD SM1 PGOOD SM2 PGOOD SM3 PGOOD LDO1 PGOOD LDO2 PGOOD LDO3 PGOOD LDO4 PGOOD LDO5
Function SM1 OUTPUT SM2 OUTPUT SM3 OVP LDO1 OUTPUT LDO2 OUTPUT LDO3 OUTPUT LDO4 OUTPUT LDO5 OUTPUTSTATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS
When 0 OK OK OK OK OK OK OK OK
When 1 FAULT FAULT FAULT FAULT FAULT FAULT FAULT FAULT
ADC STATUS
REGISTER ADC_READING_HI, B7: CONVERSION COMPLETE ;INTERNAL STATUS BITS (NO I
2
C REGISTER BIT AVAILABLE: INPUT OUT OF RANGE (HI OR LO), ANLG1 PIN IMPEDANCE TO AGND2 EXCEEDS 1 m Ω.See additional details in the Analog-to-Digital Converter section.
OTHER SYSTEM STATUS: THERMAL FAULT DETECTED
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INTERRUPT CONTROLLER – I
2
C REGISTERS
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The I
2
C registers that control an interrupt generation (INT: HI →LO) are shown below. The HEX address for eachregister is shown by the register name, together with the R or W functionality for the register bits. Shaded valuesindicate default initial power-up values.INTERRUPT AND POWER GOOD FAULT MANAGEMENT REGISTERS
B7 B6 B5 B4 B3 B2 B1 B0
INTMASK1, ADDRESS=03, ALL BITS R/W
Bit name MASK_ISM1 MASK_ISM2 MASK_ISM3 MASK_ILDO1 MASK_ILDO2 MASK_ILDO3 MASK_ILDO4 MASK_ILDO5
Function MASK INT by MASK INT by MASK INT by MASK INT by MASK INT by Mask INT by MASK INT by MASK INT bySM1 PGOOD SM2 PGOOD SM3 PGOOD LDO1 PGOOD LDO2 PGOOD LDO3 PGOOD LDO4 PGOOD LDO5 PGOODFAULT FAULT FAULT FAULT FAULT FAULT FAULT FAULT
When 0 UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED
When 1 MASKED MASKED MASKED MASKED MASKED MASKED MASKED MASKED
INTMASK2, ADDRESS=04, ALL BITS R/W
Bit name MASK_IADC MASK_IANLG1 MASK_IGPIO2 MASK_IGPIO1 MASK_ITHSHU MASK_ICHGS MASK_IADC_H MASK_IADC_LT T I O
Function MASKS INT BY MASKS INT BY MASKS INT BY MASKS INT BY MASKS INT BY MASK INT BY MASK INT BY MASK INT BYADC END OF ANLG1 HIGH GPIO2 EDGE GPIO1 EDGE THERMAL CHG_STAT ADC INPUT ADC INPUTCONVERSION IMPEDANCE TRANSITION TRANSITION FAULT REGISTER ABOVE HI BELOW LOBITS LIMIT LIMIT
When 0 UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED
When 1 MASKED MASKED MASKED MASKED MASKED MASKED MASKED MASKED
INT_ACK1, ADDRESS=05, ALL BITS R/W
Bit name ACK_SM1 ACK_SM2 ACK_SM3 ACK_LDO1 ACK_LDO2 ACK_LDO3 ACK_LDO4 ACK_LDO5
Function SM1 INT SM2 INT SM3 INT LDO1 INT LDO2 INT LDO3 INT LDO4 INT LDO5 INTREQUEST REQUEST REQUEST REQUEST REQUEST REQUEST REQUEST REQUEST
When 0 CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG
When 1 SM1 PGOOD SM2 PGOOD SM3 OVP LDO1 PGOOD LDO2 PGOOD LDO3 PGOOD LDO4 PGOOD LDO5 PGOODFAULT FAULT FAULT FAULT FAULT FAULT FAULT FAULTGENERATED GENERATED GENERATED GENERATED GENERATED GENERATED GENERATED GENERATEDINT INT INT INT INT INT INT INT
INT_ACK2, ADDRESS=06, ALL BITS READ ONLY
Bit name ACK_ADC ACK_ANLG1 ACK_GPIO2 ACK_GPIO1 ACK_THSHUT ACK_CHGSTA ACK_ADC_HI ACK_ADC_LOT
Function ADC INT ANLG1 GPIO2 INT GPIO1 INT THERMAL CHARGER INT ADC INT ADC INTREQUEST 1 COMPARATO REQUEST REQUEST FAULT INT REQUEST REQUEST 2 REQUEST 3R INT REQUESTREQUEST
When 0 CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG CLEAR FLAG
When 1 ADC DONE ANLG1 HIGH GPIO2 EDGE GPIO1 EDGE THERMAL CHARGER ADC INPUT ADC INPUTGENERATED IMPEDANCE GENERATED GENERATED FAULT STATUS ABOVE HI BELOW LOINT REQUEST DETECTION INT REQUEST INT REQUEST GENERATED CHANGE LIMIT LIMITGENERATED INT REQUEST GENERATED GENERATED GENERATEDINT REQUEST INT REQUEST INT REQUEST INT REQUEST
PGOODFAULT_MASK, ADDRESS=07, ALL BITS R/W
Bit name PGOOD SM1 PGOOD SM2 PGOOD SM3 PGOOD LDO1 PGOOD LDO2 PGOOD LDO3 PGOOD LDO4 PGOOD LDO5
Function MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOOD MASK PGOODFAULT BY FAULT BY FAULT BY FAULT BY FAULT BY FAULT BY FAULT BY FAULT BYSM1 SM2 SM3 LDO1 LDO2 LDO3 LDO4 LDO5
When 0 UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED UNMASKED
When 1 MASKED MASKED MASKED MASKED MASKED MASKED MASKED MASKED
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FUNCTIONALITY GUIDE — SYSTEM POWER AND CHARGE MANAGEMENT
AC
BAT
OUT
USB
TMR
ISET
1
TS
BAT
OUT
DPPM
POWERPATH
CONTROL
LINEAR
CHARGER
Battery
GND
+
-
AC _DC Adapter
Output
USBPower
ACSWITCH
USBSWITCH BATTERY
SWITCH
SYSTEMPOWERBUS
TPS 65820
Withtheabovecomponentsthefollowingsystem
parametersareset :
FastChargeCurrent = 1A (100% scaling, inputlimit=2.5A)
Safety Timer = 5hours, 30 minpre-charge
DPPMthreshold = 4.3V
Temphot: 65C
TempCold : 5C
SystemPower
Selection
InputCurrentLimit
Selection
ChargeVoltage
FastCharge
CurrentScaling
ChargeSuspend
I2CREGISTERS
R
37.4k
DPPM
W
A1
C26
22 Fm
C25
10 Fm
50k
NTC
W
R
49.9k
TMR
W
C2
10 Fm
C23
47nF
A1
R
1k
SET
W
A1
C24
0.22 Fm
A1
C1
10 Fm
POWER PATH AND CHARGE MANAGEMENT
Overview
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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CHARGE MANAGEMENT
Fast Charge
(1)
Precharge Termination Charge Precharge SafetyTimer Power UpCurrent Voltage Voltage Timeout DefaultCharge Charge Current Current Current ScalingCurrent Value Scaling
I
O(BAT)
, 25%, 50%, 75%, 10% of I(TERM), 10% of 25%, 50%, 75%, 4.2 V or 3 V Programmable Charger ONProgrammable, 100% of I
O(BAT)
I
O(BAT)
I
O(BAT)
100% of I
(TERM)
4.36 V1.5A max value
Set via external Fixed ratio Fixed ratio Fixed Set via externalSet via I
2
C Set via I
2
C Set via I
2
Cresistor resistor
(1) The input current limit (see system power management below ) regulates the input current, effectively limiting the charge current if theinput current limit is lower than the fast charge current value programmed.
POWER PATH MANAGEMENT
INPUT CURRENT LIMIT INPUT CONNECTED TO OUT PIN POWER UP DEFAULT
AC PIN USB PIN INPUT POWER TO SYSTEM BATTERY TO SYSTEM
2.5 A typ 100 mA max or #1 – AC Battery connected to system, Input power to system,500 mA max or #2 – USB independently of battery USB mode selected,2.5 A typ #3 – Battery (when AC pin power and USB pin power are voltage 100 mA maxnot detected )
Internal fixed Automatic internal algorithmSet via I
2
C Set via I
2
C, overridescurrent limit
internal algorithm
Figure 30. Required External Components, Recommended Values, External Connections
The TPS65820 has an integrated charger with power path integrated MOSFETs. This topology, shown in thesimplified block diagram below, enables using an external input power to run the system and charge the batterysimultaneously. The power path has dual inputs that can be used to select either an external AC_DC adapter(AC pin) or an USB port power (USB pin) to power the end equipment main power rail (OUT pin, also referred toas the system power bus) and charge the battery pack (connected to BAT pin).
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BAT
BATTERY
STATUS
ISET1
CHARGE
CONTROL AND
POWERPATH
MANAGEMENT
VREF
I( )
I(OUT)/ K( SET)
TS
OUT
V(DPPM)
DPPM
V(SET)
V(ISET1)
V(PRECHG)
CHMODE
V(USB2)
INPUT_LIM
V(USB1)
V(ACOC)
V(OUT)
VO(REG)
V(OUT)
VO(REG)
TJ(REG)
TJ
V(BAT)
VO(REG)
BATTERY
STATUS
DETECTION
SYSTEM
STATUS
DETECTION
Dynamically
Controlled
Oscillator
TimerFault
VREF
USB
AC
SCALING
ATTENUATION
CONTROL SIGNALS
BATOFF
USBOFF
ACOFF
TMR
OUT
USB
AC
BAT
On, Reset
SystemPower
Selection
InputCurrentLimit
Selection
ChargeVoltage
FastCharge
CurrentScaling
ChargeSuspend
ChargerStatus
InputPowerStatus
ChargerControlLoops
Charge
Current
Loop
DPPM
Loop Thermal
Loop
ChargeVoltage
Loop
USBControlLoops
USBInputCurrent
LimitLoop
ACInputCurrent
LimitLoop
SystemVoltage
RegulationLoop
SystemVoltage
RegulationLoop
ACControlLoops
ACSWITCH
BATTERY
SWITCH
USBSWITCH
I2C
REGISTERS TPS65820
I(AC)/ KINTAC
I(USB)/ KINTUSB
I(AC)
I(USB)
CE
LATCH
CHG_ UVLO
CE
500Ω
500
OUTSHORT
OUTSHORT
BATSHORT
VREF
ISET1
SYSTEM
STATUS
BAT
DISCHARGE
CIRCUIT
1kΩ
BAT
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Figure 31. TPS65820 Charger and Power Path Section Simplified Block Diagram
The power path has three integrated power MOSFETs: the battery to system MOSFET (battery switch), the ACinput to system MOSFET (AC switch) and the USB input to system MOSFET (USB switch). Each of those powerMOSFETs can be operated either as an ON/OFF switch or as a linear pass element under distinct operatingconditions, as defined by the control circuits that set the power MOSFET gate voltage.
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POWER PATH MANAGEMENT FUNCTION
Detecting the System Status
POWERPATH
CONTROL LOGIC
ACDETECTED
USBDETECTED
USBOVP
ACOVP
OUT SHORTED
BAT
SHORTED
OUT LOWER
THANBAT
VBATSH
AC
USB
OUT
BAT
VOVP
VOVP
BAT
VOUTSH
BAT
OUT
BAT
NOBATT
SHORT
DPPM
1V
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The TPS65820 regulates the voltage at the OUT pin to 4.6 V, when one of the external supplies connected topins AC or USB is powering the OUT pin. The selected input (AC or USB pin) current is limited to a value definedby I
2
C register settings. The input current limit function assures compatibility with USB standard requirements,and also implements a protection function by limiting the maximum current supplied by an external AC_DCadapter or USB port power terminal.
The AC power MOSFET and USB power MOSFET operating modes are set by integrated control loops. Each ofthe power MOSFETs is controlled by two loops: one system voltage regulation loop and one input current limitingloop. The integrated loops modulate the AC or USB power MOSFETs drain to source resistance to regulateeither the OUT pin voltage or to limit the input current. If no input power is present (AC and USB input power notdetected) the AC and USB power MOSFETs are turned OFF, and the battery MOSFET is turned ON, connectingthe BAT pin to the OUT pin.
The battery switch is turned ON when the AC or USB input power is detected and the charger function isenabled, charging the battery pack. During charge the battery MOSFET switch operation mode is defined by thecharger control loops. The battery MOSFET switch drain-to-source resistance is modulated by the charge currentloop and charge voltage loop in order to implement the battery charging algorithm. In addition ot that multiplesafety functions are activated (thermal shutdown, safety timers, short-circuit recovery), and additional functions(thermal loop and DPPM loop) optimize the charging process.
The power path and charge management block operate independently of the other TPS65820 circuits. Internalcircuits check battery parameters (pack temperature, battery voltage, charge current) and system parameters(AC and USB voltage, battery voltage detection), setting the power path MOSFETs operating modesautomatically. The TPS65820 has integrated comparators that monitor the battery voltage, AC pin voltage, USBpin voltage and the OUT pin voltage. The data generated by those comparators is used by the power pathcontrol logic to define which of the integrated power path switches is active. A simplified block diagram for thesystem status detection is shown below.
Figure 32. TPS65820 Systems Status Detection, Charger and Power Path Section
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Power Path Logic: Priority Algorithm
Input Current Limit
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Table 6 lists the system power detection conditions. V
IN(DT)
, V
OUTSH
, V
BATSH
, V
OVP
are TPS65820 internalreferences, refer to the electrical characteristics for additional details.
Table 6. System Status Detection, Charger and Power Path Section
AC input voltage detected V
(AC)
– V
(BAT)
> V
IN(DT)
USB input voltage detected V
(USB)
– V
(BAT)
> V
IN(DT)
AC overvoltage detected V
(AC)
> V
OVP
USB overvoltage detected V
(USB)
> V
OVP
AC PIN TO OUT pin OR USB TO OUT PIN short detected V
(OUT)
< V
INOUTSH
BAT pin to OUT pin short detected V
(BAT)
– V
(OUT)
> V
BATOUTSH
Battery supplement mode need detected V
(BAT)
– V
(OUT)
> V
SUP
Blank BAT to OUT short-circuit detection V
(DPPM)
< 1V
The system power bus supply is automatically selected by the power path control logic, following an internalalgorithm. The power path function detects an external input power connection when the input voltage exceedsthe battery pack voltage. It also detects a supplement mode need (battery switch must be turned ON) when thesystem voltage (OUT pin) is below the battery voltage. A connected and non-selected external supply or thebattery is automatically switched to the system bus, following the priority algorithm, when the external supplycurrently selected is disconnected from the system.
The input power priority is hard-wired internally, with the AC input having the higher priority, followed by the USBinput (2
nd
) and the battery pack (3
rd
). Using the I
2
C CHG_CONFIG register control bit CE the user can overridethe power path algorithm, connecting the battery to the system power bus. Care must be taken when using thebattery to system connection option, as the system power bus is not connected back to the AC or USB inputs(even if those are detected) when the battery is removed. Table 7 describes the priority algorithm.
Table 7. Power Path Control Logic Priority Algorithm
EXTERNAL SUPPLY
SWITCH MODECE BIT SYSTEM POWERDETECTED(I
2
C CHG_CONFIG Register) SOURCEAC USB AC USB Battery
YES NO ON OFF ACNO YES OFF ON USBON if supplement mode isHI
required, OFF otherwiseYES YES ON OFF ACNO NO OFF OFF BATTERYLO XX XX OFF OFF ON BATTERY
The power path status is stored in register CHG_STAT.
The USB input current is limited to the maximum value programmed by the host, using the I
2
C interface. If thesystem current requirements exceed the input current limit, the output voltage collapses, the charge current isreduced, and finally, the supplement mode is set. The input current limit value is set with the I
2
C charge controlregister bits PSEL and ISET2, and it is applied to the USB input ONLY. The AC input current limit is fixed to theinternal short-circuit limit value.
Table 8. Charge Current Scaling via I
2
C
INPUT CURRENT LIMITPSEL (I
2
C) ISET2 (I
2
C)
USB AC
LO LO 100 mA 2.75 ALO HI 500 mA 2.75 AHI LO 2.75 A 2.75 AHI HI 2.75 A 2.75 A
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System Voltage Regulation
Input Overvoltage Detection
Output Short-Circuit Detection
Battery Short-Circuit Detection
Boot-Up Algorithm
No-Battery Detection Circuit
BAT
OUT
V -V
(OUT) (NOBATID)
+
_
ANLG1
Battery
I C
2
TPS65820
PACKID
Resistor
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The system voltage is regulated to a fixed voltage when one of the input power supplies is connected to thesystem. The system voltage regulation is implemented by a control loop that modulates the selected switchRds(on).
The typical system regulation voltage is 4.6 V.
The AC and USB input voltages are monitored by voltage comparators that identify an overvoltage condition. Ifan overvoltage condition is detected a status register bit is set, indicating a potential fault condition.
When an overvoltage condition is detected the AC or USB switches state is not modified. If any of those switcheswas ON, it is kept in the ON state. During overvoltage conditions the system voltage is still regulated, and nomajor safety issues are observed when not modifying the input switch state.
If the input overvoltage condition results in excessive power dissipation, the thermal shutdown circuit is activated,the AC and USB switches are turned OFF and the BAT switch is turned ON.
If the OUT pin voltage falls below an internal threshold V
INOUTSH
the AC and USB switches are turned off andinternal pullup resistors are connected from AC pin to OUT pin and USB pin to OUT pin. When the short circuit isremoved those resistors enable the OUT pin voltage to rise above the V
INOUTSH
threshold, returning the system tonormal operation.
If the OUT pin voltage falls below the BAT pin voltage by more than an internal threshold V
BATOUTSH
the batteryswitch is turned off and internal pullup resistor is connected between the OUT pin and the BAT pin. This resistorenables detection of the short removal, returning the system to normal operation.
During the initial TPS65820 power-up the contents of the ISET2, CE and SUSPEND bits on the control registerare ignored for a time period t
BOOT
. During that time the charger is enabled, and the selected input current limit isset internally to 100 mA max. At the end of t
BOOT
period the control register settings are implemented.
The ANLG1 pin may be used to detect the connection of an external resistor that is embedded in a battery packand is used as a pack ID function. The ANLG1 pin has an internal current source connected between OUT andANLG1, which is automatically enabled when the TPS65820 is not in SLEEP mode. The current levels forANLG1 pin can be programmed via I
2
C register ADC_WAIT, bits BATID_n, as shown below:
Figure 33. Battery Removal Detection, ANLG1 Pin
46 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
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Using the Input Power to Run the System and Charge the Battery Pack
BATTERY CHARGE MANAGEMENT FUNCTION
Operating Modes
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
An internal comparator with a fixed deglitch time, t
DGL(NOBAT)
monitors the ANLG1 pin voltage, if V(ANLG1) >V(OUT) – V
NOBATID
a battery removed condition is detected and an internal discharge switch is activated,connecting an internal resistor from BAT pin to AGND1. Note that ANLG1 can also be used as an analog inputfor the ADC converter, in this case the voltage at pin ANLG1 must never exceed the V(OUT) - V
NOBATID
thresholdto avoid undesired battery discharge.
The external supply connected to AC or USB pins must be capable of supplying the system power and thecharger current. If the external supply power is not sufficient to run the system and charge the battery pack theTPS65820 executes a two-stage algorithm that prevents a low voltage condition at the system power bus:1. The charge current is reduced, until the total (charger + system current) is at a level that can be supplied bythe external input supply. This function is implemented by a dedicated charger control loop (see DPPMsection in charger functional description for additional details).2. The battery switch is turned ON if the charge current is reduced to zero and the input current is not enoughto run the system. In this mode of operation both the battery and the external input power supply the systempower ( supplement operation mode).
The supplement operation mode is automatically set by the TPS65820 when the input power is switched to theOUT pin, and the OUT pin voltage falls below the battery voltage.
The TPS65820 supports charging of single-cell Li-Ion or Li-Pol battery packs. The charge process is executed inthree phases: precharge (or preconditioning), constant current and constant voltage.
The charge parameters are selectable via I
2
C interface and using external components. The charge processstarts when external input power is connected to the system, the charger is enabled by the I
2
C registerCHG_CONFIG bits CE=HI and CHGON=HI, and the battery voltage is below the recharge threshold, V(BAT) <V
(RCH)
. When the charge cycle starts a safety timer is activated. The safety timer timeout value is set by anexternal resistor connected to TMR pin.
When the charger is enabled two control loops modulate the battery switch drain to source impedance to limit theBAT pin current to the programmed charge current value (charge current loop) or to regulate the BAT pin voltageto the programmed charge voltage value (charge voltage loop). If V(BAT) < 3 V (typ) the BAT pin current isinternally set to 10% of the programmed charge current value. A typical charge profile is shown below, for anoperation condition that does not cause the IC junction temperature to exceed 125 °C (typ).
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 47
Product Folder Link(s): TPS65820
Batteryvoltage,
V(BAT)
Charge
Complete
Status,
Charger
Off
Pre-
conditioning
Phase
Current
Regulation
Phase
VoltageRegulationand
ChargeTermination
Phase
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
BatteryCurrent,
I(BAT)
VO(BATREG)
V(LOWV)
T(PRECHG) T(CHG)
FAST-CHARGE
CURRENT
IO(BAT)
IO(PRECHG) , I(TERM)
DONE
DONE
BAT
ISET 1
I /K
(OUT) (SET)
OUT
ChargeVoltage
Loop
Battery
Switch
SystemVoltage
RegulationLoop
VREF
Thermal
Loop
VTJ
V(OUT)
I(BAT)
V(BAT)
VO(REG)
VO(REG)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Figure 34. Typical Charge Cycle, Thermal Loop not Active
If the operating conditions cause the IC junction temperature to exceed 125 °C the charge cycle is modified, withthe activation of the integrated thermal control loop. The thermal control loop is activated when an internalvoltage reference, which is inversely proportional to the IC junction temperature, is lower than a fixed,temperature-stable internal voltage. The thermal loop overrides the other charger control loops and reduces thecharge current until the IC junction temperature returns to 125 °C, effectively regulating the IC junctiontemperature.
Figure 35. Voltage and Thermal Regulation Loops
48 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65820
Battery
Voltage,
V(BAT)
Charge
Complete
Status,
Charger
Off
Pre-
conditioning
Phase
Current
Regulation
Phase
VoltageRegulationand
ChargeTermination
Phase
PRE-CHARGE
CURRENT AND
TERMINATION
THRESHOLD
BatteryCurrent,
I(BAT)
VO(BATREG)
V(LOWV)
T(PRECHG) T(CHG)
FAST-CHARGE
CURRENT
IO(BAT)
IO(PRECHG) , I(TERM)
DONE
DONE
Thermal
Regulation
Phase
ICJunction
Temperature, Tj
T(THREG)
Battery Preconditioning
IO(PRECHG) +VPRECHG KSET
RSET
(2)
CONSTANT-CURRENT CHARGING
IO(BAT) +VSET KSET
RSET
(3)
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
A modified charge cycle, with the thermal loop active, is shown here:
Figure 36. Typical Charge Cycle, Thermal Loop Active
The TPS65820 applies a precharge current I
o(PRECHG)
to the battery if the battery voltage is below the V
(LOWV)threshold, preconditioning deeply discharged cells. The charge current loop regulates the ISET1 pin voltage to aninternal reference value, V
PRECHG
. The resistor connected between the ISET1 and AGND pins, R
SET
, determinesthe precharge rate.
The precharge rate programmed by R
SET
is always applied to a deeply discharged battery pack, independently ofthe input power selection (AC or USB). The precharge current can be calculated as follows:
where:
K
SET
is the charge current scaling factor and V
PRECHG
is the precharge set voltage.
The constant charge current mode (fast charge) is set when the battery voltage is higher than the prechargevoltage threshold. The charge current loop regulates the ISET1 pin voltage to an internal reference value, V
SET
.The fast charge current regulation point is defined by the external resistor connected to the ISET1 pin, R
SET
, asshown in the following:
where:
V
SET
(2.5 V typ) is the voltage at ISET1 pin during charge current regulation and K
SET
= Charge CurrentScaling Factor.
The reference voltage V
SET
can be reduced via I
2
C register CHG_CONFIG bits ISET1_1 and ISET1_0. V
SET
canbe selected as a percentage (75%, 50% or 25%) of the original 2.5 V typ, non-attenuated V
SET
value, effectivelyscaling down the charge current.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 49
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2.75 A
500 mA
200 mA
750 mA
800 mA
300 mA
-250 mA
SYSTEMLOAD
INPUT
CURRENT
BATTERY
CHARGE
CURRENT
BATTERY
CHARGING,
USBINPUT LIMIT
SET TO 2.75 A
BATTERY
CHARGING,
INPUT LIMIT SET
TO 500 mA
BATTERY
DISCHARGING,
SUPPLEMENT
MODESET
(800mA DEFINED
BY RSET VALUE)
I(USB)
I(OUT )
CHARGE TERMINATION AND RECHARGE
ITERM +VTERM KSET
RSET
(4)
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The ISET1 resistor always sets the maximum charge current, if the AC input is selected. When the USB input isselected, the maximum charge current is defined by the USB input current limit and the programmed chargecurrent. If the USB input current limit is lower than the I
O(OUT)
value, the battery switch is set in the dropout regionand the charge current is defined by the input current limit value and system load, as shown in the followingcurves:
Figure 37. Input Current Limit Impact on Effective Charge Current
The TPS65820 monitors the charging current during the voltage regulation phase. Charge is terminated whenthe charge current is lower than an internal threshold, set to 10% (typ) of the fast charge current rate. Thetermination point applies to both AC and USB charging, and it can be calculated as follows:
where
V
TERM
is the termination detection voltage reference.
The voltage at ISET1 pin is monitored to detect termination, and termination is detected when V(SET1) < V
TERM(0.25 V typ). The voltage reference V
TERM
is internally set to 10% of the V
SET
reference voltage, and it is modifiedif the reference voltage V
SET
is scaled via I
2
C register CHG_CONFIG bits ISET1_1 and ISET1_0. V
TERM
isreduced by the same percentage used to scale down V
SET
.
The table below shows charge current and termination thresholds for a 1-A charge current set (1-k Ωresistorconnected to ISET1 pin), with the selected input current limit set to a value higher than the programmed chargecurrent. The termination current is scaled for all charge current modes (AC or USB), as it is always set by theISET1 pin external resistor value.
Table 9. Charge Current and Termination Threshold Selection Example
Charge Control Register Bits Charge Current, (% of typical value Vset Vterm Charge Terminationprogrammed by ISET1 resistor) (V) (mV) Current (A) Current (mA)ISET1_1 ISET1_0
0 0 25% 0.6 60 0.24 200 1 50% 1.25 115 0.5 401 0 75% 1.9 160 0.78 601 1 100% 2.5 250 1 100
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BATTERY VOLTAGE REGULATION, CHARGE VOLTAGE
TEMPERATURE QUALIFICATION
DYNAMIC POWER PATH MANAGEMENT
VDPPM +RDPPM KDPPM IDPPM
(5)
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Once termination is detected, a new charge cycle starts if the voltage on the BAT pin falls below the V
(RCH)threshold. A new charge start is also triggered if the charger is enabled/disabled/enabled via I
2
C (CHG_CONFIGregister bits CE or CHGON), or if both AC and USB input power are removed and then at least one of them isre-inserted.
The termination is disabled when the thermal loop OR DPPM loop are active, and during supplement mode. Thecharge termination is also disabled when the I
2
C control bit TERM_OFF is set to HI, in the CHG_CONFIGregister. A new charge cycle is started if the control bit TERM_OFF is set to HI after termination was detected.
The voltage regulation feedback is Implemented by sensing the BAT pin voltage, which is connected to thepositive side of the battery pack. The TPS65820 monitors the battery-pack voltage between the BAT and AGND1pins, when the battery voltage rises to the V
O(REG)
threshold the voltage regulation phase begins and thecharging current tapers down.
The charging voltage can be selected as 4.2 V or 4.365 V (typ). The default power-up voltage is 4.2 V. As asafety measure the 4.365 V charge voltage is programmed only if two distinct bits are set via I
2
C: VCHG=HI inthe CHG_CONFIG, and CHG_VLTG=LO in the GPIO3 register.
The TPS65820 continuously monitors battery temperature by measuring the voltage between the TS and AGND1pins. An internal current source provides the bias for a negative-temperature coefficient thermistor (NTC), andthe TS pin voltage is compared to the window set by internal thresholds V
LTF
and V
HTF
to determine if charging isallowed. A voltage outside the V
LTF
to V
HTF
window is considered a temperature fault, and charge is suspended.Charge resumes when the temperature returns to the valid window range.
With a 50-k Ω(at 25 °C) thermistor, the valid temperature window is set between 0 °C to 45 °C. The temperaturewindow can be enlarged by adding external resistors to the TS pin application circuit.
For the TPS65820 device, the charger output is disabled whenever the TS pin is not in the valid range, whetheror not the presence of a battery is detected.
Under normal operating conditions, the OUT pin voltage is regulated when the AC or USB pin is powering theOUT pin and the battery pack is being charged. If the total (system + charge current) exceeds the available inputcurrent, the system voltage drops below the regulation value.
The dynamic power path management function monitors the system output voltage. A condition where theexternal input supply rating has been exceeded or the input current limit has been reached is detected when theOUT pin voltage drops below an user-defined threshold, V
DPPM
:
where:
R
DPPM
= external resistor connected to DPPM pinK
DPPM
= DPPM scaling factorI
DPPM
= DPPM pin internal current source
To correct this situation the DPPM loop reduces the charge current, regulating the OUT pin voltage to theuser-defined V
DPPM
threshold. The DPPM loop effectively identifies the maximum current that can be delivered bythe selected input and dynamically adjusts the charge current to specify that the end equipment is alwayspowered. In order to minimize OUT voltage ripple during DPPM operation, the V
DPPM
threshold should be set justbelow the system regulation voltage.
If the charge current is reduced to zero by the DPPM and the input current is still lower than the OUT pin load,the output voltage falls below the DPPM threshold, decreasing until the battery supplement mode is set [V
(OUT)
=V
(BAT)
– V
SUP(DT)
].
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CHARGER OFF MODE
PRECHARGE SAFETY TIMER
CHARGE SAFETY TIMER
TIMER FAULT RECOVERY
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The TPS65820 charger circuitry enters the low-power OFF mode if both AC and USB power are not detected.This feature prevents draining the battery during the absence of input supply.
The TPS65820 activates an internal safety timer during the battery pre-conditioning phase. The precharge safetytimer time-out value is set by the external resistor connected to TMR pin, RTMR, and the timeout constants K
PREand K
TMR
:t
PRECHG
= K
PRE
×R
TMR
×K
TMR
The K
PRE
constant typical value is 0.1, setting the precharge timer value to 10% of the charge safety timer value.
When the charger is in suspend mode, set via I
2
C register CHG_CONFIG bit CHGON or set by a packtemperature fault, the precharge safety timer is put on hold (i.e., charge safety timer is not reset). Normaloperation resumes when the charger exits the suspend mode. If V(BAT) does not reach the internal voltagethreshold V
PRECHG
within the precharge timer period a fault condition is detected and the charger is turned off.
If the TMR pin is left floating and internal resistor, 50 k Ωtyp, is used to generate the timebase used to set theprecharge timeout value. The typical precharge timeout value can be then calculated as :
T
PRECHG
= K
PRE
×50K ×K
TMR
As a safety mechanism the TPS65820 has a user-programmable timer that measures the total fast charge time.This timer (charge safety timer) is started at the end of the pre-conditioning period. The safety charge timeoutvalue is set by the value of an external resistor connected to the TMR pin (R
TMR
). The charge safety timertime-out value is calculated as follows:t
CHG
= K
TMR
×R
TMR
When the charger is in suspend mode, set via I
2
C register CHG_CONFIG bit CHGON or set by a packtemperature fault, the charge safety timer is put on hold (i.e., charge safety timer is not reset). Normal operationresumes when the charger exits the suspend mode. If charge termination is not reached within the timer period afault condition is detected, and the charger is turned off.
The charge safety timer is held in reset if the TMR pin is left floating or if the control bit TERM_OFF,in theCHG_EN I
2
C register, is set to HI. Under this mode of operation an internal resistor, 50 k Ωtyp, sets the internalcharger and power path deglitch and delay times, as well as the precharge safety timer timeout value.
The TPS65820 provides a recovery method to deal with timer fault conditions. The following summarizes thismethod:
•Condition 1: Charge voltage above recharge threshold, V
RCH
, and timeout fault occurs.
Recovery method: The IC waits for the battery voltage to fall below the recharge threshold. This could happenas a result of a load on the battery, self-discharge or battery removal. Once the battery falls below the rechargethreshold, the IC clears the fault and starts a new charge cycle.•Condition 2: Charge voltage below recharge threshold, V
(RCH)
, and timeout fault occurs.
Recovery method: Under this scenario, the IC connects an internal pullup resistor from OUT pin to Bat pin. Thispullup resistor is used to detect a battery removal condition and remains on as long as the battery voltage staysbelow the recharge threshold. If the battery voltage goes above the recharge threshold, the IC disables thepullup resistor connection and executes the recovery method described for condition 1.
All timers are reset and all timer fault conditions are cleared when a new charge cycle is started either via I
2
C(toggling CHG_CONFIG bits CE, CHGON) or by cycling the input power. All timers are reset and all timer faultconditions are cleared when the TPS65820 enters the UVLO mode.
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Product Folder Link(s): TPS65820
DYNAMIC TIMER FUNCTION
1 2
1
2
TIMERINTERNAL CLOCKPERIOD
MULTIPLICATIONFACTOR
V(SET1)V(ISET1)
V(SET)V(PRECHG)
,
CHARGE AND SYSTEM POWER MANAGEMENT — I
2
C REGISTERS
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The charge and precharge safety timers are programmed by the user to detect a fault condition if the chargecycle duration exceeds the total time expected under normal conditions. The expected total charge time isusually calculated based on the fast charge current rate.
When the thermal loop or the DPPM loops are activated the charge current is reduced, and a false safety timerfault can be observed if this mode of operation is active for a long periods. To avoid this undesirable faultcondition the TPS65820 activates the dynamic timer function when the DPPM and thermal loops are active. Thedynamic timer function slows down the safety timers clock, effectively adding an extra time to the programmedtimeout value as follows:1. If the battery voltage is below the battery depleted threshold: the precharge timer value is modified while thethermal loop or the DPPM loop are active2. If the battery voltage is above the precharge threshold: the safety timer value is modified if the DPPM or thethermal loop are active AND the battery voltage is below the recharge threshold.
The TPS65820 dynamic timer function circuit monitors the voltage at pin ISET1 during precharge and fastcharge. When the charger is regulating the charge current, the voltage at pin ISET1 is regulated by the controlloops to either V
SET
or V
PRECHG
. If the thermal loop or DPPM loops are active, the voltage at pin ISET1 is lowerthan V
SET
or V
PRECHG
, and the dynamic timer control circuit changes the safety timers clock period based on theV
SET
/V
(ISET1)
ratio (fast charge) or V
PRECHG
/V
(ISET1)
ratio (precharge).
The maximum clock period is internally limited to twice the value of the programmed clock period, which isdefined by the resistor connected to TMR pin, as shown in the following figure:
Figure 38. Safety Timer Internal Clock Slowdown
The effective charge safety timer value can then be expressed as follows:Effective precharge timeout = t
(PRECHG)
+ t
(PCHGADD)Effective charge safety timeout = t
(CHG)
+ t
(CHGADD)
where the added timeout values, t
(PCHGADD)
, t
(CHGADD),
are equal to the sum of all time periods when either thethermal loop or DPPM loop were active. The maximum added timeout value is internally limited to 2 ×t
(CHG)
or 2×t
(PRECHG)
.
The I
2
C registers that control charger and power path related functions are shown below. The HEX address foreach register is shown by the register name, together with the R or W functionality for the register bits. Shadedvalues indicate default initial power-up values. Note that the CHG_STAT register contents are valid only wheneither AC or USB power are applied to the TPS65820. The output of linear regulator LDO_PM can be used as anindicator of external input power detection; if LDO_PM is in regulation the CHG_STAT register contents are valid.
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 53
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TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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CHG_CONFIG, ADDRESS=9, ALL BITS R/W
B7 B6 B5 B4 B3 B2 B1 B0
Bit name VCHG CHGON TERM_OFF ISET1_1 ISET1_0 ISET2 PSEL CE
(1)
Function CHARGE CHARGE TERMINATION CHARGE CURRENT SCALING USB SELECTED SYSTEMVOLTAGE ENABLE ENABLE FACTOR CURRENT INPUT POWERSELECTION CONTROL LIMIT CURRENT SELECTIONLIMIT
When 0 4.36 V CHARGE TERMINATION 00 = 0.25 10 = 0.75 100 mA USE USB BATTERY TOSUSPENDED ENABLED 01 = 0.5 11 = 1 CURRENT SYSTEMNote: Relative to charge current LIMITprogrammed by external ISET pinWhen 1 4.2 V CHARGE ON TERMINATION 500 mA INPUT INPUT POWERresistor.DISABLED CURRENT TO SYSTEM
(1)
LIMIT SET TOMAXIMUM
(1) The CE bit state is latched inside the charger control logic (CE latch) during an OUT pin UVLO event, prior to resetting the chargecontrol register bit CE to its power up default value. The charger CE latch controls the charger and power path state as long as theTPS65820 is in UVLO mode and an external supply is connected to the charger block. The CE latch is reset to its power-up value(CE=LO) only when the input power is removed from the charger block. The CE latch is disabled and the CE charge control register bitsets the charger and power path MOSFETs state when the TPS65820 exits the UVLO mode. This feature avoids a host software loopwhen the host algorithm requires a depleted (or absent) battery to be connected to the system bus while input power is present.
GPIO3, ADDRESS = 1C, ALL BITS R/W. NOTE: ONLY BIT B4 CONTROLS CHARGER-RELATED FUNCTIONALITY
B7 B6 B5 B4 B3 B2 B1 B0
Bit name GPIO3i/O GPIO3_LEVEL LDO0_ENABLE CHARGE _VLTG RTC_SET GPIO2 _INTSRC GPIO1 _INTSRC GPIO2 _SM2
Function SEE SEE Table 17 SEE Table 17 CHARGE RTC_LDO SEE Table 17 SEE Table 17 SEE Table 17Table 17 VOLTAGE OUTPUTSELECTION VOLTAGESAFETY BIT
When 0 4.2 V 3.1 V
When 1 4.36 V 2.6 V
CHG_STAT, ADDRESS = A, ALL BITS READ-ONLY – POWER UP DEFAULTS SHOW SYSTEM STATUS WHEN EXITING POWER DOWN
B7 B6 B5
(1)
B4 B3 B2 B1 B0
Bit name BAT_STAT
(2) (3)
INPUT _PWR THDPPM_ON ACPG USBPG STAT1 STAT2 INP_OV
Function BATTERY SELECTED THERMAL AC INPUT USB INPUT CHARGE STATUS AC OR USBSUPPLEMENT INPUT LOOP AND POWER POWER INPUT OVPMODE STATUS POWER DPPM STATUS STATUS DETECTIONSTATUS STATUS
When 0 SUPPLEMENT AC INPUT BOTH OFF AC NOT USB NOT 00 = FAULT/SUSPEND/OFF NO OVPMODE OFF SELECTED DETECTED DETECTED 01 = CHARGE DONE10 = FAST CHARGE ONWhen 1 SUPPLEMENT USB INPUT DPPM ON OR AC USB OVP11 = PRECHARGEMODE ON SELECTED THERMAL ON DETECTED DETECTED DETECTED
(1) The TPS65820 generates a charger status interrupt if a DPPM event occurs.(2) The battery supplement is entered when V
(BAT)
– V
(OUT)
> 60 mV (typ), and it ends when V
(BAT)
– V
(OUT)
< 20 mV. When the systempower bus current exceeds the input current limit of the external supply current capability, the supplement mode is set. An oscillatorybehavior for BAT_STAT bit can happen if the battery switch dropout voltage is less than 20 mV (typ) when in supplement mode.(3) The BAT_STAT is always masked internally, and does not generate interrupts
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Product Folder Link(s): TPS65820
FUNCTIONALITY GUIDE — LINEAR REGULATORS
RTC _O UT
SIM
LDO1
LDO 2
LDO3
VIN _ LDO3 5
LDO4
L DO 35 _REF
L DO_P M
AG ND2
VIN_L D O12
L DO5
AG ND1
LDO0
HI PSRR L D O S
A2
OU T
A1
TPS65820
ON /OFF , OutputVoltage
DischargeControl ON /OFF ON /OFF
OutputVoltage
I2 C
REG ISTER S
3.3V
10mA
1.224-4.4V
100mA
1.224-4.4V
100mA
1.25-3.3V
150mA
3.1V
8mA
3.3V
150mA
1.25-3.3V
150mA
1.224-4.4V
100mA
C142.2 Fm
C111 Fm
C120.1 Fm
C132.2 Fm
C71 Fm
C152.2 Fm
C51 Fm
C32.2 Fm
C4100mF
C84.7 Fm
C104.7 F
m
C94.7 Fm
C64.7 Fm
1.8V/3V
8mA
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
SELECTABLE OUTPUT VOLTAGE LDO
Supply ON/OFF Output Discharge OUTPUT VOLTAGE (V), set via I
2
C IO Max Acc % Power UpControl Switch (mA) Default# of Steps Available Values (V)
LDO1 Yes, set via Yes, enabled via I
2
C 8 1.25/1.5/1.8/2.5/2.85/3/3.2/3.3 150 3 ON, 2.85 VI
2
CLDO2 Yes, set via Yes, enabled via I
2
C 8 1.25/1.5/1.8/2.5/2.85/3/3.2/3.3 150 3 ON, 3.3 VI
2
CSIM Yes, set via No 2 1.8 / 3 8 2 OFF, 1.8 VI
2
CRTC_OUT Yes, set via No 2 2.6/3.1 8 5 ON, 2.6VI
2
C
PROGRAMMABLE OUTPUT VOLTAGE LDO
Supply ON/OFF Output Discharge OUTPUT VOLTAGE (V), set via I
2
C IO Max Acc % Power UpControl Switch (mA) DefaultRange # of Steps Min Step
LDO3 yes, set via I
2
C Yes, enabled via I
2
C 1.224 – 4.46 128 25 mV 100 3 ON, 1.25 VLDO4 yes, set via I
2
C Yes, enabled via I
2
C 1.224 – 4.46 128 25 mV 100 3 ON, 2.75 VLDO5 yes, set via I
2
C Yes, enabled via I
2
C 1.224 – 4.46 128 25 mV 100 3 ON, 2.81 V
FIXED OUTPUT VOLTAGE LDO ’ S
Supply ON/OFF Control OUTPUT IO Max (mA) Acc % Power Up DefaultVOLTAGE (V)
LDC0 Yes, via I
2
C 3.3, fixed 150 3 OFFLDO_PM NO, enabled internally 3.3, fixed 20 5 ON if AC or USB power detected
Figure 39. Required External Components, Recommended Values, External Connections
Copyright © 2006 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 55
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LINEAR REGULATORS — FUNCTIONAL DESCRIPTION
Simplified Block Diagram
SHORT CIRCUIT
PROTECTION
BIAS
CONTROL
LDO3-5 ONLY
DISCHARGE
CONTROL
LDO1, LDO2,
LDO3-5 ONLY
VREF
+
_
INPUT SUPPLY
OUTPUT
VOLTAGE
SETTING
Programmable
LDOsonly
ON/OFF
CONTROL
AllLDOs
except
LDO_PM
DISCHARGE
CONTROL
ENABLE
LDO1, LDO2,
LDO3-5 ONLY
I2C
REGISTERS
OUTPUT VOLTAGE
OUTPUT
CURRENT
SAMPLE
OUTPUT
VOLTAGE
SAMPLE
Connecting the LDO Input Supply
ON/OFF Control
Output Discharge Switch
Special Functions
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The TPS65820 offers nine Integrated Linear Regulators, designed to be stable over the operating load rangewith use of external ceramic capacitors, as long as the recommended filter capacitor values (see applicationdiagram and pinout description) are used. The output voltage can be programmed via I
2
C (LDO0-2, LDO3-5) orhave a fixed output voltage.
A simplified block diagram for the LDOs is shown in Figure 40 .
Figure 40. Simplified Block Diagram
Both LDO1-2 and LDO3-5 have uncommitted input power supply pins (VIN_LDO12, VIN_LDO35), which shouldbe externally connected to the OUT pin. Optionally the LDO0-2 and LDO3-5 input supplies can be connected tothe output of the available buck converters SM1 or SM2, as long as the resulting overall power-up sequencemeets the system requirements.
The RTC_OUT, SIM, LDO0 and LDO_PM linear regulators are internally connected to the OUT pin.
All the LDO ’ s, with exception of LDO_PM LDO, have a ON/OFF control which can be set via I
2
C commands,facilitating host management of the distinct system power rails. The LDO_PM LDO On/OFF control is internallyhard-wired, and it is set to ON when either AC or USB input power is detected.
LDO1, LDO2 AND LDO3-5 have integrated switches that discharge each output to ground when the LDO is setto OFF by an I
2
C command. The output discharge switch function can be disabled by using I
2
C register controlbits. The discharge switches are enabled after the initial power-up
The RTC_OUT, SIM (Subscriber line interface module) and LDO_PM linear regulators are designed to supportlower load currents. The SIM and RTC_LDO have low leakage in OFF mode, with the input pin voltage above orbelow the output pin voltage. The LDO_PM can be used for USB enumeration, or a status indication of inputpower connection.
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Output Voltage Monitoring
LINEAR REGULATORS — I
2
C REGISTERS
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Internal power good comparators monitor the LDO outputs and detect when the output voltage is below 90% ofthe programmed value. This information is used by the TPS65820 to generate interrupts or to trigger distinctoperating modes, depending on specific I
2
C register settings. See interrupt and sequencing controller section foradditional details.
The I
2
C registers that control LDO-related functions are shown below. The HEX address for each register isshown by the register name, together with the R or W functionality for the register bits. Shaded values indicatedefault initial power-up values.
B7 B6 B5 B4 B3 B2 B1 B0
EN_LDO: ADDRESS = B, ALL BITS R/W
Bit name LDO1_EN LDO2_EN LDO3_EN LDO4_EN LDO5_EN SIM_SET SIM EN1 RTC_EN
Function LDO1 … 5 ON/OFF CONTROL SIM LDO output SIM/RTC ON/OFF CONTROLvoltage
When 0 OFF OFF OFF OFF OFF 3 V OFF OFF
When 1 ON ON ON ON ON 1.8 V ON ON
LDO12: ADDRESS = C, ALL BITS R/W
Bit name LDO1_DISCH LDO1_2 SET LDO1_1 SET LDO1_0 SET LDO2_DISCH LDO2_2 SET LDO2_1 SET LDO2_0 SET
Function LDO1 output LDO1 OUTPUT VOLTAGE SETTING LDO2 Output LDO2 OUTPUT VOLTAGE SETTINGdischarge switch dischargeenable switch enable
When 0 OFF 000 = 1.25 V 001=1.5 V Default = 2.85 V OFF 000 = 1.25 V 001 = 1.5 V Default = 3.3 V010 = 1.8 V 011=2.5 V 010 = 1.8 V 011 = 2.5 VWhen 1 ON ON100 = 2.85 V 110=3 V 100 = 2.85 V 110 = 3 V110 = 3.2 V 111=3.3 110 = 3.2 V 111 = 3.3 V
LDO3, ADDRESS = D, ALL BITS R/W
Bit name LDO3_DISCH LDO3_6 SET LDO3_5 SET LDO3_4 SET LDO3_3 SET LDO3_2 SET LDO3_1 SET LDO3_0 SET
Function LDO3 output LDO3 OUTPUT VOLTAGE SETTINGdischarge switch
enable
When 0 OFF See Table 10 for LDO3-5 output voltage setting, Power-up default = 1.25 V
When 1 ON
LDO4, ADDRESS = E, ALL BITS R/W
Bit name LDO4_DISCH LDO4_6 SET LDO4_5 SET LDO4_4 SET LDO4_3 SET LDO4_2 SET LDO4_1 SET LDO4_0 SET
Function LDO4 output LDO4 OUTPUT VOLTAGE SETTINGdischarge switch
enable
When 0 OFF See Table 10 for LDO3-5 output voltage setting, Power-up default = 2.75 V
When 1 ON
LDO5, ADDRESS = F, ALL BITS R/W
Bit name LDO5_DISCH LDO5_6 SET LDO5_5 SET LDO5_4 SET LDO5_3 SET LDO5_2 SET LDO5_1 SET LDO5_0 SET
Function LDO5 output LDO5 OUTPUT VOLTAGE SETTINGdischarge switch
enable
When 0 OFF See Table 10 for LDO3-5 output voltage setting, Power-up default = 2.81 V
When 1 ON
GPIO3, ADDRESS = 1C, ALL BITS R/W. NOTE: ONLY BIT B5 CONTROLS LDO-RELATED FUNCTIONALITY
Bit name GPIO3i/O GPIO3 LEVEL LDO0 ENABLE CHARGE RTC_SET GPIO2_INTSRC GPIO1_INTSRC GPIO2_SM2_VLTG
Function SEE Table 17 SEE Table 17 LDO0 ON/OFF SEE Battery RTC_LDO SEE Table 17 SEE Table 17 SEE Table 17CONTROL Voltage OUTPUTRegulation, VOLTAGECharge VoltageWhen 0 LDO0 OFF 3.1 V
When 1 LDO0 ON 2.6 V
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Table 10. LDO 3 – 5 Programming Step ValuesStep B6 – B0 Vset Step B6 – B0 Vset Step B6 – B0 Vset Step B6-B0 Vset
0 000 0000 1.224 32 010 0000 2.04 64 100 0000 2.015 96 110 0000 2.856
1 000 0001 1.25 33 010 0001 2.066 65 100 0001 2.04 97 110 0001 2.882
2 000 0010 1.275 34 010 0010 2.091 66 100 0010 2.907 98 110 0010 3.723
3 000 0011 1.301 35 010 0011 2.117 67 100 0011 2.933 99 110 0011 3.749
4 000 0100 1.326 36 010 0100 2.142 68 100 0100 2.958 100 110 0100 3.774
5 000 0101 1.352 37 010 0101 2.168 69 100 0101 2.984 101 110 0101 3.8
6 000 0110 1.377 38 010 0110 2.193 70 100 0110 3.009 102 110 0110 3.825
7 000 0111 1.403 39 010 0111 2.219 71 100 0111 3.035 103 110 0111 3.851
8 000 1000 1.428 40 010 1000 2.244 72 100 1000 3.06 104 110 1000 3.876
9 000 1001 1.454 41 010 1001 2.27 73 100 1001 3.086 105 110 1001 3.902
10 000 1010 1.479 42 010 1010 2.295 74 100 1010 3.111 106 110 1010 3.927
11 000 1011 1.505 43 010 1011 2.321 75 100 1011 3.137 107 110 1011 3.953
12 000 1100 1.53 44 010 1100 2.346 76 100 1100 3.162 108 110 1100 3.978
13 000 1101 1.556 45 010 1101 2.372 77 100 1101 3.188 109 110 1101 4.004
14 000 1110 1.581 46 010 1110 2.397 78 100 1110 3.213 110 110 1110 4.029
15 000 1111 1.607 47 010 1111 2.423 79 100 1111 3.239 111 110 1111 4.055
16 001 0000 1.632 48 011 0000 2.448 80 101 0000 3.264 112 111 0000 4.08
17 001 0001 1.658 49 011 0001 2.474 81 101 0001 3.29 113 111 0001 4.106
18 001 0010 1.683 50 011 0010 2.499 82 101 0010 3.315 114 111 0010 4.131
19 001 0011 1.709 51 011 0011 2.525 83 101 0011 3.341 115 111 0011 4.157
20 001 0100 1.734 52 011 0100 2.55 84 101 0100 3.366 116 111 0100 4.182
21 001 0101 1.76 53 011 0101 2.576 85 101 0101 3.392 117 111 0101 4.208
22 001 0110 1.785 54 011 0110 2.601 86 101 0110 3.417 118 111 0110 4.233
23 001 0111 1.811 55 011 0111 2.627 87 101 0111 3.443 119 111 0111 4.259
24 001 1000 1.836 56 011 1000 2.652 88 101 1000 3.468 120 111 1000 4.284
25 001 1001 1.862 57 011 1001 2.678 89 101 1001 3.494 121 111 1001 4.31
26 001 1010 1.887 58 011 1010 2.703 90 101 1010 3.519 122 111 1010 4.335
27 001 1011 1.913 59 011 1011 2.729 91 101 1011 3.545 123 111 1011 4.361
28 001 1100 1.938 60 011 1100 2.754 92 101 1100 3.57 124 111 1100 4.386
29 001 1101 1.964 61 011 1101 2.78 93 101 1101 3.596 125 111 1101 4.412
30 001 1110 1.989 62 011 1110 2.805 94 101 1110 3.621 126 111 1110 4.437
31 001 1111 2.015 63 011 1111 2.831 95 101 1111 3.647 127 111 1111 4.463
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FUNCTIONALITY GUIDE — SWITCHED MODE STEP-DOWN CONVERTERS
L1
PGND 1
SM2
L2
VIN_ SM1
VIN_ SM2
PGND 2
SM1
SYNCBUCK
P2
OUT
TPS65820
OperatingMode
OutputVoltage
PhaseControl
DischargeControl
OperatingMode
OutputVoltage
PhaseControl
DischargeControl
I2CREGISTERS
LSM 1
LSM 2
1.0-3.4V
600mA
0.6-1.8V
600mA
3.3 Hm
3.3 Hm
VO(SM2)
C20
10 Fm
C19
10 Fm
VO(SM1)
C22
10 Fm
C21
10 Fm
P1
STEP-DOWN SWITCHED MODE CONVERTERS: SM1 and SM2
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
BUCK CONVERTERS, I
2
C PROGRAMMABLE OUTPUT VOLTAGE
Supply PFM Mode Standby IO Max PWM Freq SLEW RATE, mV/ µs, Set Power Up DefaultOUTPUT VOLTAGE (V), Set via I
2
C,Mode (mA) and PhaseSeparate Settings for Normal or via I
2
CStandby Mode
Range # of Steps Min Acc Range # of MinStep (%) Steps Step
SM1 PFM/PWM Standby 0.6 – 1.8 32 40 mV 3 600 1.5MHz, 0 °0, 0.24 8 0.24 ON, skip mode off,with mode to 15.36 PWM only, 1.24automatic with V(on/stby), 15.36mode distinct mV/ µsselection or voltagePWM only. available
.SM2 Mode of 1 – 3.4 32 80mV 3 600 1.5MHz, 0, 8 0.48 ON, skip mode on,Standbyoperation set 0/90/180 0.48- PWM/PFM, 1.8 Vmode set
270 °, with 30.72 (on/stby), 180 °,via I
2
C
via I
2
C or
respect to 30.72 mV/ µswith
SM1, set viaGPIO pin
I
2
C
Figure 41. Required External Components, Recommended Values, External Connections
The TPS65820 has two highly efficient step down synchronous converters. The integration of the power stageswitching MOSFETs reduces the external component count, and only the external output inductor and filtercapacitor are required. The integrated power stage supports 100% duty cycle operation. Multiple operationmodes are available, enabling optimization of the overall system performance under distinct load conditions.
The converters have two modes of operation: a 1.5 MHz fixed frequency pulse width modulation (PWM) mode atmoderate to heavy loads, and a pulse frequency modulation (PFM) mode at light loads. The converter outputvoltage is programmable via I
2
C registers SM1_SET1 and SM2_SET1.
When the SM1/SM2 converters are disabled an integrated switch automatically discharges the converter outputcapacitor. The discharge switch function can be disabled by setting the control bits DISCHSM1 and DISCHSM2to LO, in I
2
C registers SM1_SET2 and SM2_SET2.
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GATE
CONTROL
LOGIC
SM1 OUTPUT
VOLTAGESETTING
SM1/SM2 PHASE
CONTROL
I2C
REGISTERS
SM1 OPERATING
MODE :
ON/OFF,
PWM, PFM, STANDBY
SM1 DISCHARGE
SWITCHENABLE ,
LOWPFMRIPPLE
L1
PGND1
VIN_SM1
SM1
SM2 OUTPUT
VOLTAGESETTING
L2
PGND2
VIN_SM2
SM2
SM 1 CONVERTER
3.3 Hµ
10 Fµ
VO(SM1)
10 Fµ
3.3 Hµ
10 Fµ
VO(SM2)
10 Fµ
OUT
P1
P2
+
_
+
_29 Ω
V( V IN_ S M 1)
39 Ω
V(VIN_SM1)
SET
RESET
OUT
EN_PFM
POWERSTAGE
CURRENT COMPARATORS
I(L1)
I(L1)
SM1
CONTROL
LOGIC
EN_PFM
EN_PWM
EN_ALL
DCHGON
SM2 OPERATING
MODE :
ON/OFF,
SM1 DISCHARGE
SWITCHENABLE ,
LOWPFMRIPPLE
TPS65820
LSM1
LSM2
C21 C22
C19
C20
PWMCONTROL
PFMCONTROL
PFMON
PWMON
DAC
EN_PWM
SM2CONVERTER
SAMETOPOLOGY ASSM1CONVERTER
PWM, PFM, STANDBY
PWM, PFM, STANDBY
IPFM(LEAVE) +V(VIN_SM3)
29 W,IPFM(ENTER) +V(VIN_SM3)
39 W
(6)
Output Voltage Slew Rate
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Figure 42. SM1/SM2 Converter
The TPS65820 SM1 and SM2 buck converters can be set to operate only in PWM mode or to switchautomatically between PFM and PWM modes. The average load current is monitored, and the PFM mode is setif the average load current is below the threshold IPFM(ENTER). When in PFM mode the load current is alsomonitored, and the PWM mode is set when the load current exceeds the threshold I
PFM(LEAVE)
. The thresholds forautomatic PFM/PWM switching are calculated as shown in Equation 6 for the SM1 converter, the samethresholds apply to the SM2 converter by replacing VIN_SM1 by VIN_SM2 :
The automatic switching mode is enabled via the control bits PFM_SM1 and PFM_SM2 on I
2
C registersSM1_SET1 and SM2_SET1.
I
2
C registers enable setting the output voltage slew rate, when transitioning from one programmed voltage to anew programmed voltage value. These events can be triggered by a new output voltage selection or by switchingfrom a low power mode (standby) to a normal operating mode. During a transition, the output voltage is steppedfrom the currently programmed voltage to the new target voltage. The slew rate from the initial voltage to the finalvoltage can be selected using I
2
C registers, SM1_SET2 and SM2_SET2, ranging from 0.24 mV/ µs to 15.36mV/ µs for the SM1 converter and 0.48 to 30.72 mV/ µs for the SM2 converter. If the slew rate is set to OFF, theoutput voltage goes from the current value to the programmed value in a single step.
During the transition to standby mode the Power Good comparators are disabled.
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Soft Start
Dropout Operation at 100% Duty Cycle
V(VIN_SM1) vV(SM1) )I(L1)ǒRDSON(PSM1) )RLǓ
(7)
Output Voltage Monitoring
Standby Mode
PWM Operation
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
SM1 and SM2 have an internal soft start circuit that limits the inrush current during start-up. An initial delay (170µs typ) from the converter enabled command to the converter effectively being operational is required, to assurethat the internal circuits of the converter are properly biased. At the end of that initial delay the soft start isinitiated, and the internal compensation capacitor is charged with a low value current source. The soft start timeis typically 750 µs, with the output voltage ramping from 5% to 95% of the final target value.
The TPS65820 buck converters offer a low input to output voltage difference while still maintaining operationwhen the duty cycle is set to 100%. In this mode of operation the P-channel switch is constantly turned on,enabling operation with a low input voltage. The dropout operation starts if:
Where:
I(L1) = Output current plus inductor ripple current.R
L
= DC resistance of the inductor
Equation 7 can be also used for the SM2 converter, replacing SM1 by SM2 and L1 by L2.
The output voltage of converters SM1 and SM2 is monitored by internal comparators, and an output low voltagecondition is detected when the output voltage is below 90% of the programmed value. The power good status forSM1 and SM2 is accessible via I
2
C, see interrupt controller section for more details.
The power good comparators for SM1 and SM2 are disabled during the transition to standby mode operation.They are enabled when the transition to standby mode is complete.
Using the I
2
C SM1 and SM2 can be set in stand-by mode. In STANDBY mode the PFM operation mode is setand the output voltage is defined by I
2
C registers SM1_STANDBYand SM2_STANDBY, and it can be set to avalue different than the normal mode output regulation voltage. The standby mode can also be set by the GPIOpins, if those are configured as control pins that define the SM1/SM2 operating mode.
During PWM operation the converters use a fast response voltage mode controller scheme with input voltagefeed-forward, enabling the use of small ceramic input and output capacitors. At the beginning of each clock cyclethe P-channel MOSFET switch is turned on, and the oscillator starts the voltage ramp. The inductor currentramps up until the ramp voltage reaches the error amplifier output voltage, when the comparator trips and thep-channel MOSFET switch is turned off. Internal adaptative break-before-make circuits turn on the integratedn-channel MOSFET switch after an internal, fixed dead-time delay, and the inductor current ramps down, untilthe next cycle is started. When the next cycle starts the ramp voltage is reset to its low value and the p-channelMOSFET switch is turned on again.
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GATE
CONTROL
LOGIC
OSC
PGND1
VIN_SM1
3.3 Hm
OUT
(L1)
+
_
+
_LSM1
OUTPUT
VOLTAGE
SETTING
PWMCONTROL SECTION
(SHOWNFORSM1,SAMETOPOLOGY FORSM2)
RAMP PEAK-TO-PEAKVOLTAGE
PROPORTIONAL TOVIN_SM1
ERROR AMP WITH “TYPE-3
LIKE” COMPENSATION
VO(SM1)
C21
10 Fm
C22
10 Fm
L1
SM1
Phase Control in PWM Mode
PFM Mode Operation
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Figure 43. PWM Operation
The integrated power MOSFETs current is monitored at all times and the power MOSFET is turned off if itsinternal short-circuit current limit is reached.
The SM1 and SM2 converters operate synchronized to each other when both are in PWM mode, with converterSM1 as the master. I
2
C control register bits S1S2PHASE in register SM1_SET2 enables delaying the SM2 PWMclock with respect to SM1 PWM clock, selecting a phase shift from 0 to 270 degrees. The out-of-phase operationreduces the average current at the input node, enabling use of smaller input filter capacitors when bothconverters are connected to the same input supply.
When using the I
2
C interface, the SM1 and SM2 converters can have the automatic power-saving PFM modeenabled. When the PFM mode is set, the switching frequency is reduced and the internal bias currents aredecreased, optimizing the converter efficiency under light-load conditions.
In PFM mode, the output voltage is monitored by a voltage comparator, which regulates the output voltage to theprogrammed value, V
O(SM1)
. If the output voltage is below V
O(SM1)
, the PFM control circuit turns on the powerstage, applying a burst of pulses to increase the output voltage. When the output voltage exceeds the targetregulation voltage, V
O(SM1)
, the power stage is disabled, and the output voltage drops until it is below theregulation voltage target, when the power stage is enabled again.
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GATE
CONTROL
LOGIC
L1
PGND1
VIN_SM1
SM1
OUT
P1
-
_
+
_
+
_
SET
RESET
OUT
OUTPUT VOLTAGE
COMPARATOR POWERSTAGEPEAK
CURRENT COMPARATORS
I(L1)
I(L1)
LSM1
BIASCONTROL
PFMCONTROL SECTION
(SHOWNFORSM1,SAMETOPOLOGY FORSM2)
V(VIN_SM1)
39 W
V(VIN_SM1)
29 W
VO(SM1) +
3.3 HmVO(SM1)
C21
10 Fm
C22
10 Fm
BURST
V(OUT)
IPFM(ENTER)
IPFM(LEAVE)
BURST
INDUCTOR
CURRENT
OUTPUT
VOLTAGE
LOWRIPPLE
PFMOPERATION
MAXIMUMEFFICIENCY
PFMOPERATION
TCOMP
TCOMP
TCOMP
TCOMP
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Figure 44. PFM Mode Operation
During burst operation two current comparators control the power stage integrated MOSFETs. Thesecomparators monitor the instantaneous inductor current and compare it to the internal thresholds I
PFM(ENTER)
andI
PFM(LEAVE)
, turning the p-channel switch on if the inductor current is less than I
PFM(LEAVE)
and turning it off if theinductor current exceeds I
PFM(ENTER)
. The n-channel switch is turned on when the p-channel MOSFET is off.
The PFM output voltage comparator quiescent current may be reduced using the I
2
C register bits PFM_RPL1and PFM_RPL2 in registers SM1_SET and SM2_SET. The voltage comparator quiescent current is reduced ifPFM_RPL1 and PFM_RPL2 bits are set to LO, and the comparator response time (t
COMP
, see Figure 45 )increases. A reduction in quiescent current increases the converter efficiency at light loads, at the expense of alarger output voltage ripple when in PFM mode.
The ripple is minimized if PFM_RPL1 and PFM_RPL2 bits are set to HI, at the expense of reduced efficiencyunder light loads. The operation under low and high ripple settings is described in Figure 45 .
Figure 45. PFM mode operation waveforms
When a burst of pulses is generated, the PFM current comparators control the power stage MOSFETs to limitthe inductor current to a value between the thresholds I
PFM(LEAVE)
and I
PFM(ENTER)
. The number of pulses in aburst cycle is proportional to the load current, and the average current is always below I
PFM(LEAVE)
once PFMoperation is set. The typical burst operation in PFM mode is shown in Figure 46 .
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BURST
IPFM(LEAVE)
LOADCURRENT
V(OUT)
IPFM(LEAVE)
IPFM(ENTER)
INDUCTORCURRENT
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Figure 46. Typical Burst Operation in PFM Mode
The PFM operation is disabled and PWM operation set if one of the following events happen during PFMoperation:
1. The total burst operation time exceeds 10 µs, typ.2. The output voltage falls below 2% of the target regulation voltage.
The PFM mode can be disabled through the serial interface to force the individual converters to stay in fixedfrequency PWM mode.
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SWITCHED MODE STEP-DOWN CONVERTERS — I
2
C REGISTERS
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The I
2
C registers that control buck converter-related functions are shown below. The HEX address for eachregister is shown by the register name, together with the R or W functionality for the register bits. Shaded valuesindicate default initial power-up values.B7 B6 B5 B4 B3 B2 B1 B0
SM1_SET1, ADDRESS=10, ALL BITS R/W
Bit name SM1 EN PFM_RPL1 PFM_SM1 SetV4_SM1 SetV3_SM1 SetV2_SM1 SetV1_SM1 SetV0_SM1
Function SM1 ON/OFF SM1 PFM SM1 PFM SM1 OUTPUT VOLTAGE REGULATION VALUE, STANDBY MODE NOT SETCONTROL FUNCTION MODE ON/OFFOPERATION CTRL
When 0 OFF MAXIMIZE PWM/PFM See Table 11 for SM1, SM2 voltage setting, Power-up default = 1.24 VEFFICIENCY
When 1 ON MINIMIZE Only PWMOUTPUT
RIPPLE
SM1_SET2, ADDRESS=11, ALL BITS R/W
Bit name NOT USED STANDBY_SM DISCHSM1 S1S2PHASE_1 S1S2PHASE_0 SLEWSM1_2 SLEWSM1_1 SLEWSM1_01
Function NOT SM1 STANDBY SM1 output SM2 PWM CLOCK DELAY, SM1 OUTPUT SLEW RATE SETTINGUSED MODE ON discharge WITH RESPECT TO SM1 PWMswitch enable CLOCK
When 0 NOT OFF OFF 00 = 0 10 = 180 000 = 0.24 010 = 0.96 100 = 5.84 110 = 15.36USED 01 = 90 11 = 270 001 = 0.48 011 = 1.92 101 = 7.68 111 =Units: degrees Default = 180 IMMEDIATEWhen 1 NOT ON ON
Unit: mV/ µsDefault = 15.36USED
SM1_STANDBY, ADDRESS=12, B4-B0 R/W, B7-B5 READ ONLY
Bit name NOT USED NOT USED NOT USED SetV4_SM1SL SetV3_SM1SL SetV2_SM1SL SetV1_SM1SL SetV0_SM1SL
Function NOT USED NOT USED NOT USED SM1 OUTPUT VOLTAGE REGULATION VALUE, STANDBY MODE SET
When 0 NOT USED NOT USED NOT USED See Table 11 for SM1, SM2 voltage setting, Power-up default = 1.24 V
When 1 NOT USED NOT USED NOT USED
SM2_SET1, ADDRESS=13, ALL REGISTER BITS R/W
Bit name SM2 EN PFM_RPL2 PFM_SM2 SetV4_SM2 SetV3_SM2 SetV2_SM2 SetV1_SM2 SetV0_SM2
Function SM2 ON/OFF SM2 PFM SM2 PFM SM2 OUTPUT VOLTAGE REGULATION VALUE, STANDBY MODE NOT SETCONTROL FUNCTION MODE ON/OFFOPERATION CTRL
When 0 OFF MAXIMIZE PWM/PFM See Table 11 for SM1, SM2 voltage setting, Power-up default = 1.8 VEFFICIENCY
When 1 ON MINIMIZE ONLY PWMOUTPUT
RIPPLE
SM2_SET2, ADDRESS=14, ALL REGISTER BITS R/W
Bit name NOT USED STANDBY_SM DISCHSM2 NOT USED NOT USED SLEWSM2_2 SLEWSM2_1 SLEWSM2_02
Function NOT USED SM2 STANDBY SM2 output NOT USED NOT USED SM2 OUTPUT SLEW RATE SETTINGMODE ON discharge
switch enable
When 0 NOT USED OFF OFF NOT USED NOT USED 000 = 0.48 010 = 1.92 100 = 7.68110 = 30.72 001 = 0.096 011 = 3.84When 1 NOT USED ON ON NOT USED NOT USED
101 = 15.36 111 = IMMEDIATEUnit: mV/ µsDefault = 30.72
SM2_STANDBY, ADDRESS=15, ALL REGISTER BITS R/W
Bit name NOT USED NOT USED NOT USED SetV4_SM2SL SetV3_SM2SL SetV2_SM2SL SetV1_SM2SL SetV0_SM2SL
Function NOT USED NOT USED NOT USED SM1 OUTPUT VOLTAGE REGULATION VALUE, STANDBY MODE SET
When 0 NOT USED NOT USED NOT USED See Table 11 for SM1, SM2 voltage setting, Power-up default = 1.8 V
When 1 NOT USED NOT USED NOT USED
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Table 11. Programmable Settings for SM1 and SM2 (Including STANDBY)SetV4_ SetV3_ SetV2_ SetV1_ SetV0_ Vset SM1 Vset SM2 SetV4_ SetV3_ SetV2_ SetV1_ SetV0_ Vset SM1 Vset SM2SM SM SM SM SM SM SM SM SM SM
0 0 0 0 0 0.6 1 1 0 0 0 0 1.24 2.28
0 0 0 0 1 0.64 1.08 1 0 0 0 1 1.28 2.36
0 0 0 1 0 0.68 1.16 1 0 0 1 0 1.32 2.44
0 0 0 1 1 0.72 1.24 1 0 0 1 1 1.36 2.52
0 0 1 0 0 0.76 1.32 1 0 1 0 0 1.4 2.6
0 0 1 0 1 0.8 1.4 1 0 1 0 1 1.44 2.68
0 0 1 1 0 0.84 1.48 1 0 1 1 0 1.48 2.76
0 0 1 1 1 0.88 1.56 1 0 1 1 1 1.52 2.84
0 1 0 0 0 0.92 1.64 1 1 0 0 0 1.56 2.92
0 1 0 0 1 0.96 1.72 1 1 0 0 1 1.6 3
0 1 0 1 0 1 1.8 1 1 0 1 0 1.64 3.08
0 1 0 1 1 1.04 1.88 1 1 0 1 1 1.68 3.16
0 1 1 0 0 1.08 1.96 1 1 1 0 0 1.72 3.24
0 1 1 0 1 1.12 2.04 1 1 1 0 1 1.76 3.32
0 1 1 1 0 1.16 2.12 1 1 1 1 0 1.8 3.4
0 1 1 1 1 1.2 2.2 1 1 1 1 1 0.6 1
A
SM1, SM2 PHASE SMX_SLEW RATE, SMX = SM1 OR SM2
SM1 SM2S1S2_PHASE1 S1S2_PHASE0 PHASE SLEWX_2 SLEWX_1 SLEWX_0
mV/ µs mV/ µs
0 0 0 °0 0 0 0.24 0.480 1 90 °0 0 1 0.48 0.961 0 180 °0 1 0 0.96 1.921 1 270 °0 1 1 1.92 3.841 0 0 3.84 7.681 0 1 7.68 15.361 1 0 15.36 30.721 1 1 Immediate
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FUNCTIONALITY GUIDE – ANALOG TO DIGITAL CONVERTER
ANLG1
ANLG2
ADC _ REF
8 CHANNEL
MUX
A/D
CONVERTER
ADC
AGND 2
OUT
A 2
A 2
SYSTEMPOWERBUS
ADC
CONTROL
LOGIC
EXTERNAL ANALOG
INPUTVOLTAGE
6INTERNAL
CHANNELS
C17
4.7 Fm
ANALOG-TO-DIGITAL CONVERTER
Overview
Input Channels
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
10 BIT SUCCESSIVE APPROXIMATION ADC
ADC Input Channels Trigger Mode Conversion Converter Mode Trigger Delay Wait Time, Multiple Power UpCount Conversions DefaultInternal External Range Min Step
Charge ANLG1 and 1, 4, 8, 16, 32, Single, average, 0-750 µs, 50 µsµs: 20, 40, 60, 80, 160, ADC offGPIB, I
2
Ccurrent, ANLG2 64, 128, 256 find max value, 16 steps 240, 320, 640driven, repeatthermistor voltages find min value
ms: 1.28, 1.92, 2.56,temperature,
5.12, 10.24, 15.36, 20.48IC junction
temperature,
RTC_OUT
voltage, OUTvoltage,
battery
voltage
Fixed Selectable via Selectable via Selectable via Selectable via Selectable Selectable
Selectable via I
2
Cinternally
I
2
C I
2
C I
2
C I
2
C via I
2
C via I
2
C
Figure 47. Required External Components, Recommended Values, External Connections
The TPS65820 has a 10 bit integrated successive approximation A/D, capable of running A/D conversions oneight distinct channels in a variety of modes. Two of the eight channels are connected to uncommitted pinsANLG1 and ANLG2, and can be used to convert external voltages. The other six channels monitor systemparameters which are critical to the overall system monitoring. The channel selection is set via I
2
C.
A dedicated set of I
2
C registers enables configuration of the ADC to perform a conversion cycle with either asingle conversion or a multiple conversions. The ALU generates a data set containing maximum value detection,minimum value detection and average value calculation for each conversion cycle. Each cycle can be performeda single time or multiple times.
The following channels are available for selection via the I
2
C register ADC_SET bits CHSEL_SET bits:
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FUNCTIONAL OVERVIEW
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SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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Table 12. ADC Input Channel Oerview
Voltage Range Under Full Scale Reading
LSBChannel Connection Parameter Sampled Normal Operating Special Features (Internal reference
ValueConditions selected )
CH1 ANLG1 pin User defined User defined Internal pullup current 2.535 V Full-scalesource programmable readingCH2 ANLG2 pin 2.535 Vvia I
2
C : 0/10/50/60 µA÷1023CH3 ISET1 pin Voltage proportional to 0 V (charger off) to — 2.535 Vcharge current 2.525 V (fast charge)CH4 TS pin Voltage proportional to pack 0 V (short) to 4.7 V (no Internal 20- µA pullup 2.535 Vtemperature thermistor) current source (ONonly when AC/USBare present)CH5 Internal Voltage proportional to IC 1.85 V at T
J
= 25 °C, — 2.535 Vjunction junction temperature – 6.5 mV/ °C slope typtemperature
CH6 RTC_OUT Internal LDO output voltage 0 V to 3.3 V — 4.7 VpinCH7 OUT pin System power bus voltage 0 V to 4.4 V — 4.7 VCH8 BAT pin Battery pack positive 0 V to 4.4 V — 4.7 Vterminal voltage
The TPS65820 ADC can be subdivided in four sections:1. Input selection: The input selection section has two major blocks, the input bias control and an 8 channelMUX. The input bias control provides the bias currents that are applied to pins ANLG1 and ANLG2 and pinTS. The TS pin bias current is fixed (20 µA typ), and the bias currents for pins ANLG1 and ANLG2 are set onI
2
C register ADC_WAIT.
The TS and ANLG1 pin current sources are automatically enabled when the input power is detected,providing the required setup to measure a pack thermistor temperature (TS pin) or a battery ID resistor(ANLG1 pin). ANLG1 and ANLG2 can be used to measure external resistive loads or analog voltages. Thebias current sources are always connected to the OUT pin internally.
The internal MUX connects one of the monitored analog inputs to the ADC engine, following the selectiondefined on register ADC_SET.2. ADC engine: The ADC engine uses an internal or external voltage reference, as defined by the ADC_REFbit on the ADC_SET control register. If the internal reference is selected ADC_REF is connected to aninternal LDO that regulates the ADC_REF pin voltage to generate the ADC supply and internal voltagereference. The internal LDO maximum output current is 6 mA typical, and a conversion should be startedonly after the external capacitor is fully charged.
If an external reference is used it should be connected to the ADC_REF pin. When an external reference isselected the internal LDO connected to ADC_REF is disabled. Care must be taken when selecting anexternal reference as the ADC reference voltage, as it affects the ADC LSB absolute value.3. Trigger control and synchronization : The ADC engine starts a conversion of the selected input when thetrigger control circuit sends a start command. The trigger control circuit starts the ADC conversion andtransfers the ADC output data to the arithmetic logic unit (ALU) at the end of the conversion. It alsosynchronizes the data transfer from the ALU to the I
2
C ADC_READING register at the end of a conversioncycle, and generates the ADC status information sent to the ADC registers.
An ADC engine conversion is triggered by the TPS65820 trigger control circuit using either an internal triggeror an external trigger. The internal trigger is automatically generated by the TPS65820 at the end of eachADC engine conversion, following the timing parameters set on I
2
C registers ADC_SET, ADC_DELAY andADC_WAIT.
The GPIO3 pin can be used as an external trigger if the bit ADC_TRG_GPIO3 is set HI, in the I
2
C registerADC_DELAY. In the external trigger mode a new conversion is started after the GPIO3 pin has an edgetransition, following the timing parameters set on I
2
C registers ADC_SET, ADC_DELAY and ADC_WAIT.
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8 CHANNEL
MUX
CURRENT SAMPLE
ARITHMETICLOGIC
UNIT
ANLG1
ANLG2
TJ
TS
ISET1
RTC_OUT
OUT
BAT
10 BIT SUCCESSIVE
APROXIMATION ADC
SUPPLY REF
ACCUMULATOR
TRIGGERCONTROL
AND
SYNCHRONIZATION
START DONE
ADCREFERENCE
ANDSUPPLY
SELECTION
BIASCONTROL
ANLG 1/
ANLG 2 BIAS
SELECTION
ADCSUPPLY
AND
REFERENCE
SELECTION
OUT
ADC
CHANNEL
SELECTION
ADCCONFIGURATION :
TRIGGER, HOLDOFF, REPEAT
MODES
DELAY ANDWAIT TIMING
ALUMODE :
SINGLE,
AVERAGE ,
MIN,, MAX
TOI2C:
STATUS AND
CONVERSION
DATA
ADC_REF
I2C
I2C
TPS65820
A 2
4.7 Fm
ADC Conversion Cycle
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
4. Arithmetic Logic Unit (ALU): The ALU performs mathematical operations on the ADC output data asdefined by the I
2
C ADC_READING registers. It executes average calculations or minimum /maximumdetection. The result of the calculations is stored in an 11-bit accumulator register (1 bit allocated forcarry-over). The accumulator value is transferred to the I
2
C data register at the end of a conversion cycle.
A simplified block diagram for the ADC is shown in Figure 48 .
Figure 48. ADC Simplified Block Diagram
A conversion cycle includes all the steps required to successfully sample the selected input signal and transferthe converted data to the I
2
C, generating an interrupt request to the host ( pin : HI →LO). The number ofindividual conversions (samples) in a conversion cycle is defined by the I
2
C ADC_SET register bitsREAD_MODE settings, and can range from a single sample to 256 samples. The conversion cycle settings forthe ALU is defined by register ADC_READING and it can be set to average, maximum value detection, minimumvalue detection or no processing (ADC engine output loaded in the accumulator directly).
The conversion cycle starts with the first sampling and ends when:•The required ALU operations are performed on the final sample, and•The ALU accumulator data is transferred to the I
2
C ADC_READING register, and•The register bit ADC_STATUS in the ADC_READING register is set to LO.
A conversion cycle is always started by the external host when the ADC_EN bit in the ADC_SET register istoggled from LO to HI by a I
2
C write operation. Resetting the ADC_EN bit to LO before the current conversioncycle ends ( INT: LO →HI, ADC_STATUS bit set to LO) is not recommended, as the ADC keeps its currentconfiguration until the current conversion cycle ends.
At the end of a conversion cycle the output data is stored at registers in the ALU block. The ADC_STATUS bit isset to LO ( DONE ) and an interrupt is generated ( INT pin : HI →LO ) if the ADC_STATUS bit is unmasked, at theinterrupt masking registers INT_MASK. It should be noted that the minimum, maximum and average values areALWAYS calculated by the ALU for each conversion cycle.
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External Trigger Operation
Detecting an External Trigger Event
GPIO3
INTERNAL ADC
CONVERSIONSTART
CONVERTER
MODE ARMED CONVERTING
TDLY(TRG)
TDLY(TRG)
Executing Multiple Sample Cycles With an External Trigger
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The value loaded in the I
2
C registers ADC READING_HI and ADC READING_LO at the end of a conversioncycle is defined by control bits ADC_READ0 and ADC_READ1 in register ADC READING_HI. The average,minimum, maximum and last sample values for a conversion cycle can be read if the external host executes anI
2
C write operation, changing the values of bits ADC_READ0 and ADC_READ1, followed by an I
2
C readoperation on registers ADC READING_HI and ADC READING_LO. The minimum, maximum, average, and lastvalues have the same value if a conversion cycle with only one sample is executed.
The ADC_READ0 and ADC_READ1 bits can not be modified during the execution of a conversion cycle. A newconversion cycle should be started only after the current conversion cycle is completed, by toggling the ADC_ENbit from HI to LO and HI again.
The trigger control circuit can be programmed to use an external signal to start a conversion. The TPS65820GPIO3 input is configurable as an ADC trigger, with ADC conversion starting on either a rising edge or fallingedge. When using an external trigger the trigger delay, trigger wait time delay and trigger holdoff mode can beprogrammed using I
2
C registers.
The procedure to start an externally-triggered conversion cycle has the following steps:1. Verify that the current conversion cycle has ended (ADC_STATUS=LO, I
2
C register ADC_READING_HI)2. Set ADC_EN=LO
3. Configure ADC sampling mode, ALU mode, trigger parameters, etc.4. Set ADC_EN=HI
After step 4 the ADC is armed, waiting for an external trigger detection to start a conversion cycle. Similarly tothe non-triggered mode, the ADC configuration should not be modified until the current conversion cycle ends.Note that in the external trigger mode the current cycle does not end if the converter is armed and an externaltrigger is not detected.
An external trigger event is detected when the GPIO3 input has an edge that matches the edge detectionprogrammed in the EDGE bit, at the I
2
C register ADC_DELAY. The internal ADC trigger can be delayed withrespect to the external trigger signal edge. The delay time value is set by the ADC_DELAY register bitsDELAY_n, and can range from 0 µs (no delay) to 750 µs. A conversion is started only if the external triggerremains at its active level when the delay time expires, as shown in Figure 49 . In a positive-edge detection theactive trigger level is HI; in a negative-edge detection the active trigger level is LO.
Figure 49. ADC Conversion Triggerd by GPIO3 Positive Edge Triggered Active Level Hi
When executing conversion cycles that require multiple samples it may be desirable to synchronize the inputsignal conversion using either an external trigger that has a periodic repetition rate or an external asynchronoustrigger that indicates when the external input signal being converted is valid. The TPS65820 has additionaloperating modes and timing parameters that can be programmed using the I
2
C to configure multiple sampleconversion cycles.
In multiple sample cycles the host can select the wait time between samples using the bits WAITn in theADC_WAIT register to set the wait time between samples. The wait time is measured between the end of aconversion and the start of a new conversion.
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GPIO3
INTERNAL ADC
CONVERSIONSTATUS
FIRST
SAMPLE
LAST
SAMPLE
ON
OFF
tWAIT(TRG)
tDLY(TRG)
CONVERSIONCYCLE
GPIO3
INTERNAL ADC
CONVERSIONSTATUS
FIRST
SAMPLE
LAST
SAMPLE
ON
OFF
TWAIT(TRG)
TDLY(TRG)
TDLY(TRG)
CONVERSIONCYCLE
Continuous Conversion Operation (Repeat Mode)
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
With the default power-up settings (HOLDOFF=LO, ADC_DELAY register), the TPS65820 executes a multiplesample conversion cycle if the first sample is taken when the trigger is at its active level. Subsequent samplesare converted at the end of the wait time, even if the trigger returns to the non-active level. The external triggerlevel edge is ignored until the current conversion cycle ends.
Figure 50. ADC Conversion Triggerd by GPIO3 Positive Edge Triggered Active Level Hi; Holdoff = LC
If the sample conversion needs to be synchronized with an external trigger, during multiple sample conversioncycles, the control bit HOLDOFF should be set to HI. When the holdoff mode is active, the internal trigger startsa sample conversion only if the external trigger was detected and is at its active level at the end of the wait time,as shown in Figure 51 .
Figure 51. ADC Conversion Triggerd by GPIO3 Positive Edge-Triggered Active Level HI,Holdoff = HI, Four Sample Cycles
When the multiple sample cycles are executed the host must configure the maximum and minimum limits for theADC output using registers DLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. A conversion cycle ends if anyindividual conversion result exceeds the maximum limit value or is below the minimum limit value. When an outof limit conversion is detected an interrupt is sent to the host, and the ADC_STATUS bit on register ADCREADING_HI is set to DONE.
The TPS65820 ADC can be set to operate in a continuous conversion mode, with back-to-back conversioncycles executed. The REPEAT mode is targeted at applications where an input is continuously monitored for aperiod of time, and the host must be informed if the monitored input is out of the range set by I
2
C registersDLOLIM1, DLOLIM2, DHILIM1 and DHILIM2. In REPEAT mode each conversion is started when the ADC trigger(internal or external) is detected, and a new conversion cycle is started when the current conversion cycle ends.All the trigger and sampling modes available for normal conversion cycles are available in repeat mode.Executing I
2
C read operations to get the ADC readings for average, minimum, maximum and last sample valuesis possible in REPEAT mode. However, this is not a recommended operation, as the REPEAT mode does notgenerate a DONE status flag making it difficult to synchronize the ADC data reading to the end of a conversioncycle.
The recommended use of the REPEAT mode is :1. Configure the ADC conversion cycle : trigger mode, sample mode, select input signal, etc.2. Configure the HI and LO limits for the ADC readings3. Set the ADC_DELAY register bit REPEAT to HI4. Toggle ADC_DELAY register bit ADC_EN bit from LO to HI
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ADC Input Signal Range Setting
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5. Monitor the INT pin. An interrupt triggered by ADC_STATUS=LO indicates that the selected input signal isout of range
To exit the continuous mode the host must follow the steps below, if external trigger mode was set :1. Exit external trigger mode2. Set REPEAT bit to LO, effectively terminating the repeat mode. This generates an additional conversion; atthe end of this conversion the ADC is ready for a new configuration.3. Set ADC_EN to LO, after on-going conversion ends
To exit the continuous mode the host must follow the steps below, if internal trigger mode was set :
1. Set REPEAT bit to LO, effectively terminating the repeat mode.2. Set ADC_EN to LO, after on-going conversion ends
The registers DHILIMn and DLOLIMn can be used by the host to set maximum and minimum limits for the DACengine output. At the end of each conversion the ADC output is checked for the maximum and minimum limits,and a status flag is set if the converted data exceeds the high limit or is under the low limit. In multiple sampleoperation the converted data range is checked when all programmed samples have been converted.
The host can mask or unmask interrupts caused by the ADC range status bits using the INT_MASKn registers.
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ADC State Machine
LOAD ADC
CONFIGURATION
DATA FROMI2C
TRIGGERMODE,
TRIGGERDELAY
SAMPLEWAIT TIME,
HOLDOFFMODE
REPEAT ON /OFF
ALUMODE : AVG /MAX /MIN
NUMBEROFSAMPLES
ADCINPUT RANGE
ADCCHANNEL
ADC
ENABLED
(I2C) ?
TRIGGER
EDGE
DETECT
EXTERNAL
TRIGGER
HOLDOFF
ON
1) SET ADC
BUSY STATUS
2) START
CONVERSION
TRIGGER
EDGE
MODE
TRIGGER
HI
TRIGGER
LO
N
CONVERSIONS
?
NTH
CONVERSION
DONE
WAIT TIME
0 µsto 20.5 msec
START TRIGGER
DELAY
1) LOADDATA IN
ALU
2) ALUOUTPUT
STOREDIN
ACCUMULATOR
ALU
DATA OUT OF
RANGE
REPEAT
MODE
1) LOADI2CDATA
REGISTERWITH
ALUDATA
2) SET ADCSTATUS
TODONE
3) INT SENT TOHOST
IFNON-MASKED
1) SET ADC_ HIOR
ADC_LOFAULT
2) SET ADCSTATUS
TODONE
3) INT SENT TOHOST
IFNON-MASKED
CURRENT
CYCLEENDS
HOSTSTARTSNEW
CONVERSION
CYCLEBY SETTING
ADC_EN=HI
YES
NO
YES
YES
YES, CHECK
TRIGGER
NO
NO
NO
NO
NO
NO, SEND
DATA
TOI2C
YESFAULT
DETECTED
YES
NO
FALLING
EDGE
RISING
EDGE
ADCCONVERSION
COMPLETE
ALUOUTPUT
DATA READY YES
TRIGGER
VALID
TRIGGER
DELAY
OVER
NO, OPPOSITE
TRIGGEREDGE
HAPPENED
BEFOREDELAY
TIME
NO
YES
ADC
ENABLED
(I2C) ?
NO
YES
NO, SEND
DATA
TOI2C
ADC
ENABLED
(I2C) ?
NO, HOSTENDS
CURRENT
CONVERSION
CYCLESETTING
ADC_EN=LO
YES, CURRENT
CONVERSION
CYCLESTILL
ACTIVE,
ADC_EN = HI
TPS
65800READY
FORNEW
CONVERSION
CYCLE
I2CWRITEOPERATION
CONFIGURESNEXT
CONVERSIONCYCLE
ADC_EN=LO
NO,
ADC+EN=LO,
NEEDTO
RECONFIGURE
ADC
PARAMETERS
ALU
RESET
BATTERY DETECTION CIRCUIT
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The ADC state machine with all the trigger and operation modes is shown in Figure 52 .
Figure 52. Trigger and Operation Modes for the ADC State Machine
The ANLG1 pin has an internal current source connected between OUT and ANLG1, which is automaticallyturned on when the OUT pin voltage exceeds the minimum system voltage set by the SYS_IN pin externalresistive divider. The current levels for ANLG1 pin can be programmed via I
2
C register ADC_WAIT, bitsBATID_n. An integrated switch discharges the BAT pin to AGND1 when V(ANLG1)> V(OUT) – V
(NOBATID)
,enabling implementation of a battery removal function if an external pack resistor ID is connected betweenANLG1 and ground.
The ANLG1 pin may be used to monitor other parameters than a pack ID resistor. When ANLG1 pin is used as ageneric ADC analog input V(ANLG1) should never exceed V(OUT) – V
(NOBATID)
, to avoid undesired batterydischarge caused by activation of the battery pin discharge circuit.
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ADC – I
2
C REGISTERS
TPS65820
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The I
2
C registers that control ADC-related functions are shown below. The HEX address for each register isshown by the register name, together with the R or W functionality for the register bits. Default, initial power-upvalues are shown in bold. In the timing equations, replace Bn with 1 for HI state, and 0 for LO state.B7 B6 B5 B4 B3 B2 B1 B0
ADC_SET, ADDRESS=1E, ALL BITS R/W
Bit Name ADC_ENABLE ADC_REF_EN CHSEL2_SET CHSEL1_SET CHSEL0_SET READ_MODE2 READ_MODE1 READ_MODE0
Function ADC ON/OFF ADC ADC CHANNEL SELECTION ADC SAMPLING SETTINGSCONTROL REFERENCE
SELECTION
When 0 OFF Internal 000 = ANLG1 011 = V(TS) 110 = V(OUT) 000 = 1 011 = 16 110 = 128001 = ANLG2 100 = Tj 111 = V(BAT) 001= 4 100 = 32 111 = 256When 1 ON External
010 = V(ISET1) 101 = Default = 010 = 8 101 = 64 Default = 1V(RTC_OUT) ANLG1
ADC READING_HI, ADDRESS=1F, BITS B3/B4 R/W, ALL OTHER BITS READ ONLY
Bit Name ADC_STATUS NOT USED NOT USED ADC_READ1 ADC_READ0 D10 D9_MSB D8
Function CURRENT NOT USED NOT USED ALU OUTPUT DATA ADC ADC CONVERSION OUTPUTCONVERSION SELECTION AVERAGE BITSSTATUS CARRYOVER
BIT
When 0 DONE NOT USED NOT USED 00=LAST 10 = MAXIMUM VALID ONLY AFTER ADC01=AVERAGE 11 = MINIMUM CONVERSION ENDS SEEWhen 1 BUSY NOT USED NOT USED
Default= LAST ADC_READING_LO
ADC READING_LO, ADDRESS=20, READ ONLY
Bit Name D7 D6 D5 D4 D3 D2 D1 D0_LSB
Function ADC CONVERSION OUTPUT BITS, VALID ONLY AFTER ADC CONVERSION ENDS
Value VALUE=[B10*512 + B9*256 + B8*128 + B7*64 + B6*32 + B5*16 + B4*8 + B3*4 + B2*2 + B1] * [ VRNG(CHn) / 1023] ; Unit=Volts,The LSB bit value is proportional to the ADC reference voltage - See V
RNG(CHn)
in electrical parameters
DHILIM1, ADDRESS=21, ALL BITS R/W
Bit Name NOT USED NOT USED NOT USED NOT USED NOT USED DHILIM10 DHILIM9 DHILIM8
Function RESERVED ADC MAX INPUT LIMIT RANGE SETTING (3MSBs)
DHILIM2, ADDRESS=22, ALL BITS R/W
Bit Name DHILIM7 DHILIM6 DHILIM5 DHILIM4 DHILIM3 DHILIM2 DHILIM1 DHILIM0_LSB
Function ADC MAX INPUT LIMIT RANGE SETTING (8 LSBs)
DLOLIM1, ADDRESS=23, ALL BITS R/W
Bit Name NOT USED NOT USED NOT USED NOT USED NOT USED DLOLIM10 DLOLIM9 DLOLIM8
Function RESERVED ADC MIN INPUT LIMIT RANGE SETTING (3 MSBs)
DLOLIM2, ADDRESS=24, ALL BITS R/W
Bit Name DLOLIM7 DLOLIM6 DLOLIM5 DLOLIM4 DLOLIM3 DLOLIM2 DLOLIM1 DLOLIM0_LSB
Function ADC MIN INPUT LIMIT RANGE SETTING (8 LSBs)
ADC_DELAY, ADDRESS=25, ALL BITS R/W
Bit Name ADC_TRG_GPIO3 EDGE _GPIO3 HOLDOFF REPEAT Delay_3 Delay_2 Delay_1 Delay_0
Function USE GPIO3 AS GPIO3 ADC REPEAT ADC EXTERNAL TRIGGER DELAY SETTINGADC TRIGGER TRIGGER HOLDOFF MODEMODE ON/OFF ON/OFFCONTROL
When 0 OFF Falling Edge OFF OFF t
DLY(TRIG)
= B4*400 + B3 * 200 + B2*100 + B1* 50, Units = µsDefault =0µsWhen 1 ON Rising Edge ON ON
ADC_WAIT, ADDRESS=26, ALL BITS R/W
Bit Name ADC_cH2I_D1 ADC_cH2I_D0 BATIDI_D1 BATIDI_D0 WAIT_D3 WAIT_D2 WAIT_D1 WAIT_LSB
Function ANLG2 PULLUP CURRENT ANLG1 PULLUP CURRENT ADC SAMPLE WAIT TIME, MULTIPLE SAMPLES MODESOURCE VALUE SOURCE VALUE
When 0 11:60 µA, 10:50 µA, 01:10 µA, 00: 0 11:60 µA, 10:50 µA, 01:10 µA, 0000 = 0 0100 = 0.08 1000 = 0.64 1100 = 5.12Default= 00 00: WEAK PULLUP 0001 = 0.02 0101 = 0.16 1001 = 1.28 1101 = 10.24When 1
Default : 00 0010 = 0.04 0110 = 0.24 1010 = 1.92 1110 = 15.360011 = 0.06 0111 = 0.32 1011 = 2.56 1111 = 20.48Units = ms Default = 0
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FUNCTIONALITY GUIDE — LED AND PERIPHERAL DRIVERS
L3
SM3
PGND3
4.7 Hm
PWM
LED_PWM
RED
BLUE
GREEN
P3
AGND0
A0
PWM
DRIVER
RGB
DRIVER
WHITELED
DRIVER
DISPLAY ANDI/O
SM3_SW
OUT
TPS65820
WHITELEDS
LSM3
EXTERNAL
PERIPHERALS
RGBLED
D1
R
10
FB3
W
C27
1 Fm
C18
100pF
FB3
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
WHITE LED CONSTANT CURRENT DRIVER
Driver PWM Output LED Current Eff (%) Power UpVoltage DefaultDuty Cycle # of Steps Io(Typ) Max Acc (%)Range
SM3 Off (0%), 256 5 V – 25 V Set by external resistor 25 mA 25 80 Off (0%)0.4% -99.6%
Set via I
2
C
OPEN DRAIN PWM DRIVERS
Driver PWM Freq (kHz) PWM Duty Cycle Io(max) Power Up DefaultmARange # of Steps Min Step
PWM 0.5/1/1.5/2/3/ 4.5/7.8/15.6 Off (0%), 8 6.25% 150 Off(0%)Set via I
2
C 6.25% to 100Set via I
2
CLED_PWM 15.625 or 23.4 , set via I
2
C Off(0%), 256 0.4% 150 Off (0%)0.4% to 99.6%Set via I
2
C
RGB OPEN DRAIN LED DRIVER
Driver Flash Period (same for RGB) Flash On time (same for RGB) Brightness Io mA Power Up(Individual R/G/B Control) Default
Range # of Min Step Range # of Min Step Duty (%) # of MinSteps Steps Steps Steps
RED, No flash, 16 0.5 s 0.1 – 0.6 s 8 0.1 s Off (0%), 32 3.125% 0/4/8/12 Flash Off, 0GREEN, or 1 – 8 s Set via I
2
C 3.125 to mA,BLUE Set via I
2
C 96.87 0%Set via I
2
C brightness
duty cycle
Figure 53. Required External Components, Recommended Values, External Connections
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WHITE LED CONSTANT CURRENT DRIVER
L3
3.3 Hm
SM3
PGND3
FB3
P3
P3
OUT
GATE
DRIVE
GATE
DRIVE
500 mA
+
_
INDUCTORPEAK
CURRENT
DETECTION
LEDLOWCURRENT
DETECTION
+
_
OUTPUT OVP
DETECTION +
_
CONTROL LOGIC AND
MINIMUMOFF TIME
MAXIMUMON TIME
SOFT
START
DUTY CYCLE
CONTROL
OFF
OFFON EN
ON
LEDSWITCH
FREQUENCY
ANDDUTY
CYCLE
TPS65820
250 mV
I2CREGISTER
28V
LED
SWITCH
POWER
STAGE
SWITCH
LSM3
D1
SM3_SW
R
10
FB3
W
C27
1 Fm
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The TPS65820 has an integrated boost converter (SM3) that is optimized to drive white LEDs connected in aseries configuration. Up to six series white LEDs can be driven, with programmable current and duty cycleadjustable via a dedicated I
2
C register.
The SM3 boost converter (SM3) has a 30-V, 500-mA, low-side integrated power stage switch that drives theexternal inductor. Another integrated 30-V, 25-mA switch (LED switch) is used to modulate the brightness of theexternal white LEDs. A simplified block diagram is shown in Figure 54
Figure 54. Simplified Block Diagram
The SM3 converter operates like a standard boost converter. The LED current is defined by the value of theexternal resistor R
FB3
, connected from pin FB3 to AGND1. The integrated power stage switch control monitorsthe LED switch current (FB3) and the integrated power stage switch current, implementing a topology thateffectively regulates the LED current independently of the input voltage and number of LEDs connected. Thehigh voltage rating of the integrated switches enables driving up to six white LEDs, connected in a seriesconfiguration.
The internal LED switch, in series with the external LEDs, disconnects the LEDs from ground during shutdown. Inaddition, the LED switch is driven by a PWM signal that sets the duty cycle, enabling adjustment to the averageLED current by modifying the settings of the I
2
C register SM3_SET. With this control method, the LED brightnessdepends on the LED switch duty cycle only, and is independent of the PWM control signal.
The duty cycle control used in the SM3 converter LED switch is implemented by generating a burst of highfrequency pulses, with a pattern that is repeated periodically. For a duty cycle of 50%, all of the high frequencypulses have a 50% duty cycle. The duty cycle control sets individual pulses to 100% duty cycle when increasingthe LED_PWM output duty cycle; for decreasing LED_PWM output duty cycles, individual pulses are set to 0%duty cycle. An example of distinct duty cycles is shown in Figure 55 , the sum of the individual pulses on/off timeover the repetition period are equivalent to the duty cycle obtained with traditional single-pulse duty cycle circuits.
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SM3CONVERTER
>50%DUTY CYCLE
REPETITIONPERIOD
SM3CONVERTER
50%DUTY CYCLE
SM3CONVERTER
<50%DUTY CYCLE
SM3 Control Logic Overview
Peak Current Control (Boost Converter)
IP(typ) +IMAX(L3) )V(OUT)
L 100 ns, or : IP(typ) +500 mA )V(OUT)
L 100 ns
(8)
Soft Start
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Figure 55. Example of Distinct Duty Cycles
The repetition period can be set using the register SOFT_RESET control bit SM3_LF_OSC to either 180 Hz (HI)or 122 Hz (LO). Each repetition period has a total of 256 pulses, enabling a resolution of 0.4% whenprogramming the duty cycle.
The SM3 boost converter operates in a pulse frequency modulation (PFM) scheme with constant peak currentcontrol. This control scheme maintains high efficiency over the entire load current range and enables the use ofsmall external components, as the switching frequency can reach up to 1 MHz depending on the load conditions.The LED current ripple is defined by the external inductor size.
The converter monitors the sense voltage at pin FB3, and turns on the integrated power stage switch when V
(FB3)is below the 250-mV (typ) internal reference voltage and the LED Switch is ON, starting a new cycle. Theintegrated power switch turns off when the inductor current reaches the internal 500-mA (typ) peak current limit,or if the switch is on for a period longer than the maximum on-time of 6 µs (typ). The integrated power switchalso turns off when the LED switch is set to OFF. As the integrated power switch is turned off, the externalSchottky diode is forward biased, delivering the stored inductor energy to the output. The main switch remains offuntil the FB3 pin voltage is below the internal 250-mV reference voltage and the LED switch is turned ON, whenit is turned on again.
This PFM peak current control scheme sets the converter in discontinuous conduction mode (DCM), and theswitching frequency depends on the inductor, input/output voltage and LED current. Lower LED currents reducethe switching frequency, with high efficiency over the entire LED current range. This regulation scheme isinherently stable, allowing a wide range for the selection of the inductor and output capacitor.
The SM3 integrated power stage switch is turned on until the inductor current reaches the DC current limitI
MAX(L3)
(500 mA, typ). Due to internal delays, typically around 100 ns, the actual current exceeds the DC currentlimit threshold by a small amount. The typical peak current limit can be calculated as shown in Equation 8
The current overshoot is directly proportional to the input voltage, and inversely proportional to the inductorvalue.
All inductive step-up converters exhibit high in-rush current during start-up. If no special precautions are taken,voltage drops can be observed at the input supply rail during start-up, with unpredictable results in the overallsystem operation.
The SM3 boost converter limits the inrush current during start-up by increasing the current limit in three steps:1. 125 mA (typ),2. 250 mA (typ) and3. 500 mA (typ)
The two initial steps (125 mA and 250 mA) are active for 256 power stage switching cycles.
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Enabling the SM3 Converter
Overvoltage Protection
Undervoltage Lockout Operation
Thermal Shutdown Operation
PWM DRIVERS
PWM Pin Driver
LED_PWM Pin Driver
LED_PWM,>50%DUTY CYCLE
LED_PWM,50%DUTY CYCLE
LED_PWM,<50%DUTY CYCLE
REPETITIONPERIOD
TPS65820
SLVS663B – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
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The SM3_SET I
2
C register controls the SM3 LED switch duty cycle. If the register is set to all zeros SM3 is set toOFF mode. When the host writes a value other than 00 in SM3_SET the SM3 converter is enabled, entering thesoft start phase and then normal operation. The SM3 converter can operate with duty cycles varying from 0.4%to 99.6%, with LED switch frequencies of 122 Hz or 180 Hz. The LED switch operating frequency is set by bitSM3_LF, in the SOFT_RESET register.
The output voltage of the boost converter is sensed at pin SM3, and the integrated power stage switch is turnedOFF when V(SM3) exceeds the internal overvoltage threshold V
OVP3
. The converter returns to normal operationwhen V(SM3) < V
OVP3
– V
HYS(OVP3)
.
When the TPS65820 enters the UVLO mode, the SM3 converter is set to OFF mode with the power stageMOSFET switch and the LED switch open (off).
When the TPS65820 enters the thermal shutdown mode, the SM3 converter is set to OFF mode with the powerstage MOSFET switch and the LED switch open (off).
The TPS65820 offers one low-frequency, open-drain PWM driver, capable of driving up to 150 mA. The PWMfrequency and duty cycle are defined by the PWM I
2
C register settings. The PWM parameters are set in I
2
Cregister PWM. Available frequency values range from 500 Hz to 15 kHz, with 8 frequency values and 16 dutycycle options (6.25% each).
The TPS65820 has another PWM driver output (pin LED_PWM), which is optimized to drive a backlight LED.The LED_PWM driver controls the external LED current intensity using a pulse-width control method, with dutycycle being set by the I
2
C register LED_PWM.
The pulse width method implemented generates a burst of high frequency pulses, with a pattern that is repeatedperiodically. For a duty cycle of 50%, all of the high -frequency pulses have a 50% duty cycle. The duty cyclecontrol sets individual pulses to 100% duty cycle when increasing the LED_PWM output duty cycle; fordecreasing LED_PWM output duty cycles individual pulses are set to 0% duty cycle. An example of distinct dutycycles is shown in Figure 56 ; the sum of the individual pulses on/off time over the repetition period is equivalentto the duty cycle obtained with traditional single-pulse duty cycle circuits.
Figure 56. Example of Distinct Duty Cycles
The repetition period can be set using the register SOFT_RESET control bit SM3_LF_OSC to either 183 Hz (HI)or 122 Hz (LO). Each repetition period has a total of 256 pulses, enabling a resoltuion of 0.4% whenprogramming the duty cycle. The LED_SET register enables control of the duty cycle via I
2
C, with duty cycleranging from 0.4% to 99.6%. Setting the LED_SET register to all zeros forces the LED_PWM pin to 0% dutycycle (OFF).
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RGB Driver
GREEN
ILEDB
RED
BLUE
FLASH
CONTROL
LED
CURRENT
SETTINGS
RGB
DUTY
CYCLE
CONTROL
LED
CONTROL
LOGIC
OUT
RRED RGRN RBLUE
ILEDR
ILEDG
TPS65820
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The TPS65820 has a dedicated driver for an RGB external LED. Three outputs are available (pins RED,GREEN, BLUE), with common settings for operation mode (flash on/off, flash period, flash on time), LED currentand phase delay between outputs. The TPS65820 RGB driver continually flashes the external LEDs connectedto the RED, GREEN and BLUE pins using the flash operation parameters defined in register RGB_FLASH.
The currents for the external LEDs can be programmed via I
2
C, and external resistors are not required to limitthe LED current. However, they can be added to set the LED current if the available I
2
C values are notcompatible with the current application, as shown in the circuit below:
Figure 57. Limiting the External LED Current
The flashing-mode parameters defined in register RGB_FLASH enable setting the flashing period from 1 to 8seconds in 0.5-s steps, or to continuous operation. Flashing operation is enabled by setting the FLASH_EN bit inregister RGB_FLASH to HI. This bit must be set HI to enable the RGB current-sink channels.
Each driver has an individual duty cycle control. The duty cycle modulation method used is similar to thePWM_LED duty cycle control, with high frequency pulses being generated when the driver (RED, GREEN, orBLUE pins) is ON. The repetition period for the RGB drivers has a total of 32 pulses, enabling a 3.125%resolution when programming the individual RED, GREEN and BLUE drivers duty cycles. The duty cycles foreach driver can be set individually using control bits on registers RGB_RED, RGB_GREEN and RGB_BLUE.
The RGB drivers can be programmed to sink 4, 8, or 12 mA, with no external current limiting resistor.
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White LED, PWM Drivers — I
2
C Registers
TPS65820
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The I
2
C registers that control LED AND PWM driver related functions are shown below. The HEX address foreach register is shown by the register name, together with the R or W functionality for the register bits. Shadedvalues indicate default initial power-up values. In the equations replace Bn with 1 for HI state, and 0 for LO state.B7 B6 B5 B4 B3 B2 B1 B0
SM3_SET, ADDRESS=16, ALL BITS R/W
Bit Name SM3_I7 set SM3_I6 set SM3_I5 set SM3_I4 set SM3_I3 set SM3_I2 set SM3_I1 set SM3_I0 set
Function SM3 DUTY CYCLE CONTROL
Value See Table 13 for SM3 duty cycle settings, default = 0 (OFF)
RGB_FLASH, ADDRESS= 17, ALL BITS R/W
Bit Name FLASH_EN FLASH_ON2 FLASH_ON1 FLASH_ON0 FLASH_PER3 FLASH_PER2 FLASH_PER1 FLASH_PER0
Function FLASH MODE FLASH MODE ON TIME FLASH MODE PERIODON/OFF CTRL
When 0 OFF See Table 14 for RGB ON TIME settings, default = See Table 14 for RGB FLASH settings, default = 10.1When 1 ON
RGB_RED, ADDRESS=18, ALL BITS R/W
Bit Name RGB_ISET1 RGB_ISET0 PHASE PWMR_D4 PWMR_D3 PWMR_D2 PWMR_D1 PWMR_D0
Function RGB LED CURRENT SETTINGS PHASE REG DRIVER DUTY CYCLE CONTROLCONTROL
When 0 00 = 0 10 = 8 mA GREEN out of See Table 14 for RGB_RED DUTY settings, default = 001 = 4 mA 11 = 12 mA Φwith REDand BLUE
When 1 BLUE out of Φwith RED andGREEN
RGB_GREEN, ADDRESS=19, ALL BITS R/W
Bit Name NOT USED NOT USED NOT USED PWMG_D4 PWMG_D3 PWMG_D2 PWMG_D1 PWMG_D0
Function NOT USED NOT USED NOT USED GREEN DRIVER DUTY CYCLE CONTROL
Value NOT USED NOT USED NOT USED See Table 14 for RGB_GREEN DUTY settings, default = 0
RGB_BLUE, ADDRESS=1A, ALL BITS R/W
Bit Name NOT USED NOT USED NOT USED PWMB_D4 PWMB_D3 PWMB_D2 PWMB_D1 PWMB_D0
Function NOT USED NOT USED NOT USED BLUE DRIVER DUTY CYCLE CONTROL
Value NOT USED NOT USED NOT USED See Table 14 for RGB_BLUE DUTY settings, default = 0
PWM, ADDRESS=1D, ALL BITS R/W
Bit Name PWM_EN PWM1_F2 PWM_F1 PWM_F0 PWM_D3 PWM_D2 PWM_D1 PWM_D0
Function PWM ON/OFF PWM DRIVER FREQUENCY SETTINGS PWM DRIVER DUTY CYCLE SETTINGSCONTROL
When 0 Disabled 000 = 15.6 kHz 011 = 3 kHz 110 = 1 kHz See Table 15 for PWM DUTY settings, default = 0.0625001 = 7.8 kHz 100 = 2 kHz 111 = 500 HzWhen 1 Enabled
010 = 4.5 kHz 101 = 1.5 kHz Default = 15.6kHz
LED_PWM, ADDRESS=27, ALL BITS R/W
Bit Name LPWM_7 set LPWM_6 set LPWM_5 set LPWM_4 set LPWM_3 set LPWM_2 set LPWM_1 set LPWM_0 set
Function LED_PWM DRIVER DUTY CYCLE CONTROL
Value See Table 13 for LED_PWM DUTY settings, default = 0 (OFF)
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Table 13. SM3 and LED_PWM Duty Cycle SettingsDec B7 – B0 Dcpu Dec B7 – B0 Dcpu Dec B7 – B0 Dcpu Dec B7 – B0 Dcpu Dec B7 – B0 Dcpu
0 0000 0000 – 52 0011 0100 0.203 104 0110 1000 0.406 156 1001 1100 0.609 208 1101 0000 0.813
1 0000 0001 0.004 53 0011 0101 0.207 105 0110 1001 0.410 157 1001 1101 0.613 209 1101 0001 0.816
2 0000 0010 0.008 54 0011 0110 0.211 106 0110 1010 0.414 158 1001 1110 0.617 210 1101 0010 0.820
3 0000 0011 0.012 55 0011 0111 0.215 107 0110 1011 0.418 159 1001 1111 0.621 211 1101 0011 0.824
4 0000 0100 0.016 56 0011 1000 0.219 108 0110 1100 0.422 160 1010 0000 0.625 212 1101 0100 0.828
5 0000 0101 0.020 57 0011 1001 0.223 109 0110 1101 0.426 161 1010 0001 0.629 213 1101 0101 0.832
6 0000 0110 0.023 58 0011 1010 0.227 110 0110 1110 0.430 162 1010 0010 0.633 214 1101 0110 0.836
7 0000 0111 0.027 59 0011 1011 0.230 111 0110 1111 0.434 163 1010 0011 0.637 215 1101 0111 0.840
8 0000 1000 0.031 60 0011 1100 0.234 112 0111 0000 0.438 164 1010 0100 0.641 216 1101 1000 0.844
9 0000 1001 0.035 61 0011 1101 0.238 113 0111 0001 0.441 165 1010 0101 0.645 217 1101 1001 0.848
10 0000 1010 0.039 62 0011 1110 0.242 114 0111 0010 0.445 166 1010 0110 0.648 218 1101 1010 0.852
11 0000 1011 0.043 63 0011 1111 0.246 115 0111 0011 0.449 167 1010 0111 0.652 219 1101 1011 0.855
12 0000 1100 0.047 64 0100 0000 0.250 116 0111 0100 0.453 168 1010 1000 0.656 220 1101 1100 0.859
13 0000 1101 0.051 65 0100 0001 0.254 117 0111 0101 0.457 169 1010 1001 0.660 221 1101 1101 0.863
14 0000 1110 0.055 66 0100 0010 0.258 118 0111 0110 0.461 170 1010 1010 0.664 222 1101 1110 0.867
15 0000 1111 0.059 67 0100 0011 0.262 119 0111 0111 0.465 171 1010 1011 0.668 223 1101 1111 0.871
16 0001 0000 0.063 68 0100 0100 0.266 120 0111 1000 0.469 172 1010 1100 0.672 224 1110 0000 0.875
17 0001 0001 0.066 69 0100 0101 0.270 121 0111 1001 0.473 173 1010 1101 0.676 225 1110 0001 0.879
18 0001 0010 0.070 70 0100 0110 0.273 122 0111 1010 0.477 174 1010 1110 0.680 226 1110 0010 0.883
19 0001 0011 0.074 71 0100 0111 0.277 123 0111 1011 0.480 175 1010 1111 0.684 227 1110 0011 0.887
20 0001 0100 0.078 72 0100 1000 0.281 124 0111 1100 0.484 176 1011 0000 0.688 228 1110 0100 0.891
21 0001 0101 0.082 73 0100 1001 0.285 125 0111 1101 0.488 177 1011 0001 0.691 229 1110 0101 0.895
22 0001 0110 0.086 74 0100 1010 0.289 126 0111 1110 0.492 178 1011 0010 0.695 230 1110 0110 0.898
23 0001 0111 0.090 75 0100 1011 0.293 127 0111 1111 0.496 179 1011 0011 0.699 231 1110 0111 0.902
24 0001 1000 0.094 76 0100 1100 0.297 128 1000 0000 0.500 180 1011 0100 0.703 232 1110 1000 0.906
25 0001 1001 0.098 77 0100 1101 0.301 129 1000 0001 0.504 181 1011 0101 0.707 233 1110 1001 0.910
26 0001 1010 0.102 78 0100 1110 0.305 130 1000 0010 0.508 182 1011 0110 0.711 234 1110 1010 0.914
27 0001 1011 0.105 79 0100 1111 0.309 131 1000 0011 0.512 183 1011 0111 0.715 235 1110 1011 0.918
28 0001 1100 0.109 80 0101 0000 0.313 132 1000 0100 0.516 184 1011 1000 0.719 236 1110 1100 0.922
29 0001 1101 0.113 81 0101 0001 0.316 133 1000 0101 0.520 185 1011 1001 0.723 237 1110 1101 0.926
30 0001 1110 0.117 82 0101 0010 0.320 134 1000 0110 0.523 186 1011 1010 0.727 238 1110 1110 0.930
31 0001 1111 0.121 83 0101 0011 0.324 135 1000 0111 0.527 187 1011 1011 0.730 239 1110 1111 0.934
32 0010 0000 0.125 84 0101 0100 0.328 136 1000 1000 0.531 188 1011 1100 0.734 240 1111 0000 0.938
33 0010 0001 0.129 85 0101 0101 0.332 137 1000 1001 0.535 189 1011 1101 0.738 241 1111 0001 0.941
34 0010 0010 0.133 86 0101 0110 0.336 138 1000 1010 0.539 190 1011 1110 0.742 242 1111 0010 0.945
35 0010 0011 0.137 87 0101 0111 0.340 139 1000 1011 0.543 191 1011 1111 0.746 243 1111 0011 0.949
36 0010 0100 0.141 88 0101 1000 0.344 140 1000 1100 0.547 192 1100 0000 0.750 244 1111 0100 0.953
37 0010 0101 0.145 89 0101 1001 0.348 141 1000 1101 0.551 193 1100 0001 0.754 245 1111 0101 0.957
38 0010 0110 0.148 90 0101 1010 0.352 142 1000 1110 0.555 194 1100 0010 0.758 246 1111 0110 0.961
39 0010 0111 0.152 91 0101 1011 0.355 143 1000 1111 0.559 195 1100 0011 0.762 247 1111 0111 0.965
40 0010 1000 0.156 92 0101 1100 0.359 144 1001 0000 0.563 196 1100 0100 0.766 248 1111 1000 0.969
41 0010 1001 0.160 93 0101 1101 0.363 145 1001 0001 0.566 197 1100 0101 0.770 249 1111 1001 0.973
42 0010 1010 0.164 94 0101 1110 0.367 146 1001 0010 0.570 198 1100 0110 0.773 250 1111 1010 0.977
43 0010 1011 0.168 95 0101 1111 0.371 147 1001 0011 0.574 199 1100 0111 0.777 251 1111 1011 0.980
44 0010 1100 0.172 96 0110 0000 0.375 148 1001 0100 0.578 200 1100 1000 0.781 252 1111 1100 0.984
45 0010 1101 0.176 97 0110 0001 0.379 149 1001 0101 0.582 201 1100 1001 0.785 253 1111 1101 0.988
46 0010 1110 0.180 98 0110 0010 0.383 150 1001 0110 0.586 202 1100 1010 0.789 254 1111 1110 0.992
47 0010 1111 0.184 99 0110 0011 0.387 151 1001 0111 0.590 203 1100 1011 0.793 255 1111 1111 0.996
48 0011 0000 0.188 100 0110 0100 0.391 152 1001 1000 0.594 204 1100 1100 0.797
49 0011 0001 0.191 101 0110 0101 0.395 153 1001 1001 0.598 205 1100 1101 0.801
50 0011 0010 0.195 102 0110 0110 0.398 154 1001 1010 0.602 206 1100 1110 0.805
51 0011 0011 0.199 103 0110 0111 0.402 155 1001 1011 0.605 207 1100 1111 0.809
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Table 14. RGB Duty Cycle Control SettingsRGB_D4 RGB_D3 RGB_D2 RGB_D1 RGB_D0 DC(%) FLASH_PER3 FLASH_PER2 FLASH_PER1 FLASH_PER0 P(s)
0 0 0 0 0 0.00 0 0 0 0 1
0 0 0 0 1 3.23 0 0 0 1 1.5
0 0 0 1 0 6.45 0 0 1 0 2
0 0 0 1 1 9.68 0 0 1 1 2.5
0 0 1 0 0 12.90 0 1 0 0 3
0 0 1 0 1 16.13 0 1 0 1 3.5
0 0 1 1 0 19.35 0 1 1 0 4
0 0 1 1 1 22.58 0 1 1 1 4.5
0 1 0 0 0 25.80 1 0 0 0 5
0 1 0 0 1 29.03 1 0 0 1 5.5
0 1 0 1 0 32.25 1 0 1 0 6
0 1 0 1 1 35.48 1 0 1 1 6.5
0 1 1 0 0 38.70 1 1 0 0 7
0 1 1 0 1 41.93 1 1 0 1 7.5
0 1 1 1 0 45.15 1 1 1 0 8
0 1 1 1 1 48.38 1 1 1 1 Continuous
1 0 0 0 0 51.60
1 0 0 0 1 54.83
1 0 0 1 0 58.05 FLASH_ON2 FLASH_ON1 FLASH_ON0 ON_TIME (s)
1 0 0 1 1 61.23 0 0 0 0.1
1 0 1 0 0 64.50 0 0 1 0.15
1 0 1 0 1 67.73 0 1 0 0.2
1 0 1 1 0 70.95 0 1 1 0.25
1 0 1 1 1 74.18 1 0 0 0.3
1 1 0 0 0 77.40 1 0 1 0.4
1 1 0 0 1 80.63 1 1 0 0.5
1 1 0 1 0 83.85 1 1 1 0.6
1 1 0 1 1 87.08
1 1 1 0 0 90.30
1 1 1 0 1 93.53
1 1 1 1 0 96.75
1 1 1 1 1 99.98
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Table 15. PWM Frequency and Duty Cycle Settings
PWM FREQUENCY TABLE PWM_D DUTY CYCLE
PWM_F2 PWM_F1 PWM_F0 f (Hz) PWM2_D3 PWM2_D2 PWM2_D1 PWM2_D0 D_cycle (pu)
0 0 0 15,600 0 0 0 0 0.06250 0 1 7,800 0 0 0 1 0.1250 1 0 4,500 0 0 1 0 0.18750 1 1 3,000 0 0 1 1 0.251 0 0 2,000 0 1 0 0 0.31251 0 1 1,500 0 1 0 1 0.3751 1 0 1,000 0 1 1 0 0.43751 1 1 500 0 1 1 1 0.51 0 0 0 0.56251 0 0 1 0.6251 0 1 0 0.68751 0 1 1 0.751 1 0 0 0.81251 1 0 1 0.8751 1 1 0 0.937511111
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FUNCTIONALITY GUIDE – GENERAL PURPOSE INPUTS/OUTPUTS
GPIO1
GPIO
CONTROL
GPIO2
GPIO3
I2C
SETTINGS
GPIO
FUNCTION
ANDMODE
TPS65820
CONFIGURATIONMODES:
1-OUTPUT
2-ADC TRIGGERCONTROL
3-LDC0ENABLE
4-CHARGEVOLTAGESELECTION
CONFIGURATIONMODES:
1-OUTPUT
2-SM1/SM2STANDBY CONTROL INPUT
3-SM1ON/OFFCONTROL INPUT
4-INTERRUPT REQUEST CONTROL INPUT
GENERATES PINHI LO TRANSITIONINT ®
CONFIGURATIONMODES:
1-OUTPUT
2-SM2 CONTROL
3-
4-GENERATES PINHI LO TRANSITION
ON/OFF
INTERRUPT REQUEST CONTROL INPUT
INT ®
TPS65820
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GPIO3 FUNCTIONS
CONFIGURED AS OUTPUT CONFIGURED AS INPUT POWER-UP
DEFAULTOUTPUT LEVEL Io(max) A/D CONVERSION START TRIGGERmA
HI or LO at output set 5 Falling or rising edge selected via I
2
C Input, no modevia I
2
C selected
GPIO2 FUNCTIONS
CONFIGURED AS OUTPUT CONFIGURED AS INPUT POWER-UP
DEFAULTOUTPUT LEVEL Io(max) HOST INTERRUPT SM2 ENABLEmA REQUEST
HI or LO at output set 5 Set INT pin to LO via I
2
C GPIO2 level sets SM2 converter ON/OFF operation. Input, no modevia I
2
C when GPIO2 pin edge is GPIO2 pin level (HI or LO) for ON operation selecteddetected. Rising or falling selected via I
2
Cedge detection selected viaI
2
CThe host interrupt request and SM2 enable GPIO2 functions are mutually exclusive,and they should NOT be configured simultaneously
GPIO1 FUNCTIONS
CONFIGURED AS OUTPUT CONFIGURED AS INPUT POWER-UP
DEFAULTOUTPUT LEVEL Io(max) HOST INTERRUPT SM1 ENABLE SM1 AND SM2 STANDBYmA REQUEST CONTROL
HI or LO at output set 5 Set INT pin to LO via I
2
C GPIO1 level sets SM1 GPIO1 level sets SM2 and Input, no modevia I
2
C when GPIO1 pin edge is converter ON/OFF SM1 converters in standby selecteddetected. Rising or falling operation. GPIO2 pin mode. GPIO1 pin level (HIedge detection set via I
2
C level (HI or LO) for ON or LO) for standby modeoperation set via I
2
C set selected via I
2
CThe host interrupt request, SM1 enable and SM1/SM2 standby control GPIO1functions are mutually exclusive, and they should NOT be configured simultaneously.
Figure 58. Required External Components, Recommended Values, External Connections
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General Purpose I/Os — GPIO 1, 2, 3
GPIOs Input Level Configuration
S1
S2
D
C ENB
Multiplexer
Q
Q
SET
CLR
D
GPIO
SignalPin
HI=RisingEdge,
LO=FallingEdge
UVLO
GPIOConfig= OUTPUT
Equivalentcircuitforinternal
logicwhenconfiguredasedge
interruptwithnomasking
I CINTACKREAD
C
2
ommand?
INT INT
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
The TPS65820 integrates 3 general purpose open drain ports (GPIOs) that can be configured as selectableinputs or outputs. When configured as outputs the output level can be set to LO or HI via I
2
C commands. Whenthe GPIOs are configured as inputs the action to be taken when a transition or HI/LO level is detected at theGPIO pin is selectable via I
2
C.
When configured as inputs the GPIOs can be set in the following modes:1. Interrupt request: In this mode of operation, a transition at the GPIO pin generates an interrupt request at theinterrupt controller. The GPIO interrupt request can be masked at the INT_MASK register. This operationmode is available for GPIOs 1 and 2.2. SM1 and SM2 control: The GPIOs can be used to turn the converters SM1 and SM2 ON/OFF, as well assetting them in standby mode. This control mode is available for GPIO1 (SM1 on/off and SM1/SM2 standby)and GPIO2 (SM2 on/off control).3. ADC trigger : GPIO3 can be configured as an external ADC trigger. The GPIO3 trigger configuration bit islocated at the ADC register ADC_DELAY.
When using I
2
C commands, the GPIO1 and GPIO2 pins can be configured as logic output signals or aslevel-controlled inputs which enables (or disables) the switch mode converters SM1 and/or SM2. These pins mayalso be configured as rising- or falling-edge-triggered inputs to externally control the generation of an interruptsignal ( INT), if desired.
The GPIO3 pin may be used as an external trigger source to start an A/D conversion cycle or as a logic output.
See Figure 59 for a description of the logic used for GPIO1 and GPIO2 inputs when configured foredge-triggered interrupt generation. The signal from the GPIO pin input is double-latched before being sent to theinterrupt contoller logic. The inversion of the Q output from the first flip-flop must be HI to allow the output latch tobe cleared when a READ command occurs. On the initial edge of the GPIO signal, the Q output of the flip-flop isset (HI). The INT line is asserted (LO) after the initial selected edge from the GPIO pin. On the next falling (orrising) edge of the GPIO pin, the interrupt can again be cleared (which allows the INT pin to go back high). TheINT signal is cleared (set back HI) after an I
2
C READ operation is performed.
Thus, two successive edges of the GPIO signal, followed by an I
2
C READ command, are required to clear theINT pin output. If no I
2
C READ commands occur, repeatedly applying edges to the GPIO pin does not toggle thestate of the INT pin output.
In addition to an I
2
C READ command after two GPIO edges, a UVLO event or reconfiguration of the GPIO pinsas outputs also de-asserts the INT signal.
Figure 59. GPIO 1 or GPIO2 Configured as an Interrupt Request Input
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Function Implementation: I
2
C Commands Versus GPIO Commands
GPIO Configuration Table
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Some of the GPIO SM1/SM2 control functions overlap I
2
C register control functions. Table 16 describes theTPS65820 action when the GPIO ’ s command and I
2
C registers commands are not compatible with each other.
Table 16. GPIO Commands and I
2
C Registers Commands
SM1 AND SM2 ON/OFF I
2
C COMMAND GPIO COMMAND SM1 OR SM2 MODE SET
CONVERTER DISABLED DON ’ T CARE DISABLEDCONVERTER ENABLED CONVERTER ENABLED ENABLEDDON ’ T CARE CONVERTER DISABLED DISABLED
SM1 AND SM2 STANDBY I
2
C COMMAND GPIO COMMAND SM1 OR SM2 MODE SET
DO NOT SET STANDBY DON ’ T CARE NORMALSET STANDBY SET STANDBY STANDBYDON ’ T CARE DO NOT SET STANDBY NORMAL
Table 17 describes the I
2
C register settings required to program the available GPIO modes.
Table 17. Recommended GPIO Configuration Procedure
GPIO MODE I
2
C I
2
C REGISTER BIT SETTING ADDITIONAL DETAILSREGISTERS
GPIO3 = OUTPUT GPIO3 GPIO3I/O=HI AND GPIO3OUT=HI GPIO3 PIN SET TO HIGH IMPEDANCEMODEGPIO3I/O=HI AND GPIO3OUT=LO V(GPIO3) = V
OL
GPIO3 =INPUT GPIO3 AND GPIO3I/O=LO AND ADC_TRG_GPIO3=HI AND GPIO3 pin rising edge triggers ADCADC CONVERSION ADC_DELAY EDGE_GPIO3=HI conversionSTART TRIGGER
GPIO3I/O=LO AND ADC_TRG_GPIO3=HI AND GPIO3 pin falling edge triggers ADCEDGE_GPIO3=LO conversion
GPIO2 = OUTPUT GPIO12 GPIO2I/O=HI AND GPIO2OUT=HI GPIO2 PIN SET TO HIGH IMPEDANCEMODEGPIO2I/O=HI AND GPIO2OUT=LO V(GPIO2) ≤V
OL
GPIO2=INPUT, GPIO12 AND GPIO2I/O=LO AND GPIO2INT=HI AND INT pin HI →LO →HI at V(GPIO2) fallingHOST INTERRUPT GPIO3 GPIO2LVL=HI AND GPIO2SM2=LO edgeREQUEST
GPIO2I/O=LO AND GPIO2INT=HI AND INT pin HI →LO →HI at V(GPIO2) risingGPIO2LVL=HI AND GPIO2SM2=LO edge
GPIO2=INPUT, GPIO12 AND GPIO2I/O=LO AND GPIO2INT=LO AND SM2 converter ON at V(GPIO2)=HISM2 ENABLE GPIO3 GPIO2LVL=HI AND GPIO2SM2=HIGPIO2I/O=LO AND GPIO2INT=LO AND SM2 converter ON at V(GPIO2)=LOGPIO2LVL=LO AND GPIO2SM2=HI
GPIO1 = OUTPUT GPIO12 GPIO1I/O=HI AND GPIO1OUT=HI GPIO1 PIN SET TO HIGH IMPEDANCEMODEGPIO1I/O=HI AND GPIO1OUT=LO V(GPIO1) ≤V
OL
GPIO1=INPUT, GPIO12 AND GPIO1I/O=LO AND GPIO1INT=HI AND INT pin HI →LO →HI at V(GPIO1) fallingHOST INTERRUPT GPIO3 GPIO1LVL=HI AND GPIO1SM1=LO AND edgeREQUEST GPIO1SMSBY=LO
GPIO1I/O=LO AND GPIO1INT=HI AND INT pin HI →LO →HI at V(GPIO1) risingGPIO1LVL=LO AND GPIO1SM1=LO AND edgeGPIO1SMSBY=LO
GPIO1=INPUT, GPIO12 AND GPIO1I/O=LO AND GPIO1INT=LO AND SM1 converter ON at V(GPIO1)=HISM1 ENABLE GPIO3 GPIO1LVL=HI AND GPIO1SM1=HI ANDGPIO1SMSBY=LO
GPIO1I/O=LO AND GPIO1INT=LO AND SM1 converter ON at V(GPIO1)=LOGPIO1LVL=LO AND GPIO1SM1=HI ANDGPIO1SMSBY=LO
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GPIOs — I
2
C Registers
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Table 17. Recommended GPIO Configuration Procedure (continued)
GPIO MODE I
2
C I
2
C REGISTER BIT SETTING ADDITIONAL DETAILSREGISTERS
GPIO1=INPUT, GPIO12 AND GPIO1I/O=LO AND GPIO1INT=LO AND SM1/SM2 converter standby set atSM1/SM2 STANDBY GPIO3 GPIO1LVL=HI AND GPIO1SM1=LO AND V(GPIO1) = HICONTROL GPIO1SMSBY=HI
GPIO1I/O=LO AND GPIO1INT=LO AND SM1/SM2 converter standby set atGPIO1LVL=LO AND GPIO1SM1=LO AND V(GPIO1) = LOGPIO1SMSBY=HI
The I
2
C registers that control GPIO-related functions are shown below. The HEX address for each register isshown by the register name, together with the R or W functionality for the register bits. Shaded values indicatedefault initial power-up values.
B7 B6 B5 B4 B3 B2 B1 B0
GPIO12, ADDRESS=1B, ALL BITS R/W
Bit Name GPIO2I/O GPIO1I/O GPIO2OUT GPIO1OUT GPIO2LVL GPIO1LVL GPIO1SMSBY GPIO1SM1
Function GPIO2 MODE GPIO1 MODE SET GPIO2 SET GPIO1 GPIO2 EDGE GPIO1 EDGE GPIO 1 GPIO1LEVEL LEVEL AND LEVEL AND LEVEL CONTROLS CONTROLS(OUTPUT (OUTPUT DETECTION DETECTION SM1 AND SM2 SM1 ON/OFFONLY) ONLY) STANDBY
ON/OFF
When 0 INPUT INPUT LOW LOW RISING EDGE, RISING EDGE, DISABLED DISABLEDLO LEVEL LO LEVEL
When 1 OUTPUT OUTPUT HIGH HIGH FALLING FALLING ENABLED ENABLEDEDGE, HI EDGE, HILEVEL LEVEL
GPIO3, ADDRESS=1C, ALL BITS R/W
Bit Name GPIO3I/O GPIO3OUT LDO0_EN CHG_VOLT RTC_SET GPIO2 INT GPIO1 INT GPIO2SM2
Function GPIO3 MODE SET GPIO3 LDO0 ON/OFF CHARGE RTC_LDO GPIO2 GPIO1 SM2 ON/OFFLEVEL CONTROL VOLTAGE OUTPUT TRIGGERS TRIGGERS CONTROL(OUTPUT SAFETY BIT VOLTAGE INT:HI →LO INT:HI →LOONLY)
When 0 INPUT LOW OFF 4.20 V 3.1 V DISABLED DISABLED DISABLED
When 1 OUTPUT HIGH ON 4.36 V 2.6 V ENABLED ENABLED ENABLED
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APPLICATION INFORMATION
INDUCTOR AND CAPACITOR SELECTION — CONVERTERS SM1 AND SM2
F+1
2pLC
Ǹ+27.7 kHz (a) for L +3.3 mH andC +10 mF
(9)
Itarget +VOUT
0.3 IOUT_MAX
ǒ1*VOUT
VIN_MAXǓ
f
(10)
DIL+VL
L Dt+VOUT
L
ǒ1*VOUT
VIN Ǔ
f
(11)
ILmax +IOUTmax )
DIL
2
(12)
TPS65820
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SM1 and SM2 are designed with internal voltage mode compensation and the stabilization is based on choosingan LC filter that has a corner frequency around 27 kHz. It is not recommended to use LC values that would beoutside the range of 13 kHz to 40 kHz.
Equation 9 calculates the corner frequency of the output LC filter. The standard recommended LC values are3.3 µH and 10 µF.
The inductor value, along with the input voltage VIN, output voltage V
OUT
and switching frequency f define theripple current. Typically the ripple current target is 30% of the full load current. At light loads it is desirable forripple current to be less then 150% of the light load current.
The inductor should be chosen with a rating to handle the peak ripple current., if an inductor ’ s current gets higherthan its rated saturation level (DCR), the inductance starts to fall off, and the inductor ’ s ripple current increasesexponentially. The DCR of the inductor plays an important role in efficiency and size of the inductor. Largerdiameter wire has less DCR but may increase the size of the inductor
Equation 10 calculates the target inductor value. If an inductor value has already been chosen, Equation 11 ,calculates the inductor ’ s ripple current under static operating conditions. The ripple amplitude can be calculatedduring the on time (positive ramp) or during the off time (negative ramp). It is easiest to calculate the ripple usingthe off time since the inductor ’ s voltage is the output voltage.
Equation 12 calculates the peak current due to the output load and ripple current
For a faster transient response, a lower inductor and higher capacitance allows the output current to ramp faster,while the addition capacitance holds up the output longer (a 2.2- µH inductor in combination with a 22- µF outputcapacitor are recommended).
The highest inductor current occurs at the maximum input voltage. The peak inductor current during a transientmay be higher than the steady state peak current and should be considered when choosing an inductor.Monitoring the inductor current for non-saturation operation during a transient of 1.2 ×I_loadmax at Vin_maxensures adequate saturation margin.
Table 18. Inductors for Typical Operation Conditions
DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER
DCDC3 converter 3.3 µH CDRH2D14NP-3R3 Sumida3.3 µH PDS3010-332 Coilcraft3.3 µH VLF4012AT-3R3M1R3 TDK2.2 µH VLF4012AT-2R2M1R5 TDK2.2 µH NR3015T2R2 Taoup-Uidem
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OUTPUT CAPACITOR SELECTION, SM1, SM2 CONVERTERS
IRMSCout +
1*VOUT
VIN
2 L f 1
3
Ǹ
(13)
VRMSCout +
1*VOUT
VIN
L f ǒ1
8 Cout f)ESRǓ
(14)
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Table 18. Inductors for Typical Operation Conditions (continued)
DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER
DCDC2 converter 3.3 µH CDRH2D18/HPNP-3R3 Sumida3.3 µH VLF4012AT-3R3M1R3 TDK2.2 µH VLCF4020-2R2 TDKDCDC1 converter 3.3 µH CDRH3D14/HPNP-3R2 Sumida3.3 µH CDRH4D28C-3R2 Sumida3.3 µH MSS5131-332 Coilcraft2.2 µH VLCF4020-2R2 TDK
The advanced fast-response voltage mode control scheme of the SM1, SM2 converters implemented in theTPS65020 allow the use of small ceramic capacitors with a typical value of 10 µF for a 3.3- µH inductor, withouthaving large output voltage under and overshoots during heavy load transients.
Ceramic capacitors having low ESR values have low output voltage ripple, and recommended values andmanufacturers are listed in Table 1 . Often, due to the low ESR, the ripple current rating of the ceramic capacitoris adequate to meet the inductor ’ s currents requirements.
The RMS ripple current is calculated as:
At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is thesum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging anddischarging the output capacitor: The output voltage ripple is maximum at the highest input voltage Vin.
At light load currents, the converters operate in PFM and the output voltage ripple is dependent on the outputcapacitor value. The output voltage ripple is set by the internal PFM output voltage comparator delay and theexternal capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
Table 19. Input/Output Capacitors for Typical Operation Conditions
CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS
22 µF 1260 TDK C3216X5R0J226M Ceramic22 µF 1260 Taiyo Yuden JMK316BJ226ML Ceramic10 µF 0805 Taiyo Yuden JMK212BJ106M Ceramic10 µF 0805 TDK C2012X5R0J106M Ceramic22 µF 0805 TDK C2012X5R0J226MT Ceramic22 µF 0805 Taiyo Yuden JMK212BJ226MG Ceramic
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INPUT CAPACITOR SELECTION, SM1, SM2 CONVERTERS
OUTPUT VOLTAGE SELECTION, SM1, SM2 CONVERTERS
R1 +ƪVSMxOUT
VFB *1ƫR2
(16)
DESIGN EXAMPLES
SM1, SM2 CONVERTER DESIGN EXAMPLE
Ltarget +VOUT
0.3 IOUT_MAX
ƪ1*VOUT
VIN_MAXƫ
fsw +3.35 mH, 3.3 mH is a good target.
(17)
C+1
L[2 p fc]2+10.5 mF 10 mF is a good target.
(18)
CHARGER DESIGN EXAMPLE
RISET +KSET VSET
IPGM
+1 kW
(19)
RDPPM +VDPPM_OUT
KDPPM IDPPM
+3.74 kW
(20)
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Buck converters have a pulsating input current that can generate high input voltage spikes at V
IN
. A low ESRinput capacitor is required to filter the input voltage, minimizing the interference with other circuits connected tothe same power supply rail. Each dc-dc converter requires a 10- µF ceramic input capacitor on its input pin.
Typically the output voltage is programmed by the I
2
C. An external divider can be added to raise the outputvoltage, if the available I
2
C values do not meet the application requirements. Care must be taken with this specialoption, since this external divider (gain factor) would apply to any selected I
2
C output voltage value for thisconverter.
Equation 16 calculates R1, Let R2 = 20 k Ω:
Where V
FB
is the I
2
C selected voltage, is the desired output voltage and R1/R2 is the feedback divider.
Design Conditions and Parametrs for SM1 or SM2:Vin_SM1/2: 4.6V typical (May be less if input source is limited).Vout_SM1/2: 1.24 VIout_max: 0.6 Afsw = 1500 kHzfc = 25 kHz
Design Conditions and Parameters for Charger:Vout: 4.6 V; (OUT pin is input to charger)Fast-charge current, I
PGM
: 1 ADPPM-OUT threshold: 4.3 V; (charging current reduces when OUT falls to this level)Safety timer: 5 hrBattery short-circuit delay, t
DELAY
: 47 µs; (delays BAT short circuit during hot plug of battery)TS Temperature range: DisabledK
SET
= 400; V
SET
= 2.5 V; K
DPPM
= 1.15; I
DPPM
= 100 µA; K
TMR
= 0.36 s/ Ω
Program Fast Charge Current Level:
Program DPPM_OUT Voltage Level (Level at Which Charging Current Reduces)
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CDPPM +tDELAY IDPPM +4.7 Nf
(21)
RTMR +tSAFETY*HR 3600 secńhr
KTMR +50 kW
(22)
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.............................................................................................................................................................. SLVS663B – MAY 2006 – REVISED APRIL 2008
Program BAT Short-Circuit Delay (Used for Inserting Battery)
Program 5-Hour Safety timer
Disable/Program TSR
TS
= 49.9k – fixed resistor to disable TS input.V
TS
= I
TS
×R
TS
= 20 µA×49.9 k Ω= 0.998 V
The TS pin has a 20- µA current source output that biases the resistor or thermistor. If V
TS
is within the 0.5- to2.5-V window, normal operation is allowed. If a 503AT thermistor is used, the typical range is 4 °C to 41 °C.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS65820RSHR ACTIVE VQFN RSH 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS65820RSHRG4 ACTIVE VQFN RSH 56 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS65820RSHT ACTIVE VQFN RSH 56 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TPS65820RSHTG4 ACTIVE VQFN RSH 56 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 8-Dec-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS65820RSHR VQFN RSH 56 2000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
TPS65820RSHT VQFN RSH 56 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65820RSHR VQFN RSH 56 2000 367.0 367.0 38.0
TPS65820RSHT VQFN RSH 56 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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