8-129
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
RF1K49211
7A, 12V, 0.020 Ohm, Logic Level, Single
N-Channel LittleFET™ Power MOSFET
The RF1K49211 Single N-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It was designed for
use in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low-voltage bus
switches. This product achieves full-rated conduction at a
gate bias in the 3V - 5V range, thereby facilitating true on-off
power control directly from logic level (5V) integrated circuits.
Formerly developmental type TA49211.
Features
• 7A, 12V
•r
DS(ON) = 0.020Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC MS-012AA
Ordering Information
PART NUMBER PACKAGE BRAND
RF1K49211 MS-012AA RF1K49211
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4921196.
SOURCE(2)
DRAIN(8)
NC(1)
DRAIN(7)
DRAIN(6)
DRAIN(5)
SOURCE(3)
GATE(4)
BRANDING DASH
1234
5
Data Sheet August 1999 File Number
4303.1
8-130
Absolute Maximum Ratings TA = 25oC Unless Otherwise Specified RF1K49211 UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 12 V
Drain to Gate Voltage (Rgs = 20KΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 12 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V
Drain Current
Continuous (Pulse Width = 1s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 7
Refer to Peak Current Curve A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Refer to UIS Curve
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
0.016 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TA = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V, (Figure 13) 12 - - V
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA, (Figure 12) 1 - 2 V
Zero Gate Voltage Drain Current IDSS VDS = 12V,
VGS = 0V TA = 25oC--1µA
TA = 150oC--50µA
Gate to Source Leakage Current IGSS VGS = ±10V - - 100 nA
Drain to Source On Resistance rDS(ON) ID = 7A, VGS = 5V, (Figures 9, 11) - - 0.020 Ω
Turn-On Time tON VDD = 6V, ID≅ 7A,
RL = 0.86Ω, VGS =5V,
RGS = 25Ω
- - 250 ns
Turn-On Delay Time td(ON) -50-ns
Rise Time tr- 150 - ns
Turn-Off Delay Time td(OFF) - 120 - ns
Fall Time tf- 160 - ns
Turn-Off Time tOFF - - 350 ns
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 9.6V,
ID≅ 7A,
RL = 1.37Ω
Ig(REF) = 1.0mA
(Figure15)
-6075nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 35 45 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 2 2.5 nC
Input Capacitance CISS VDS = 12V, VGS = 0V,
f = 1MHz
(Figure 14)
- 1850 - pF
Output Capacitance COSS - 1600 - pF
Reverse Transfer Capacitance CRSS - 600 - pF
Thermal Resistance Junction to Ambient RθJA Pulse Width = 1s
Device mounted on FR-4 material - - 62.5 oC/W
Source to Drain Diode Specifications
PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 7A - - 1.25 V
Reverse Recovery Time trr ISD = 7A, dISD/dt = 100A/µs--95ns
RF1K49211
8-131
Typical Performance Curves
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
TA, AMBIENT TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
4
2
025 50 75 100 125 150
6
ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE (oC)
8
t1, RECTANGULAR PULSE DURATION (s)
0.01
0.1
1
10
10-3 10-1 100101102103
10-2
ZθJA, NORMALIZED THERMAL
IMPEDANCE
PDM
t1t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
SINGLE PULSE
10-4
10-5
0.001
VDS, DRAIN TO SOURCE VOLTAGE (V)
11050
0.01
1
100
10
0.1
0.1
ID, DRAIN CURRENT (A)
DC
5ms
100ms
1s
10ms
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
VDSS(MAX) = 12V
TJ = MAX RATED
TA = 25oC
t, PULSE WIDTH (s)
300
10
1
10-5 10-4 10-3 10-2 10-1 100101
VGS = 5V
100
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25 150 - TA
125
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TA = 25oC
RF1K49211
8-132
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. SWITCHING TIME vs GATE TO SOURCE
RESISTANCE FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
(Continued)
1 10 100
10
0.1
50
1
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 150oC
STARTING TJ = 25oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.01 0
10
20
30
012345
VGS = 3V
40
50
VGS = 4V
ID, DRAIN CURRENT (A)
VGS = 10V
VGS = 5V
VGS = 2.5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
023451
0
10
20
30
40
50
150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 10V
ID(ON), ON-STATE DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
-55oC
25oC
50
100
150
200
03.52.5 43
VGS, GATE TO SOURCE VOLTAGE (V)
rDS(ON), ON-STATE RESISTANCE (mΩ)
2 4.5 5
ID = 3.5A
ID = 7.0A
ID = 15A
ID = 1.75A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 10V
VDD = 6V, ID = 7A, RL= 0.86Ω
0
100
200
250
01020304050
300
350
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE (Ω)
tf
tr
td(OFF)
td(ON)
150
50
0.0
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
NORMALIZED ON RESISTANCE
TJ, JUNCTION TEMPERATURE (oC)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 5V, ID = 7A
RF1K49211
8-133
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
Typical Performance Curves
(Continued)
-80 -40 0 40 80 120 160
0.6
0.8
1.0
1.2
NORMALIZED GATE
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA1.2
1.1
1.0
0.9
0.8
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
3500
3000
1000
00246810
C, CAPACITANCE (pF)
2500
VDS, DRAIN TO SOURCE VOLTAGE (V)
CISS
COSS
CRSS
2000
500
1500
12
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
12
9
6
3
0
20IG REF()
IG ACT()
----------------------t, TIME (µs) 80IGREF()
IGACT()
----------------------
5.00
3.75
2.50
1.25
0
RL = 1.71Ω
IG(REF) = 0.75mA
VGS = 5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS VDD = BVDSS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RF1K49211
8-134
Soldering Precautions
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which
the devices are subjected.
1. Always preheat the device.
2. Thedeltatemperaturebetweenthepreheatandsoldering
should always be less than 100oC. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
3. Themaximumtemperaturegradientshouldbelessthan5oC
per second when changing from preheating to soldering.
4. Thepeak temperatureinthe solderingprocess shouldbe
at least 30oC higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
exceed 260oC for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
7. During cooling, mechanical stress or shock should be
avoided.
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
FIGURE 20. GATE CHARGE TEST CIRCUIT FIGURE 21. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms
(Continued)
VGS
RL
RGS
DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10V
VDS
VGS
IG(REF)
0
0
RF1K49211
8-135
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
PSPICE Electrical Model
SUBCKT RF1K49211 2 1 3 ; rev 6/26/96
CA 12 8 2.11e-9
CB 15 14 2.99e-9
CIN 6 8 1.30e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 15.81
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 2.37e-10
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.50e-3
RGATE 9 20 1.57
RLDRAIN 2 5 10
RLGATE 1 9 10.4
RLSOURCE 3 7 2.37
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 11.42e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),3))}
.MODEL DBODYMOD D (IS = 1.36e-12 RS = 1.65e-2 TRS1 = 3.88e-3 TRS2 = -5.45e-6 CJO = 2.95e-9 TT = 2.70e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 2.75e-3 TRS1 = -5.01e-4 TRS2 = -1.60e-4)
.MODEL DPLCAPMOD D (CJO = 2.40e-9 IS = 1e-30 N = 10 M = 0.55)
.MODEL MMEDMOD NMOS (VTO = 1.62 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.57)
.MODEL MSTROMOD NMOS (VTO = 2.08 KP = 98.0 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.402 KP = 0.067 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 15.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 8.51e-4 TC2 = 7.88e-7)
.MODEL RDRAINMOD RES (TC1 = 1.55e-2 TC2 = 5.78e-5)
.MODEL RSLCMOD RES (TC1 =1.02e-4 TC2 = 1.07e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.20e-3 TC2 = -7.29e-6)
.MODEL RVTEMPMOD RES (TC1 = -5.10e-4 TC2 = 8.07e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.1 VOFF = -1.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF = -4.1)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 2.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.5 VOFF = -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RF1K49211
