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1
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32
X
S04
ISSI®
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip
Package (MCP) — 32 Mbit Simultaneous Operation Flash
Memory and 4 Mbit Static RAM PRELIMINARY INFORMATION
AUGUST 2002
MCP FEATURES
•Power supply voltage 2.7V to 3.3V
•High performance:
Flash: 70ns maximum access time
SRAM: 70ns maximum access time
•Package: 73-ball BGA
•Operating Temperature: -40C to +85C
FLASH FEATURES
•Power Dissipation:
Read Current at 1 Mhz: 7 mA maximum
Read Current at 5 Mhz: 18 mA maximum
Sleep Mode: 5 µA maximum
•Simultaneous Read and Write Operations:
Zero latency between read and write operations; Data
can be programmed or erased in one bank while data
is simultaneously being read from the other bank
•Low-Power Mode:
A period of no activity causes flash to enter a
low-power state
•Erase Suspend/Resume:
Suspends of erase activity to allow a read in the
same bank
•Sector Erase Architecture:
8 words of 4k size and 63 words of 32K size (32 Mbit)
Any combination of sectors, or the entire flash can
be simultaneously erased
•Erase Algorithms:
Automatically preprograms/erases the flash memory
entirely, or by sector
•Program Algorithms:
Automatically writes and verifies data at specified
address
•Hidden ROM Region:
64KB with a Factory-serialized secure electronic
serial number (ESN), which is accessible through a
command sequence
•Data Polling and Toggle Bit:
Allow for detection of program or erase cycle
completion
•Ready-Busy output (RY/BY)
Detection of program or erase cycle completion
•Over 100,000 write/erase cycles
•Low supply voltage (Vccf ≤ 2.5V) inhibits writes
•WP/ACC input pin:
If VIL, allows protection of boot sectors
If VIH, allows removal of boot sector protection
If Vacc, program time is reduced by 40%
•Boot sector: Top or Bottom
SRAM FEATURES (4 Mb density)
•Power Dissipation:
Operating: 40 mA maximum
Standby: 7 µA maximum
•Chip Selects: CE1s, CE2s
•Power down feature using CE1s, or CE2s
•Data retention supply voltage: 1.5 to 3.3 volt
•Byte data control: LBs (DQ0–DQ7), UBs
(DQ8–DQ15) — in x16 mode
GENERAL DESCRIPTION
The flash and SRAM MCP is available in 32 Mbit Flash/4
Mbit SRAM having a data bus of either x8 or x16. The 32
Mbit flash is composed of 2,097,152 words of 16 bits or
4,194,304 bytes of 8 bits. The 4Mb SRAM has 262,144
words of 16 bits or 524,288 bytes of 8 bits. Data lines DQ0-
DQ7 handle the x8 format, while lines DQ0-DQ15 handle
the x16 format.
The package uses a 3.0V power supply for all operations.
No other source is required for program and erase opera-
tions. The flash can be programmed in system using this
3.0V supply, or can be programmed in a standard EPROM
programmer.
The 32 Mbit flash/4 Mbit SRAM is offered in a 73-pin BGA
package. The flash is compatible with the JEDEC Flash
command set standard . The flash access time is 70ns or
85ns and the SRAM access time is 70ns or 85ns.
The Flash architecture is composed of two banks which
allows simultaneous operation on each. Optimized per-
formance can be achieved by first initializing a program or
erase function in one bank, then immediately starting a
read from the other bank. Both operations would then be
operating simultaneously, with zero latency.
2
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
LOGIC SYMBOL
MCP BLOCK DIAGRAM
A0-A20, A-1
SA
CEf
CE1s
CE2s
OE
WE
WP/ACC
RESET
UBs
LBs
I/Of
I/Os
DQ0-DQ15
22
16 or 8
RY/BY
GND
GND
V
CCf
RY/BY
4-MBIT
Static RAM
32-MBIT
Flash Memory DQ0-DQ15/A-1
A0-A20
A0-A20
A-1
WP/ACC
RESET
CEf
I/Of
SA
LBs
UBs
WE
OE
CE1s
CE2s
I/Os
DQ0-DQ15
A0-A17
V
CCS
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH MEMORY BLOCK DIAGRAM
STATE CONTROL
&
COMMAND REGISTER
RESET
WE
CE
BYTE
WP/ACC
DQ0-DQ15
A0-A20
A0-A20
A0-A20
A0-A20
A0-A20
Lower Bank Address
Upper Bank Address
Y -Decoder
Latches and
Control Logic
Lower
Bank
Upper
Bank
X-Decoder
Y -Decoder
Latches and
Control Logic
X-Decoder
Status
Control
DQ0-DQ15
DQ0-DQ15
DQ0-DQ15
OE BYTE
OE BYTE
V
CC
GND
RY/BY
Organization Type Bank 1 Size Bank 2 Size Boot Block
Type A 4Mb 28Mb Top
Type B 8Mb 24Mb Top
Type C 16Mb 16Mb Top
Type D 4Mb 28Mb Bottom
Type E 8Mb 24Mb Bottom
Type F 16Mb 16M b Bottom
FLASH BANK ORGANIZATION
Note:
For device part number, see Part Number Logic Diagram or Ordering Information
4
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
PIN DESCRIPTIONS
A0-A17 Address Inputs, Common
A18-A20, A-1 Address Inputs, Flash
DQ0-DQ15/A-1 Data Inputs/Outputs
RESET Reset
CE1s, CE2s Chip Selects, SRAM
I/Of I/O Configuration, Flash
CEf Chip Enable Input, Flash
OE Output Enable Input
WE Write Enable Input
I/Os I/O Configuration, SRAM
LBsLower-byte Control(DQ0-DQ7), SRAM
UBsUpper-byte Control (DQ8-DQ15), SRAM
WP/ACC Write Protect/Acceleration Pin,
Flash
RY/BY Ready/Busy Output
SA High Order Address Pin, SRAM (x8)
NC No Connection
Vccf Power, Flash
Vccs Power, SRAM
GND Ground
PIN CONFIGURATION (32 Mb Flash and 4 Mb SRAM)
PACKAGE CODE:
B 73 BALL FBGA (Top View) (8.00 mm x 11.60 mm Body, 0.8 mm Ball Pitch)
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
L
M
N
C
N
C
N
C
N
C
N
C
N
C
N
C
A
3
A2
A1
A
0
CE
f
CE
1
S
A7
A
6
A
5
A4
V
ss
OE
DQ0
Q
D
Q8
LB
UB
A1
8
A17
DQ1
Q
DQ9
Q
DQ10
Q
D
Q2
NC
/
RE
S
E
T
RY/
BY
/
D
Q3
V
ccf
DQ1
1
NC
N
C
WE
C
E2
s
A2
0
D
Q4
V
ccS
I
/
O
s
N
C
A
8
A1
9
A
9
A1
0
D
Q6
D
Q
1
3
D
Q
1
2
D
Q5
A11
A12
A1
3
A14
SA
D
Q7
D
Q
1
4
A1
5
N
C
N
C
A1
6
I
/Of
G
N
D
N
C
N
C
N
C
N
C
N
C
N
C
Shared
Flash Onl
y
SRAM Onl
y
*
D
Q
15/A-
1
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
OPERATION(1,3) CECE
CECE
CEfCECE
CECE
CE1s CE2s OEOE
OEOE
OE WEWE
WEWE
WE SA(6) LBLB
LBLB
LBsUBUB
UBUB
UBsDQ
0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WPWP
WPWP
WP
/ACC(5)
Full Standby H H X X XXXX High-Z High-Z H X
HXLX XXXX High-Z High-Z H X
Output Disable H L H H H X X X High-Z High-Z H X
H L H X X X H H High-Z High-Z H X
L H X H H X X X High-Z High-Z H X
L X L H H X X X High-Z High-Z H X
Read from Flash(2) LHXL HXXX DOUT DOUT HX
LXLL HXXX DOUT DOUT HX
Write to Flash L H X H L X X X DIN DIN HX
LXLHLXXX DIN DIN HX
Read from SRAM H L H L H X L L DOUT DOUT HX
H L H L H X H L High-Z DOUT HX
HLHL HXLH DOUT High-Z H X
Write to SRAM H L H X L X L L DIN DIN HX
H L H X L X H L High-Z DIN HX
HLHX LXLH DIN High-Z H X
Temporary Sector X X X X XXXX X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X XXXX High-Z High-Z L X
Reset X X L X XXXX High-Z High-Z L X
Boot Block Sector X X X X XXXX X X X L
Write Protection
Notes:
1. Any operations not indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. SA: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS
User Bus Operations (Flash=Word mode: I/Of = Vccf, SRAM= Word Mode: I/Os = Vccs)
6
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
OPERATION(1,3) CECE
CECE
CEfCE1CE1
CE1CE1
CE1sCE2s DQ15/A-1 OEOE
OEOE
OE WEWE
WEWE
WE SA(6) LBLB
LBLB
LBsUBUB
UBUB
UBsDQ0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WP/A CC(5)
Full Standby H H X X X X X X X High-Z High-Z H X
H X L X X X X X X High-Z High-Z H X
Output Disable H L H X H H X X X High-Z High-Z H X
H L H X X X X H H High-Z High-Z H X
L H X A-1 H H X X X High-Z High-Z H X
L X L A-1 H H X X X High-Z High-Z H X
Read from Flash(2) L H X A-1 L H X X X DOUT DOUT HX
L X L A-1 L H X X X DOUT DOUT HX
Write to Flash L H X A-1 H L X X X DIN DIN HX
L X L A-1 H L X X X DIN DIN HX
Read from SRAM H L H X L H X L L DOUT DOUT HX
H L H X L H X H L High-Z DOUT HX
HLH XLHXLH DOUT High-Z H X
Write to SRAM H L H X X L X L L DIN DIN HX
H L H X X L X H L High-Z DIN HX
HLH XXLXLH DIN High-Z H X
Temporary Sector X X X X X X X X X X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X X X X X X High-Z High-Z L X Re-
set X X L X X X X X X High-Z High-Z L X
Boot Block Sector X X X X X X X X X X X X L
Write Protection
Notes:
1. Any operations not indicated this column are inhibited..
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. LBs, UBs: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS
User Bus Operations (Flash=BYTE mode: I/Of = GND, SRAM= Word Mode: I/Os = Vccs)
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
OPERATION(1,3) CECE
CECE
CEfCECE
CECE
CE1s CE2s OEOE
OEOE
OE WEWE
WEWE
WE SA LBLB
LBLB
LBs(6) UBUB
UBUB
UBs(6) DQ0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WPWP
WPWP
WP
/ACC(5)
Full Standby H H X X XXXX High-Z High-Z H X
HXLX XXXX High-Z High-Z H X
Output Disable H L H H H X X X High-Z High-Z H X
H L H X X X H H High-Z High-Z H X
L H X H H X X X High-Z High-Z H X
L X L H H X X X High-Z High-Z H X
Read from Flash(2) LHXL HXXX DOUT DOUT HX
LXLL HXXX DOUT DOUT HX
Write to Flash L H X H L X X X DIN DIN HX
LXLHLXXX DIN DIN HX
Read from SRAM H L H L H SA X X DOUT High-Z H X
Write to SRAM H L H X L SA X X DIN High-Z H X
Temporary Sector X X X X XXXX X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X XXXX High-Z High-Z L X
Reset X X L X XXXX High-Z High-Z L X
Boot Block Sector X X X X XXXX X X X L
Write Protection
DEVICE BUS OPERATIONS
User Bus Operations (Flash=WORD mode: I/Of = Vccf, SRAM= Byte Mode: I/Os = GND
Notes:
1. Any operations not indicated this column are inhibited..
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. LBs, UBs: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
8
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Notes:
1. Any operations not indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH all at once.
4. It is also used for the extended sector group protections.
5. WP/ACC = VIL: protection of boot sectors.
WP/ACC = VIH: removal of boot sectors protection.
WP/ACC = VACC (9V): Program time will reduce by 40%.
6. LBs, UBs: Don’t care or open.
7. L = VIL, H = VIH, X = VIL or VIH.
8. See DC CHARACTERISTICS.
DEVICE BUS OPERATIONS
User Bus Operations (Flash=Byte mode: I/Of = GND, SRAM= Byte Mode: I/Os = GND)
OPERATION(1,3) CE CE
CE CE
CEf
CE1 CE1
CE1 CE1
CE1s CE2s DQ15/A-1 OEOE
OEOE
OE WEWE
WEWE
WE SA LBLB
LBLB
LBs(6)UBUB
UBUB
UBs(6) DQ0-DQ7DQ8-DQ15 RESETRESET
RESETRESET
RESET WP/ACC(5)
Full Standby H H X X X X X X X High-Z High-Z H X
H X L X X X X X X High-Z High-Z H X
Output Disable H L H X H H X X X High-Z High-Z H X
H L H X X X X H H High-Z High-Z H X
L H X A-1 H H X X X High-Z High-Z H X
L X L A-1 H H X X X High-Z High-Z H X
Read from Flash(2) L H X A-1 L H X X X DOUT DOUT HX
LX LA-1LHXXX DOUT DOUT HX
Write to Flash L H X A-1 H L X X X DIN DIN HX
LX LA-1HL XXX DIN DIN HX
Read from SRAM H L H X L H SA X X DOUT High-Z H X
Write to SRAM H L H X X L SA X X DIN High-Z H X
Temporary Sector X X X X X X X X X X X VID(8) X
Group Unprotection(4)
Flash Hardware X H X X X X X X X High-Z High-Z L X
Reset X X L X X X X X X High-Z High-Z L X
Boot Block Sector X X X X X X X X X X X X L
Write Protection
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH - TOP BOOT SECTOR ADDRESS
Sector Sector
Type Type Type Sector Address Size (x8) (x16)
C B A A20-A12 KB/KW Address Range Address Range
Bank2 Bank2 Bank2 SA0 000000xxx 64/32 000000h–00FFFFh 000000h–007FFFh
Bank2 Bank2 Bank2 SA1 000001xxx 64/32 010000h–01FFFFh 008000h–00FFFFh
Bank2 Bank2 Bank2 SA2 000010xxx 64/32 020000h–02FFFFh 010000h–017FFFh
Bank2 Bank2 Bank2 SA3 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
Bank2 Bank2 Bank2 SA4 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
Bank2 Bank2 Bank2 SA5 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
Bank2 Bank2 Bank2 SA6 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
Bank2 Bank2 Bank2 SA7 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
Bank2 Bank2 Bank2 SA8 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh
Bank2 Bank2 Bank2 SA9 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
Bank2 Bank2 Bank2 SA10 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
Bank2 Bank2 Bank2 SA11 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
Bank2 Bank2 Bank2 SA12 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
Bank2 Bank2 Bank2 SA13 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
Bank2 Bank2 Bank2 SA14 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
Bank2 Bank2 Bank2 SA15 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
Bank2 Bank2 Bank2 SA16 010000xxx 64/32 100000h–10FFFFh 080000h–087FFFh
Bank2 Bank2 Bank2 SA17 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
Bank2 Bank2 Bank2 SA18 010010xxx 64/32 120000h–12FFFFh 090000h–097FFFh
Bank2 Bank2 Bank2 SA19 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
Bank2 Bank2 Bank2 SA20 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
Bank2 Bank2 Bank2 SA21 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
Bank2 Bank2 Bank2 SA22 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
Bank2 Bank2 Bank2 SA23 010111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
Bank2 Bank2 Bank2 SA24 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
Bank2 Bank2 Bank2 SA25 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
Bank2 Bank2 Bank2 SA26 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
Bank2 Bank2 Bank2 SA27 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh
Bank2 Bank2 Bank2 SA28 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
Bank2 Bank2 Bank2 SA29 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
10
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH - TOP BOOT SECTOR ADDRESS (Continued)
Sector Sector
Type Type Type Sector Address Size (x8) (x16)
C B A A20-A12 KB/KW Address Range Address Range
Bank2 Bank2 Bank2 SA30 011110xxx 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh
Bank2 Bank2 Bank2 SA31 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
Bank1 Bank2 Bank2 SA32 100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh
Bank1 Bank2 Bank2 SA33 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
Bank1 Bank2 Bank2 SA34 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
Bank1 Bank2 Bank2 SA35 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
Bank1 Bank2 Bank2 SA36 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
Bank1 Bank2 Bank2 SA37 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
Bank1 Bank2 Bank2 SA38 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
Bank1 Bank2 Bank2 SA39 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
Bank1 Bank2 Bank2 SA40 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
Bank1 Bank2 Bank2 SA41 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
Bank1 Bank2 Bank2 SA42 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
Bank1 Bank2 Bank2 SA43 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
Bank1 Bank2 Bank2 SA44 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
Bank1 Bank2 Bank2 SA45 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
Bank1 Bank2 Bank2 SA46 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
Bank1 Bank2 Bank2 SA47 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
Bank1 Bank1 Bank2 SA48 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
Bank1 Bank1 Bank2 SA49 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
Bank1 Bank1 Bank2 SA50 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
Bank1 Bank1 Bank2 SA51 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
Bank1 Bank1 Bank2 SA52 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
Bank1 Bank1 Bank2 SA53 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
Bank1 Bank1 Bank2 SA54 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
Bank1 Bank1 Bank2 SA55 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
Bank1 Bank1 Bank1 SA56 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
Bank1 Bank1 Bank1 SA57 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
Bank1 Bank1 Bank1 SA58 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Note:
The address range is A20:A-1 in byte mode (I/Of=VIL ) or A20:A0 in word mode (I/Of=VIH ). The bank address
bits are A20–A18 for Type A, A20 and A19 for Type B, and A20 for Type C.
Device Sector
Address Size (x8) (x16)
A20-A12 KB/KW Address Range Address Range
Type C Type B Type A 111111xxx 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh
FLASH - TOP BOOT SECURITY SECTOR ADDRESSES
(Hidden-ROM)
Sector Sector
Type Type Type Sector Address Size (x8) (x16)
C B A A20-A12 KB/KW Address Range Address Range
Bank1 Bank1 Bank1 SA59 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
Bank1 Bank1 Bank1 SA60 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
Bank1 Bank1 Bank1 SA61 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
Bank1 Bank1 Bank1 SA62 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
Bank1 Bank1 Bank1 SA63 111111000 8/4 3F0000h–3F1FFFh 1F8000h–1F8FFFh
Bank1 Bank1 Bank1 SA64 111111001 8/4 3F2000h–3F3FFFh 1F9000h–1F9FFFh
Bank1 Bank1 Bank1 SA65 111111010 8/4 3F4000h–3F5FFFh 1FA000h–1FAFFFh
Bank1 Bank1 Bank1 SA66 111111011 8/4 3F6000h–3F7FFFh 1FB000h–1FBFFFh
Bank1 Bank1 Bank1 SA67 111111100 8/4 3F8000h–3F9FFFh 1FC000h–1FCFFFh
Bank1 Bank1 Bank1 SA68 111111101 8/4 3FA000h–3FBFFFh 1FD000h–1FDFFFh
Bank1 Bank1 Bank1 SA69 111111110 8/4 3FC000h–3FDFFFh 1FE000h–1FEFFFh
Bank1 Bank1 Bank1 SA70 111111111 8/4 3FE000h–3FFFFFh 1FF000h–1FFFFFh
FLASH - TOP BOOT SECTOR ADDRESS (Continued)
12
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Sector Sector
Type Type Type Sector Address Size (x8) (x16)
F E D A20-A12 KB/KW Address Range Address Range
Bank1 Bank1 Bank1 SA0 000000000 8/4 000000h–001FFFh 000000h–000FFFh
Bank1 Bank1 Bank1 SA1 000000001 8/4 002000h–003FFFh 001000h–001FFFh
Bank1 Bank1 Bank1 SA2 000000010 8/4 004000h–005FFFh 002000h–002FFFh
Bank1 Bank1 Bank1 SA3 000000011 8/4 006000h–007FFFh 003000h–003FFFh
Bank1 Bank1 Bank1 SA4 000000100 8/4 008000h–009FFFh 004000h–004FFFh
Bank1 Bank1 Bank1 SA5 000000101 8/4 00A000h–00BFFFh 005000h–005FFFh
Bank1 Bank1 Bank1 SA6 000000110 8/4 00C000h–00DFFFh 006000h–006FFFh
Bank1 Bank1 Bank1 SA7 000000111 8/4 00E000h–00FFFFh 007000h–007FFFh
Bank1 Bank1 Bank1 SA8 000001xxx 64/32 010000h–01FFFFh 008000h–00FFFFh
Bank1 Bank1 Bank1 SA9 000010xxx 64/32 020000h–02FFFFh 010000h–017FFFh
Bank1 Bank1 Bank1 SA10 000011xxx 64/32 030000h–03FFFFh 018000h–01FFFFh
Bank1 Bank1 Bank1 SA11 000100xxx 64/32 040000h–04FFFFh 020000h–027FFFh
Bank1 Bank1 Bank1 SA12 000101xxx 64/32 050000h–05FFFFh 028000h–02FFFFh
Bank1 Bank1 Bank1 SA13 000110xxx 64/32 060000h–06FFFFh 030000h–037FFFh
Bank1 Bank1 Bank1 SA14 000111xxx 64/32 070000h–07FFFFh 038000h–03FFFFh
Bank1 Bank1 Bank2 SA15 001000xxx 64/32 080000h–08FFFFh 040000h–047FFFh
Bank1 Bank1 Bank2 SA16 001001xxx 64/32 090000h–09FFFFh 048000h–04FFFFh
Bank1 Bank1 Bank2 SA17 001010xxx 64/32 0A0000h–0AFFFFh 050000h–057FFFh
Bank1 Bank1 Bank2 SA18 001011xxx 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
Bank1 Bank1 Bank2 SA19 001100xxx 64/32 0C0000h–0CFFFFh 060000h–067FFFh
Bank1 Bank1 Bank2 SA20 001101xxx 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
Bank1 Bank1 Bank2 SA21 001110xxx 64/32 0E0000h–0EFFFFh 070000h–077FFFh
Bank1 Bank1 Bank2 SA22 001111xxx 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
Bank1 Bank2 Bank2 SA23 010000xxx 64/32 100000h–10FFFFh 080000h–087FFFh
Bank1 Bank2 Bank2 SA24 010001xxx 64/32 110000h–11FFFFh 088000h–08FFFFh
Bank1 Bank2 Bank2 SA25 010010xxx 64/32 120000h–12FFFFh 090000h–097FFFh
Bank1 Bank2 Bank2 SA26 010011xxx 64/32 130000h–13FFFFh 098000h–09FFFFh
Bank1 Bank2 Bank2 SA27 010100xxx 64/32 140000h–14FFFFh 0A0000h–0A7FFFh
Bank1 Bank2 Bank2 SA28 010101xxx 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
Bank1 Bank2 Bank2 SA29 010110xxx 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
FLASH - BOTTOM BOOT SECTOR ADDRESS
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Sector Sector
Type Type Type Sector Address Size (x8) (x16)
F E D A20-A12 KB/KW Address Range Address Range
Bank1 Bank2 Bank2 SA30 010111xxx 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
Bank1 Bank2 Bank2 SA31 011000xxx 64/32 180000h–18FFFFh 0C0000h–0C7FFFh
Bank1 Bank2 Bank2 SA32 011001xxx 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
Bank1 Bank2 Bank2 SA33 011010xxx 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
Bank1 Bank2 Bank2 SA34 011011xxx 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
Bank1 Bank2 Bank2 SA35 011100xxx 64/32 1C0000h–1CFFFFh 0E0000h–0E7FFFh
Bank1 Bank2 Bank2 SA36 011101xxx 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
Bank1 Bank2 Bank2 SA37 011110xxx 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh
Bank1 Bank2 Bank2 SA38 011111xxx 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
Bank2 Bank2 Bank2 SA39 100000xxx 64/32 200000h–20FFFFh 100000h–107FFFh
Bank2 Bank2 Bank2 SA40 100001xxx 64/32 210000h–21FFFFh 108000h–10FFFFh
Bank2 Bank2 Bank2 SA41 100010xxx 64/32 220000h–22FFFFh 110000h–117FFFh
Bank2 Bank2 Bank2 SA42 100011xxx 64/32 230000h–23FFFFh 118000h–11FFFFh
Bank2 Bank2 Bank2 SA43 100100xxx 64/32 240000h–24FFFFh 120000h–127FFFh
Bank2 Bank2 Bank2 SA44 100101xxx 64/32 250000h–25FFFFh 128000h–12FFFFh
Bank2 Bank2 Bank2 SA45 100110xxx 64/32 260000h–26FFFFh 130000h–137FFFh
Bank2 Bank2 Bank2 SA46 100111xxx 64/32 270000h–27FFFFh 138000h–13FFFFh
Bank2 Bank2 Bank2 SA47 101000xxx 64/32 280000h–28FFFFh 140000h–147FFFh
Bank2 Bank2 Bank2 SA48 101001xxx 64/32 290000h–29FFFFh 148000h–14FFFFh
Bank2 Bank2 Bank2 SA49 101010xxx 64/32 2A0000h–2AFFFFh 150000h–157FFFh
Bank2 Bank2 Bank2 SA50 101011xxx 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
Bank2 Bank2 Bank2 SA51 101100xxx 64/32 2C0000h–2CFFFFh 160000h–167FFFh
Bank2 Bank2 Bank2 SA52 101101xxx 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
Bank2 Bank2 Bank2 SA53 101110xxx 64/32 2E0000h–2EFFFFh 170000h–177FFFh
Bank2 Bank2 Bank2 SA54 101111xxx 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
Bank2 Bank2 Bank2 SA55 110000xxx 64/32 300000h–30FFFFh 180000h–187FFFh
Bank2 Bank2 Bank2 SA56 110001xxx 64/32 310000h–31FFFFh 188000h–18FFFFh
Bank2 Bank2 Bank2 SA57 110010xxx 64/32 320000h–32FFFFh 190000h–197FFFh
Bank2 Bank2 Bank2 SA58 110011xxx 64/32 330000h–33FFFFh 198000h–19FFFFh
FLASH - BOTTOM BOOT SECTOR ADDRESS (Continued)
14
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH - BOTTOM BOOT SECTOR ADDRESS (Continued)
Sector Sector
Type Type Type Sector Address Size (x8) (x16)
F E D A20-A12 KB/KW Address Range Address Range
Bank2 Bank2 Bank2 SA59 110100xxx 64/32 340000h–34FFFFh 1A0000h–1A7FFFh
Bank2 Bank2 Bank2 SA60 110101xxx 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
Bank2 Bank2 Bank2 SA61 110110xxx 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
Bank2 Bank2 Bank2 SA62 110111xxx 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
Bank2 Bank2 Bank2 SA63 111000xxx 64/32 380000h–38FFFFh 1C0000h–1C7FFFh
Bank2 Bank2 Bank2 SA64 111001xxx 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
Bank2 Bank2 Bank2 SA65 111010xxx 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
Bank2 Bank2 Bank2 SA66 111011xxx 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
Bank2 Bank2 Bank2 SA67 111100xxx 64/32 3C0000h–3CFFFFh 1E0000h–1E7FFFh
Bank2 Bank2 Bank2 SA68 111101xxx 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
Bank2 Bank2 Bank2 SA69 111110xxx 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
Bank2 Bank2 Bank2 SA70 111111xxx 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh
Note:
The address range is A20:A-1 in byte mode (I/Of=VIL ) or A20:A0 in word mode (I/Of=VIH ). The bank address
bits are A20–A18 for Type D, A20 and A19 for Type E, and A20 for Type F.
FLASH - BOTTOM BOOT SECURITY SECTOR ADDRESSES
(Hidden-ROM)
Device Sector
Address Size (x8) (x16)
A20-A12 KB/KW Address Range Address Range
Type F Type E Type D 000000xxx 64/32 000000h-00FFFFh 000000h-007FFFh
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15
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 000000XXX SA0
01
SGA1 000010XXX SA1 to SA3
11
SGA2 0001XXXXX SA4 to SA7
SGA3 0010XXXXX SA8 to SA11
SGA4 0011XXXXX SA12 to SA15
SGA5 0100XXXXX SA16 to SA19
SGA6 0101XXXXX SA20 to SA23
SGA7 0110XXXXX SA24 to SA27
SGA8 0111XXXXX SA28 to SA31
SGA9 1000XXXXX SA32 to SA35
SGA10 1001XXXXX SA36 to SA39
SGA11 1010XXXXX SA40 to SA43
SGA12 1011XXXXX SA44 to SA47
SGA13 1100XXXXX SA48 to SA51
SGA14 1101XXXXX SA52 to SA55
SGA15 1110XXXXX SA56 to SA59
00
SGA16 111101XXX SA60 to SA62
10
SGA17 111111000 SA63
SGA18 111111001 SA64
SGA19 111111010 SA65
SGA20 111111011 SA66
SGA21 111111100 SA67
SGA22 111111101 SA68
SGA23 111111110 SA69
SGA24 111111111 SA70
SECTOR GROUP ADDRESS (TYPE A, TYPE B, TYPE C)
(Top Boot Block)
16
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Sector Group A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 000000000 SA0
SGA1 000000001 SA1
SGA2 000000010 SA2
SGA3 000000011 SA3
SGA4 000000100 SA4
SGA5 000000101 SA5
SGA6 000000110 SA6
SGA7 000000111 SA7
01
SGA8 000010XXX SA8 to SA10
11
SGA9 0001X XXXX SA11 to SA14
SGA10 0010XXXXX SA15 to SA18
SGA11 0011XXXXX SA19 to SA22
SGA12 0100XXXXX SA23 to SA26
SGA13 0101XXXXX SA27 to SA30
SGA14 0110XXXXX SA31 to SA34
SGA15 0111XXXXX SA35 to SA38
SGA16 1000XX XXX SA39 to SA42
SGA17 1001XX XXX SA43 to SA46
SGA18 1010XX XXX SA47 to SA50
SGA19 1011XX XXX SA51 to SA54
SGA20 1100XX XXX SA55 to SA58
SGA21 1101XX XXX SA59 to SA62
SGA22 1110XX XXX SA63 to SA66
00
SGA23 111101 XXX SA67 to SA69
10
SGA24 111111 XXX SA70
SECTOR GROUP ADDRESS (TYPE D, TYPE E, TYPE F)
(Bottom Boot Block)
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Type A12 to A19 A6A1A0A–1(1) Code (HEX)
Manufacturer’s Code X VIL VIL VIL VIL 04h
TYPE A Device ID Byte X VIL VIL VIH VIL 55h
Word X VIL VIL VIH X 2255h
TYPE D Device ID Byte X VIL VIL VIH VIL 56h
Word X VIL VIL VIH X 2256h
TYPE B Device ID Byte X VIL VIL VIH VIL 50h
Word X VIL VIL VIH X 2250h
TYPE E Device ID Byte X VIL VIL VIH VIL 53h
Word X VIL VIL VIH X 2253h
TYPE C Device ID Byte X VIL VIL VIH VIL 5Ch
Word X VIL VIL VIH X 225Ch
TYPE F Device ID Byte X VIL VIL VIH VIL 5Fh
Word X VIL VIL VIH X 225Fh
Sector Group Protect Sector VIL VIH VIL VIL 01h(2)
Group
Address
FLASH MEMORY AUTOSELECT CODES
Note:
1. A–1 is used for Byte mode.
2. Output 01h at protected sector address and output
00h at unprotected sector address.
18
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH MEMORY COMMAND DEFINITIONS
Note:
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
*2: This command is valid during Fast Mode.
*3: This command is valid while RESET=VID.
*4: The valid Address is A0 to A6.
*5: This command is valid during Hi-ROM mode.
*6: The data “00h” is also acceptable.
Command Sequence
Bus
6
1
1
3
2
2
4
1
3
4
6
4
Bus
Write
Cycle
Req'd
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus
Cycle Write Cycle Write Cycle Read/Write Cycle Cycle
—
PA
Data
Read / Reset * 1
Hidden-Rom Exit
* 5
Extended Sector
Group Protection
* 3
Set to Fast Mode
Fast Program * 2
Data
Data
2AAH
555H
—
Addr. Addr.
XXXH
BA
BA
555H
AAH
—
Addr. Addr.
Data
—
Addr.
Data
—
Addr.
——
—
Data
Read / Reset —
PA
SPA
XXXH
—
60H
F0H*6
—
SPA
—
—
PA
—
—
SPA
—
—
—
—
—
—
RA
—
—
—
—
—
—
—
—
—
—
55H
—
—
—
—
—
—
—
—
—
—
—
—
HRA
555H
AAAH
SA
—
—
—
—
—
—
—
—
—
30H
10H
—
—
—
30H
——
—
—
—
—
—
—
—
—
—
—
—
—
—
—
55H
55H
55H
55H
55H
—
—
55H
PD
F0H
AAH
AAH
AAH
AAH
F0H —
—
RD
—
AAH
PD
AAH
—
—
—
—
—
SD
—
—
PD
AAH
00H
A0H
80H
80H
—
—
20H
—
—
40H
—
88H
A0H
80H
90H
AAH
B0H
30H
—
555H
AAAH
—
—
XXXH
BA
XXXH
AAH
A0H
90H
60H
98h
AAh
AAH
AAH
AAH
55H
55H
55H
55H
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
55H
AAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
2AAH
555H
555H
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
(HRBA)
2AAH
555H
2AAH
555H
2AAH
555H
555H
AAAH
555H
AAAH
555H
AAAH
XXXH
Reset from Fast
Mode * 2
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
555H
AAAH
Autoselect
Program
Chip Erase
Sector Erase
Sector Erase
Suspend
Sector Erase
Resume
Query * 4
Hidden-ROM
Entry
Hidden-ROM
Program
* 5
Hidden-ROM
Erase
* 5
90H
—
—
55H
55H
—
(BA)
AAAH
(HRBA)
AAAH
555H
AAAH
3
3
4
6
(BA)
1
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19
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
MCP ABSOLUTE MAXIMUM RATINGS(1,2,3)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +125 °C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for Data, –0.3 to VCCf + 0.4 V
Address and Control Pins –0.3 to VCCs + 0.4 V
VIN RESET(5) -0.5 TO +13.0 V
VIN WP/ACC(6) -0.5 TO +10.5 V
VCCf/VCCs Voltage on Vcc Supply Relative to GND(4) –0.3 to 4.0 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions
may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
4. Minimum DC voltage on input or I/O pins is –0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for
periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.3 V or VCCs+0.3 V. During voltage transitions, input or
I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns.
5. Minimum DC input voltage on RESET pin is –0.5 V. During voltage transitions, RESET pin may undershoot VSS to –2.0 V for periods
of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed 9.0 V. Maximum DC input
voltage on RESET pin is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
6. Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to –2.0 V for
periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0V for periods of up
to 20 ns, when VCCf is applied.
Type D, Type E, Type F, (Bottom Boot Type)
Word mode: 000000h to 007FFFh
Byte mode: 000000h to 00FFFFh
HRBA = Bank address of the Hidden-ROM area
Type A, Type B, Type C, (Top Boot Type) :
A15 = A16 = A17 = A18 = A19 = A20 = 1
Type D, Type E, Type F, (Bottom Boot Type) :
A15 = A16 = A17 = A18 = A19 = A20 = 0
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA.
SD = Sector protection verify data.
Output 01h at protected sector addresses and output 00h at
unprotected sector addresses.
The system should generate the following address patterns;
Word mode : 555h or 2AAh to addresses A0 to A10
Byte mode : AAAh or 555h to addresses A–1 and A0 to A10
Address bits A11 to A20 = X = “H” or “L” for all address
commands except for Program Address (PA), Sector Address
(SA),and Bank Address (BA).
Bus operations are defined in “Device Bus Operations”.
RA = Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased.
The combination of A20 , A19, A18 , A17 , A16 , A15 , A14 ,
A13 , and A12 will uniquely select any sector.
BA = Bank address (A15 to A20 )
SPA = Sector group address to be protected.
Set sector group address (SGA) and (A6 , A1 , A0 ) = (0, 1, 0)
for protect; or SGA and (A6, A1, A0) = (1, 1, 0) for unprotect.
HRA= Address of the Hidden-ROM area
Type A, Type B, Type C, (Top Boot Type)
Word mode: 1F8000h to 1FFFFFh
Byte mode: 3F0000h to 3FFFFFh
20
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
MCP OPERATING RANGE
Range Ambient Temperature VCCF,VCCS
Industrial –40°C to +85°C 2.7–3.3V
CAPACITANCE(1)
Symbol Parameter Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 11 14 pF
COUT Output Capacitance VOUT = 0V 12 16 pF
CIN2 Control Pin Capacitance VIN = 0V 14 16 pF
CIN3WP/ACC Pin Capacitance VIN = 0V 21.5 26 pF
Notes:
1. Test conditions: TA = 25°C, f = 1 MHz
STANDARD VOLTAGE RANGE: VCC = 2.7-3.3 V
FLASH
MEMORY SRAM UNITS
Max Access Time 70 85 70 85 ns
CE Access 70 85 70 85 ns
OE Access 30 35 35 45 ns
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21
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Symbol Parameter Test Conditions Min. Max. Unit
ILI Input Leakage VIN=VSS to VCCf, VCCs -1.0 1.0 µA
ILO Output Leakage VOUT=VSS to VCCf, VCCs -1.0 1.0 µA
VIL Input Low Level -0.2 0.5 V
VIH Input High Level 2.4 VCC + 0.3(2) V
VID Voltage for Sector 11.5 12.5 V
Protection, and Temporar y
Sector Unprotection (RESET)(1)
VACC Voltage for Program 8.5 9.5 V
Acceleration ( WP/ACC)(1)
VOL Output Low Level VCCf = VCCf min., VCCS=VCCS min. — 0.4 V
IOL = 1.0mA
VOH Output High Level VCCf = VCCf min., VCCS=VCCS min. 2.4 — V
IOH = -0.5mA
VLKO Flash Low Vccf 2.3 2.5 V
Notes:
1. Applicable for only VCCf applying.
2. VCC indicates lower of VCCf or VCCs.
MCP DC CHARACTERISTICS
22
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH DC CHARACTERISTICS
Symbol Parameter Test Conditions Min. Max. Unit
ILIT RESET Inputs VCCf=VCCf max., VCCs=VCCs max. — 35 µA
Leakage Current RESET = 12.5V
ILIA ACC Inputs VCCf=VCCf max., VCCs=VCCs max. — 20 µA
Leakage Current WP/ACC = Vacc max.
ICC1f FLASH Vcc (1) CEf=VIL tCycle = 5Mhz Byte — 16 mA
Active Current (Read) OE=VIH tCycle = 5Mhz Word — 18
tCycle = 1Mhz Byte — 7
tCycle = 1Mhz Word — 7
ICC2f FLASH Vcc Active(2) CEf=VIL —35mA
Current(Program/Erase) OE=VIH
ICC3f FLASH Vcc Active(4) CEf=VIL Byte — 51 mA
Current OE=VIH Word 53
(Read-While-Program)
ICC4f FLASH Vcc Active(4) CEf=VIL Byte — 51 mA
Current OE=VIH Word 53
(Read-While-Erase)
ICC5f FLASH Vcc Active CEf=VIL —35mA
Current OE=VIH
(Erase-Suspend-Program)
ISB1f FLASH Vcc VCCf = Vcc max, CEf= VCCf = + 0.3V — 5 µA
Standby Current RESET, CEf, WP/ACC = VCCf = + 0.3V
ISB2f FLASH Vcc VCCf = Vcc max, RESET= VSS = + 0.3V — 5 µA
Standby Current WP/ACC = VCCf = + 0.3V
(RESET)
ISB3f FLASH Vcc(3) VCCf = Vcc max. CEf, = VSS = + 0.3V — 5 µA
Standby Current RESET, WP/ACC = VCCf = + 0.3V
(Auto Sleep Mode) VIN = VCCf + 0.3V OR VSS + 0.3V
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns..
4. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
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23
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Parameter Symbol Condition Min Unit
CE Recover Time _ tCCR _0ns
CE Hold Time _ tCHOLD _3ns
AC CHARACTERISTICS - CE CE
CE CE
CE TIMING
Timing Diagram for Alternating SRAM to Flash
CEf
CE1s
CE2s
t
CCR
t
CCR
t
CCR
t
CCR
t
CHOLD
t
CHOLD
WE
24
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH READ ONLY SWITCHING CHARACTERISTICS
(Over Operating Range)
Symbol Parameter Min. Max. Min. Max. Unit
tRC Cycle Time 70 85 — ns
tACC Address to Output Delay — 7 0 — 85 ns
tCE Chip Enable to Output Delay — 7 0 — 85 ns
tOE Output Enable to Output Delay — 3 0 — 35 ns
tDF Chip Enable to Output High-Z — 2 5 — 30 ns
tDF Output Enable to Output High-Z — 2 5 — 30 ns
tOH Output Hold Time from Addresses, 0 — 0 — ns
CEf or OE, Whichever Occurs First
tREADY RESET Pin Low to Read Mode — 2 0 — 2 0 µs
FLASH AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load 1 TTL gate and 30pF
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25
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH READ CYCLE
Address
DQ
CEf
OE
WE
Address Stable
Output valid High-Z
High-Z
t
OEH
t
RC
t
OE
t
DF
t
CE
t
OEH
t
OH
26
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH HARDWARE RESETRESET
RESETRESET
RESET / READ OPERATION TIMING DIAGRAM
Address
DQ
CEf
RESET
Address Stable
Output valid
High-Z
tRC
tACC
tRH
tCEtRH
t
RP
tOH
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27
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH ERASE/PROGRAM OPERATION CHARACTERISTICS
(Over Operating Range)
-70 ns -85ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 70 - 85 - ns
tAS Address Setup Time (WE to Addr.) 0 - 0 - ns
tASO Address Setup Time to CEf Low During 15 - 15 - ns
Toggle Bit Polling
tAH Address Hold Time (WE to Addr.) 45 - 45 - ns
tAHT Address Hold Time from CEf or 0 - 0 - ns
OE High During Toggle Bit Polling
tDS Data Setup Time 35 - 45 - ns
tDH Data Hold Time 0 - 0 - ns
tOES Output Enable Setup Time 0 - 0 - ns
tOEH Output Enable Hold Time Read 0 - 0 - ns
tOEH Output Enable Hold Time 10 - 10 - ns
Toggle and Data Polling
tCEPH CEf High During Toggle Bit Polling 20 - 20 - ns
tOEPH OE High During Toggle Bit Polling 20 - 20 - ns
tGHEL Read Recover Time Before Write (OE to CEf) 0 - 0 - ns
tGHWL Read Recover Time Before Write (OE to WE)0-0-ns
tWS WE Setup Time (CEf to WE) 0 - 0 - ns
tCS CEf Setup Time (WE to CEf) 0 - 0 - ns
tWH WE Hold Time (CEf to WE) 0 - 0 - ns
tCH CEf Hold Time (WE to CEf) 0 - 0 - ns
tWP Write Pulse Width 30 - 35 - ns
tCP CEf Pulse Width 30 - 35 - ns
tWPH Write Pulse Width High 30 - 30 - ns
tCPH CEf Pulse Width High 30 - 30 - ns
tWHWH1 Byte Programming Operation - 12 - 15 µs
tWHWH1 Word Programming Operation - 15 - 20 µs
tWHWH2 Sector Erase Operation
(1)
- 0.7 - 1 s
tVCS VCCf Setup Time 50 - 50 - µs
Note:
1. This value is typical, not maximum and does not include the preprogramming time.
2. This timing is for Sector Protection Operation.
3. The time between writes must be less than “tTOW ” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW ” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
4. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD ” to suspend the erase operation.
28
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
-70 ns -85ns
Symbol Parameter Min. Max. Min. Max. Unit
tVLHT Voltage Transition Time
(2)
4- 4 - µs
tVIDR Rise Time to VID
(2)
500 - 500 - ns
tVACCA Rise Time to VACC 500 - 500 - ns
tRB Recovery Time from RY/BY 0- 0 - ns
tRP RESET Pulse Width 500 - 500 - ns
tEOE Delay Time from Embedded Output Enable - 70 - 85 ns
tRH RESET High Level Period Before Read 200 - 200 - ns
tBUSY Program/Erase Valid to RY/BY Delay - 90 - 90 ns
tTOW Erase Time-out Time
(3)
50 - 50 - µs
tSPD Erase Suspend Transition Time
(4)
-
20
-20µs
Note:
1. This does not include the preprogramming time.
2. This timing is for Sector Protection Operation.
3. The time between writes must be less than “tTOW ” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW ” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
4. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD ” to suspend the erase operation.
FLASH ERASE/PROGRAM OPERATION CHARACTERISTICS (Continued)
(Over Operating Range)
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29
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH WRITE CYCLE
(WE CONTROL)
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode (the addresses differ from ×8 mode, i.e. AAAh).
ADDRESS
DQ
CEf
OE
WE
A0h DQ
7
Dout
PA
555h PA
Data Polling
PD Dout
t
AS
3rd Bus Cycle
t
SH
t
WC
t
RC
t
OE
t
CE
t
OH
t
DF
t
DS
t
DH
t
WHWH1
t
CS
t
CH
t
GHWL
t
WP
t
WPH
30
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH WRITE CYCLE (CECE
CECE
CEff
ff
f CONTROL)
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode (the addresses differ from ×8 mode, i.e. AAAh).
ADDRESS
DQ
CEf
OE
WE
A0h DQ
7
Dout
PA
555h PA
Data Polling
PD
tAS
3rd Bus Cycle
tAH
tWC
tDS tDH
tWHWH1
tWS tWH
tGHEL tCP tCPH
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
*SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
Note:
These waveforms are for the ×16 mode (the addresses differ from ×8 mode: AAAh, 555h, AAAh, AAAh, 555h, SA*).
ADDRESS
DQ
CEf
OE
WE
55h 10h/
30h
Vccf
55h AAh
80h
AAh
555h 2AAh 555h 555h 2AAh SA*
30h for Sector Erase
tWC tAS tAH
tCS tCH
tWP tWPH
tVCS
tGHWL
tDS tDH
32
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH AC WAVEFORMS
FOR DATA POLING DURING EMBEDDED ALOGRITHM OPERATIONS
*DQ7 = Valid Data (the device has completed the Embedded operation.)
Data In
DQ0/DQ6
CEf
OE
WE
RY/BY
DQ
Data In
DQ7
DQ0 to DQ6 = Output Flag DQ0 to DQ6
Valid Data
DQ7 =
Valid Data
tDF
tBUSY
tWHWH1 or 2
tOE
tEOE
tOEH
tCEf
tCH
High - Z
High - Z
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH AC WAVEFORMS
FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS
* DQ6 stops toggling (the device has completed the Embedded operation).
Toggle Toggle Toggle Toggle Output
Data Data Data Data Valid
Data
ADDRESS
DQ
6
/DQ
2
CEf
OE
WE
t
DH
t
BUSY
t
OEH
t
OE
RY/BY
t
CEf
*
t
OEH
t
OEPH
t
CEPH
t
AHT
t
ASO
t
AHT
t
AS
34
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH BACK-TO-BACK READ/WRITE TIMING DIAGRAM
Note:
This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
ADDRESS
DQ
CEf
OE
WE
BA1 BA1 BA1
tRC
tAS tAH tACC
tCE
BA2
(555h) BA2
(PA) BA2
(PA)
Read Command Read Command Read Read
Valid Valid Valid Valid Valid
Output Input Output Input Output Status
tWC tRC tWC tRC tRC
tDS tDH tDF
tDF
tOEH
(PD)
tGHWL tWP
(A0h)
tOE tCEPH
tAHT
tAS
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35
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH RY/BYBY
BYBY
BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS
FLASH RESET,RESET,
RESET,RESET,
RESET, RY/BYBY
BYBY
BY TIMING DIAGRAM
WE
C
E
f
RY/BY
The rising edge of the last write pulse
Entire programming
or erase operations
t
BUSY
WE
RESET
RY/BY
t
READY
t
RP
t
RB
36
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH TEMPORARY SECTOR GROUP UNPROTECTION
RESET
V
CC
f
V
ID
V
IH
CEf
WE
RY/BY
Program or Erase Command Sequence
Unprotection Period
t
VIRD
t
VCS
t
VLHT
t
VLHT
t
VLHT
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH EXTENDED SECTOR GROUP PROTECTION
SGAx: Sector Group Address to be protected. SGAy: Next Group Sector Address to be protected
UNPROTECTION: Implement with A6 = 1, A1 = 1, A0 = 0. Time-out approximately 15 ms.
TIME-OUT : Time-Out window = 250 µs (Min.)
RESET
ADDRESS
A0
A1
A6
CEf
OE
WE
Data
Vccf
60h 60h 40h 01h 60h
SGAX SGAYSGAX
TIME-OUT
t
VCS
VIDR
VLHT
t
WC
t
WP
t
OE
t
WC
38
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
FLASH ACCELERATED PROGRAM
WP/ACC
VCCf
VACC
VIH
CEf
WE
RY/BY
Acceleration Period
tVACCR
tVCS tVLHT
tVLHT tVLHT
Program Command Sequence
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39
PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
SRAM READ CYCLE SWITCHING CHARACTERISTICS(1)
(Over Operating Range)
70 ns
85ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 70 — 85 — ns
tAA Address Access Time — 70 — 85 ns
tOHA Output Hold Time 10 — 10 — ns
tACE1
CE1
s
Access Time — 70 — 85 ns
tDOE OE Access Time — 35 — 45 ns
tHZOE(2) OE to High-Z Output — 25 — 35 ns
tLZOE(2) OE to Low-Z Output 5 — 5 — ns
tHZCE1(2)
CE1
s
to High-Z Output 0 25 0 35 ns
tLZCE1(2)
CE1
s
to Low-Z Output 10 — 10 — ns
tBA
LB
s
,
UB
s
Access Time — 70 — 85 ns
tHZB
LB
s
,
UB
s
to High-Z Output 0 25 0 35 ns
tLZB
LB
s
,
UB
s
to Low-Z Output 0 — 0 — ns
Notes:
1. See SRAM AC Test Conditions
2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
SRAM POWER SUPPLY CHARACTERISTICS(1)
(Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
ICC Vcc Dynamic Operating VCCS = Max., — 40 mA
Supply Current IOUT = 0 mA, f = fMAX
ICC1Operating Supply VCCS = Max., — 8 mA
Current IOUT = 0 mA, f = 0
ISB2CMOS Standby VCCS = Max., — 7 µA
Current (CMOS Inputs) CE1
s
≥
VCCS – 0.2V,
CE2
s
≤ 0.2V,
VIN
≥
VCCS – 0.2V, or
VIN
≤
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
40
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
SRAM AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to Vccs
Input Rise and Fall Times 5 ns
Input and Output Timing VCCS/2
and Reference Level
Output Load 1TTL gate and 30pf
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA tOHA
tRC
D
OUT
ADDRESS
AC WAVEFORMS
SRAM READ CYCLE NO. 1(1,2) (Address Controlled) (CE1S = OE = VIL, UBs or LBs = VIL)
AC WAVEFORMS
SRAM READ CYCLE NO. 2(1,3) (CE1S, OE, AND UBs/ LBs Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1, UBs, or LBs = VIL.
3. Address is valid prior to or coincident with CE1 LOW transition.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
t
HZCE1
ADDRESS
OE
CE1s
CE2s
DOUT
LBs, UBs
t
HZB
t
BA
t
LZB
42
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1)
(Over Operating Range)
70ns 85ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 70 — 85 — ns
tSCE1 CE1s to Write End 60 — 70 — ns
tAW Address Setup Time to Write End 60 70 — ns
tHA Address Hold from Write End 0 — — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWB LBs,UBs Valid to End of Write 60 — 70 — ns
tPWE WE Pulse Width 50 —— 60 — ns
tSD Data Setup to Write End 30 — 35 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE(2) WE LOW to High-Z Output — 25 — 35 ns
tLZWE(2) WE HIGH to Low-Z Output 0 — 0 — ns
Notes:
1. See SRAM AC Test Conditions.
2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE1s and WE inputs and at least
one of the LBs and UBs inputs being in the LOW state.
2. WRITE = (CE1s) [ (LBs) = (UBs) ] (WE).
AC WAVEFORMS
SRAM WRITE CYCLE NO. 1(1,2)
(CE1S Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
PWE
(4)
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE1
s
CE2
s
WE
DOUT
DIN
LBs, UBs
44
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
SRAM WRITE CYCLE NO. 2
(WE Controlled: OE is HIGH During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
PWE1, 2
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CE1s
CE2s
WE
LBs, UBs
DOUT
DIN
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
SRAM WRITE CYCLE NO. 3
(WE Controlled: OE is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
PWE1, 2
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CE1s
CE2s
WE
LBs, UBs
DOUT
DIN
46
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
WRITE CYCLE NO. 4
(UBs/LBs Controlled, CE1s is LOW, CE2s is HIGH)
DATA UNDEFINED
t
WC
ADDRESS 1 ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1 WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
UBs, LBs
WE
D
OUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD t
HD
t
SA
t
HA t
HA
UB_CSWR4.eps
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
SRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 1.5 3.3 V
IDR Data Retention Current Vcc = 3.0V, CS1 ≥ Vcc – 0.2V — 7 µ A
tSDR Data Retention Setup Time See Data Retention Waveform 0 — n s
tRDR Recovery Time See Data Retention Waveform tRC —ns
SRAM DATA RETENTION WAVEFORM
(CE1 Controlled)
VCC
CE1s ≥ VCC - 0.2V
tSDR tRDR
VDR
CE1s
GND
2.7V
VIH
Data Retention Mode
48
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PRELIMINARY INFORMATION Rev. 00B
08/01/02
IS71VPCF32XS04 ISSI
®
ORDERING INFORMATION
Industrial Range: -40oC to +85oC
SRAM
Data Boot Flash Bank Flash SRAM
Order Part No. Bus Section Organization Speed(ns) Speed(ns) Package
IS71VPCF32AS04-7070BI 8/16 Top 4Mb, 28Mb 70 7 0 73-ball BGA
IS71VPCF32BS04-7070BI 8/16 Top 8Mb, 24Mb 70 7 0 73-ball BGA
IS71VPCF32CS04-7070BI 8/16 Top 16Mb, 16Mb 70 70 73-ball BGA
IS71VPCF32DS04-7070BI 8/16 Bottom 4Mb, 28Mb 7 0 70 73-ball BGA
IS71VPCF32ES04-7070BI 8/16 Bottom 8Mb, 24Mb 70 70 73-ball BGA
IS71VPCF32FS04-7070BI 8/16 Bottom 16Mb, 16Mb 70 70 73-ball BGA
IS71VPCF32AS04-7085BI 8/16 Top 4Mb, 28Mb 70 8 5 73-ball BGA
IS71VPCF32BS04-7085BI 8/16 Top 8Mb, 24Mb 70 8 5 73-ball BGA
IS71VPCF32CS04-7085BI 8/16 Top 16Mb, 16Mb 70 85 73-ball BGA
IS71VPCF32DS04-7085BI 8/16 Bottom 4Mb, 28Mb 7 0 85 73-ball BGA
IS71VPCF32ES04-7085BI 8/16 Bottom 8Mb, 24Mb 70 85 73-ball BGA
IS71VPCF32FS04-7085BI 8/16 Bottom 16Mb, 16Mb 70 85 73-ball BGA
IS71VPCF32AS04-8570BI 8/16 Top 4Mb, 28Mb 85 7 0 73-ball BGA
IS71VPCF32BS04-8570BI 8/16 Top 8Mb, 24Mb 85 7 0 73-ball BGA
IS71VPCF32CS04-8570BI 8/16 Top 16Mb, 16Mb 85 70 73-ball BGA
IS71VPCF32DS04-8570BI 8/16 Bottom 4Mb, 28Mb 8 5 70 73-ball BGA
IS71VPCF32ES04-8570BI 8/16 Bottom 8Mb, 24Mb 85 70 73-ball BGA
IS71VPCF32FS04-8570BI 8/16 Bottom 16Mb, 16Mb 85 70 73-ball BGA
IS71VPCF32AS04-8585BI 8/16 Top 4Mb, 28Mb 85 8 5 73-ball BGA
IS71VPCF32BS04-8585BI 8/16 Top 8Mb, 24Mb 85 8 5 73-ball BGA
IS71VPCF32CS04-8585BI 8/16 Top 16Mb, 16Mb 85 85 73-ball BGA
IS71VPCF32DS04-8585BI 8/16 Bottom 4Mb, 28Mb 8 5 85 73-ball BGA
IS71VPCF32ES04-8585BI 8/16 Bottom 8Mb, 24Mb 85 85 73-ball BGA
IS71VPCF32FS04-8585BI 8/16 Bottom 16Mb, 16Mb 85 85 73-ball BGA
