ICs for Communications ISDN Subscriber Access Controller for Upn-Interface Terminals SmartLink-P PSB 2197 User's Manual 02.95 PEB 2197 Revision History: Original Version: 02.95 Previous Releases: Page Subjects (changes since last revision) Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview". General Information Table of Contents Page 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Low Cost Digital Telephone Using the SmartLink-P . . . . . . . . . . . . . . . . .20 Low Cost Digital Feature Phone Using the SmartLink-P . . . . . . . . . . . . . .21 Upn-Terminal Repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Network Termination Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 S/T-Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 HDLC-Controller on IOM-2 Extensions . . . . . . . . . . . . . . . . . . . . . . . . . .25 2 2.1 2.1.1 2.1.2 2.1.3 2.1.3.1 2.1.3.2 2.1.3.3 2.1.4 2.1.5 2.1.6 2.1.6.1 2.1.6.2 2.2 2.2.1 2.2.2 2.2.3 2.2.3.1 2.2.3.2 2.2.4 2.2.5 2.3 2.3.1 2.3.2 2.3.3 2.3.3.1 2.3.3.2 2.3.4 2.3.5 2.3.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Terminal Equipment (TE) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 General Functions and Device Architecture (TE-mode) . . . . . . . . . . . . . .26 Clock Generation (TE-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Interfaces (TE-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 IOM-2 Interface in TE-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Upn-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 D-Channel-Arbitration in TE-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 HDLC-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Terminal Specific Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 LCD-Contrast Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Ring Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Terminal Repeater (TR) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 General Functions and Device Architecture (TR-Mode) . . . . . . . . . . . . . .56 Clock Generation (TR-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Interfaces (TR-Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 IOM-2 Interface in TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Upn-lnterface in TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 D-Channel-Arbitration in TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 HDLC-Controller Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 General Functions and Device Architecture (HDLC-Controller Mode) . . .63 Clock Generation (HDLC-Controller Mode) . . . . . . . . . . . . . . . . . . . . . . . .64 Interfaces (HDLC-Controller Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 IOM-2 Interface in HDLC-Controller Mode . . . . . . . . . . . . . . . . . . . . . . .65 D-Channel-Arbitration in HDLC-Controller Mode . . . . . . . . . . . . . . . . . . .66 HDLC-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Semiconductor Group 3 02.95 General Information Table of Contents Page 3 3.1 3.1.1 3.1.2 3.1.2.1 3.1.2.2 3.1.2.3 3.1.2.4 3.1.2.5 3.1.2.6 3.1.3 3.1.4 3.1.4.1 3.1.4.2 3.1.4.3 3.1.5 3.1.6 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 TE-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Control of the Upn-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Power-Down of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Activation/Deactivation of the Upn-lnterface . . . . . . . . . . . . . . . . . . . . . . .68 Layer-1 Command/lndication Codes in TE-Mode . . . . . . . . . . . . . . . . . . .69 State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 TE-Mode State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Example of the Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Operation of the Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . .75 Control of the HDLC-Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HDLC-Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HDLC-Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Examples for the HDLC-Controller Operation . . . . . . . . . . . . . . . . . . . . . .79 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 TR-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Control of the Upn-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Activation/Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . .96 Layer-1 Command/Indication Codes in TR-Mode . . . . . . . . . . . . . . . . . . .97 State Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 TR-Mode State Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Example of the Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . .101 D-Channel Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 HDLC-Controller Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Interrupt Structure and Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Control of the Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Control of the HDLC-Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Control of Terminal Specific Functions . . . . . . . . . . . . . . . . . . . . . . . . . .104 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 4 4.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 SmartLink-P Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG. Purchase of Siemens I2C components conveys a license under the Philips' I2C patent to use the components in the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983. Semiconductor Group 4 02.95 General Information Introduction The PSB 2197, SmartLink-P, implements the subscriber access functions for a digital terminal to be connected to a two-wire Upn-interface. The PSB 2197 SmartLink-P is an optimized device for TE-applications, covering the complete layer-1 and basic layer-2 functions for digital terminals. The PSB 2197 SmartLink-P combines the functions of the Upn-transceiver with reduced loop length (one channel of the OCTAT-P PEB 2096) and a simple HDLC-controller for signaling data onto one chip. A pulse width modulator is included to provide an LCD-contrast control or a ring tone signal. The serial control port of the SmartLink-P is compatible to most serial interfaces of microcontrollers. In addition it provides the microcontroller clock signal as well as an undervoltage detector and reset generation including a watchdog function. The Terminal Repeater function of the SmartLink-P allows to cascade two telephones which are controlled by one Upn-interface from the line card or to extend the loop length by using an IEC-Q transceiver. The SmartLink-P can also be used as a simple HDLC-controller which provides the TIC-bus access procedure. In this mode, the Upn-transceiver is inactive. The PSB 2197 SmartLink-P interfaces to voice/data devices via the IOM-2 interface and provides an additional bit clock and strobe signal for standard codecs. The upstream B-channel information may be muted or loop back the downstream data. The PSB 2197 SmartLink-P is a 1-micron CMOS device offered in a P-DSO-28 package. It operates from a single 5-V supply. Note: Upn in the document refers to a version of the Up0-standard with a reduced loop length. Semiconductor Group 5 ISDN Subscriber Access Controller for Upn-Interface Terminals (SmartLink-P) PSB 2197 Preliminary Data 1 CMOS IC Features * Cost/performance-optimized Upn-interface transceiver, compatible to PEB 2096 OCTAT-P and PSB 2195 ISAC-P or PSB 2196 ISAC-P TE * HDLC-controller with 2 x 4 byte FIFO per direction * IOM-2 interface for terminal application including bit clock and strobe signal * Uplink MUTE function P-DSO-28-1 * Selective B-channel loop back * Serial control port * Pulse width output LCD-contrast control or ring tone generation * CPU-clock and reset output * Watchdog timer * Test loops * Advanced CMOS-technology * Low power consumption: active: 100 mW max. Type Ordering Code Package PSB 2197T Q67100-H6462 P-DSO-28-1 (SMD) Semiconductor Group 6 02.95 Features Pin Configurations (top view) P-DSO-28-1 PWO/RING/MODE RST RST VSS LIa Line Interface LIb VDD TR/TE XTAL1 XTAL2 INT TST VSS VDDDET/TCM 1 2 3 4 5 6 7 8 10 11 12 13 14 28 27 26 25 24 23 22 PSB 2197T 21 20 19 18 17 16 15 ITP06294 Semiconductor Group 7 SDS BCL VDD VSS DCL FSC DD DU MOSI MISO SCLK VDD MCLK CS Features 1.1 Pin Definitions and Functions Pin No. TE-Mode TR-Mode HDLCController Mode P-DSO-28 Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Function 15 CS I CS I CS I Chip Select. A low level indicates a microprocessor access to the SmartLink-P. It masks the INT-output. 11 INT OD INT OD INT OD Interrupt Request. INT becomes active if the SmartLink-P requests an interrupt. INT is masked by CS. 16 MCLK O 0, low O 0, low O Microprocessor Clock. Clock output for the microcontroller. 3 RST O inv. RST O inv. RST O Reset. High active reset output. In TRmode and HDLCcontroller mode, RST outputs the inverse of the RST-input. 2 RST I/O (OD) RST I RST I Reset. Low active reset output and input (TE, open drain), low active reset input in TR-mode. 8 TR/TE (VSS) I TR/TE (VDD) I TR/TE (VDD) I Terminal Repeater/ TE-Mode Selection. Selects terminal repeater mode (VDD) or TE-mode (VSS). Semiconductor Group 8 Features Pin Definitions and Functions (cont'd) Pin No. TE-Mode TR-Mode HDLCController Mode P-DSO-28 Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Function 20 MOSI I MOSI I MOSI I Master Out Slave In. Receive data line of the serial control interface. Operates only as slave. 19 MISO O MISO O MISO O Master In Slave Out. Transmit data line of the serial control interface. Operates only as slave. MISO is tristate while CS is high. 18 SCLK I SCLK I SCLK I Serial Clock. Clock signal of the serial control interface. 22 21 DD DU I/O (OD) I/O (OD) DD DU I/O (OD) I/O (OD) DD DU I/O (OD) I/O (OD) Data Downstream. Data Upstream. Transfer the data of the IOM-2 interface. External pull-up resistors in the range of 4.7 k to 820 are required. Semiconductor Group 9 Features Pin Definitions and Functions (cont'd) Pin No. TE-Mode TR-Mode HDLCController Mode Input (I) Output (O) Open Drain (OD) Function XTAL1 I Crystal 1. Connection for a crystal or used as external clock input. For HDLC-controller mode XTAL1 requires a clock signal of at least 80 clock periods after reset. Crystal 2. Connection for a crystal. Not connected if an external clock is supplied on XTAL1. (TE & TR-mode) Symbol Input (I) Output (O) Open Drain (OD) Symbol 9 XTAL1 I XTAL1 I 10 XTAL2 O XTAL2 O 24 DCL O DCL I DCL I Data Clock. IOMinterface clock signal. Clock frequency is twice the IOM-data rate. TE: clock output IOM-2: 1536 kHz TR, HDLC: clock input IOM-2: 1536 kHz 23 FSC O FSC I FSC I Frame Sync. TE: Frame synchronization output. High during IOMchannel 0 on the IOM-2 interface. TR, HDLC: Input synchronization signal IOM-2 mode. Semiconductor Group Input (I) Output (O) Open Drain (OD) Symbol P-DSO-28 O 10 Features Pin Definitions and Functions (cont'd) Pin No. TE-Mode TR-Mode HDLCController Mode P-DSO-28 Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Function 5 6 Lla Llb I/O I/O Lla Llb I/O I/O Lla Llb I/O I/O Line Interface a. Line Interface b. Upn-transceiver signals. In HDCL-controller mode both pins must be connected via a 10 k resistor. 27 BCL O 0, low O BCL O Bit Clock. IOM-bit clock signal (768 kHz) in TE- and HDLC-controller mode if programmed by SDS-bits. In TR-mode, the default value of CTRL4 fixes BCL to `0'. 28 SDS O 0, low O SDS O Serial Data Strobe. Strobe signal to indicate 64 kbit/s time-slot in TE- and HDLC-mode. In TR-mode, the default value of CTRL4 fixes SDS to `0'. 1 PWO/ RING O HDLC/ I TR HDLC/ TR I Pulse Width Output/Ring/Mode. Provides the output of the pulse width modulator or ring tone generator. Selects between HDLC-(1) and TR-(0) mode if TR/TE = 1. Semiconductor Group 11 Features Pin Definitions and Functions (cont'd) Pin No. TE-Mode TR-Mode HDLCController Mode P-DSO-28 Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Symbol Input (I) Output (O) Open Drain (OD) Function 14 VDDDET I TCM I VDDDET I VDDDET/T-Channel Mode. In TE- and HDLC-mode, this pin selects if the VDD detection is active (`0') and reset pulses are generated or whether it is deactivated (`1') and an external reset has to apply on pin RST. In TR-mode, TCM is used to select the T-channel source (S/G or `1'). 12 TST I TST I TST I Test Pin. This input is used to select the test mode register via the serial interface. See test mode description. For normal operation, this pin must be tied to high (VDD). 7, 17, 26 VDD VDD VDD Power Supply (+ 5 V 5 % (Upn-specification), 10 % operational). 4, 13, 25 VSS VSS VSS Ground. Semiconductor Group 12 Features Please note that pin 4 and pin 7 are the supply pins for the analog drivers Lla/b. They are disconnected internally from the other supply pins except for the ESD-protection circuitry. To overcome ESD-problems it is necessary to put series resistors in the low voltage output drivers. The resistor value is in range 40 to 50 . The following output drivers will have these resistors: INT, MCLK, RST, RST, MISO, BCL, SDS, PWO/Ring/MODE. The resistor doesn't affect the high voltage output driver. The following output drivers will not have the resistors: DD, DU, XTAL2, Lla, Llb. Semiconductor Group 13 Features 1.2 Logic Symbol TE-Mode R IOM -2 +5V 0V 15.36 MHz 100 ppm VDD VSS XTAL1 U pn XTAL2 LI a DD DU LI b FSC DCL SDS BCL VDD TR/TE VSS VDDDET/TCM PWO/RING SCLK MOSI MISO CS INT MCLK RST Microcontroller Figure 1 Logic Symbol of the SmartLink-P TE-Mode Semiconductor Group TST 14 VDDDET RST ITL06295 Features TR-Mode 15.36 MHz 100 ppm 0V +5V XTAL2 VSS VDD R XTAL1 U pn LI a IOM -2 DD DU FSC LI b DCL TST VDD TR/TE VDD PWO/RING/MODE VSS VDDDET/TCM RST RST SCLK MOSI CS VSS Figure 2 Logic Symbol of the SmartLink-P TR-Mode Semiconductor Group 15 VSS VDD ITL06296 TCM Features +5V 0V VDD VSS HDLC-Controller Mode 80 Clocks During Reset XTAL1 LI a R IOM -2 DD DU LI b FSC TST VDD TR/TE VDD PWO/RING/MODE VDD DCL SDS BCL VDDDET/TCM SCLK MOSI MISO CS INT RST Microcontroller Figure 3 Logic Symbol of the SmartLink-P HDLC-Controller Mode Semiconductor Group 16 VDDDET RST ITL06297 Features 1.3 Functional Block Diagram TE-Mode R IOM -2 / PCM U pn R D-Channel Controller Pulse Width Modulator Ring Tone Generator IOM -2 Interface U pn Transceiver TIC FIFO Serial Control Port Clock, Reset ITB06298 Microcontroller Figure 4 Block Diagram of the SmartLink-P TE-Mode Semiconductor Group 17 Features TR-Mode R IOM -2 U PN R U PN Transceiver TIC IOM -2 Interface Reset ITB05321 Figure 5 Block Diagram of the SmartLink-P TR-Mode Semiconductor Group 18 Features HDLC-Controller Mode R IOM -2 R D-Channel Controller IOM -2 Interface TIC FIFO Serial Control Port Reset ITB06299 Microcontroller Figure 6 Block Diagram of the SmartLink-P HDLC-Controller Mode Semiconductor Group 19 Features 1.4 System Integration 1.4.1 Low Cost Digital Telephone Using the SmartLink-P A low cost digital telephone behind a PBX consists of the SmartLink-P, a standard codec and a microcontroller with on-chip ROM. This architecture is shown in figure 7. The SmartLink-P performs the conversion between the Upn-interface and the lOM-2 interface of the B-channel and D-channel information. The D-channel signaling information is processed by an HDLC-controller inside the SmartLink-P which provides 2 x 4 byte FlFOs in each direction. The serial strobe signal controls the time-slot which is used by the codec. A frequency signal generated by the SmartLink-P can be used for ring tone generation. The C510 family of microcontrollers are versions of the standard C501 core enhanced by the synchronous serial interface (SSI). R IOM -2/PCM Extensions DU, DD, BCL, SDS or DU, DD, DCL, FSC Microcontroller Codec MC68HC05 SAB C510 Serial I/O U pn SmartLink-P PSB 2197 DC/DC Handset Loudspeaker 1 2 3 4 5 6 7 8 9 * 0 # Keyboard +5 V LED Matrix Figure 7 Low Cost Digital Telephone Using the SmartLink-P Semiconductor Group 20 Piezo Ringer ITS06300 Features 1.4.2 Low Cost Digital Feature Phone Using the SmartLink-P A low cost digital feature phone behind a PBX consists of the SmartLink-P, a feature codec like the ARCOFI-SP PSB 2163 and a microcontroller with on-chip ROM. This architecture is shown in figure 8. The SmartLink-P performs the conversion between the Upn-interface and the IOM-2 interface of the B-channel and D-channel information. The D-channel signaling information is processed by an HDLC-controller inside the SmartLink-P which provides 2 x 4 byte FlFOs in each direction. The parallel microcontroller interface is designed in a way to share the control lines with an LCD-display controller reducing the required number of l/O-lines. A pulse width modulated signal can be used to control the contrast of an LCD-display. The C510 family of microcontrollers are versions of the standard C501 core enhanced by the synchronous serial interface (SSI). R IOM -2 Extensions Serial I/O DU, DD, DCL, FSC U pn Microcontroller SmartLink-P MC68HC05 SAB C510 R ARCOFI -SP PSB 2163 PSB 2197 DC/DC Handset LoudMicrospeaker phone 1 2 3 4 5 6 7 8 9 * 0 # Keyboard SIEMENS HL IT 49-89-4144 LED Matrix LCD Display Figure 8 Low Cost Digital Feature Phone Using the SmartLink-P Semiconductor Group 21 +5 V ITS06301 Features 1.4.3 Upn-Terminal Repeater The SmartLink-P is designed to operate as a Upn-terminal repeater (figure 9). It provides a mechanism to control further Upn-terminals by using the T-channel of the Upn-interface and the TlC-bus on the IOM-2 interface. The terminal repeater function allows to cascade two Upn-telephones up to a loop length of 100 m. Telephone 1 R IOM -2 U pn R SmartLink-P TR-Mode ARCOFI -SP or Codec SmartLink-P TE-Mode PSB 2197 PSB 2163 PSB 2197 Terminal Repeater Plug-IN Board LineCard Basic-Telephone Board R IOM -2 U pn R ARCOFI -SP or Codec SmartLink-P TE-Mode PSB 2163 PSB 2197 Telephone 2 Figure 9 Upn-Terminal Repeater Semiconductor Group 22 ITS06302 Features 1.4.4 Network Termination Module The combination of the PEB 2091 (IEC-Q) and PSB 2197 (SmartLink-P) allows the extension of the loop length between the line card and Upn-terminals up to 8 km. The SmartLink-P provides the regular Upn-interface to connect standard Upn-terminals to it. NT-Module R IOM -2 U 2B1Q SmartLink-P TR-Mode IEC-Q TE-Mode PSB 2197 PSB 2091 LineCard R IOM -2 U pn R ARCOFI -SP or Codec SmartLink-P TE-Mode PSB 2163 PSB 2197 Telephone Figure 10 Network Termination Using the SmartLink-P Semiconductor Group 23 ITS06303 Features 1.4.5 S/T-Interface Option A telephone based on the SmartLink-P may be extended by an S/T-interface option to connect standard S/T-interface terminals like ISDN PC cards or videophones to it (figure 11). This option uses a PSB 20810 (mask version of the SBCX, PEB 2081) for the S/T-interface. The D-channel arbitration between the D-channel controller of the SmartLink-P and the upstream D-channel data of the S/T-interface is done by the TIC-bus of the IOM-2 interface. Telephone R IOM -2 U pn R ARCOFI -SP or Codec Masked SBCX PSB 20810 PSB 2163 S/T Interface Plug-IN Board Basic-Telephone Board TerminalAdapter V.24, X.21, X.25 ISDN PC-Card ISDN Videophone ITS06304 S/T Bus Figure 11 Upn-Telephone with S/T-Interface Option Semiconductor Group 24 SmartLink-P PSB 2197 LineCard Features 1.4.6 HDLC-Controller on IOM-2 Extensions The SmartLink-P can be used as a HDLC-controller to access the D-channel via the TlC-bus procedure. In this mode, the Upn-interface is not active. Option Board with Requires D-Channel Access SmartLink-P HDLC-Controller Mode PSB 2197 Basic-Telephone Board R IOM -2 U pn R ARCOFI -SP or Codec SmartLink-P TE-Mode PSB 2163 PSB 2197 MC 68HC05 Microcontroller MC 68HC05 Microcontroller SAB C510 SAB C510 LineCard ITS06305 Figure 12 HDLC-Controller on IOM-2 Extensions Semiconductor Group 25 Functional Description 2 Functional Description Selection between TE-, TR-Mode and HDLC-Controller Mode The selection between the three operating modes is done via the combination of TR/TE-input and PWO/Ring/Mode input. If TR/TE is connected to VSS (GND), the terminal equipment mode is selected. PWO/Ring/Mode operates as output providing the LCD-contrast or ringing signal. If TR/TE is connected to VDD (+ 5 V), the PWO/Ring/Mode input selects between TR-mode (`0') and HDLC-controller mode (`1'). The TR-mode remains as a stand-alone function with the requirement that CS must be connected to VDD and MOSI should be connected to VSS. If the HDLC-controller mode is selected, the Upn-state machine must reach a defined reset state. Therefore it is necessary to provide a clock signal to XTAL1 which is active during reset and remains active at least 80 clock periods after reset. It is recommended to connect the IOM-2 DCL-signal to XTAL1. 2.1 Terminal Equipment (TE) Mode 2.1.1 General Functions and Device Architecture (TE-mode) Figure 13 depicts the detailed architecture of the PSB 2197 SmartLink-P in TE-mode: * Upn-interface transceiver, functionally fully compatible to both PEB 2095 IBC and PEB 2096 OCTAT-P, also features the terminal repeater mode * Serial control port * Reset and microcontroller clock generation * HDLC-controller with 2 x 4 byte FlFOs per direction * IOM-2 interface for terminal application * MUTE function * B-channel loop on IOM-2 * Pulse width modulator for LCD-contrast control or ring tone generation * Watchdog timer Semiconductor Group 26 Functional Description DU DD FSC DCL BCL SDS R IOM -2 Interface LI a LI b TIC- Bus PWO HDLC Transmitter Pulse Width Modulator HDLC Receiver Timing CIO DPLL OSC 15.36 MHz TR/TE Serial Control Port SCLK MOSI MISO CS INT RST Figure 13 Device Architecture of the SmartLink in TE-Mode Semiconductor Group VDDDET/TCM Reset Logic 27 RST MCLK ITS06306 Functional Description 2.1.2 Clock Generation (TE-Mode) In TE-mode, the oscillator is used to generate a 15.36-MHz clock signal. This signal is used by the DPLL to synchronize the IOM-2 clocks to the received Upn-frames. The oscillator clock is divided by 2 to generate a 7.68-MHz clock which drives the remaining functions. The prescaler for the microcontroller clock divides the 7.68-MHz clock by 1, 2, 4 or 8. The pulse width modulator and the ring tone generator receive their clock signal from a divider which generates a 128-kHz and 32-kHz signal. The later signal is also used to drive the reset/watchdog counter. Note that only the IOM-2 clock signals (FSC, DCL, BCL) may be stopped during the power-down state. The oscillator and the other modules remain active all the time. DU DD U pn State Machine HDLC Controller TIC Bus Controller (CIO) R IOM -2 Interface FSC 15.36 MHz DCL DPLL BCL 15.36 MHz OSC 7.68 MHz :2 Divider 128 kHz 32 kHz MCLK Prescaler Pulse Width Ring Tone PWO/RING Reset/ Watchdog RST ITS06307 Figure 14 Clock Generation in TE-Mode Semiconductor Group 28 Functional Description 2.1.3 Interfaces (TE-Mode) The PSB 2197 SmartLink-P serves four interfaces in TE-mode: * Serial microcontroller interface for higher layer functions incl. reset and microcontroller clock generation * IOM-2 interface: between layer-1 and layer-2 and as a universal backplane for terminals * Upn-interface towards the two-wire subscriber line * Pulse width modulator/Ringing output 2.1.3.1 Microcontroller Interface The SmartLink-P provides a serial control interface which is compatible to the SPI-interface of Motorola or Siemens C510 family of microcontrollers. Serial Control Interface The SmartLink-P is programmable via a serial control interface. It provides access to the D-channel FlFOs as well as global control/status registers. It consists of 5 lines: SCLK, MOSI, MISO, CS, INT. CS is used to start a serial access to the SmartLink-P registers: Following a falling edge on CS, data is transmitted in groups of eight bits until the CS-line becomes inactive. The data transfer is synchronized by the SCLK-input. MISO changes with the falling edge of SCLK while the contents of MOSI is latched on the rising edge of SCLK. Data is transferred with the MSB first and LSB last. The structure of the serial control interface is designed to provide a fast full duplex data transfer. Two control/status bytes are transferred followed by the data of the HDLC FlFOs. Two additional control bytes can be transferred on request. Figure 15 shows the timing of a serial control interface transfer. Semiconductor Group 29 Functional Description ~ ~ CS SCLK MISO D7 D6 D5 D4 D3 D2 D1 STA2 or RFIFO ~ ~ ~ ~ STA1 D0 CTRL1 D7 D6 D5 D4 D3 D2 D1 D0 CTRLn or XFIFO ~ ~ x D7 D6 D5 D4 D3 D2 D1 D0 ~ ~ MOSI D7 D6 D5 D4 D3 D2 D1 D0 INT CMDR_ ENABLE ITD06308 Figure 15 Serial Control Interface Timing The serial control port outputs a status byte (STA1) while the first control byte (CTRL1) is received. This status byte informs whether D-channel information follows and about the transmitter status. Following this byte a second status byte (STA2) is transmitted while the second control byte (CTRL2) is received. Following these two bytes, FlFO-data or additional control bytes may be transmitted. The contents of the RFIFO is transmitted if a receive FlFO-status bit was set (RPF, RME) until a receiver command (RMC, RHR, RMD) has been received. After four bytes have been read, the SmartLink continues to transmit RFIFO data as long as transfers are made (as long as CS is low and clocks are transferred). The contents of the RFIFO will be repeated after 4 bytes. A new FlFO-access continues with the next byte. The CTRL2 byte specifies the number of bytes which have to be transferred into the XFIFO in receive direction. Additional data bytes will be ignored. During transfer of CTRL3 and CTRL4, RFIFO data will not be output. Semiconductor Group 30 Functional Description The access to the serial control interface may be stopped at any time by setting the CS-input to `1'. If this happens in the middle of a RFlFO-byte, the information of that byte will be lost. In receive direction, the contents of the shift register will not be written into the XFIFO or the proper register. If the access is stopped during the transfer of RFlFO-data, the SmartLink will output the remaining number of bytes in the next access, but no RFlFO-status bit will be set. Thus, the microcontroller has to monitor the number of transferred bytes. A minimum interval of 10 DCL clock periods (6.5 s) is necessary between serial accesses (rising edge of previous access until falling edge of next access). This time is required to perform the commands entered in the CTRL2-register correctly. CS 10 x DCL ITD06309 An earlier access CTRL2-commands. may result in an incorrect execution of the previous Figure 16 shows some examples of the data transfer over the serial control interface. Semiconductor Group 31 Functional Description CS MISO STA1 STA2 RFIFO Byte 1 RFIFO Byte 2 RFIFO Byte 3 RFIFO Byte 4 RFIFO Byte 1 MOSI CTRL1 CTRL2 XFIFO XFIFO CTRL1 CTRL2 CTRL3 CTRL4 XFIFO XFIFO SCLK Indeterminate State ITD06310 a) Transfer of STA 1/ CTRL1 only b) Transfer of STA 1, 2; CTRL1, 2 CS CS MISO STA1 MISO STA 1 STA 2 MOSI CTRL1 MOSI CTRL1 CTRL 2 c) Transfer of CTRL3 and CTRL4 CS MISO STA1 STA 2 MOSI CTRL1 CTRL 2 CTRL 3 Indeterminate State ITD06311 Figure 16 Examples of SCI-Transfers Semiconductor Group CTRL 4 32 Functional Description Figure 17 shows an example how the SmartLink-P is interfaced to a Siemens SAB C510 family of microcontrollers or a Motorola MC68HC05 microcontroller. PORT CS SCLK SCLK SAB C510 68HC11 68HC05 SDO SDI SDI SDO INT INT XTAL1/EXTAL SmartLink-P PSB 2197 MCLK RST RST RST ITS06312 TR/TE Figure 17 Interfacing the SmartLink-P to a Siemens SAB C510x or Motorola Microprocessor Microprocessor Clock Output The microprocessor clock is provided by the MCLK-output. Four clock rates are provided by a programmable prescaler. These are 7.68 MHz, 3.84 MHz, 1.92 MHz, 0.96 MHz. Switching between the clock rates is based on the lowest frequency and realized without spikes. The value after reset is 3.84 MHz. The clock rate is changed after CS becomes inactive. Interrupt Output The interrupt output is an open drain output. The INT-line can be activated at any time. The interrupt output is masked while CS is active. Nevertheless, the interrupt request itself will only be cleared if STA1 or STA2 (in case of C/l-change) is read (2). If CS becomes active and STA1 is not read during this access, INT becomes active again after CS is turned high (1). Semiconductor Group 33 Functional Description INT-Request (Internal) INT CS SCLK MISO x STA1 (1) (2) ITD06313 Figure 18 Interrupt Output Reset Logic The SmartLink in provides two reset outputs (RST, RST) if the undervoltage detection is active. An alternative mode selects RST as input while RST outputs the inverse of RST. The undervoltage detection is not active in this mode. Additionally, a watchdog timer is included which is started by a particular sequence. If it underruns, a reset signal is generated and some of the internal registers are reset. Undervoltage Detection During power-up, the reset output is active until the threshold voltage of VHH has been reached. After that, a period of tr is counted until the reset output becomes inactive. It stays inactive until the supply voltage drops below threshold level VHL. While the supply voltage is below the thresholds, the microcontroller clock MCLK is stopped and the MCLK-output remains low. If the supply voltage falls below threshold VHL, the clock is stopped immediately which may result in a shorter high period of the clock signal. Semiconductor Group 34 Functional Description For VHL and the hysteresis between VHL and VHH the following values are specified. Parameter Limit Values Unit min. max. VHL 4.2 4.4 V Hysteresis (VHH - VHL) 50 230 mV tr has a value of 1792 periods of the internal 32-kHz clock which is equal to 56 ms. The minimum period (tmin) for the undervoltage detection is at maximum 11 s. The delay (td) after threshold voltages have been passed is maximum 1 s. During power-up, the reset pulse may be extended due to the oscillator start until a stable 15.36-MHz clock is achieved. Figure 19 shows the undervoltage control timing. ~ ~ VHH VHL VDD t min RST ~ ~ ~ ~ RST td td tr tr MCLK ITD06314 Figure 19 Undervoltage Control Timing Semiconductor Group 35 Functional Description Watchdog Timer The counter which is used for the reset generation can be used as watchdog timer. Once the power detection reset has been elapsed, the counter is disabled. It can be enabled as watchdog timer with the first `10' sequence of the WTC1- and WTC2-bits. Once enabled, the software has to program `01', `10' sequences into the WTC1-, WTC2-bits each within 56 ms. If the next sequence doesn't occur within this period, a reset pulse is generated at the reset output which has a width of 56 ms. The watchdog reset will only effect the CTRL3-register to reset the SDS-bits so that SDS and BCL become low. The watchdog timer will also reset the CTRL1-register (PW5-0 bits, PRE1, 0) and the LCRI-bit so that the PWO/Ring output becomes low. RST RST WTC1, 2 '10' Watchdog Enabled '01' < 56 ms '10' < 56 ms '01' < 56 ms 56 ms 56 ms ITS06315 Figure 20 Watchdog Operation IOM-Clocks Signals during Reset The undervoltage detection generates internally a short reset pulse which is used to reset the internal registers and to trigger the 56 ms counter. After the short internal pulse is released, the Upn-transceiver is reset. As a result, lOM-clocks are generated at the begin of the 56 ms external reset pulse and last for 11 lOM-frames (1.375 ms). After that, the lOM-clocks are stopped if the Upn-interface remains deactivated. Generation of lOM-clocks is started after the SPU-bit is set in CTRL4 or if an external device requests lOM-clocks by pulling the data upstream (DU) line low. They are also started if an activation of the Upn-interface is triggered by the line card or terminal repeater. Semiconductor Group 36 Functional Description ~ ~ Internal Reset ~ ~ ~ ~ RST ~ ~ FSC DU ~ ~ INT HDLC X mit -Reset STA 1 : CIC = 1 STA 2 : CI 0 = 0000 C/I = 1111 in Buffer No further CIC R until IOM -Clocks are running ITD06316 Figure 21 IOM-Clocks Signals during Reset The ClC-bit in the STA1-register is set when the microcontroller reads the STA1-register for the first time because the Upn-transceiver outputs a `DR' indication when it is reset. The `DC' C/l-indication is stored in the C/l-buffer register. The software, after reading the STA1- and STA2-register will not get another ClC-status change unless the lOM-clocks are running. The value of the buffer register is transferred into the STA2-register only while lOM-clocks are running. If the SmartLink is configured for an external reset, the lOM-clocks remain running during the reset input is active. IOM-clocks will be stopped after the Upn-transceiver is reset following the end of the reset pulse. Semiconductor Group 37 Functional Description 2.1.3.2 IOM-2 Interface in TE-Mode The SmartLink-P supports the IOM-2 terminal mode. The interface consists of four lines: FSC, DCL, DD and DU. FSC transfers a frame start signal of which the rising edge indicates the start of an IOM-2 frame (8 kHz). The FSC-signal is generated by the receive DPLL which synchronizes it to the received Upn-frame. The DCL-signal is the clock signal to synchronize the data transfer on both data lines (768 kbit/s frequency is twice the transmission rate (1.536 MHz)). The first rising edge indicates the start of a bit while the second falling edge is used to latch the contents of the data lines. Additionally the BCL- and SDS-signals are provided to connect standard codecs to the SmartLink-P. The BCL (bit clock) provides a clock signal synchronous to the lOM-data at the same data rate. SDS provides a strobe signal which is active high during the B1- or B2- or IC1-channel. The length of the FSC-signal on the IOM-2 interface will be reduced to one DCL-period every eighth IOM-2 frame. A reduced FSC-signal is generated after a code violation has been received from the Upn-interface. IOM-2 Driver The output driver of the DD- and DU-pins is open drain. The output drivers are active for the selected time-slot bits and remain tristate during the rest of the frame. IOM-2 Frame Structure The principle frame structure of the IOM-2 terminal mode is shown in figure 22. The frame is composed of three channels. Semiconductor Group 38 Functional Description CH0 CH1 CH2 MR MX DU B1 B2 R IOM R IOM MON0 D CI0 U pn U pn MR MX IC1 R IOM R IOM IC2 MON1 CI1 IOM Transceiver BAC TAD R STA 2 CTRL 3 IOM R U pn Output only during TIC-Bus Access MR MX MR MX DD B1 B2 Upn Upn MON0 D CI0 R IOM R IOM IC1 IC2 IOM Transceiver Upn IOM MON1 R S/G A/B CI1 Upn IOM Used for Enabling the HDLC Transmitter (if programmed) R R ITD06317 Figure 22 IOM-2 Terminal Mode * Channel 0 contains 144 kbit/s of user and signaling data (2B + D) plus a MONITOR and command/indicate channel for control and programming of the layer-1 transceiver. * Channel 1 contains two 64-kbit/s intercommunication channels plus a MONITOR and command/indicate channel to program or transfer data to other IOM-2 devices. * Channel 2 is used for the TlC-bus access. Only the command/indicate bits are specified in this channel. Semiconductor Group 39 Functional Description IOM-2 Time-Slots used by the SmartLink-P The SmartLink-P accesses a subset of all IOM-2 channels. It provides access to the D-channel, the C/l-channel 0 and to the TlC-bus. The information of the B1-, B2- and D-channel time-slots is forwarded transparently between the IOM-2 interface and the transceiver (in the activated state). Other time-slots (like IC1, IC2, MON0, MON1 with control/status bits) are not influenced by the SmartLink-P. They can be controlled by other devices connected to the IOM-2 interface. The most significant three bits of the C/l-channel 1 are received in the STA2-register. Command/Indicate 0 C/l-code changes occur at maximum rate of 250 s (2 x lOM-frames). During activation the following sequence could occur: PU 2. Reg. 1. Reg. RSY AR AI RSY AR AI PU CS PU AI STA 2 STA 2 ITD06318 If the software is not able to follow each change, it will at least get the first one and the last one. Thus it knows from where it started and about the current status. Stop/Go Bit The Stop/Go (S/G) bit can be controlled by the received Upn T-channel to transmit the state of the line card arbiter to the HDLC-controller of the terminal. If selected by the SGE-bit, the HDLC-transmitter evaluates the state of the S/G-bit before and during transmission of an HDLC-frame. Semiconductor Group 40 Functional Description Available/Busy Bit The AB-bit has been added to the IOM-2 frame for the operation of a S/T-terminal adapter based on the SBCX. Since the SmartLink is not capable of transferring monitor channel data, a masked version of the SBCX was defined which reaches all necessary modes after reset. This part is called PSB 20810. The terminal needs to know if a PSB 20810 is plugged in to switch the routing of the downstream T-channel correctly. MUTE Function The SDS-bits control the data path of the upstream B-channel information. B-channel information may either be transparent (IOM Upn) or disconnected. In the latter state, a constant value of all `1' is transmitted to the Upn-interface instead of the IOM-2 B-channel information. This feature can be used to realize a MUTE function together with a simple codec. The downstream B-channel data is not influenced. B-Channel Loopback The information of a B-channel (B1 or B2) received from the Upn-interface can be looped back to the Upn-interface. The selection is done via the SDS2-0 bits. SDS2-0 (Mute) 1 U pn DU (Loopback) U pn Transceiver B1 or B2 DD ITS06319 Figure 23 B-Channel Manipulation Semiconductor Group 41 Functional Description 2.1.3.3 Upn-Interface Figure 24 demonstrates the general principles of the Upn-interface communication scheme. A frame transmitted by the exchange (LC) is received by the terminal equipment (TE) after a line propagation delay. The terminal equipment waits the minimum guard time (5.2 s) while the line clears. It then transmits a frame to the exchange. The exchange will begin a transmission every 250 s (known as the burst repetition period). However, the time between the reception of a frame from the TE and the beginning of transmission of the next frame by the LC must be greater than the minimum guard time. Within a burst, the data rate is 384 kbit/s and the 38-bit frame structure is as shown in figure 24. The framing bit (LF) is always logical `1'. The frame also contains the user channels (2B + D). Note that the B-channels are scrambled. It can readily be seen that in the 250-s burst repetition period, 4 D-bits, 16 B1-bits and 16 B2-bits are transferred in each direction. This gives an effective full duplex data rate of 16 kbit/s for the D-channel and 64 kbit/s for each B-channel. The final bit of the frame is called the M-bit. Four successive M-bits, from four successive Upn-frames, constitute a superframe (figure 24). Three signals are carried in this superframe. The superframe is started by a code violation (CV). From this reference, bit 3 of the superframe is the service channel bit (S). The S-channel bit is transmitted once in each direction in every fourth burst repetition period. Hence the duplex S-channel has a data rate of 1 kbit/s. It conveys test loop control information from the LC to the TE and reports of transmission errors from the TE to the LC. Bit 2 and bit 4 of the superframe are the T-bits. Not allocated to a specific function until now (cf PEB 2095 IBC and PEB 20950 ISAC-P) they can be used for D-channel control in conjunction with PEB 20550 ELIC and PEB 2096 OCTAT-P. In order to decrease DC-offset voltage on the line after transmission of a CV in the M-bit position, it is allowed to add a DC-balancing bit to the burst. The LC-side transmits this DC-balancing bit, when transmitting INFO 4 and when line characteristics indicate potential decrease in performance. Note that the guard time in TE is always defined with respect to the M-bit, whereas AMIcoding includes always all bits going in the same direction. The coding technique used on the Upn-interface is half-bauded AMI-code (i.e. with a 50 % pulse width). A logical `0' corresponds to a neutral level, a logical `1' is coded as alternate positive and negative pulses. In the terminal repeater mode, no DC-balancing bit will be generated. The loop length of the TR-mode is limited to 100 m. Semiconductor Group 42 Functional Description tr LT, TR td TE tg td LF B1 B2 D B1 B2 M DC 1 8 8 4 8 8 1 99 s CV T S T ITD05337 Binary Value 0 1 0 0 1 1 0 1 0 1 +V Line Signal 0 -V CV. ITD05338 Figure 24 Upn-Interface Structure Scrambler/Descrambler B-channel data on the Upn-interface is scrambled to give a flat continuous power density spectrum and to ensure enough pulses are present on the line for a reliable clock extraction to be performed at the downstream end. The SmartLink-P therefore contains a scrambler and descrambler, in the transmit and receive directions respectively. The basic form of these are illustrated in figure 25. The form is in accordance with the CCITT V.27 scrambler/descrambler and contains supervisory circuitry which ensures no periodic patterns appear on the line. Semiconductor Group 43 Functional Description D0 = Di + Ds ( Z -6 + Z -7 ) Scrambler OUT Z -1 Ds Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Ds Z -6 Di Ds Z -6 + Ds Z -7 + Ds Z -7 + ITD05339 Scrambler IN Do = Di = Ds (1 + Z -6 + Z -7 ) Descrambler IN Z -1 Ds Z -1 Z -1 Z -1 Z -1 Z -1 Z -1 Ds Z -6 Do + Ds Z -6 + Ds Z -7 Descrambler OUT + Ds Z -7 ITD05340 Figure 25 Scrambler/Descrambler Info Structure on the Upn-Interface The signals controlling the internal state machine on the Upn-interface are called infos. In effect these pass information regarding the status of the sending Upn-transceiver to the other end of the line. They are based upon the same format as the Upn-interface frames and their precise form is shown in table 1. When the line is deactivated info 0 is exchanged by the Upn-transceivers at either end of the line. Info 0 effectively means there is no signal sent on the line in either direction. When the line is activated info 3 upstream and info 4 downstream are continually exchanged. Both info 3 and info 4 are effectively normal Upn-interface data frames containing user data and exchanged in normal burst mode. Note that the structure of info 1 and info 2 are the same, they only differ in the direction of transmission. Similarily info 3/info 4 and info 1w/info 2w also constitute info pairs. This will be important when considering looped states. As we will see, the other infos are exchanged during various states which occur between activation and deactivation of the line. Semiconductor Group 44 Functional Description Table 1 Upn-Interface Info Signals Name Direction Description Info 0 Upstream Downstream No signal on the line Info 1w Upstream Asynchronous wake signal 2-kHz burst rate F0001000100010001000101010100010111111 Code violation in the framing bit Info 1 Upstream 4-kHz burst signal F000100010001000100010101010001011111M1) DC2) Code violation in the framing bit Info 2 Downstream 4-kHz burst signal F000100010001000100010101010001011111M1) DC2) Code violation in the framing bit Info 3 Upstream 4-kHz burst signal No code violation in the framing bit User data in B-, D- and M-channels B-channels scrambled, DC-bit2) optional Info 4 Downstream 4-kHz burst signal No code violation in the framing bit User data in B-, D- and M-channels B-channels scrambled, DC-bit2) optional Note: 1) The M-channel superframe is transparent: S-bits transparent (1-kbit/s channel) T-bits transparent (2-kbit/s channel) 2) DC-balancing bit Semiconductor Group 45 Functional Description The following test patterns are also included: Name Direction Description Info T1 Upstream Test signal single pulse 2-kHz burst rate 100000000... Info T2 Upstream Test signal continuous pulses 192-kHz clock rate 111111111... Upn-Transceiver Figure 26 depicts the transceiver architecture and the analog connections of the SmartLink-P. External to the line interface pins Lla and Llb a transformer and external resistors are connected as shown. Note that the internal resistors of the transformer are calculated as zero. The actual values of the external resistors must take into account the real resistor of the chosen transformer. The receiver section consists of an amplifier followed by a peak detector controlling the thresholds of the comparators. In conjunction with a digital oversampling technique the PSB 2197 SmartLink-P covers the electrical requirements of the Upn-interface for loop lengths of up to 4.5 kft on AWG 24 cable and 1.0 km on J-Y(ST) Y 2 x 2 x 0.6 cable. Semiconductor Group 46 Functional Description Transformer Ratio 2:1 U pn 25 2:1 175 100 nF SmartLink-P 0.33 F PSB 2197 175 25 ITS06320 Transformer Ratio 1:1.25 U pn 29 1: 1.25 78 SmartLink-P 100 nF 0.33 F PSB 2197 78 29 ITS06321 Figure 26 Upn-Transceiver of the SmartLink-P Upn-Transceiver Timing The receive PLL uses the 15.36-MHz clock to generate an internal 384-kHz signal which is used to synchronize the PLL to the received Upn-frame. The PLL outputs the FSCsignal as well as the 1.536-MHz double bit clock signal and the 768-kHz bit clock. The length of the FSC-signal is reduced in the next IOM-2 frame which is started while a Upn-frame is received, after a code violation has been detected. The reduced length of the FSC-signal provides synchronization between the TE- and the TR-transceiver to gain the shortest delays on the Upn T-channel data forwarding. Semiconductor Group 47 Functional Description D U pn B1 B2 CV D B1 B2 B1 B2 CV D B1 B2 B1 B2 T D B1 B2 B1 B2 T B1 B2 FSC DU B1 B2 B1 B2 D DD D B1 B2 BAC B1 B2 D D S/G ITD05348 Figure 27 Upn-Transceiver Timing B1-, B2-Channels The lOM-interface B-channels are used to convey the two 64-kbit/s user channels in both directions. However, the PSB 2197 SmartLink-P only transfers the data transparently in the activated state (incl. analog loop activated) while the data are set to `1' in any non activated state (cf. state descriptions). D-Channel Similar to the B-channels the layer-1 (Upn) part of the PSB 2197 SmartLink-P transfers the D-channel transparently in both directions in the activated state. T-Bit Transfer In TE-mode the layer-1 (Upn) part of the PSB 2197 SmartLink-P conveys the T-bit position of the Upn-interface to either the S/G-bit position or the A/B-bit position according to the register programming. The exact bit polarities are as follows: Downstream (Upn IOM) T-to A/B-mapping (CTRL3: TCM = 1): T = 0: T = 1: A/B = 0 S/G = 1 blocked A/B = 1 S/G = 1 available T-to S/G-mapping (CTRL3: TCM = 0): T = 0: T = 1: Semiconductor Group A/B = 1 S/G = 1 blocked A/B = 1 S/G = 0 available 48 Functional Description Upstream (IOM Upn) The T-channel in upstream direction is controlled by the BAC-bit of the IOM-2 interface. The T-channel transmits the inverse of the BAC-bit. Special care is taken so that the slave terminal will only send one HDLC-frame until the TlC-bus of the master IOM-2 interface is release. This is achieved by a circuitry which latches the BAC-state of `1' until at least one T-bit has been transmitted with the value of `0' which releases the TlC-bus of the master IOM-2 interface. BAC to T-mapping: BAC = 1 BAC = 0 T=0 T=1 no D-channel request D-channel request Control of the Upn-Transceiver An incorporated finite state machine controls the activation/deactivation procedures and communications with the layer-2 section via the lOM-Command/Indicate (Cl) channel 0. Diagnostics Functions Two test loops allow the local or the remote test of the transceiver function. Test loop 3 is a local loop which loops the transmit data of the transmitter to its receiver. The information of the IOM-2 upstream B- and D-channels is looped back to the downstream B- and D-channels. The M-bit is also transparent which means that the state of the BAC-bit is looped back to the S/G- or AB-bit. Test loop 2 is activated by the Upn-interface and loops the received data back to the Upn-interface. The D-channel information received from the line card is transparently forwarded to the downstream IOM-2 D-channel. The downstream B-channel information on IOM-2 is fixed to `FF'H while test loop 2 is active. Semiconductor Group 49 Functional Description 2.1.4 D-Channel-Arbitration in TE-Mode The SmartLink-P supports different kinds of D-channel arbitration in order to share the upstream D-channel by several communication controllers and to allocate the D-channel from the Upn-interface. The following functions are performed depending on the register settings: - Allocation of the upstream D-channel bits on the IOM-2 interface via the TlC-bus. - Control of the HDLC-transmitter by the stop/go bit. TlC-Bus Access The terminal IC-bus provides an access mechanism to share the D-channel in upstream direction by several communication controllers (ICC, ISAC, SmartLink) connected to one layer-1 device. The Bus Accessed bit (BAC) is used to indicate that the TlC-bus is currently occupied and other devices have to wait. The different communication controllers use individual TlC-bus addresses in the range of `0' to `7'. A collision detection mechanism checks each bit of the TIC-bus address for congestion. Since a `0' has higher priority against a `1', a TlC-bus address of `0' has the highest priority and `7' has the lowest one. TlC-Bus Access Mechanism During idle state, the Bus Accessed bit (BAC) is set to `1' and the TlC Bus Address (TBA) is `7'. If a communication controller needs access to the D-channel bits, it will check the state of the BAC bit. If BAC is `1' (idle) it will place its TlC-bus address on the TAD2-0 bits. After each bit has been outputted, it checks for collision and stops transmitting if a collision is detected (`1' transmitted, `0' detected on the DU-line). If the TlC-bus address has been transmitted successfully, the D-channel and C/I-channel 0 are controlled from the controller in the next frame and the BAC-bit is set to `0'. After the TlC-bus access is completed, the TlC-bus returns to the idle state (BAC = `1', TAD = `111') and other devices can gain access. A device which has detected a collision during the transmission of the TlC-bus address will restart after the BAC-bit becomes idle `1' again. In order to provide access to all controllers, the device which has gained successful access to the TlC-bus will wait for two idle frames before it starts another access. Note: The SmartLink will also set the BAC-bit if the TlC-bus address of seven (`111') is programmed. This is different to the TlC-bus operation of the ICC (PEB 2070) and ICC-based devices (ISAC-S (TE), ISAC-P (TE)). Stop/Go Bit The stop/go bit controls the transmitter output of the D-channel HDLC-controller if selected by the SGE-bit. The transmitter is active, as long as the stop/go bit indicates go (`0'). Semiconductor Group 50 Functional Description The S/G-bit is checked before a HDLC-frame is started and monitored during the transmission of the HDLC-frame. The HDLC-transmitter aborts the transmission of an HDLC-frame if the S/G-bit becomes `Stop' after the begin of a frame was transmitted. It will output `11' in the D-bits of the lOM-frame beginning with the following lOM-frame after S/G becomes `Stop' until `Go' is indicated. The evaluation of the S/G-bit must be enabled by the CTRL3:SGE-bit. The stop/go bit can be controlled by the downstream T-bit which indicates the receive capability of the line card or by the PSB 20810 in case a S/T-interface adapter is plugged onto the IOM-2 interface. HDLC-Controller Access Modes The access mode of the D-channel HDLC-controller is programmable. It can ignore the TlC-bus, use the TlC-bus to gain access and evaluate the S/G-bit. Table 2 shows the possible combinations. Table 2 HDLC-Controller Access Modes TBU SGE TIC-Bus Access S/GEvaluation Application 1 0 Yes No TIC-bus access without S/G-bit evaluation 1 1 Yes Yes TIC-bus access with S/G-bit evaluation 0 0 No No Permanent D-channel access without S/G-bit evaluation 0 1 No Yes Permanent D-channel access with S/G-bit evaluation If the HDLC-controller is set to a mode where the S/G-bit is evaluated, the transmission is started if the S/G-bit becomes go (`0') and stopped if the S/G-bit becomes stop (`1'). If the D-channel becomes not available before the final bit of the closing flag has been sent, the transmission is aborted. In case the collision occurred during the first XFIFO contents, the frame is automatically retransmitted. If the first XFIFO contents has already been sent, a XMR-status is generated and the microcontroller has to repeat the complete frame again. Semiconductor Group 51 Functional Description 2.1.5 HDLC-Controller The HDLC-controller performs the layer-2 functions of the D-channel protocol: - - - - - Flag generation/detection Zero bit insertion/deletion CRC-generation/check (CCITT polynomial X16 + X12 + X6 + 1) Abort generation Idle signal generation (`1') HDLC-Frame Formatting The HDLC-transmitter starts a HDLC-frame with a flag. It continues with the data of the XFIFO. The end of a frame is indicated by a closing flag preceeded by the 16-bit CRC-check sum or by an abort sequence. Flag Data CRC Flag XFIFO Figure 28 HDLC-Transmitter Format The HDLC-receiver hunts for flags which are not followed by another flag or an abort sequence. It stores the information in the RFIFO until the end of the frame has been detected. The status of the received frame (CRC-status, end of frame condition etc.) is reported via a status byte which is stored in the RFIFO immediately following the last byte of a message. The HDLC-receiver of the SmartLink will receive two frames correctly if they are separated by only one common flag (shared flag). It will also receive two frames correctly if they are separated by two flags (back-to-back frames). Flag Data CRC Data RSTA RFIFO Figure 29 HDLC-Receiver Format Semiconductor Group 52 Flag Functional Description 2.1.6 Terminal Specific Functions 2.1.6.1 LCD-Contrast Control The Pulse Width Output/Ring provides a pulse width modulated signal which can be varied in 14 linear steps between OFF and ON. The repetition frequency is 8.5 kHz. The LCD-contrast control is enabled by setting the LCRI-bit to `0'. The output of the PWM is filtered by a low pass filter and transformed to the required voltage range by an external transistor as shown in figure 30. V DD PWO LCD Contrast SmartLink-P PSB 2197 - V LCD 117.6 s ITS06322 Figure 30 LCD-Contrast Control Semiconductor Group 53 Functional Description 2.1.6.2 Ring Tone Generation The SmartLink-P can generate frequencies at the Pulse Width Output/Ring. The ring tone generator uses a 16 kHz-clock input and divides it by a programmable value of n = 1 to 63. The PWO/Ring output is tristate while PW5-0 are `000000'. The following list shows examples of frequencies: Value (PW5-0) Frequency (Hz) 8 (001000) 2000 10 (001010) 1600 11 (001011) 1454 12 (001100) 1333 14 (001110) 1142 15 (001111) 1066 17 (010001) 941 19 (010011) 842 20 (010100) 800 21 (010101) 761 23 (010111) 695 27 (011011) 592 29 (011101) 551 33 (010001) 484 36 (100100) 444 41 (101001) 390 51 (110011) 313 Ring tones change or stop at the end of a half or full cycle. This includes switching to tristate. Semiconductor Group 54 Functional Description Piezo PWO/RING SmartLink-P PSB 2197 16 kHz :(n+1) n = 1...63 PWO/ RING 250...8000 Hz ITS06323 Figure 31 Ring Tone Generation Semiconductor Group 55 Functional Description 2.2 Terminal Repeater (TR) Mode 2.2.1 General Functions and Device Architecture (TR-Mode) In TR-mode the following functions are provided: * Upn-interface transceiver, functionally fully compatible to both PEB 2095 IBC and PEB 2096 OCTAT-P, also features the terminal repeater mode * IOM-2 interface for terminal application * A microcontroller clock is not generated TR-Mode 15.36 MHz 100 ppm XTAL2 U pn XTAL1 0V + 5V VSS VDD LI a R IOM -2 DD DU LI b FSC DCL TR/TE ( +5 V ) PWO/RING/MODE ( +5 V ) VDDDET/TCM RST SCLK MOSI CS RST VSS Figure 32 Device Architecture in TR-Mode Semiconductor Group 56 VSS VDD ITS06324 Functional Description 2.2.2 Clock Generation (TR-Mode) In TR-mode, the oscillator is used to generate a 15.36-MHz clock signal. This signal is used by the DPLL to synchronize Upn-frames to the received IOM-2 clocks (FSC, DCL). No other clocks are generated. DU DD U pn - State Machine 15.36 MHz OSC 15.36 MHz D - Channel Arbitration TIC - Bus Controller (CIO) IOM R -2 Interface FSC DPLL DCL ITS05355 Figure 33 Clock Generation in TR-Mode Semiconductor Group 57 Functional Description 2.2.3 Interfaces (TR-Mode) In TR-mode, two interfaces are active: * IOM-2 interface: as a universal backplane for terminals * Upn-interface towards the two-wire slave subscriber line The microcontroller interface remains active in TR-mode. As a result, the CS-input has to be connected to VDD and MOSI has to be connected to VSS avoid accidental programming. 2.2.3.1 IOM-2 Interface in TR-Mode The SmartLink-P supports the IOM-2 terminal mode. The interface consists of four lines: FSC, DCL, DD and DU. FSC and DCL provide the clock inputs to synchronize the Upn-transceiver to the IOM-2 interface. DU and DD are open drain outputs. CH0 CH1 CH2 MR MX DU B1 B2 MON0 D CI0 MR MX IC1 IC2 MON1 CI1 ** R IOM R IOM U pn U pn BAC TAD ** IOM Transceiver IOM U pn R Indicates Activated State of Upn Interface R 'O' Indicates Presents of TR IOM '011' * Output only during TIC-Bus Access MR MX MR MX DD B1 B2 R IOM R IOM MON0 D CI0 U pn U pn IC1 R IOM R IOM IC2 MON1 Transceiver CI1 Used to Control the T-Channel U pn ITD05356 Figure 34 IOM-2 Frame Structure in TR-Mode Semiconductor Group S/G A/B 58 R Functional Description The SmartLink-P transfers the B-channel information between the IOM-2 and the Upn-interface during the activated state. During all other states, `FF' is output. The C/l-channel 0 as well as the upstream D-bits are occupied by the TR-SmartLink after a TlC-bus access has been performed. The BAC- and TAD-bits are used for the TlC-bus access. The SmartLink-P in TR-mode pulls bit 5 of the upstream command/indicate channel 1 to `0' after reset and remains `0' for identification of the TR-module by a terminal SmartLink-P or ISAC-P TE. Bit 6 of the upstream C/l-channel 1 is also controlled by the SmartLink-P in TR-mode. It is set to `0' if the Upn-interface is in the activated state. Otherwise, the bit remains `1'. 2.2.3.2 Upn-lnterface in TR-Mode Upn-Transceiver The transmitter uses the received FSC-signal to start the generation of a Upn-frame. If a short FSC-length (1 x DCL) is detected, the superframe counter is reset and the next Upn-frame will transmit the CV in the M-bit. During normal length of the FSC-signal (64 DCL-clocks), the superframe counter is not changed. FSC D BAC DU B1 B2 D B1 B2 D B1 B2 D Upstream S/G B1 B2 B1 B2 T B1 B2 D B1 B2 B1 B2 D B1 B2 D DD B1 B2 U pn D B1 B2 D Downstream B1 B2 B1 B2 CV D B1 B2 D Upstream B1 B2 CV B1 B2 D Downstream T ITD05357 Figure 35 Upn-Transceiver Timing Semiconductor Group 59 Functional Description Control of the Upn-Transceiver An incorporated finite state machine controls the activation/deactivation procedures and communications with the layer-2 section via the lOM-Command/Indicate (C/l) channel 0. In TR-mode, activation from the terminal side is started by a power-up sequence in case the FSC- and DCL-clocks are turned off. After that, a TlC-bus access is performed and activation is started by outputting the C/l-code `AR'. After that, the Upn-interface is activated and after completion of the procedure, the C/l-code `Al' is output. The length of the FSC-signal is monitored. The state-machine of the Upn-transceiver is reset every time, a FSC-period of less than 96 bits is detected. It will generate a reset signal for the state machine which is active for 6 lOM-frames. As a result, 4 or 5 info 0 frames will be transmitted on Upn a to force the TE-device in the level detect (resynchronization) state. This number of info 0 frames is still less than is required to detect Info 0 by the TE-device (2 ms, 8 info 0 frames). This procedure is necessary to avoid incorrect switching of internal B-channel buffers which corrupt the sequence of B-channel transfer between IOM and Upn. 2.2.4 D-Channel-Arbitration in TR-Mode The D-channel arbitration is done using the TlC-bus features and the T-channel of the Upn-interface. TlC-Bus Idle If the TlC-bus is idle (BAC = `1', TAD = `111'), upstream D-channel data is transparently switched to the IOM-2 D-channel. No C/l0-code is transmitted by the TR-SmartLink. D-Channel Request A D-channel request is indicated by the terminal connected to the TR-SmartLink by setting the upstream T-channel to `1' (inverse of its IOM-2 BAC-bit). As a result, the TR-SmartLink tries to access the TlC-bus by outputting the TIC-bus address (`011'). After successful transmission of all three bits, the BAC-bit is set to `1' in the following IOM-2 frame and the TlC-bus is occupied. On the C/l-channel 0, the code `Al' (`1100') is output. D-Channel Release After the terminal connected to the TR-SmartLink has completed its HDLC-frame, the upstream T-channel becomes `0' (inverse of its IOM-2 BAC-bit). This transition from T = `1' to T = `0' is delayed by the TR-SmartLink by two lOM-frames before the TlC-bus is released. This delay is necessary to assure that the D-channel contents of the Upnframe which included the T-channel is output completely. Semiconductor Group 60 Semiconductor Group Figure 36 D-Channel Arbitration in TR-Mode 61 Slave-DD Slave-DU Master-DD Master-DU FSC xx 0 01 CV xx01 CV 0 11 0 0 11 0 xx T 0 10 1111 T 0 01 1 01 0 11 S 0 11 1001 S 0 11 0 11 0 10 T 0 10 1111 T 0 01 0 xx 0 11 CV 0 xx 10xx CV 0 11 0 xx 1 10 T 0 xx T 0 xx 1 xx 1 TAD xx ITD06326 0 0 Functional Description Functional Description 2.2.5 Reset In TR-mode, the undervoltage detection is not active. To reset the SmartLink-P in TR-mode an external reset signal must be applied on the RST input. The reset will deactivate the Upn-transceiver and it will abort any TIC-bus access currently in progress. The TIC-bus returns to idle. While the reset signal is active, at least 40 clock pulses must be applied to XTAL1 and at least 4 DCL-pulses. More than 10 clock pulses on XTAL1 are required after reset becomes inactive. At least 6 IOM-frames are necessary after reset is released to put the Upn-transceiver in its deactivated state from which an asynchronous awake is possible if a level is detected on the Upn-interface pins. RST XTAL 1 <_ 40 Clocks <_ 10 Clocks FSC DCL R <_ 6 IOM -Frames <_ 4 DCL U pn Reset U pn deactivated Software Awake possible ITD06327 Figure 37 Semiconductor Group 62 Functional Description 2.3 HDLC-Controller Mode 2.3.1 General Functions and Device Architecture (HDLC-Controller Mode) Figure 38 depicts the detailed architecture of the PSB 2197 SmartLink-P in HDLCcontroller mode: * * * * Serial control port HDLC-controller with 2 x 4 byte FlFOs per direction TlC-bus access control IOM-2 interface for terminal application DU DD FSC DCL BCL SDS R IOM -2 Interface TIC- Bus HDLC Transmitter HDLC Receiver CIO Serial Control Port SCLK MOSI MISO CS Reset Logic INT XTAL 1 Clock TR/TE VDD PWO/RING/MODE VDD VDDDET/TCM RST RST Figure 38 Device Architecture of the SmartLink-P in HDLC-Controller Mode Semiconductor Group 63 1) VDDDET ITS06328 Functional Description 2.3.2 Clock Generation (HDLC-Controller Mode) In HDLC-controller mode, the oscillator input is used to achieve the reset state of the Upn-transceiver. All other functions which use the oscillator frequency in TE-mode (undervoltage detection, watchdog, microcontroller clock output, PWO/RING) are disabled. The IOM-2 clock signals (FSC, DCL) are used to synchronize the HDLC-data transfer and the access to the TIC-bus. A bit clock signal as well as a strobe signal for B1, B2 or IC1 may be generated. DU DD HDLC Controller TIC-Bus Controller (CIO) R IOM -2 Interface SDS BCL FSC DCL ITS06329 Figure 39 Clock Generation in HDLC-Controller Mode 2.3.3 Interfaces (HDLC-Controller Mode) The PSB 2197 SmartLink-P serves two interfaces in HDLC-controller mode: * Serial microcontroller interface for higher layer functions * IOM-2 interface: between layer-1 and layer-2 and as a universal backplane for terminals * Bit clock and strobe signal generation 2.3.3.1 Microcontroller Interface The SmartLink-P provides a serial microcontroller interface which is compatible to the SPI-interface of Motorola or Siemens C510x microcontrollers. Its function is identical to the TE-mode. Semiconductor Group 64 Functional Description 2.3.3.2 IOM-2 Interface in HDLC-Controller Mode The SmartLink-P supports the IOM-2 terminal mode. The interface consists of four lines: FSC, DCL, DD and DU. FSC and DCL provide the clock inputs to synchronize the data transfer over the IOM-2 interface. DU and DD are open drain outputs. A bit clock and strobe signal may be generated locally. CH0 CH1 CH2 MR MX DU B1 B2 MON0 D CI0 MR MX IC1 R IOM R IOM IC2 MON1 Transceiver BAC TAD CI1 CTRL 1:2-0 IOM R STA 2 CTRL 3 IOM R U pn Output only during TIC-Bus Access MR MX MR MX DD B1 B2 MON0 D CI0 IC1 IC2 IOM Transceiver Upn IOM MON1 S/G A/B CI1 R Used for Enabling the HDLC Transmitter (if programmed) R ITD06330 Figure 40 IOM-2 Frame Structure in HDLC-Controller Mode The C/l-channel 0 as well as the upstream D-bits are occupied by the HDLC-controller mode SmartLink after a TlC-bus access has been performed. The BAC- and TAD-bits are used for the TlC-bus access. The SmartLink-P in HDLC-controller mode outputs the value of CTRL1:2-0 as Cl1 bits 7 to 5. After reset, they remain `1'. All other time-slots are not influenced by the SmartLink-P in HDLC-controller mode. Semiconductor Group 65 Functional Description 2.3.4 D-Channel-Arbitration in HDLC-Controller Mode The D-channel arbitration is identical to the one in TE-mode. 2.3.5 HDLC-Controller The HDLC-controller functions are identical to the ones in TE-mode. 2.3.6 Reset The HDLC-controller mode is reset by applying a reset pulse to the RST-input. To bring the Upn-transceiver to a low power state, the following requirements must be fulfilled: While reset is active, at least 40 clock pulses must be applied to XTAL1. After reset is released, another 10 clock pulses are required. The Upn-transceiver enters its low power deactivated state after 6 lOM-frames which are generated after the 50 clock pulses on XTAL1 have elapsed. RST XTAL1 < 40 Clocks <_ 10 Clocks FSC DCL <_ 6 IOM R -Frames U pn Reset U pn Deactivated ITD06331 Figure 41 Reset Semiconductor Group 66 Operational Description 3 Operational Description 3.1 TE-Mode 3.1.1 Interrupt Structure and Logic The SmartLink-P provides one interrupt output which is used to indicate a change in the receiver or transmitter status or a change in the CI0-code. The microcontroller has to read the first status byte (STA1). The first status byte indicates changes of the receiver/transmitter section. CI0-code changes are indicated by the ClC-bit. In case of a CI0-change, the microcontroller has to evaluate the second status byte (STA2). It contains the new CI0-code value. Reading the STA1-status byte clears the interrupt request and the RPF-, RME-, XFS-, RFO-bits. The ClC-status bit and the interrupt generation by that bit is cleared by reading STA2. INT And/Or CTRL2 RIE ISYNC RPF RME XFS1 XFS0 RFO CIC RBC1 RBC0 STA1 CI1/7 CI1/6 CI1/5 XFW CI0 CI0 CI0 CI0 STA2 ITS06332 Figure 42 SmartLink-P Interrupt Structure The transmitter and C/l-change interrupts are permanently enabled. The generation of receiver interrupts is enabled by the RlE-bit. After reset, this bit is cleared and receiver interrupts are disabled. Changes in the received CI1-bits as well as a change in the XFW-bit will never generate an interrupt. Semiconductor Group 67 Operational Description 3.1.2 Control of the Upn-Transceiver 3.1.2.1 Power-Down of the IOM-2 Interface In order to reduce power consumption in the non-operational status the IOM-2 interface is brought into power down while the Upn-transceiver is in the deactivated state. The clocks are stopped at bit position 30 (starting with 1). FSC remains high, DCL remains at low voltage level, the data lines remaining pulled up by the external pull up resistors. For the exact procedures please refer to the IOM-2 Reference Guide Edition 3.91. Since the length of the FSC-signal is reduced every eight frames, the oscillator stops only during the regular length of a FSC-signal. BCL and SDS if enabled remain `0' during power-down. During power-down state (C/l = `1111'), only the lOM-clock signals are turned off. The oscillator, the Upn-awake detector is active as well as the microcontroller clock, pulse width modulator clock and watchdog counter. The power-down state is left when an asynchronous awake signal has been detected. The IOM-clocks are started. After the asynchronous awake signal is stopped, one device on IOM-2 must output CI0-codes different from `DI' (Deactivation Indication, `1111') to keep the IOM-2 interface running. The asynchronous awake may be generated by any device by pulling the DU-line to `0'. The SmartLink in TE-and HDLC-controller mode can force DU to `0' by setting the SPU-bit in CTRL4. 3.1.2.2 Activation/Deactivation of the Upn-lnterface The Upn-transceiver functions are controlled by commands issued in the CTRL4register. These commands are transmitted over the C/l-channel 0 and trigger certain procedures such as activation/deactivation and switching of test loops. Indications from layer-1 are obtained by evaluating the second status byte (STA2) after a ClC-status is indicated (STA1). Semiconductor Group 68 Operational Description 3.1.2.3 Layer-1 Command/lndication Codes in TE-Mode Command (Upstream) Abbr. Code Remarks Timing TIM 0000 Layer-2 device requires clocks to be activated Reset RES 0001 Software reset Send Single Pulses SSP 0010 Ones (AMI) pulses transmitted at 4 kHz Send Continuous Pulses SCP 0011 Ones (AMI) pulses transmitted continuously Activate Request AR 1000 Activate Request Loop 3 ARL 1001 Deactivation Indication Dl 1111 Indication (Downstream) Abbr. Code Deactivation Request DR 0000 Power-Up PU 0111 Test Mode Acknowledge TMA 0010 Acknowledge for both SSP and SCP Resynchronization RSY 0100 Receiver not synchronous Activation Request AR 1000 Receiver synchronized Activation Request Loop 3 ARL 1001 Local loop synchronized Activation Request Loop 2 ARL2 1010 Remote loop synchronized Activation Indication AI 1100 Local analog loop Remarks Activation Indication Loop 3 AIL 1101 Local loop activated Activation Indication Loop 2 AIL2 1110 Remote loop activated Deactivation Confirmation 1111 Line and lOM-interface are powered down Semiconductor Group DC 69 Operational Description 3.1.2.4 State Diagrams Activation/Deactivation The internal finite state machine of the PSB 2197 SmartLink-P controls the activation/deactivation procedures. Such actions can be initiated by signals on the Upn-transmission line (INFO's) or by control (C/l) codes sent over the C/I-channel 0 of the lOM-interface. The exchange of control information in the C/I-channel is state oriented. This means that a code in the C/l-channel is repeated in every lOM-frame until a change is necessary. A new code must be recognized in two consecutive IOM-frames to be considered valid (double last look criterion). The activation/deactivation procedures implemented by the PSB 2197 SmartLink-P agree with the Upn-interface as it is implemented by the PSB 2196 ISAC-P TE. In the state diagrams a notation is employed which explicitly specifies the inputs and outputs on the Upn-interface and in the C/I-channel 0. 3.1.2.5 TE-Mode State Description Reset, Pending Deactivation State after reset or deactivation from the Upn-interface by info 0. Note that no activation from the terminal side is possible starting from this state. A `DI'-command has to be issued to enter the state deactivated. Deactivated The Upn-interface is deactivated and the IOM-2 interface is or will be deactivated. Activation is possible from the Upn-interface and from the IOM-2 interface. Power-Up The Upn-interface is deactivated and the IOM-2 interface is activated, i.e. the clocks are running. Pending Activation Upon the command Activation Request (AR) the PSB 2197 SmartLink-P transmits the 2-kHz info 1w towards the network, waiting for info 2. Level Detect, Resynchronization During the first period of receiving info 2 or under severe disturbances on the line the Upn-receiver recognizes the receipt of a signal but is not (yet) synchronized. Semiconductor Group 70 Operational Description Synchronized The Upn-receiver is synchronized and detects info 2. It continues the activation procedure by transmission of info 1. Activated The Upn-receiver is synchronized and detects info 4. It concludes the activation procedure by transmission of info 3. All user channels are now conveyed transparently. Analog Loop 3 Pending Upon the C/l-command Activation Request Loop (ARL) the PSB 2197 SmartLink-P loops back the transmitter to the receiver and activates by transmission of info 1. The receiver is not yet synchronized. Analog Loop 3 Synchronized After synchronization the transmitter continues by transmitting info 3. Analog Loop 3 Activated After recognition of the looped back info 3 the channels are looped back transparently. Test Mode Acknowledge After entering test mode initiated by SCP-, SSP-commands. Semiconductor Group 71 Operational Description DC ARL DI DI Deactivated Test Mode i TIM i0 SCP TMA SSP TIM i0 it i * AR i0 DI ARL SCP SSP Loop 3 TIM AR PU AR Pending Activation DI TIM DI TIM PU Power-Up AR i1w i0 i0 i0 RSY i0 i0 DI AR Level Detect i0 i0 i0 i2 AR + DI ARL2 AR DR i2 x i4 x i0 DI RES TIM Reset i0 Synchronized * i0 i1 i2 RST RES i4 OUT IN Ind. Cmd. DI AI + AIL2 i2 DI AR i4 Activated i3 i4 i0 DR AR Pending Deactivation i0 IOM State U pn i0 Unconditional transitions initiated by commands: RES, SSP, SCP External pin: RST + : AR, AI indications if S = 0 ; ARL2, AIL2 indications if S = 1 (analog Loop 2) Figure 43 State Diagram TE-Mode Semiconductor Group R TIM 72 ix ir ITD05369 Operational Description ARL RES AR TIM DI PU ARL Pend. Loop 3 i1 i0 i2 RES AR TIM DI ARL ARL Loop 3 Synchroni. i3 i2 x i4 i2 i4 OUT IN Ind. Cmd. RES AR TIM DI AIL ARL Loop 3 Activated i3 IOM R i4 State U pn i4 ix ir ITD05370 Figure 44 State Diagram TE-Mode (Test Loop 3) Semiconductor Group 73 Operational Description 3.1.2.6 Example of the Activation/Deactivation Figure 45 shows the activation/deactivation procedure between the line card (Octat-P) and the terminal (SmartLink-P). TE PowerDown LC DC DC INFO 0 DI DI ~~ ~~ ~~ Deactivated State ~~ SPU = 1 PU AR, SPU = 0 INFO 1w T1 INFO 2 T1 RSY AR INFO 0 T2 T2 INFO 1 AR RDS INFO 4 T3 ~~ T3 INFO 3 AI ~~ AI ~~ ~~ INFO 0 T4 DR DR INFO 0 T4 DC DC INFO 0 DI R IOM -2 U pn Interface Figure 45 Activation/Deactivation (LC, TE) Semiconductor Group Activated State 74 DI R IOM -2 Deactivated State ITD05371 Operational Description 3.1.3 Operation of the Serial Control Interface A state machine controls the operation of the serial control port. It performs the necessary read and write operations to the internal registers. Begin of Transmission The begin of a transmission is indicated by pulling CS low. This will force the MlSO-output to drive the current value of the shift register output. At the same time, the execution of HDLC-controller commands is disabled. The first falling edge will force the state machine to load the current value of STA1 into the shift register and output the MSB. The following clocks shift the contents of STA1 over the MlSO-line. At the same time, the MOSI-line receives the value of CTRL1. Its value is stored in the CTRL1-register with the rising edge of the last clock period. The state machine will transfer the contents of STA2 into the shift register at the next falling edge on the clock line and outputs the MSB of the shift register. The next clock pulses transfer the STA2-value while CLTR2 is received. The rising edge of the eighth clock period is used to transfer the contents of the shift register into CTRL2-register. The command bits are disabled until the end of the transfer. In transmit direction (SmartLink-P P), the contents of RFlFO-data will follow if a receive status condition was reported and receiver command has not been issued. Similar to register accesses, this occurs with the first falling edge of the clock signal. In receive direction (P SmartLink-P), the operation of the state machine depends on the value of XBC1, 0 and HXC1, 0 bits. If HXC1, 0 indicates a XTF or XTF x XME-command, the number of bytes indicated in XBC1, 0 are received and transferred into the XFIFO with the rising edge of every eighth clock signal. If HXC1, 0 indicates no command (`00') and XBC1, 0 indicates `01', the following two bytes are stored in CTRL3 and CTRL4 with the rising edge of every eighth clock signal. RFlFO-data is not output if CTRL2 indicates that CTRL3 and CTRL4 will follow. All further information will be ignored. End of Transfer At the end of the transfer which is determined by the CS-line to become high, the commands (XTF, XTF x XME, XRES, RMC, RMD, RRES) are enabled again. Semiconductor Group 75 Operational Description Error Detection The state machine monitors the number of bits transferred. Only if eight bits have been transmitted, the contents of the shift register is transferred into the proper register. No special error indication is provided. In order to avoid locking of the HDLC-operation by a spurious clock pulse on the serial control interface, two additional status bits are added. RFO (Receive Frame Overflow) indicates that the start of a frame could not be stored in the RFIFO. This indication is helpful if the value of the STA1-byte has been changed so that the RPF- or RME-status bit was not transferred correctly. The microcontroller has to acknowledge the RFIFO by RMC-commands until all frames which were buffered in the RFIFO have been read. XFW (Transmit FIFO Write Enable) informs that the XFIFO is free and data can be entered. In case a XPR-status bit is not transferred correctly over the serial control interface, the microcontroller may poll the XFW-bit after a certain period of time to see if the XFIFO is accessible. Timing between Bytes The bytes can follow immediately or with gaps between the bytes. There is no maximum pause specified. The only requirement is that the CS-Iine remains active during the gap. Minimum Pause between Accesses A minimum time of 10 DCL clocks must elapse between two accesses to the serial control interface (CS becoming low) to assure that a previously entered command is executed correctly. Semiconductor Group 76 Operational Description 3.1.4 Control of the HDLC-Data Transfer The control of the HDLC-data transfer is optimized for full duplex operation via the serial control interface. A standard interrupt response takes up to six bytes to read/write the HDLC FlFOs. 3.1.4.1 HDLC-Transmitter The HDLC-transmitter consists of a 2 x 4 byte FIFO. One half is connected with the transmit shift register while the other half is accessible via the microcontroller interface. Two status bits are controlled by the HDLC-transmitter to indicate a new status. The HDLC-transmitter is controlled by two bits which act as command. The corresponding bits of the CTRL2-register start the command. After the command has been executed, these bits are reseted automatically. One command is used to indicate that the contents of the XFIFO is part of a frame and has to be transmitted (XTF). Another command (XTF x XME) indicates that the final part of a message has been entered into the XFIFO and has to be transmitted. In this case, the CRC-bytes as well as the closing flag is appended to the last byte from the XFIFO. The last command (XRES) resets the HDLC-transmitter, aborts a HDLC-frame currently in transmission and generates an XPR-status after the command has been completed. A new frame immediately entered after the XPR-status bit was set is delayed until the abort sequence has been completed. Three state changes are indicated by the transmit FlFO-status bits. XPR indicates that the FIFO is able to load up to four new bytes to begin a message or to continue the frame. XMR indicates that the current frame has been aborted via the S/G-bit after the first FlFO-contents. The data of the frame has to be reentered. A XPR-status is generated immediately after XMR has been read to indicate that the FIFO is able to load new data. XDU indicates that the contents of the FIFO has been transmitted and no endof-frame indication was issued. The transmitted frame has been aborted by a sequence of seven `1'. XFS1 XFS0 Status State Action 0 0 No status change Non or enter begin of message 0 1 XPR Transmit Pool Ready Enter up to four bytes 1 0 XMR Transmit Message Repeat Retransmit the message 1 1 XDU Transmit Data Underrun Frame has been aborted Semiconductor Group 77 Operational Description The HDLC-transmitter and the transmit buffer are controlled by two bits of the second control byte (CTRL2). HXC1 HXC0 Command State 0 0 No command 0 1 XTF 1 0 XTF x XME Transmit Transparent Frame and Transmit Message End 1 1 XRES Transmit Transparent Frame Transmitter Reset 3.1.4.2 HDLC-Receiver The HDLC-receive FIFO contains 2 x 4 bytes. One half of the RFIFO (top half) is connected to the receiver shift register while the second half (CPU half) is accessible from the microcontroller. Data is stored into the top half until the second half is empty. If all four bytes contain valid data or the final part of a frame is stored in the CPU half, a status bit is set. The RPF-status bit indicates that all four bytes contain valid data which do not contain the last part of a message. The RME-interrupt indicates that the final part of a message is available from the RFIFO. In this case, the value of the RBC-bits have to be evaluated to determine the number of valid bytes in the RFIFO. At the end of the RFlFO-data transfer, a RMC-command has to be issued via the CTRL2-register. This command acknowledges the previous RPF- or RME-status and empties the RFIFO so that the next part of the frame or the next frame may be transferred from the top half to the CPU half. The RMC-command may also be sent if none of the RFlFO-data has been read. The HDLC-receiver is controlled by two bits. Their combination indicates to reset the receiver, to acknowledge the RFlFO-contents, to ignore the remaining part of a frame. The later command can be used to suppress further reception of a frame after the address field has been received and it indicates a different destination. Appr. State Action RPF Receive Pool Full Four valid bytes are in the RFIFO. The RMC, RMD or RRES-command free's the RFIFO. RME Receive Message End Up to four bytes are in the RFIFO. RBC1, 0 determine the number of valid bytes. The RMC, RMD or RREScommand free's the RFIFO. Semiconductor Group 78 Operational Description HRC1 HRC0 Command 0 0 No command 0 1 RMC Acknowledges a previous RPF- or RME-status. The CPU RFIFO half can be used to store the next frame or the next part of a frame. 1 0 RMD The remaining part of a message is not forwarded and the receiver FIFO is cleared. The next RPF-or RME-interrupt is generated by the following HDLC-frame. 1 1 RRES HDLC-receiver is reset and the receive buffer is cleared. 3.1.4.3 Examples for the HDLC-Controller Operation Transmission of a Frame 3 Bytes and 13 Bytes A frame of three bytes may be entered during one serial access. The XTF x XME-command is set in the second control byte. The next XPR-status is generated after the closing flags has been transmitted successfully. A frame of more than 4 bytes is split into groups of four or less bytes. In case of 13 bytes, for the first and the following two blocks, the XTF-bit is set in the CTRL2-register and the XBC-value contains `11'. The XPR-status is generated if the CPU XFIFO is ready to buffer the next part of the message. The last block of a message is indicated by setting the XTF x XME-command and the generation of XPR is delayed until the closing flag has been transmitted. Semiconductor Group 79 Operational Description Dr Flag Data 1 Data 2 Data 3 CRC Dx CRC Flag CS MISO STA1 STA 2 STA1 MOSI CTRL1 CTRL 2 Data 1 Data 2 Data 3 CTRL1 INT CTRL1: WTC1, 2 = xx PW 5-0 = x CTRL 2: XHC1, 0 = 10 (XTF x XME) XBC 1, 0 = 10 RIE = 1 ISYNG = 0 HRC1, 0 = 00 CTRL1: WTC1, 2 = xx PW5-0 = x STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx Figure 46a Transmission of Frames Semiconductor Group 80 ITD06333 Semiconductor Group Figure 46b Transmission of Frames 81 INT MOSI MISO CS Dx Dr ST1 = STA1 CLn = CTRLn Dn = Data byte n CL1 CL2 STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx D4 STA 2: CI 1.x = xxx XFW =1 CI 0 = xxxx D3 STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx D2 ST 2 CTRL1: WTC1, 2 = xx PW 5-0 = x D1 ST1 CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 CL 2 ST2 CTRL1: WTC1, 2 = xx PW 5-0 = x CL1 ST1 Flag STA 2: CI 1.x = xxx XFW =1 CI 0 = xxxx CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 D5 Data 1 D6 D7 Data 2 D8 Data 3 ITD06334 Data 4 Operational Description Semiconductor Group Figure 46c Transmission of Frames 82 INT MOSI MISO CS Dx Dr Data 5 Data 6 Data 7 Data 8 Data 11 CTRL1: WTC1, 2 = xx PW 5-0 = x STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: XHC 1, 0 = 10 XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 00 CL1 CL2 D 13 ST1 ST 2 Data 10 CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 Data 9 CTRL1: WTC1, 2 = xx PW 5-0 = x CL1 CL 2 D9 D 10 D11 D12 ST1 ST2 ST1 = STA1 CLn = CTRLn Dn = Data byte n Data 12 Data 13 CRC CRC Flag ITD06345 STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx CTRL1: WTC1, 2 = xx PW5-0 = x CL1 ST1 Operational Description Operational Description Retransmission of a Frame In case the stop/go bit is evaluated for D-channel access control, the chances are that two terminals start transmitting at the same time and one has to abort its transmission and repeat the message. In this case, retransmission occurs automatically if the collision occurred within the first block of data. Otherwise, a XMR-status indicates that the message has to be retransmitted and therefore the data of the first block has to be written into the XFIFO. Semiconductor Group 83 Semiconductor Group Figure 47a Retransmission of a Frame 84 INT MOSI MISO CS Dx Dr STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx D6 D7 Data 2 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 CL1 CL2 D 5 STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx D4 CTRL1: WTC1, 2 = xx PW 5-0 = x D3 Data 1 CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 D2 ST1 ST 2 Flag CTRL1: WTC1, 2 = xx PW 5-0 = x CL1 CL 2 D1 ST1 ST2 STn = STAn CLn = CTRLn Dn = Data byte n D8 Flag Data 1 Data 2 ITD06335 Data 3 Operational Description Semiconductor Group Figure 47b Retransmission of a Frame 85 INT MOSI MISO CS Dx Dr Data 4 STn = STAn CLn = CTRLn Dn = Data byte n Data 5 Data 7 Flag CL1 ST1 ITD06346 STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx CRC STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CRC STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx Data 10 CTRL1: WTC1, 2 = xx PW5-0 = x Data 9 CTRL 2: XHC 1, 0 = 10 XBC1, 0 = 01 RIE = 1 ISYNC = 0 HRC1, 0 = 00 Data 8 CTRL1: WTC1, 2 = xx PW 5-0 = x CL1 CL 2 D9 D 10 ST1 ST2 Data 6 Operational Description Operational Description Transmit Data Underrun In case the XFIFO becomes empty without detecting a XME-bit, the transmitter aborts the current frame by an abort sequence and the XDU-status is indicated. STn = STAn CLn = CTRLn Dn = Data byte n Dr Flag Dx Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 7x1 CS MISO ST1 ST2 ST1 ST2 ST1 MOSI CL1 CL2 D1 D2 D3 D4 CL1 CL2 D5 D6 D7 D8 ST1 INT CTRL2: CTRL1: WTC1, 2 = xx RIE = 1 ISYNC = 0 PW5 - 0 = x HRC1, 0 = 00 XHC1, 0 = 01 XBC1, 0 = 11 STA1: RPF = 0 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = xx STA2: CI1.x = xxx XFW = 1 CI0 = xxxx CTRL1: CTRL2: WTC1, 2 = xx RIE = 1 PW5 - 0 = x ISYNC = 0 HRC1, 0 = 00 XHC1, 0 = 01 XBC1,, 0 = 11 STA1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx STA2: CI1.x = xxx XFW = 1 CI0 = xxxx CTRL1: WTC1, 2 = xx PW5 - 0 = x CTRL1: WTC1, 2 = xx PW5 - 0 = x STA1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx STA1: RPF = 0 RME = 0 XFS1, 0 = 11 CIC = x RBC1, 0 = xx ITD06336 Figure 48 Transmit Data Underrun Semiconductor Group 86 Operational Description Reception of a Frame with 3 Bytes and with 13 Bytes The RPF- or RME-bit indicate that valid data is in the RFIFO. Both RPF- and RME-status have to be served within 2 ms to prevent an underrun condition indicated by the RDO-bit in the RSTA-value. Dr Flag Data 1 Data 2 Data 3 CRC CRC Flag Dx CS MISO STA1 STA2 Data 1 Data 2 Data 3 RSTA MOSI CTRL1 CTRL2 INT CTRL2: CTRL1: WTC1, 2 = xx XHC1, 0 = 00 XBC1, 0 = 00 PW5 - 0 = x RIE = 1 ISYNG = 0 HRC1, 0 = 01 (RMC) STA1: RPF = 0 RME = 1 XFS1, 0 = 00 CIC = x RBC1, 0 = 00 Figure 49a Reception of Frames Semiconductor Group 87 STA2: CI1.x = xxx XFW = 1 CI0 = xxxx ITD06337 Semiconductor Group Figure 49b Reception of Frames 88 INT MOSI MISO CS Dx Dr Flag Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 CL2 D2 D3 Data 9 STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 PW 5-0 = x XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) CL1 D1 Data 8 ST1 ST2 Data 7 D4 ITD06338 Data 10 Operational Description Semiconductor Group INT D6 D7 Data 13 Figure 49c Reception of Frames 89 STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 PW 5-0 = x XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) CL2 CL1 MOSI D5 Data 12 ST1 ST2 Data 11 MISO CS Dx Dr D8 CRC CL2 D10 D11 D12 STA 1: RPF = 1 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = 00 STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: CTRL1: WTC1, 2 = xx XHC1, 0 = 00 PW5-0 = x XBC 1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) CL1 D9 Flag ST1 ST2 CRC CL2 RST STA1: RPF = 0 RME = 1 XFS 1, 0 = 00 CIC = x RBC1, 0 = 10 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx ITD06347 CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 PW 5-0 = x XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) CL1 ST1 ST2 D13 Operational Description Operational Description Full Duplex Operation In case of a full duplex operation where a frame is received at the same time one is transmitted, an optimization of the serial interface service is possible. The ISYNC-bit in the CTRL2-value selects whether receive and transmit interrupts occur at any time or if the interrupt is generated only if both status bits are active. To use the synchronization it is necessary that the third XPR-status has been indicated since this guarantees that the transmission of the frame has not been stopped within the first bytes. After the third XPR-status is detected, the ISYNC -bit may be set and the following interrupts are delayed until both a receive and transmit status is set. After the XTF x XME-command is set or a XMR-status has been indicated it is recommended to disable the synchronous interrupt generation again. Semiconductor Group 90 Semiconductor Group Figure 50a Full Duplex Operation 91 INT MOSI MISO CS Dx Dr D2 STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx D3 Data 2 CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 01 PW 5-0 = x XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 CL1 CL 2 D1 Data 1 ST1 ST2 Flag STn = STAn CLn = CTRLn Dn = Data byte n D4 CL1 CL2 ST1 ST 2 Flag Data 4 D5 Data 1 D6 Data 5 STA1: RPF = 0 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = xx STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: CTRL1: WTC1, 2 = xx XHC 1, 0 = 01 PW 5-0 = x XBC1, 0 = 11 RIE = 1 ISYNC = 0 HRC1, 0 = 00 Data 3 D7 Data 2 D8 Data 6 Data 3 Data 7 Data 5 Data 9 Data 6 Data 10 STA 1: RPF = 1 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = 00 STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: CTRL1: WTC1, 2 = xx XHC1, 0 = 00 PW5-0 = x XBC 1, 0 = 00 RIE= 1 ISYNC = 0 HRC1, 0 = 01 CL1 CL 2 ITD06339 ST1 ST2 D 1 D2 D3 D4 Data 4 Data 8 Operational Description Semiconductor Group Figure 50b Full Duplex Operation 92 INT MOSI MISO CS Dx Dr CRC Data 8 CRC Data 9 CTRL1: WTC1, 2 = xx PW 5-0 = x STA1: RPF = 1 RME = 1 XFS 1, 0 = 01 CIC = x RBC1, 0 = 00 CTRL 2: XHC 1, 0 = 01 XBC1, 0 = 11 RIE = 1 ISYNC = 1 HRC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx STA1: RPF = 0 RME = 0 XFS 1, 0 = 01 CIC = x RBC1, 0 = xx STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx D8 Data 12 D7 CTRL 2: XHC 1, 0 = 10 XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 01 CL1 CL 2 D13 D6 Data 11 ST1 ST2 D5 Data 10 Flag CTRL1: WTC1, 2 = xx PW 5-0 = x CL1 CL2 D 9 D10 D11 D12 ST1 ST 2 Data 7 Data 10 STn = STAn CLn = CTRLn Dn = Data byte n CRC CRC STA 1: RPF = 0 RME = 0 XFS1, 0 = 01 CIC = x RBC1, 0 = xx STA 2: CI1.x = xxx XFW = 1 CI 0 = xxxx STA 1: RPF = 0 RME = 0 XFS1, 0 = 00 CIC = x RBC1, 0 = 11 ITD06348 CTRL1: WTC1, 2 = xx PW5-0 = x CL1 ST1 CTRL 2: XHC1, 0 = 00 XBC 1, 0 = 00 RIE = 1 ISYNC= 0 HRC1, 0 = 01 Flag CTRL1: WTC1, 2 = xx PW5-0 = x CL1 CL2 ST1 ST 2 D 9 D10 RST Data 13 Operational Description Operational Description Ignoring the Rest of a Message The reception of a frame may be ignored after the first bytes have been read until the frame is completed. This feature is provided instead of an address recognition feature. In this case, a RPF-interrupt indicates the first block of data and the corresponding FlFO-data is read. At the event of the next RPF-interrupt, the RMD-bit may be set in the CTRL2-value to set the corresponding command. Afterward, the next RPF- or RME-status is generated for the next frame. Semiconductor Group 93 Semiconductor Group Figure 51 Ignoring the Rest of a Message 94 STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00 STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx STA1: RPF = 1 RME = 0 XFS 1, 0 = 00 CIC = x RBC1, 0 = 00 CTRL 2: CTRL1: CTRL1: WTC1, 2 = xx XHC 1, 0 = 00 WTC1, 2 = xx PW 5-0 = x XBC1, 0 = 00 PW 5-0 = x RIE = 1 ISYNC = 0 HRC1, 0 = 01 (RMC) CL1 CL2 CL1 CL2 MOSI INT ST1 ST2 CRC STA 2: CI 1.x = xxx XFW = 1 CI 0 = xxxx CTRL 2: XHC 1, 0 = 00 XBC1, 0 = 00 RIE = 1 ISYNC = 0 HRC1, 0 = 10 (RMC) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 CRC ST1 ST2 D1 D2 D3 D4 Flag MISO CS Dx Dr ITD06340 Flag Operational Description Operational Description 3.1.5 Reset Reset Logic While the power-on reset pulse is generated or an external reset is applied, pins which operate as l/O-pins are configured as inputs. The Upn-awake detector becomes active after reset. IOM-clocks signals are active in TE-mode. BCL, SDS remain `0' because of the CTRL4-reset value. PWO/Ring/Mode is `0' because of the CTRL1- and CTRL3-reset values. The registers of the SmartLink-P are reset to the default values. Table 3 Reset State of the SmartLink-P Registers Register Value after Reset Meaning STA1 00H No C/I-change, no status change, no data in RFIFO. STA2 00H C/I is `1111'. CTRL1 00H MCLK = 3.84 MHz, Watchdog disabled, PW = `000000'. CTRL2 00H No HDLC-controller operation, no XFIFO-data. CTRL3 00H Permanent D-channel access, permanent access to C/I-channel 0 and D-channel. T-channel mapped on S/G, PW-output operates as LCD-contrast, TlC-bus access during D-channel transmission only, TAD = `000'. CTRL4 00H Normal operation of DU-line, Serial Strobe = `000' (OFF), Cl0 = `0000'. When using the undervoltage detection for reset generation, a short internal reset is generated which resets the internal functions and starts the 56 ms counter. The lOM-clocks will be stopped after the Upn-transceiver enters its deactivated state. As a result, external transceiver devices (SBCX, PSB 21810 or SmartLink in TR-mode) can not leave their reset state and they can not start activation of the IOM-2 interface. The terminal software has to enable the IOM-clocks by the SPU-bit and output the C/I-command `RES' to guarantee a correct reset of all other transceiver devices. Semiconductor Group 95 Operational Description 3.1.6 Initialization During initialization the control registers have to be setup. The necessary setup is listed in table 4. Table 4 Initialization of the SmartLink-P Registers Register Bit Effect CTRL1 PRE WTC PW MCLK-clock rate Watchdog enable if required LCD-contrast value/Ringing frequency CTRL2 XRES RRES Reset the HDLC-receiver and transmitter CTRL3 SGE, TBU SGM, BAC, TAD LCRI Select TlC-bus, S/G-operation,T-channel mapping, TlC-bus address. LCD-contrast or ringer operation of PWM CTRL4 SPU CI0 Awake the lOM-interface until the received C/l-code indicates PU. Afterwards reset SPU to `0' and enter TIM or ARx in the CI0 bits. Program strobe signal SDS 3.2 TR-Mode 3.2.1 Control of the Upn-Transceiver Application Restricted to 3.2.1.1 Activation/Deactivation of the IOM-2 Interface The Upn-transceiver functions are controlled by commands issued by the SmartLink-P depending on the current state. In downstream direction, only the commands `DR', `AR' and `DI' trigger the state machine. In upstream direction, the four indications `TIM', `AR', `AI' or `DC' are generated. If the IOM-2 interface is turned off, an asynchronous awake procedure is initiated if the SmartLink-P in TR-mode request an activation procedure. Semiconductor Group 96 Operational Description In TR-mode, the length of the FSC-signal is monitored to avoid misalignment of internal buffers in case incorrect pulses on FSC have been detected. The state-machine of the Upn-transceiver is reset every time, a FSC-period of less than 96 bits is detected. The SmartLink generates a reset signal for the state machine which is active for 6 lOM-frames. As a result, 4 or 5 info 0 frame will be transmitted on Upn to force the TE-device in the level detect (Resynchronization) state. This number of info 0 frames is still less than is required to detect info 0 by the TE-device (2 ms, 8 info 0 frames). 3.2.1.2 Layer-1 Command/Indication Codes in TR-Mode Command (downstream) Abbr. Code Remarks Deactivate request DR 0000 Activate request AR, AI, ARL2, AIL2 1xx0 Transmission of info 2 and info 4 according to the Upn-procedure Deactivation confirmation DC 1111 Info 0 or Dl received after deactivation request or no TlC-bus request Indication (upstream) Abbr. Code Remarks Timing TIM 0000 Deactivation state, activation from the line not possible Activate request AR 1000 Info 1 received Activate indication AI 1100 Deactivation indication DI 1111 Deactivation acknowledgment, quiescent state In TR-mode, the Upn-interface is activated if the C/l-code Activate Request (AR, ARL2) or Activate Indication (Al, AIL2) has been detected in downstream direction. It stays activated until the C/l-code Deactivate Indication (Dl) is received in downstream direction. Semiconductor Group 97 Operational Description 3.2.1.3 State Diagrams In TR-mode the layer-1 (Upn) part of the PSB 2197 SmartLink-P is a IOM-2 interface slave in any aspect. Therefore it is also able to activate the IOM-2 interface by pulling the data upstream line to zero asynchronously. Since the PSB 2197 SmartLink-P in TR-mode is a stand alone function without microprocessor aid, the PSB 2197 SmartLink-P in TR-mode will indicate the activated state of the slave Upn-interface by pulling bit 6 of the C/I-channel 1 on the data upstream line to `0'. The presence of a SmartLink-P in TR-mode is indicated by pulling bit 5 of the C/I-channel 1 on the data upstream line to `0'. 7 0 CI1 MR 1/0 0 (activated) Semiconductor Group 98 MX Operational Description 3.2.1.4 TR-Mode State Description Pending Deactivation State after reset or deactivation from the IOM-2 interface by command `Dl'. Note that no activation from the network side is possible starting from this state. Wait for DR This state is entered from the pending deactivation state once info 0 has been identified or after the command `Dl'. Deactivated The Upn-interface is deactivated and the IOM-2 interface is or will be deactivated. Activation is possible from the Upn-interface and from the IOM-2 interface. If activation is initiated by the terminal side it first leads to the activation of the IOM-2 interface by the indication `TIM' (Awake: DU pulled to VSS asynchronously, later on synchronously). Pending Activation 1 After activation from the line has been started the indication Activation Request (AR) is issued to get synchronization from the upstream network side. Pending Activation 2 Upon the command Activation Request (AR) the PSB 2197 SmartLink-P transmits the 4-kHz info 2 towards the network, waiting for info 1. Synchronized The Upn-receiver is synchronized and detects info 1. It continues the activation procedure by transmission of info 4. Activated The (Upn)-receiver is synchronized and detects info 3. The activation procedure is now completed and B1-, B2-, and downstream D-channels are conveyed transparently. For transmission of the upstream D-channel the TlC-bus function applies. Resynchronization Under severe disturbances on the line the Upn-receiver still recognizes the receipt of a signal but is no more synchronized. Semiconductor Group 99 Operational Description RES AR, ARL 2 AI, AIL 2 TIM 2) X Pend. Deactivation i0 i0 i0 + DC AR, ARL 2 AI, AIL 2 DI X Wait for DR i0 i0 DC DI Awake i1w DC Deactivated DR i0 i0 AR 2) AR, ARL 2 AI, AIL 2 DI DR Pend. Activation 1 i0 DR DR i1w AR, ARL 2 AI, AIL 2 Pend. Activation 2 i2 DR i1 i1 DI i1 DI DR Synchronized DR i1 x i3 Resynchronization i2 i4 DR i1 DR IN Ind. Cmd. i1 AI 1) i3 DR Activated i4 IOM R DR State U pn i3 1) : Transmitted after TIC bus access only if upstream T-channel is '1' otherwise DI is transmitted 2) : Transmitted after TIC bus access otherwise DI is transmitted R Awake : DU- line pulled to VSS for T4 if i1w is detected and IOM is deactivated Figure 52 State Diagram TR-Mode Semiconductor Group OUT i3 100 ix ir ITD05372 Operational Description 3.2.1.5 Example of the Activation/Deactivation Figure 53 shows the activation/deactivation procedure between the SmartLink-P operating in TR-mode and a SmartLink-P on the slave terminal. TE2 TR DC TE 1 LC DC INFO 0 DC Deactivated DI State INFO 0 DI DI ~~ ~~ ~~ ~~ ~~ ~~ ~~ ~~ SPU = 1 PU AR, SPU = 0 INFO 1w Awake T4 PU AR INFO 1w T1 INFO 2 T1 T1 RSY T2 INFO 2 RSY INFO 0 AR T3 T2 INFO 4 T3 AR INFO 1 T2 INFO 4 INFO 1 AR INFO 0 T2 RDS INFO 3 AI T3 INFO 3 AI AI T3 ~~ ~~ ~~ ~~ ~~ DR INFO 0 T4 INFO 0 INFO 0 R IOM -2 U pn Interface DR INFO 0 PU DC DI ~~ T4 T4 DC ~~ INFO 0 T4 TIM INFO 0 DR ~~ Activated State DI R IOM -2 U pn Interface DC Deactivated DI State R IOM -2 ITD05373 Figure 53 Activation/Deactivation (TR, TE) Semiconductor Group 101 Operational Description 3.2.2 D-Channel Access Procedure The TR-mode uses the TlC-bus access procedure to access the upstream D-channel if requested by the terminal connected to the Upn-interface. TCM (T-Channel Mode) selects the control of the downstream T-channel source. If TCM is `0', the downstream T-channel transmits the inverse value of the received stop/go bit. This is the regular operation for terminal repeater applications. If TCM is `1', the downstream T-channel is controlled by the received CI0-indication. If CI0 is different from `AI' (`1100'), the T-channel is set to `0'. While C/l indicates `AI', the T-channel is set to permanent `1'. Double last look is active so that the CI0-lndications must be received twice before the T-channel changes. This mode is necessary to operate together with the IEC-Q since the IEC-Q doesn't generate a stop/go bit so it remains `1' which would indicate stop. The terminal repeater enables the T-channel after activation is completed as long as the primary link (2B1Q) is in the activated state. TCM = `1' also disables the TIC-bus access and the output of CI1 bits. The SmartLink outputs the CI0-bits and the D-bits on the DU-line permanently. If TCM changes from `0' to `1' during operation, the change becomes effective immediately and a TIC-bus access is aborted. From that moment on, no further TIC-bus accesses are performed. TlC-Bus Access (TCM = `0' only) Idle The idle state is specified by the TlC-bus address as `111' and the BAC-bit set to `1'. During this state, the upstream D-channel is transparent and the downstream T-bit transmits the inverse of the stop/go bit. TlC-Bus Access by other D-Channel Sources If the TlC-bus is occupied by another source which is indicated by the TlC-bus address different from `111' or the BAC-bit set to `0', the downstream T-bit changes to the block value (T = `0'). TlC-Bus Request by Upn-Receiver Upon a T = `1' bit received from the slave terminal which is interpreted as a D-channel access request the PSB 2197 SmartLink-P tries to access the TlC-bus according to the specified procedure using TlC-bus address `011'. After the TlC-bus has been occupied the inverse of the S/G-bit position is transmitted via the Upn T-bit. Semiconductor Group 102 Operational Description If the T-channel becomes `0' again, the TlC-bus is released after a delay of two IOM-2 frames. The SmartLink in TE-mode guarantees that at least one T-bit set to `0' is transferred between two HDLC-frames, thus a HDLC-frame of the master can be inserted. Blocked Condition during a Frame Transmission If a blocked condition occurs during the transmission of a frame, the S/G-bit changes to stop and no further D-bits are output to the IOM-2 interface. The stop condition changes the downstream T-bit to a blocked state and the HDLC-transmitter in the slave terminal aborts the frame. If the upstream T-bit remains `0' (BAC-bit of the terminal), the TR SmartLink-P retains its TlC-bus access to make sure that the slave terminal can transmit a frame if the stop/go bit becomes `Go' again. 3.2.3 Reset State The reset state is entered after applying an active signal to the reset input. In reset state, the transceiver state machine is reset and info 0 is output on the Upn-interface. The TlC-bus access state machine is also reset so that the TlC-bus becomes idle. Semiconductor Group 103 Operational Description 3.3 HDLC-Controller Mode 3.3.1 Interrupt Structure and Logic The interrupt structure in HDLC-controller mode is identical to the TE-mode. 3.3.2 Control of the Serial Control Interface The control of the serial control interface is identical to the TE-mode. 3.3.3 Control of the HDLC-Data Transfer The control of the HDLC-data transfer is identical to the TE-mode. 3.3.4 Control of Terminal Specific Functions Control of Upstream C/l 7 to 5 In HDLC-controller mode the control of Cl1 bit 7 to 5 in upstream direction (DU) is done by the least significant three bits of CTRL1. Generation of Bit Clock and Strobe Signals The SDS-bits in CTRL4 control the generation of BCL-clocks and the output of the SDS-pin. 3.3.5 Reset The reset state is identical to the TE-mode. Semiconductor Group 104 Register Description 4 Register Description The parameterization of the SmartLink-P and the transfer of data and control information between the microprocessor and the SmartLink-P is performed through a set of registers. Table 5 SmartLink-P Register Map (TE) Bit 7 Bit 0 Reg. R/W PRE1/ WTC1 PRE0/ WTC2 PW5 PW4 PW3 PW2 PW1 PW0 CTRL1 W HXC1 HXC0 XBC1 XBC0 RIE ISYNC HRC1 HRC0 CTRL2 W SGE TBU TCM LCRI BAC TAD2 TAD1 TAD0 CTRL3 W SPU SDS2 SDS1 SDS0 CI0 CI0 CI0 CI0 CTRL4 W XFIFO W RPF RME XFS1 CI1Bit7 CI1Bit6 CI1Bit5 XFS0 RFO CIC RBC1 XFW CI0 CI0 CI0 RBC0 STA1 CI0 STA2 R R RFIFO R VFR RDO CRC RAB 0 0 0 0 RSTA R SmartLink-P Register Map (HDLC-Controller Mode) Bit 7 Bit 0 Reg. R/W 0 0 0 0 0 CI1Bit7 CI1Bit6 CI1Bit5 CTRL1 W HXC1 HXC0 XBC1 XBC0 RIE ISYNC HRC1 HRC0 CTRL2 W SGE TBU TCM 0 BAC TAD2 TAD1 TAD0 CTRL3 W SPU SDS2 SDS1 SDS0 CI0 CI0 CI0 CI0 CTRL4 W XFIFO RPF RME XFS1 CI1Bit7 CI1Bit6 CI1Bit5 VFR RDO Semiconductor Group CRC XFS0 RFO CIC RBC1 XFW CI0 CI0 CI0 RAB 0 0 105 0 RBC0 STA1 CI0 0 W R STA2 R RFIFO R RSTA R Register Description 4.1 SmartLink-P Register Summary CTRL1 Control Byte 1 (TE-Mode) Value after reset: 00H Bit 7 0H Bit 0 PRE1/ PRE0/ WTC1 WTC2 PRE1, 0 PW5 PW4 PW3 PW2 PW1 PW0 Reg. R/W CTRL1 W Prescaler Value The PRE1, 0 bits control the microcontroller clock output. If both bits are `11', the contents of PW1 and PW0 is latched and specifies the frequency. WTC1, WTC2 PRE1 PRE0 PW1 PW0 MCLK-clock frequency 1 1 0 0 3.84 MHz 1 1 0 1 7.68 MHz 1 1 1 0 1.92 MHz 1 1 1 1 0.96 MHz Watchdog Timer Control During every time period of 56 ms the processor has to program the WTC1- and WTC2 bit in the following sequence to reset and restart the watchdog timer: WTC1 WTC2 1 0 0 1 The watchdog timer is enabled by the first `10' sequence. As long as both bits are `00', the watchdog is not active. `11' has no impact on the watchdog but controls the microcontroller clock output frequency. Semiconductor Group 106 Register Description PW5-0 Pulse Width 5-0 Specifies the output of the pulse width generator dependend on the setting of LCRI-control bit (CTRL3). CTRL3: LCRI = 0 (LCD-contrast output) PW5-4 PW3-0 PW output 00 0000 Off (low) 00 0001 On period: 1/15 00 1110 On period: 14/15 00 1111 On (high) ... PW5-4 have to be `00'. CTRL3: LCRI = 1 (Ringing output) PW5-0 Frequency 000000 PWO/Ring output is tristate 000001 8000 Hz 000010 5333 Hz 000011 4000 Hz 111110 253.96 Hz 111111 250 Hz The value n (PW5-0) specifies a divider. The output frequency is calculated based on the following formula: f = 16 kHz / (n + 1) Semiconductor Group 107 Register Description CTRL1 Control Byte 1 (HDLC-Controller Mode) Value after reset: 00H Bit 7 0H 0 Bit 0 0 0 0 0 Reg. CI1Bit7 CI1Bit6 CI1Bit5 CTRL1 W Controls the bit 7 to 5 of the command/indicate channel 1 on data upstream. Cl1Bit7 0: Cl1Bit7 = 1 1: Cl1Bit7 = 0 0: Cl1Bit6 = 1 1: Cl1Bit6 = 0 0: Cl1Bit5 = 1 1: Cl1Bit5 = 0 Cl1Bit6 Cl1Bit5 Semiconductor Group R/W 108 Register Description CTRL2 Control Byte 2 Value after reset: 00H Bit 7 1H Bit 0 HXC1 HXC0 XBC1 XBC0 RIE ISYNC HRC1 Reg. R/W HRC0 CTRL2 W Note: The HDLC-controller operates on DCL/2 clock rate. lt requires 4 clock cycles to execute a command entered in the CTRL2-register. After a FlFO-part has been transferred, the corresponding interrupt is generated immediately. HXC1, 0 HDLC-Transmitter Control 1, 0 HXC provides the commands for the HDLC-transmitter: XBC1, 0 HXC1 HXC0 Command 0 0 No command, XBC selects whether CTRL3 and 4 is transmitted 0 1 XTF, Transmit Transparent Frame. XBC determines the number of valid, XFlFO-bytes to follow. 1 0 XTF x XME, Transmit Transparent Frame and Transmit Message End. XBC determines the number of valid XFlFO-bytes to follow. 1 1 XRES, Transmitter Reset Transmit Byte Count 1, 0 Indicates the number of valid bytes for the XFIFO which follow after the control bytes if HXC1, 0 is not `00'. XBC1 XBC0 Transmit Byte Count 0 0 1 Byte 0 1 2 Bytes 1 0 3 Bytes 1 1 4 Bytes If HXC1, 0 = `00', XBC1, 0 selects whether CTRL3 and CTRL4 are transmitted after CTRL2. XBC1 XBC0 0 0 No valid data follows after CTRL2. 0 1 CTRL3 and CTRL4 follow after CTRL2. Semiconductor Group 109 Register Description RIE Receiver Interrupt Enable RIE controls the generation of receive interrupts. ISYNC 0: Receiver interrupts are masked. 1: Receiver interrupts are enabled. An interrupt is generated if four bytes are valid in the RFIFO (RPF) or if the RME-bit is set. Interrupt Synchronization Used to synchronize transmit and receive interrupts to allow simultaneous access to the XFIFO and RFIFO. HRC1, 0 0: RPF-, RMEsynchronized. and XFS-interrupt generation 1: An interrupt is generated only if both a receive interrupt (RPF, RME) and a transmit interrupt (XFS1, XFS0) is active. HDLC Receiver Control 1, 0 HRC provides the commands for the HDLC-receiver: HRC1 HRC0 Command 0 0 No command 0 1 RMC, Receive Message Complete 1 0 RMD, Receive Message Delete 1 1 RRES, Receiver Reset Semiconductor Group 110 is not Register Description CTRL3 Control Byte 3 Value after reset: 00H Bit 7 2H SGE SGE Bit 0 TBU TCM LCRI BAC TAD2 TAD1 Reg. R/W TAD0 CTRL3 W Stop/Go Bit Evaluation Specifies whether the S/G-bit is evaluated for D-channel transmission. TBU 0: Permanent D-channel transmission. 1: D-channel transmission only during S/G = `go'. TIC-Bus Used Specifies whether the TlC-bus procedure is used to gain access to the C/l-channel 0 and D-channel. TCM LCRI BAC 0: Permanent access to the C/l-channel 0 and D-channel. 1: TlC-bus procedure is used to access the upstream C/I-channel 0 and D-channel. The TIC-bus address is specified in bit 0 to 2. T-Channel Mapping 0: T-channel data is mapped onto the S/G-bit (S/G = inverse T-channel). 1: T-channel data is mapped onto the AB-bit (AB = T-channel). LCD-Contrast/Ringing Output (used in TE-Mode only) 0: Pulse width output operates as LCD-contrast output. PW-0 specifies the on-to-off ratio of a fixed frequency signal. PW5-4 have to be `00'. 1: Pulse width output operates as ringing output. PW5-0 specifies the ringing frequency. TIC-Bus Access Forces the SmartLink-P to occupy the TIC-bus without transmission of D-channel data. Valid only if TBU is `1'. 0: TIC-bus used for D-channel data transmission only. 1: TIC-bus accessed permanently. Semiconductor Group 111 Register Description TAD2-0 TIC-Bus Address Specifies the TIC-bus address used by the SmartLink-P. TAD2 TAD1 TAD0 TIC-bus address 0 0 0 0 (highest priority) 0 0 1 1 0 1 0 2 1 1 0 6 1 1 1 7 (lowest priority) ... Semiconductor Group 112 Register Description CTRL4 Control Byte 4 Value after reset: 0FH Bit 7 3H SPU SDS2-0 SPU Bit 0 SDS2 SDS1 SDS0 CI0 CI0 CI0 CI0 Reg. R/W CTRL4 W Software Power-Up 0: Normal operation of DU. 1: DU is pulled low while SPU = `1'. Used to awake the IOM-interface. Serial Data Strobe Controls the generation of the serial data strobe signal and the BCL-signal. SDS2-0 also specify whether B-channel information is looped or the upstream B-channel information is muted. SDS2 SDS1 SDS0 Function of SDS Upstream Time-Slot Data 0 0 0 SDS low, BCL low Transparent 0 0 1 SDS high during IC1, BCL active Transparent 0 1 0 SDS high during B1, Transparent BCL active 0 1 1 SDS high during B2, Transparent BCL active 1 0 0 SDS low, BCL low Downstream B1 looped to upstream B1 1 0 1 SDS low, BCL low Downstream B2 looped to upstream B2 1 1 0 SDS high during B1, Upstream B1 muted BCL active 1 1 1 SDS high during B2, Upstream B2 muted BCL active Semiconductor Group 113 Register Description B-Channel Looping During the B-channel loop selected by the SDS-bits, the received B-channel data from the Upn-interface is output on the DD-line and looped back to the DU-line. The DU-line is not disconnected which means that the external components on the DU-line must output `FF' during the B-channel time-slot which is looped back. Otherwise the information is `ored' in terms of a `0' bit overwriting a `1' bit. The advantage of this method is that monitoring is possible on the lOM-interface pins. B-Channel MUTE While the B-channel MUTE function is active, the connection between the external DU-line and the internal B-channel input line is disconnected and the B-channel input sees only `1's. The DU-line will still show the output of the codec but the Upn-B-channel information is `FF'. This implementation provides no easy method to check the MUTE function since the B-channel information is scrambled before it is transmitted on the Upn-interface. CI0 Command/Indicate Channel 0 Value which is transmitted on the upstream C/l-channel 0 depending on the BAC and TBU bit. Semiconductor Group 114 Register Description STA1 Status Byte 1 Value after reset: 00H Bit 7 0H RPF RPF Bit 0 RME XFS1 XFS0 RFO CIC Reg. RBC1 RBC0 STA1 R/W R Receive Pool Full Indicates that a part of a message is stored in the RFIFO. All four bytes contain valid data. RME Receive Message End Indicates that the last part of a message is stored in the RFIFO. The RBC1, 0-value indicates the number of valid bytes in the RFIFO. This number includes the RSTA-value. XFS1, XFS0 Transmit FIFO-Status Indicates the status of the transmit FIFO. XFS1 XFS0 Appr. Transmit FlFO-Status 0 0 0 1 XPR 1 0 XMR Transmit message repeat. The S/G-bit became stop and the frame has to be reentered. Up to four bytes may be entered. 1 1 XDU No change in the transmit FlFO-status. Transmit Pool ready. Up to four bytes may be entered. Transmit Data Underrun. The transmitter became empty without XME-marking. The frame is aborted (7 `1'). The XFIFO is cleared and new data may be entered. The generation of the XPR-status is delayed until the closing flag has been transmitted completely if the previous transmitter command was XME. RFO Receive Frame Overflow The begin of an HDLC-frame (1st byte) could not be stored since the RFIFO is full. Semiconductor Group 115 Register Description CIC C/I-Code Change Indicates that a new C/l-code is available in STA2. RBC1, 0 0: No C/l-code change 1: C/l-code change occurred. The new value is stored in the STA2-register. Receive Byte Count Indicates the number of valid bytes in the RFIFO if a RME-status bit is set to `1'. This value is repeated while STA1 is read until the RMC, RMD or RRES is issued. It is not changed by reading the RFIFO. RBC1 RBC0 Number of valid bytes in the RFIFO 0 1 1 Byte 1 0 2 Byte 1 1 3 Byte 0 0 4 Byte If RME or RPF is `0', the RBC1, 0-values may have any value and should be ignored by the software. Semiconductor Group 116 Register Description STA2 Status Byte 2 Value after reset: 0FH Bit 7 1H Bit 0 CI1Bit7 CI1Bit6 CI1Bit5 XFW CI1Bit7 CI0 CI0 CI0 CI0 Reg. R/W STA2 R C/I-Channel 1 Bit 7 Indicates the state of bit 7 on the upstream C/I-channel 1. This bit is reserved to indicate the presence of a SmartLink-S in LT-S mode. CI1Bit6 0: C/I-channel 1 bit 7 is `0' (SmartLink-S present) 1: C/I-channel 1 bit 7 is `1' (SmartLink-S not present) C/I-Channel 1 Bit 6 Indicates the state of bit 6 on the upstream C/l-channel 1 to indicate the active state of the slave Upn-interface. CI1Bit5 0: C/I-channel 1 bit 6 is `0' (Slave Upn activated) 1: C/I-channel 1 bit 6 is `1' (Slave Upn not activated) C/I-Channel 1 Bit 5 Indicates the state of bit 5 on the upstream C/l-channel 1 to detect the presence of the slave Upn-interface. XFW 0: C/I-channel 1 bit 5 is `0' (TR SmartLink-P present) 1: C/I-channel 1 bit 5 is `1' (TR SmartLink-P not present) Transmit FIFO Write Enable Indicates that the XFIFO is able to receive new data. XFW is a static indication. It changes its state after a transmit command has been executed internally or if the XFIFO becomes empty. 0: XFIFO is not empty 1: XFIFO is empty. The next part of the frame or a new frame may be entered. The generation of the XFW-status bit is delayed until the closing flag has been transmitted completely if the previous transmitter command was XME. CI0 C/I-Code 0 Indicates the received (downstream) C/I-code of channel 0. Semiconductor Group 117 Register Description RSTA Receiver Status Byte Bit 7 VFR VFR Bit 0 RDO CRC RAB 0 0 0 Reg. R/W 0 Valid Frame Indicates that the frame consists of multiples of 8 bits and the minimum number of bytes between two flags was 3. RDO Receive Data Overflow Indicates that the RFIFO was not serviced in time and that at least one byte of the message could not be stored. CRC 0: No data lost 1: At least one byte lost CRC-Check Correct Indicates whether a CRC-check was okay or not. RAB 0: CRC error 1: CRC okay Receiver Abort Indicates that the frame was not closed by a flag but by an abort sequence (7 `1'). 0: Frame closed with flag 1: Frame closed with abort sequence Semiconductor Group 118 Electrical Characteristics 5 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Limit Values Unit Voltage on any pin with respect to ground VS - 0.4 to VDD + 0.4 V Ambient temperature under bias TA 0 to 70 C Storage temperature Tstg - 65 to 125 C DC-Characteristics TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V Parameter Symbol Limit Values min. Unit Test Condition Remarks typ. max. L-input voltage VIL - 0.4 0.8 V All pins except Lla, Llb H-input voltage VIH 2.0 VDD + 0.4 V All pins except Lla, Llb L-output voltage VOL L-output voltage 1 VOL1 0.45 0.45 V V IOL = 2 mA IOL = 7 mA (DD, DU only) H-output voltage H-output voltage All pins except Lla, Llb VOH VOH1 2.4 VDD - 0.5 V V IOH = - 400 A IOH = - 100 A All pins except Lla, Llb, MISO VOH VDD - 0.5 V IOH = - 1 mA MISO Semiconductor Group 119 Electrical Characteristics DC-Characteristics (cont'd) TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V Parameter Symbol Limit Values min. Power supply current TE-mode operating ICC Remarks mA DCL = 1.536 MHz VDD = 5 V inputs at VSS/VDD, no output loads except Lla, Llb; Lla, Llb load 15 mA mA DCL = 0 MHz VDD = 5 V typ. max. 10 TE-mode ICC deactivated, IOMclocks stopped Unit Test Condition 15 9 inputs at VSS/VDD, no output loads. TR-mode operating ICC TR-mode deactivated, IOM stopped ICC HDLC controller mode ICC Input leakage current Output leakage current ILI 10 A 0 V < VIN < VDD ILO 10 A 0 V VOUT VDD All pins except Lla, Llb 30 IOUT = 20 mA Lla, Llb k VDD = 5 V Lla, Llb 8.5 mA DCL = 1.536 MHz VDD = 5 V inputs at VSS/VDD, no output loads except Lla, Llb; Lla, Llb load 15 mA 7.5 mA DCL = 0 MHz VDD = 5 V inputs at VSS/VDD, no output loads. 4.5 mA DCL = 1.536 MHz VDD = 5 V inputs at VSS/VDD, no output loads. Transmitter output impedance 10 Receiver input impedance 10 Semiconductor Group transmitter inactive 120 Electrical Characteristics DC-Characteristics (cont'd) TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V Parameter Symbol Limit Values min. H-input voltage L-input voltage VIH VIL 3.5 - 0.4 H-output voltage L-output voltage VOH VOL 4.5 Unit Test Condition Remarks typ. max. VDD + 0.4 V 1.5 V 0.4 V V XTAL1 XTAL1 IOH = 100 A CI 60 pF IOL = 100 A CI 60 pF XTAL2 XTAL2 Capacitances TA = 0 to 70 C; VDD = 5 V 5 %, VSS = 0 V Parameter Symbol Limit Values min. Unit Remarks pF pF All pins except Lla, Llb max. Input capacitance I/O-capacitance CIN CI/O 7 7 Output capacitance COUT 25 pF Lla, Llb Load capacitance CI 60 pF XTAL1, XTAL2 Semiconductor Group 121 Electrical Characteristics Oscillator Circuits C LD XTAL1 External Oscillator Signal XTAL 1 XTAL 2 N.C. XTAL 2 15.36 MHz 100 ppm C LD Crystal Oscillator Mode C LD = 2 x C L - C I/O Driving from External Source Minimum High Time : 30 ns Minimum Low Time : 28 ns ITS05374 Figure 54 Oscillator Circuits XTAL1, 2 Recommended typical crystal parameters. Parameter Symbol Motional capacitance C1 20 fF Shunt C0 7 pF Load CL 30 pF Resonance resistor Rr 65 Semiconductor Group Limit Values 122 Unit Electrical Characteristics AC-Characteristics Inputs are driven to 2.4 V for a logical `1' and to 0.45 V for a logical `0'. Timing measurements are made at 2.0 V for a logical `1' and 0.8 V for a logical `0'. The AC testing input/output waveforms are shown below. 2.4 V 2.0 V 2.0 V Output 0.8 V 0.8 V C Load = 100 pF 0.45 V ITS05375 Figure 55 Input/Output Waveforms for AC-Tests Serial Control Interface Timing t CSs t CSh ~ ~ CS t CSSDX t CHCH ~ ~ ~ ~ SCLK ~ ~ MOSI t SDRh ~ ~ t SDRs MSB ~ ~ MISO t SDXd t SDXd t SDXt ~ ~ t SCIl INT ITD06341 Figure 56 SCI-Switching Characteristics Semiconductor Group 123 Electrical Characteristics Parameter Symbol Limit Values min. Unit max. SCLK-frequency tCHCH 250 ns Chip select setup time tCSs 10 ns Chip select hold time tCSh 0 ns MOSI-setup time tSDRs 50 ns MOSI-hold time tSDRh 50 ns MISO-data-out delay from CS tCSSDX 150 ns MISO-data-out delay tSDXd 150 ns CS high to INT low tCSIl 150 ns CS high to MISO-tristate tSDXt 30 ns Note: The rise time on INT after CS becomes low depends on the external pull-up resistor. Semiconductor Group 124 Electrical Characteristics IOM-2 Bus Switching Characteristics t FSW t FSD t FSD FSC t DCL t DCLH t DCLL DCL t ODD DD / DU t IIH t IIS DU / DD t BCD t BCD BCL SDSx t SDD ~ ~ t SDD ITD05382 Figure 57 IOM-2 TE-Mode (DCL, FSC output) Semiconductor Group 125 Electrical Characteristics Parameter DCL-clock period (1.536 MHz) Symbol DCL-width low FSC-period FSC-setup delay FSC-width reduced FSC-length (1 DCL) nominal FSC-length (64 DCL) DU/DD-data-in setup time DU/DD-data-in hold time DU/DD-data-out delay Bit clock delay Strobe delay from DCL Unit min. typ. max. 585 651 717 ns 40 50 60 % tDCLH tDCLL tFSC tFSD tFSW 260 326 391 ns 260 326 391 ns tIIS tIIH tODD tBCD tSDD 50 ns 50 ns tDCL DCL-duty cycle DCL-width high Limit Values s 125 - 20 585 - 20 651 41.6 20 ns 717 ns s 150 ns 20 ns 120 ns Note: Reduced FSC-length is output every eighth frame triggered by a CV in the received M-bit. Semiconductor Group 126 Electrical Characteristics t DCL t DCLH DCL t DCLL t FS t FSS t FLH t FH FSC t ODD DU Bit 1 t H t S Bit 1 DU/DD ITD05383 Figure 58 TR-, HDLC- Mode (DCL, FSC input) Semiconductor Group 127 Electrical Characteristics Parameter DCL-clock period (1.536 MHz) Symbol tDCL DCL-duty cycle DCL-width high DCL-width low FSC-period FSC-setup time FSC-hold time FSC-setup short1) FSC-hold long2) DU/DD-data-in setup time DU/DD-data-in hold time DU-data-out delay from DCL tDCLH tDCLL tFSC tFs tFh tFSS tFLH tIIs tIIh tODD Limit Values Unit min. typ. max. 488 651 814 ns 30 50 70 % 163 326 489 ns 163 326 489 ns s 125 70 ns 40 ns 70 ns 40 ns 50 ns 50 ns 150 ns Notes: 1) Nominal FSC-length = 1 DCL-period (Trigger for M = CV-generation) 2) No trigger for M = CV-generation MCLK-Timing TP ITT05653 Figure 60 MCLK-Timing Parameter Symbol Limit Values min. Clock period 0.96 MHz 1.92 MHz 3.84 MHz 7.68 MHz Tp Tp Tp Tp Duty cycle Semiconductor Group 128 typ. Unit max. 1042 521 260 130 ns ns ns ns 50 % Electrical Characteristics Reset Timings ~ ~ VHH VHL VDD t min RST ~ ~ ~ ~ RST td td tr tr MCLK ITD06314 Figure 59 Undervoltage Detection Parameter Symbol Limit Values min. max. Unit Threshold value VHL 4.2 4.4 V Hysteresis VHH - VHL 50 230 ms Minimum voltage drop Tmin 11 s Delay from VHH crossing to reset active Td 1 s VHL and (VHH - VHL) values are tested at room temperature. Typical temperature drift is - 8 mV per + 10 C temperature drift for VHL and + 3 mV per + 10 C for the hysteresis value. Components are tested at 75 C at which the absolute minimum VHL-level is set to 4.14 V for pass condition. Semiconductor Group 129 Electrical Characteristics 6 Package Outlines GPS05123 Plastic Package, P-DSO-28-1 (SMD) (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 130 Dimensions in mm