EPCQ-L Serial Configuration Devices Datasheet Subscribe Send Feedback CF52013 | 2018.05.18 Latest document on the web: PDF | HTML Contents Contents EPCQ-L Serial Configuration Devices Datasheet.................................................................. 3 Supported Devices....................................................................................................... 3 Features..................................................................................................................... 3 Operating Conditions.................................................................................................... 4 Absolute Maximum Ratings.................................................................................. 4 Recommended Operating Conditions......................................................................4 DC Operating Conditions...................................................................................... 5 ICC Supply Current............................................................................................. 5 Capacitance....................................................................................................... 5 Pin Information............................................................................................................6 EPCQ-L Device Pin Description.............................................................................. 7 Device Package and Ordering Code.................................................................................8 Package.............................................................................................................8 Ordering Code.................................................................................................... 8 Memory Array Organization........................................................................................... 8 Address Range for EPCQ-L256.............................................................................. 9 Address Range for EPCQ-L512............................................................................ 10 Address Range for EPCQ-L1024...........................................................................10 Memory Operations.................................................................................................... 11 Timing Requirements.........................................................................................11 Addressing Mode...............................................................................................12 Registers...................................................................................................................12 Status Register................................................................................................. 12 Flag Status Register.......................................................................................... 18 Non-Volatile Configuration Register......................................................................19 Summary of Operation Codes...................................................................................... 21 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)................................. 22 Write Enable Operation (06h)............................................................................. 22 Write Disable Operation (04h).............................................................................23 Read Bytes Operation (03h)................................................................................23 Fast Read Operation (Bh)................................................................................... 24 Extended Quad Input Fast Read Operation (EBh)................................................... 25 Read Device Identification Operation (9Eh or 9Fh)................................................. 26 Write Bytes Operation (02h)............................................................................... 27 Extended Quad Input Fast Write Bytes Operation (12h).......................................... 27 Erase Bulk Operation (C7h)................................................................................ 28 Erase Die Operation (C4h)..................................................................................29 Erase Sector Operation (D8h)............................................................................. 29 Power Mode...............................................................................................................30 Timing Information.....................................................................................................30 Write Operation Timing...................................................................................... 30 Read Operation Timing.......................................................................................31 Programming and Configuration File Support..................................................................31 Document Revision History for EPCQ-L Serial Configuration Devices Datasheet................... 32 EPCQ-L Serial Configuration Devices Datasheet 2 CF52013 | 2018.05.18 EPCQ-L Serial Configuration Devices Datasheet Supported Devices Table 1. Device EPCQ-L Devices Memory Size (bits) On-Chip Decompression Support(1) ISP Support Cascading Support(2) Reprogrammab Recommended Numbe le Operating r of Voltage (V) Die (256M B) EPCQL256 268,435,456 No Yes No Yes 1.8 1 EPCQL512 536,870,912 No Yes No Yes 1.8 2 EPCQL1024 1,073,741,824 No Yes No Yes 1.8 4 Features EPCQ-L devices offer the following features: * Compatibility with the Intel Stratix(R) 10, Intel Arria 10, and Intel Cyclone 10 GX devices * Native support for active serial (AS) x4 * Backward compatibility for AS x1 on the Intel Arria 10 and Intel Cyclone 10 GX devices * Low pin count and non-volatile memory * 1.8-V operation * Stacked die device for the EPCQ-L512 and EPCQ-L1024 devices * Manufactured on NOR technology * Available in FBGA24 package * Reprogrammable memory with more than 100,000 erase or program cycles * More than 20 years of data retention * Write protection support for memory sectors using status register bits * Fast read and extended quad input fast read of the entire memory using a single operation code (1) EPCQ-L devices are compatible with decompression built into the Intel(R) Arria(R) 10 and Intel Cyclone(R) 10 GX devices. (2) Multiple EPCQ-L devices may be used on a single FPGA device. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Warning: * Write bytes and extended quad input fast write bytes of the entire memory using a single operation code * In-system programming (ISP) support with the SRunner software driver * ISP support with Intel FPGA Download Cable II, Intel FPGA Download Cable, Ethernet Download Cable II, or Ethernet Download Cable download cables * By default, the memory array is erased and the bits are set to 1 * During user mode, you can use the Intel FPGA ASMI Parallel or Intel FPGA ASMI Parallel II IP cores to access the EPCQ-L device * More than 20 years data retention EPCQ-L devices are only compatible with the Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices. Operating Conditions This section covers information about the absolute maximum ratings, recommended operating conditions, DC operating conditions, ICC supply current, and capacitance for EPCQ-L devices. Absolute Maximum Ratings Table 2. Absolute Maximum Ratings Symbol VCC VIO (3) TSTG Parameter Condition Min Max Unit Supply voltage With respect to GND -0.6 2.4 V DC input/output voltage With respect to GND -0.6 VCC + 0.6 V Storage temperature No bias -65 150 C Recommended Operating Conditions Table 3. Symbol Recommended Operating Conditions Parameter VCC Supply voltage VI Input voltage Condition Min Max Unit (4) 1.7 2.0 V -0.5 0.4 + VCC With respect to GND V continued... (3) For periods of less than 10 ns, VIL can undershoot to -1.0 V and VIH can overshoot to VCC + 1.0 V. (4) The maximum VCC rise time is 100 ms. EPCQ-L Serial Configuration Devices Datasheet 4 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Symbol TA Parameter (5) Ambient operating temperature Condition For industrial use Min Max Unit -40 85 C tR Input rise time -- -- 5 ns tF Input fall time -- -- 5 ns Related Information * EPCQ-L Package and Thermal Resistance Provides more information about EPCQ-L thermal resistance. * Altera IBIS Models DC Operating Conditions Table 4. DC Operating Conditions Symbol Parameter Condition Min Max Unit VIH High-level input voltage -- 0.7 x VCC VCC + 0.4 V VIL Low-level input voltage -- -0.5 0.3 x VCC V VOH High-level output voltage IOH = -100 A (6) VCC - 0.2 -- V (7) -- 0.4 V -2 2 A Min Max Unit VOL Low-level output voltage IOL = 1.6 mA II Input leakage current VI =VCC or GND ICC Supply Current Table 5. ICC Supply Current Symbol Parameter Condition ICC0 VCC supply current Standby -- 100 A ICC1 VCC supply current During active power mode -- 20 mA Min Max Unit Capacitance Table 6. Symbol Capacitance Parameter(8) Condition CIN Input pin capacitance VIN = 0 V -- 6 pF CIN/OUT Input/Output pin capacitance VOUT = 0 V -- 8 pF (5) EPCQ-L devices can be paired with industrial-grade FPGAs operating at junction temperatures up to 100C as long as the ambient temperature for the EPCQ-L device does not exceed 85C. (6) The IOH parameter refers to the high-level TTL or CMOS output current. (7) The IOL parameter refers to the low-level TTL or CMOS output current. (8) Capacitance is sample-tested only at TA = 25C and at a 54-MHz frequency. EPCQ-L Serial Configuration Devices Datasheet 5 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Pin Information Figure 1. Pin-Out Diagram for EPCQ-L Devices in the FBGA24 Package 5 4 3 2 1 A B C D E Table 7. Signals for EPCQ-L Devices Signals Balls nCS C2 DCLK B2 DATA0 D3 DATA1 D2 DATA2 C4 DATA3 D4 VCC B4 GND B3 DNU(9) A2 A3 A4 A5 B1 B5 C1 C3 C5 D1 D5 E1 E2 continued... (9) Do not use EPCQ-L Serial Configuration Devices Datasheet 6 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Signals Balls E3 E4 E5 EPCQ-L Device Pin Description Table 8. EPCQ-L Device Pin Description Pin Name Pin Type Description nCS Input The active low nCS input signal toggles at the beginning and end of a valid operation. When this signal is high, the device is deselected and the DATA pin is tri-stated. When this signal is low, the device is enabled and is in active mode. After power up, the EPCQ-L device requires a falling edge on the nCS signal before you begin any operation. DCLK Input The FPGA provides the DCLK signal. This signal provides the timing for the serial interface. The data presented on the DATA0 pin is latched to the EPCQ-L device on the rising edge of the DCLK signal. The data on the DATA pin changes after the falling edge of the DCLK signal and is latched in to the FPGA on the next falling edge of the DCLK signal. DATA0 I/O For AS x1 mode, use this pin as an input signal pin to write or program the EPCQ-L device. During write or program operations, the data is latched on the rising edge of the DCLK signal. For AS x4 mode, use this pin as an I/O signal pin. During write or program operations, this pin acts as an input pin that serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the DCLK signal. During read or configuration operations, this pin acts as an output signal pin that serially transfers data out of the EPCQ-L device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. During the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the DCLK signal. During extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ-L device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. DATA1 I/O For AS x1 mode, use this pin as an output signal pin that serially transfers data out of the EPCQ-L device to the FPGA during read or configuration operations. For AS x4 mode, use this pin as an I/O signal pin. The transition of the signal is on the falling edge of the DCLK signal. During the extended quad input fast write bytes operation, this pin acts as an input signal pin that serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the DCLK signal. During extended quad input fast read operation, this pin acts as an output signal pin that serially transfer data out of the EPCQ-L device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. During read, configuration, or program operations, you can enable the EPCQ-L device by pulling the nCS signal low. DATA2 I/O For AS x1 mode, this pin must connect to a 1.8-V power supply. For AS x4 mode, use this pin as an output signal that serially transfers data out of the EPCQ-L device to the FPGA during read or configuration operations. The transition of the signal is on the falling edge of the DCLK signal. During the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the DCLK signal. During the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ-L device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. DATA3 I/O For AS x1 mode, this pin must connect to a 1.8-V power supply. For AS x4 mode, use this pin as an output signal that serially transfers data out of the EPCQ-L device to the FPGA during read or configuration operations. The transition of the signal is on the falling edge of the DCLK signal. continued... EPCQ-L Serial Configuration Devices Datasheet 7 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Pin Name Pin Type Description During the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the EPCQ-L device. The data is latched on the rising edge of the DCLK signal. During the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ-L device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. VCC Power GND Ground Connect the power pins to a 1.8-V power supply. Ground pin. Device Package and Ordering Code This section describes the package offered in EPCQ-L devices and the ordering codes for each EPCQ-L device. Package The EPCQ-L256, EPCQ-L512, and EPCQ-L1024 devices are available in FBGA24 packages. Related Information * EPCQ-L Device Package Information Provides more information about EPCQ-L packaging specifications, thermal resistance and dimensions. * ADV1712: Removal of 3-Year Date Code Shipment Restriction for Selected Configuration Devices (EPCQL; EPCQ 256 Mb and larger) Ordering Code Table 9. EPCQ-L Device Ordering Codes Device Ordering Code(10) EPCQ-L256 EPCQL256F24IN EPCQ-L512 EPCQL512F24IN EPCQ-L1024 EPCQL1024F24IN Memory Array Organization Table 10. Memory Array Organization in EPCQ-L Devices Details Bytes EPCQ-L256 EPCQ-L512 EPCQ-L1024 33,554,432 bytes (256 Mb) 67,108,864 bytes (512 Mb) 134,217,728 bytes (1,024 Mb) 512 1,024 2,048 Number of sectors Bytes per sector 65,536 bytes (512 Kb) continued... (10) N indicates that the device is lead free. EPCQ-L Serial Configuration Devices Datasheet 8 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Details Total numbers of subsectors(11) EPCQ-L256 EPCQ-L512 EPCQ-L1024 8,192 16,384 32,768 Bytes per subsector 4,096 bytes (32 Kb) Pages per sector Total number of pages 256 131,072 Bytes per page 262,144 524,288 256 bytes Address Range for EPCQ-L256 Table 11. Address Range for Sectors 511..0 and Subsectors 8191..0 in EPCQ-L256 Devices Sector Address Range (Byte Addresses in HEX) Start End 8191 01FFF000h 01FFFFFFh ... ... ... 8176 01FF0000h 01FF0FFFh ... ... ... ... 255 4095 00FFF000h 00FFFFFFh ... ... ... 4080 00FF0000h 00FF0FFFh ... ... ... ... 127 2047 007FF000h 007FFFFFh ... ... ... 2032 007F0000h 007F0FFFh ... ... ... ... 63 1023 003FF000h 003FFFFFh ... ... ... 1008 003F0000h 003F0FFFh ... ... ... ... 0 15 0000F000h 0000FFFFh ... ... ... 0 00000000h 00000FFFh 511 (11) Subsector Every sector is further divided into 16 subsectors with 4 KB of memory. Therefore, there are 8,192 (512 x 16) subsectors for the EPCQ-L256 device, 16,384 (1,024 x 16) subsectors for the EPCQ-L512 device, and 32,768 (2,048 x 16) subsectors for the EPCQ-L1024 device. EPCQ-L Serial Configuration Devices Datasheet 9 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Address Range for EPCQ-L512 Table 12. Address Range for Sectors 1023..0 and Subsectors 16383..0 in EPCQ-L256 Devices Sector Subsector Address Range (Byte Addresses in HEX) Start End 16383 03FFF000h 03FFFFFFh ... ... ... 16368 03FF0000h 03FF0FFFh ... ... ... ... 511 8191 01FFF000h 01FFFFFFh ... ... ... 8176 01FF0000h 01FF0FFFh ... ... ... ... 255 4095 00FFF000h 00FFFFFFh ... ... ... 4080 00FF0000h 00FF0FFFh ... ... ... ... 127 2047 007FF000h 007FFFFFh ... ... ... 2032 007F0000h 007F0FFFh ... ... ... ... 63 1023 003FF000h 003FFFFFh ... ... ... 1008 003F0000h 003F0FFFh ... ... ... ... 0 15 0000F000h 0000FFFFh ... ... ... 0 00000000h 00000FFFh 1023 Address Range for EPCQ-L1024 Table 13. Address Range for Sectors 2047..0 and Subsectors 32767..0 in EPCQ-L1024 Devices Sector Subsector 2047 Address Range (Byte Addresses in HEX) Start End 32767 07FFF000h 07FFFFFFh ... ... ... continued... EPCQ-L Serial Configuration Devices Datasheet 10 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Sector Subsector Address Range (Byte Addresses in HEX) Start End 32750 07FF0000h 07FF0FFFh ... ... ... ... 1023 16383 03FFF000h 03FFFFFFh ... ... ... 16368 03FF0000h 03FF0FFFh ... ... ... ... 511 8191 01FFF000h 01FFFFFFh ... ... ... 8176 01FF0000h 01FF0FFFh ... ... ... ... 255 4095 00FFF000h 00FFFFFFh ... ... ... 4080 00FF0000h 00FF0FFFh ... ... ... ... 127 2047 007FF000h 007FFFFFh ... ... ... 2032 007F0000h 007F0FFFh ... ... ... ... 63 1023 003FF000h 003FFFFFh ... ... ... 1008 003F0000h 003F0FFFh ... ... ... ... 0 15 0000F000h 0000FFFFh ... ... ... 0 00000000h 00000FFFh Memory Operations This section describes the operations that you can use to access the memory in EPCQL devices. When performing the operation, addresses and data are shifted in and out of the device serially, with the MSB first Timing Requirements When the active low chip select (nCS) signal is driven low, shift in the operation code into the EPCQ-L device using the serial data (DATA0) pin. Each operation code bit is latched into the EPCQ-L device on the rising edge of the DCLK. EPCQ-L Serial Configuration Devices Datasheet 11 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 While executing an operation, shift-in the desired operation code, followed by the address or data bytes as listed in Table 24 on page 21. The device must drive the nCS pin high after the last bit of the operation sequence is shifted in. For read operations, the data read is shifted out on the DATA0 pin. You can drive the nCS pin high when any bit of the data is shifted out. For write and erase operations, drive the nCS pin high at a byte boundary, that is in a multiple of eight clock pulses. Otherwise, the operation is rejected and not executed. All attempts to access the memory contents while a write or erase cycle is in progress are rejected, and the write or erase cycle continues unaffected. Addressing Mode To access the EPCQ-L256, EPCQ-L512, or EPCQ-L1024 memory, you must use the 4byte addressing mode. In 4-byte addressing mode, the address width is 32-bit. To enable the 4-byte addressing mode, you must execute the 4BYTEADDREN operation. This addressing mode takes effect immediately after you execute the 4BYTEADDREN operation and remains active in the subsequent power-ups. To disable the 4-byte addressing mode, you must execute the 4BYTEADDREX operation. If you are using the Intel Quartus(R) Prime software or the SRunner software to program the EPCQ-L256, EPCQ-L512, or EPCQ-L1024 device, you do not need to execute the 4BYTEADDREN operation. These software tools automatically enable the 4-byte addressing mode when programming the device. Note: Registers Status Register Table 14. Status Register Bits Bit Name Value Description 7 None 6 BP3 (Block Protect Bit)(12) Table 15 on page 13 through Table 20 on page 16 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally. 5 TB (Top/Bottom Bit) * Determine that the protected area starts from the top or bottom of the memory array. * 4 BP2(12) 3 BP1(12) 1=Protected area starts from the bottom of the memory array. 0=Protected area starts from the top of the memory array. Table 15 on page 13 through Table 20 on page 16 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally. continued... (12) The erase bulk and erase die operation is only available when all the block protect bits are set to 0. When any of the block protect bits are set to 1, the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation. EPCQ-L Serial Configuration Devices Datasheet 12 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Bit Name Value 2 BP0(12) 1 WEL (Write Enable Latch Bit) * * 0 WIP (Write in Progress Bit) * * Description 1=Allows the following operation to run: -- Write Bytes -- Write Status Register -- Erase Bulk -- Erase Die -- Erase Sector 0=Rejects the above mentioned operations. Allows or rejects certain operation to run. 1=One of the following operation is in progress: -- Write Status Register -- Write NVCR -- Write Bytes -- Erase 0=no write or erase cycle in progress Indicates if there is a command in progress. Read Status Register Operation (05h) The status register can be read continuously and at anytime, including during a write or erase operations. Figure 2. Read Status Register Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DCLK Operation Code (05h) DATA0 Status Register Out High Impedance DATA 7 6 5 4 3 Status Register Out 2 1 0 MSB 7 6 5 4 3 2 1 0 7 MSB Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Table 15. Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 0 0 0 0 0 None All sectors 0 0 0 0 1 Sector 511 Sectors (0 to 510) 0 0 0 1 0 Sectors (510 to 511) Sectors (0 to 509) 0 0 0 1 1 Sectors (508 to 511) Sectors (0 to 507) 0 0 1 0 0 Sectors (504 to 511) Sectors (0 to 503) 0 0 1 0 1 Sectors (496 to 511) Sectors (0 to 495) 0 0 1 1 0 Sectors (480 to 511) Sectors (0 to 479) 0 0 1 1 1 Sectors (448 to 511) Sectors (0 to 447) 0 1 0 0 0 Sectors (384 to 511) Sectors (0 to 383) 0 1 0 0 1 Sectors (256 to 511) Sectors (0 to 255) continued... EPCQ-L Serial Configuration Devices Datasheet 13 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 0 1 0 1 0 All sectors None 0 1 0 1 1 All sectors None 0 1 1 0 0 All sectors None 0 1 1 0 1 All sectors None 0 1 1 1 0 All sectors None 0 1 1 1 1 All sectors None Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Table 16. Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 1 0 0 0 0 None All sectors 1 0 0 0 1 Sector 0 Sectors (1 to 511) 1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 511) 1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 511) 1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 511) 1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 511) 1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 511) 1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 511) 1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 511) 1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 511) 1 1 0 1 0 All sectors None 1 1 0 1 1 All sectors None 1 1 1 0 0 All sectors None 1 1 1 0 1 All sectors None 1 1 1 1 0 All sectors None 1 1 1 1 1 All sectors None Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Table 17. Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 0 0 0 0 0 None All sectors 0 0 0 0 1 Sector 1023 Sectors (0 to 1022) 0 0 0 1 0 Sectors (1022 to 1023) Sectors (0 to 1021) continued... EPCQ-L Serial Configuration Devices Datasheet 14 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 0 0 0 1 1 Sectors (1020 to 1023) Sectors (0 to 1019) 0 0 1 0 0 Sectors (1016 to 1023) Sectors (0 to 1015) 0 0 1 0 1 Sectors (1008 to 1023) Sectors (0 to 1007) 0 0 1 1 0 Sectors (992 to 1023) Sectors (0 to 991) 0 0 1 1 1 Sectors (960 to 1023) Sectors (0 to 959) 0 1 0 0 0 Sectors (896 to 1023) Sectors (0 to 895) 0 1 0 0 1 Sectors (768 to 1023) Sectors (0 to 767) 0 1 0 1 0 Sectors (512 to 1023) Sectors (0 to 511) 0 1 0 1 1 All sectors None 0 1 1 0 0 All sectors None 0 1 1 0 1 All sectors None 0 1 1 1 0 All sectors None 0 1 1 1 1 All sectors None Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Table 18. Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 1 0 0 0 0 None All sectors 1 0 0 0 1 Sector 0 Sectors (1 to 1023) 1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 1023) 1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 1023) 1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 1023) 1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 1023) 1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 1023) 1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 1023) 1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 1023) 1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 1023) 1 1 0 1 0 Sectors (0 to 511) Sectors (512 to 1023) 1 1 0 1 1 All sectors None 1 1 1 0 0 All sectors None 1 1 1 0 1 All sectors None 1 1 1 1 0 All sectors None 1 1 1 1 1 All sectors None EPCQ-L Serial Configuration Devices Datasheet 15 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Table 19. Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 0 0 0 0 0 None All sectors 0 0 0 0 1 Sector 2047 Sectors (0 to 2046) 0 0 0 1 0 Sectors (2046 to 2047) Sectors (0 to 2045) 0 0 0 1 1 Sectors (2044 to 2047) Sectors (0 to 2043) 0 0 1 0 0 Sectors (2040 to 2047) Sectors (0 to 2039) 0 0 1 0 1 Sectors (2032 to 2047) Sectors (0 to 2031) 0 0 1 1 0 Sectors (2016 to 2047) Sectors (0 to 2015) 0 0 1 1 1 Sectors (1984 to 2047) Sectors (0 to 1983) 0 1 0 0 0 Sectors (1920 to 2047) Sectors (0 to 1919) 0 1 0 0 1 Sectors (1792 to 2047) Sectors (0 to 1791) 0 1 0 1 0 Sectors (1536 to 2047) Sectors (0 to 1535) 0 1 0 1 1 Sectors (1024 to 2047) Sectors (0 to 1023) 0 1 1 0 0 All sectors None 0 1 1 0 1 All sectors None 0 1 1 1 0 All sectors None 0 1 1 1 1 All sectors None Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1 Table 20. Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 1 0 0 0 0 None All sectors 1 0 0 0 1 Sector 0 Sectors (1 to 2047) 1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 2047) 1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 2047) 1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 2047) 1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 2047) 1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 2047) 1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 2047) 1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 2047) 1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 2047) 1 1 0 1 0 Sectors (0 to 511) Sectors (512 to 2047) 1 1 0 1 1 Sectors (0 to 1023) Sectors (1024 to 2047) continued... EPCQ-L Serial Configuration Devices Datasheet 16 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Status Register Content Memory Content TB Bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area 1 1 1 0 0 All sectors None 1 1 1 0 1 All sectors None 1 1 1 1 0 All sectors None 1 1 1 1 1 All sectors None Write Status Register Operation (01h) The write status register operation does not affect the write enable latch and write in progress bits. You can use the write status register operation to set the status register block protection and top or bottom bits. Therefore, you can implement this operation to protect certain memory sectors. Refer to Table 15 on page 13 through Table 20 on page 16. After setting the block protect bits, the protected memory sectors are treated as read-only memory. You must execute the write enable operation before the write status operation. When the operation is in progress, the write or erase controller bit of the flag status register is set to 0. To obtain the operation status, the flag status register must be polled(13), with nCS toggled twice in between commands. When the operation completes, the write or erase controller bit is cleared to 1. The end of operation can be detected when the flag status register outputs the write or erase controller bit to 1 each time it is polled. The following figure shows the timing diagram for the write status register operation. Figure 3. Write Status Register Operation Timing Diagram nCS 0 1 3 2 4 5 6 7 8 9 10 11 12 13 14 15 2 1 0 DCLK Operation Code (01h) Status Register 7 DATA0 6 5 4 3 MSB DATA High Impedance Immediately after the nCS signal drives high, the device initiates the self-timed write status cycle. The self-timed write status cycle usually takes 5 ms for all EPCQ-L devices and is guaranteed to be less than 8 ms. For details about tWS, refer to Table 26 on page 30. You must account for this delay to ensure that the status register is written with the desired block protect bits. Alternatively, you can check the write in progress bit in the status register by executing the read status register operation while the self-timed write status cycle is in progress. The flash controller sets the write in progress bit to 1 during the self-timed write status cycle and 0 when it is complete. (13) Poll the flag status register once for EPCQL256, twice for EPCQL512 or four times for EPQL1024. EPCQ-L Serial Configuration Devices Datasheet 17 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Flag Status Register Table 21. Flag Status Register Bits Bit Name Value Description 7 Write or Erase Controller(14) * * 1=Ready 0=Busy Indicates whether one of the following operation is in progress: * Write Status Register * Write NVCR * Write Bytes * Erase 6 Erase suspend * * 1=In effect 0=Not in effect Indicates whether an Erase operation has been or is going to be suspended. 5 Erase * 1=Failure or protection error 0=Clear Indicates whether an Erase operation has succeeded or failed. * 1=Failure or protection error 0=Clear Indicates whether a Write Bytes operation has succeeded or failed; also an attempt to write a 0 to a 1 when VPP = VPPH and the data pattern is a multiple of 64 bits. Note: Status bits are reset automatically * 4 Write * 3 Reserved 2 Write suspend * * 1=In effect 0=Not in effect Indicates whether a Write Bytes operation has been or will be suspended. 1 Protection * Indicates whether an Erase or Write Bytes operation has attempted to modify the protected array sector. * 1=Failure or protection error 0=Clear * * 1=4-bytes addressing 0=3-bytes addressing Indicates the addressing mode used. 0 Addressing Read Flag Status Register Operation(70h) The Read flag status register can be read continuously and at any time, including during a write or erase operation. You must read the Read flag status register every time a write or erase command is issued. Figure 4. Read Flag Status Register Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DCLK Operation Code (70h) DATA0 DATA High Impedance Status Register Out 7 6 5 4 3 MSB (14) Write or erase controller bit = NOT write in progress bit. EPCQ-L Serial Configuration Devices Datasheet 18 2 Status Register Out 1 0 7 MSB 6 5 4 3 2 1 0 7 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Non-Volatile Configuration Register Table 22. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration Register Operation FPGA Device Address Bytes Dummy Clock Cycles AS x1 AS x4 Intel Arria 10 and Intel Cyclone 10 GX 4-byte addressing 10 10 Intel Stratix 10 4-byte addressing -- 10 Table 23. Non-Volatile Configuration Register Operation Bit Definition Bit 15:12 11:5 4 3:1 0 Description Default Value Number of dummy cycles. When this number is from 0001 to 1110, the dummy cycles is from 1 to 14. Set these bits to 1111111. (15) (16) 1111111 Don't care. 1 Set these bits to 111. 111 (17) Address byte setting. * 0--4-byte addressing * 0000 or 1111 1 1--3-byte addressing Read Non-Volatile Configuration Register Operation (B5h) To execute a read non-volatile configuration register, drive the nCS low. For extended SPI protocol, the operation code is input on DATA0, and output on DATA1. You can terminate the operation by driving the nCS low at any time during data output. The nonvolatile configuration register can be read continuously. After all 16 bits of the register have been read, a 0 is output. (15) The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended dual input fast and standard fast read. (16) For the Intel Stratix 10 device, use the default value 1111h to set 10 dummy clock cycles. (17) You can only configure the Intel Arria 10 and Intel Cyclone 10 GX devices using the 4-byte addressing mode. EPCQ-L Serial Configuration Devices Datasheet 19 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Figure 5. Read Non-Volatile Configuration Register Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DCLK Operation Code (B5h) DATA0 High Impedance DATA NVCR Out NVCR Out 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 LS Byte MS Byte Write Non-Volatile Configuration Register Operation (B1h) You need to write the non-volatile configuration registers for EPCQ-L devices for different configuration schemes. If you are using the .jic file, the Intel Quartus Prime programmer sets the number of dummy clock cycles and address bytes. If you are using an external programmer tools (3rd party programmer tools), you must set the non-volatile configuration registers. To set the non-volatile configuration register, follow these steps: 1. Execute the write enable operation. 2. Execute the write non-volatile configuration register operation. 3. Set the 16-bit register value. Set the 16-bit register value as b'1110 1110 xxxx 1111 where xxxx is the dummy clock value. When the xxxx value is from 0001 to 1110, the dummy clock value is from 1 to 14. When xxxx is 0000 or 1111, the dummy clock value is at the default value, which is 8 for standard fast read (AS x1) mode and 10 for extended quad input fast read (AS x4) mode. Figure 6. Write Non-Volatile Configuration Register Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DCLK Operation Code (B1h) DATA0 DATA NVCR In Byte Byte 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 High Impedance EPCQ-L Serial Configuration Devices Datasheet 20 LS Byte MS Byte EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Summary of Operation Codes Table 24. Operation Codes for EPCQ-L Devices Operation Operation Code (18) Address Bytes Dummy Cycles Data Bytes DCLK fMAX (MHz) Read status register 05h 0 0 1 to infinite(19) 100 Read flag status register 70h 0 0 1 to infinite 100 (19) Read bytes 03h 4 0 1 to infinite Read non-volatile configuration register B5h 0 0 2 Read device identification 9Eh or 9Fh 0 2 1 to 20 Fast read (AS x1) 0Bh 4 8 Extended quad input fast read (AS x4) EBh 4 10 Dual I/O fast read BBh 4 10 1 to infinite 100 Write enable 06h 0 0 0 100 Write disable 04h 0 0 0 100 Write status 01h 0 0 1 100 Write bytes 02h 4 0 1 to 256 Write non-volatile configuration register B1h 0 0 2 Extended quad input fast write bytes 12h 4 0 1 to 256 Extended dual input fast write bytes D2h 4 0 1 to 256 100 C7h 4 0 0 100 C4h 4 0 0 100 D8h 4 0 0 100 Erase bulk Erase die (22) (23) Erase sector (20) (20) 50 100 (19) 100 1 to infinite (19) 100 1 to infinite (19) 100 (21) 100 100 (21) 100 continued... (18) List MSB first and LSB last. (19) The status register, data, or read device identification is read out at least once and is continuously read out until the nCS pin is driven high. (20) The default EPCQ-L dummy clocks are 8 and 10 for the fast read and extended quad input fast read operations, respectively. The Intel Quartus Prime Programmer configures the NVCR automatically during the JIC programming to meet the FPGA dummy clock requirement for configuration. (21) A write bytes operation requires at least one data byte. If more than 256 bytes are sent to the device, only the last 256 bytes are written to the memory. (22) Erase bulk is applicable to EPCQ-L256 only. (23) Erase die is applicable to EPCQ-L512 and EPCQ-L1024 only. EPCQ-L Serial Configuration Devices Datasheet 21 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Operation Operation Code (18) Address Bytes Dummy Cycles Data Bytes DCLK fMAX (MHz) Erase subsector 20h 4 0 0 100 4BYTEADDREN B7h 0 0 0 100 4BYTEADDREX E9h 0 0 0 100 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) To enable 4BYTEADDREN or 4BYTEADDREX operations, you can select the device by driving the nCS signal low, followed by shifting in the operation code through DATA0. The following figure shows the timing diagram for the 4BYTEADDREN operation. Figure 7. 4BYTEADDREN Timing Diagram nCS 0 1 3 2 4 5 6 7 DCLK Operation Code (B7h) DATA0 The following figure shows the timing diagram for the 4BYTEADDREX operation. Figure 8. 4BYTEADDREX Timing Diagram nCS 0 1 2 3 4 5 6 7 DCLK Operation Code (E9h) DATA0 Write Enable Operation (06h) When you enable the write enable operation, the write enable latch bit is set to 1 in the status register. You must execute this operation before the write bytes, write status, erase bulk, erase sector, erase die, extended quad input fast write bytes, 4BYTEADDREN, and 4BYTEADDREX operations. The following figure shows the timing diagram for the write enable operation. (18) List MSB first and LSB last. EPCQ-L Serial Configuration Devices Datasheet 22 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Figure 9. Write Enable Operation Timing Diagram nCS 1 0 3 2 5 4 7 6 DCLK Operation Code (06h) DATA0 High Impedance DATA Write Disable Operation (04h) The write disable operation resets the write enable latch bit in the status register. To prevent the memory from being written unintentionally, the write enable latch bit is automatically reset when implementing the write disable operation, and under the following conditions: * Power up * Write bytes operation completion * Write status operation completion * Erase bulk operation completion * Erase sector operation completion * Erase die operation completion * Extended quad input fast write bytes operation completion The following figure shows the timing diagram for the write disable operation. Figure 10. Write Disable Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 DCLK Operation Code (04h) DATA0 DATA High Impedance Read Bytes Operation (03h) When you execute the read bytes operation, you first shift in the read bytes operation code, followed by a 4-byte addressing mode (A[31..0]). Each address bit is latched in on the rising edge of the DCLK signal. After the address is latched in, the memory EPCQ-L Serial Configuration Devices Datasheet 23 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 contents of the specified address are shifted out serially on the DATA1 pin, beginning with the MSB. When reading back data programmed from a Raw Programming Data File (.rpd), the content is shifted out serially beginning with the LSB. Each data bit is shifted out on the falling edge of the DCLK signal. The maximum DCLK frequency during the read bytes operation is 50 MHz. Figure 11. Read Bytes Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 36 37 3 2 38 39 40 41 42 6 5 43 44 45 46 47 2 1 0 DCLK Operation Code (03h) 32-Bit Address 31 DATA0 30 29 1 0 MSB DATA1 High Impedance DATA Out 1 7 4 3 DATA Out 2 7 MSB The first byte address can be at any location. The device automatically increases the address to the next higher address after shifting out each byte of data. When the device reaches the highest address, the address counter restarts at the beginning of the same die, allowing the memory contents to be read out indefinitely until the read bytes operation is terminated by driving the nCS signal high. A complete device reading is done by executing the read operation: * two times for EPCQ-L512 devices * four times for EPCQ-L1024 devices If the read bytes operation is shifted in while a write or erase cycle is in progress, the operation is not executed and does not affect the write or erase cycle in progress. Fast Read Operation (Bh) When you execute the fast read operation, you first shift in the fast read operation code, followed by a 4-byte addressing mode (A[31..0]), and dummy cycle(s) with each bit being latched-in during the rising edge of the DCLK signal. Then, the memory contents at that address is shifted out on DATA1 with each bit being shifted out at a maximum frequency of 100 MHz during the falling edge of the DCLK signal. EPCQ-L Serial Configuration Devices Datasheet 24 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Figure 12. Fast Read Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 3 2 1 0 DCLK Operation Code (Bh) 32-Bit Address 31 DATA0 30 29 51 52 MSB High Impedance DATA1 nCS 40 41 42 43 44 45 46 2 1 47 48 49 50 6 5 53 54 55 2 1 0 DCLK Dummy Cycle(s) DATA0 7 6 5 4 3 0 DATA Out 1 DATA1 7 4 3 DATA Out 2 MSB 7 MSB 6 5 4 3 2 1 0 7 MSB The first byte address can be at any location. The device automatically increases the address to the next higher address after shifting out each byte of data. When the device reaches the highest address, the address counter restarts at the beginning of the same die, allowing the read sequence to continue indefinitely. A complete device reading is done by executing the read operation: * two times for EPCQ-L512 devices * four times for EPCQ-L1024 devices You can terminate the fast read operation by driving the nCS signal high at any time during data output. If the fast read operation is shifted in while an erase, program, or write cycle is in progress, the operation is not executed and does not affect the erase, program, or write cycle in progress. Extended Quad Input Fast Read Operation (EBh) This operation is similar to the fast read operation except that the data and addresses are shifted in and out on the DATA0, DATA1, DATA2, and DATA3 pins. EPCQ-L Serial Configuration Devices Datasheet 25 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Figure 13. Extended Quad Input Fast Read Operation Timing Diagram nCS 0 1 3 4 5 2 8 9 10 11 12 13 14 15 16 7 6 26 27 28 29 30 31 32 DCLK Operating Code (EBh) I/O Switches from Input to Output DATA0 Don't Care DATA1 Don't Care DATA2 DATA3 `1' 28 24 20 16 12 8 4 0 4 0 4 0 4 29 25 21 17 13 9 5 1 5 1 5 1 5 30 26 22 18 14 10 6 2 6 2 6 2 6 31 27 23 19 15 11 7 3 7 3 7 3 7 32-Bit Address Byte 1 Byte 2 Dummy Cycles When the device reaches the highest address, the address counter restarts at the beginning of the same die, allowing the read sequence to continue indefinitely. A complete device reading is done by executing the read operation: * two times for EPCQ-L512 devices * four times for EPCQ-L1024 devices Read Device Identification Operation (9Eh or 9Fh) This operation reads the 8-bit device identification of the EPCQ-L device from the DATA1 output pin. If this operation is shifted in while an erase or write cycle is in progress, the operation is not executed and does not affect the erase or write cycle in progress. Table 25. EPCQ-L Device Identification EPCQ-L Device Silicon ID (Binary Value) EPCQ-L256 b'0001 1001 EPCQ-L512 b'0010 0000 EPCQ-L1024 b'0010 0001 The 8-bit device identification of the EPCQ-L device is shifted out on the DATA1 pin on the falling edge of the DCLK signal. LSB is first shifted into the FPGA device. Figure 14. Read Device Identification Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 20 21 23 24 25 26 27 28 29 30 31 32 2 1 0 DCLK Operation Code (9Fh) Two Dummy Cycles 15 DATA0 14 13 3 2 1 0 Silicon ID MSB DATA1 High Impedance Dont't Care 7 MSB EPCQ-L Serial Configuration Devices Datasheet 26 6 5 4 3 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Write Bytes Operation (02h) This operation allows bytes to be written to the memory. You must execute the write enable operation before the write bytes operation. After the write bytes operation is completed, the write enable latch bit in the status register is set to 0. When you execute the write bytes operation, you shift in the write bytes operation code, followed by a 4-byte addressing mode (A[31..0]), and at least one data byte on the DATA0 pin. If the eight LSBs (A[7..0]) are not all 0, all sent data that goes beyond the end of the current page is not written into the next page. Instead, this data is written at the start address of the same page. You must ensure the nCS signal is set low during the entire write bytes operation. The following figure shows the operation sequence of the write bytes operation. Figure 15. Write Bytes Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 2073 2074 2075 2076 2077 2078 2079 2 1 0 7 DCLK Operation Code (02h) DATA0 32-Bit Address 31 MSB 30 29 3 Data Byte 1 2 1 0 7 MSB 6 5 4 3 Data Byte 2 2 1 0 7 6 5 4 3 Data Byte 256 MSB 6 5 4 3 2 1 0 MSB If more than 256 data bytes are shifted into the EPCQ-L device with a write bytes operation, the previously latched data is discarded and the last 256 bytes are written to the page. However, if less than 256 data bytes are shifted into the EPCQ-L device, they are guaranteed to be written at the specified addresses and the other bytes of the same page are not affected. The device initiates a self-timed write cycle immediately after the nCS signal is driven high. For details about the self-timed write cycle time, refer to tWB in Table 26 on page 30. You must account for this amount of delay before another page of memory is written. Alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed write cycle is in progress. The write in progress bit is set to 1 during the self-timed write cycle and 0 when it is complete. Note: You must erase all the memory bytes of EPCQ-L devices before you implement the write bytes operation. You can erase all the memory bytes by executing the erase sector operation in a sector or the erase bulk or erase die operation throughout the entire memory. Extended Quad Input Fast Write Bytes Operation (12h) This operation is similar to the write bytes operation except that the data and addresses are shifted in on the DATA0, DATA1, DATA2, and DATA3 pins. The following figure shows the operation sequence of the extended quad input fast write bytes operation. EPCQ-L Serial Configuration Devices Datasheet 27 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Figure 16. Extended Quad Input Fast Write Bytes Operation Sequence nCS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 DCLK DATA0 DATA1 DATA2 Don't Care Don't Care DATA3 Data In 2 1 32-Bit Address Operation Code (12h) `1' Data In 3 4 Data In 5 6 7 28 24 20 16 12 8 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 29 25 21 17 13 9 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 30 26 22 18 14 10 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 31 27 23 19 15 11 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 MSB MSB MSB MSB MSB MSB MSB Erase Bulk Operation (C7h) This operation sets all the memory bits to 1or 0xFF. Similar to the write bytes operation, you must execute the write enable operation before the erase bulk operation. If you are using the EPCQ-L256 device and wish to erase the whole memory of your device, you cannot use the erase die operation and instead must execute the erase bulk operation. You can implement the erase bulk operation by driving the nCS signal low and then shifting in the erase bulk operation code on the DATA0 pin. The nCS signal must be driven high after the eighth bit of the erase bulk operation code has been latched in. Figure 17. Erase Bulk Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 DCLK Operation Code (C7h) DATA0 The device initiates a self-timed erase bulk cycle immediately after the nCS signal is driven high. For details about the self-timed erase bulk cycle time, refer to tWB in Table 26 on page 30. You must account for this delay before accessing the memory contents. Alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed erase cycle is in progress. The write in progress bit is set to 1 during the self-timed erase cycle and 0 when it is complete. The write enable latch bit in the status register is reset to 0 before the erase cycle is complete. EPCQ-L Serial Configuration Devices Datasheet 28 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Erase Die Operation (C4h) This operation sets all the memory bits of a particular die in an EPCQ-L512 or EPCQL1024 device to 1 or 0xFF. Similar to the write bytes operation, you must execute the write enable operation before the erase die operation. If you are using the EPCQ-L512 or EPCQ-L1024 device, you must execute the erase die operation to erase the memory of your device. You need to issue the erase die operation for each die in your device. For example, you need to issue the erase die operation twice for the EPCQ-L512 device and four times for the EPCQ-L1024 device. EPCQ-L512 and EPCQ-L1024 devices have more than one die per device. You can implement the erase die operation by driving the nCS signal low and then shifting in the erase die operation code on the DATA0 pin, followed by the address bytes, any address within the single 256 Mb die is valid. The nCS signal must be driven high after the eighth bit of the erase die operation code has been latched in. Erase Sector Operation (D8h) The erase sector operation allows you to erase a certain sector in the EPCQ-L device by setting all the bits inside the sector to 1 or 0xFF. This operation is useful if you want to access the unused sectors as a general purpose memory in your applications. You must execute the write enable operation before the erase sector operation. When you execute the erase sector operation, you must first shift in the erase sector operation code, followed by the 4-byte addressing mode (A[31..0]) of the chosen sector on the DATA0 pin. The 4-byte addressing mode for the erase sector operation can be any address inside the specified sector. For details about the sector address range, refer to Table 11 on page 9 through Table 13 on page 10. Drive the nCS signal high after the eighth bit of the erase sector operation code has been latched in. Figure 18. Erase Sector Operation Timing Diagram nCS 0 1 2 3 4 5 6 7 8 9 36 37 38 39 3 2 1 0 DCLK Operation Code (D8h) DATA0 32-Bit Address 31 30 MSB The device initiates a self-timed erase sector cycle immediately after the nCS signal is driven high. For details about the self-timed erase sector cycle time, refer to tES in Table 26 on page 30. You must account for this amount of delay before another page of memory is written. Alternatively, you can check the write in progress bit in the status register by executing the read status operation while the self-timed erase cycle is in progress. The write in progress bit is set to 1 during the self-timed erase cycle and 0 when it is complete. The write enable latch bit in the status register is set to 0 before the self-timed erase cycle is complete. EPCQ-L Serial Configuration Devices Datasheet 29 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Power Mode EPCQ-L devices support active and standby power modes. When the nCS signal is low, the device is enabled and is in active power mode. The FPGA is configured while the EPCQ-L device is in active power mode. When the nCS signal is high, the device is disabled but remains in active power mode until all internal cycles are completed, such as write or erase operations. The EPCQ-L device then goes into standby power mode. The ICC1 and ICC0 parameters list the VCC supply current when the device is in active and standby power modes. Refer to Table 5 on page 5. Timing Information Write Operation Timing Figure 19. Write Operation Timing Diagram tCSH nCS tNCSH tNCSSU tCL tCH DCLK tDSU DATA0 DATA Table 26. tDH Bit n Bit n - 1 Bit 0 High Impedance Write Operation Timing Parameters Symbol Parameter Min Typical Max Unit fWCLK Write clock frequency (from the FPGA, download cable, or embedded processor) for write enable, write disable, read status, read device identification, write bytes, erase bulk, erase die, and erase sector operations -- -- 100 MHz tCH DCLK high time 4 -- -- ns tCL DCLK low time 4 -- -- ns tNCSSU Chip select (nCS) setup time 4 -- -- ns tNCSH Chip select (nCS) hold time 4 -- -- ns tDSU DATA[] in setup time before the rising edge on DCLK 2 -- -- ns tDH DATA[] hold time after the rising edge on DCLK 3 -- -- ns tCSH Chip select (nCS) high time 50 -- -- ns tWB Write bytes cycle time -- 0.6 5 ms tWS Write status cycle time -- 1.3 8 ms tEB Erase bulk cycle time for EPCQ-L256 -- 240 480 s continued... EPCQ-L Serial Configuration Devices Datasheet 30 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Symbol Parameter Min Typical Max Unit -- 0.7 3 s -- 0.25 0.8 s Erase die cycle time for EPCQ-L512 Erase die cycle time for EPCQ-L1024 tES Erase sector cycle time for EPCQ-L256 Erase sector cycle time for EPCQ-L512 Erase sector cycle time for EPCQ-L1024 tESS Erase subsector cycle time for EPCQ-L256 Erase subsector cycle time for EPCQ-L512 Erase subsector cycle time for EPCQ-L1024 Read Operation Timing Figure 20. Read Operation Timing Diagram nCS tCH DCLK tCL tnCLK2D DATA DATA0 Table 27. Bit N tODIS Bit N - 1 Bit 0 Add_Bit 0 Read Operation Timing Parameters Symbol Min Max Unit Read clock frequency (from the FPGA or embedded processor) for read bytes operations -- 50 MHz Fast read clock frequency (from the FPGA or embedded processor) for fast read bytes operation -- 100 MHz tCH DCLK high time 4 -- ns tCL DCLK low time 4 -- ns tODIS Output disable time after read -- 8 ns tnCLK2D Clock falling edge to DATA -- 7 ns fRCLK Parameter Programming and Configuration File Support The Intel Quartus Prime software provides programming support for EPCQ-L devices. When you select an EPCQ-L device, the Intel Quartus Prime software automatically generates the Programmer Object File (.pof) to program the device. The software allows you to select the appropriate EPCQ-L device density that most efficiently stores the configuration data for the selected FPGA. You can program the EPCQ-L device in-system by an external microprocessor using the SRunner software driver. The SRunner software driver is developed for embedded EPCQ-L device programming that you can customize to fit in different embedded systems. The SRunner software driver reads .rpd files and writes to the EPCQ-L devices. The programming time is comparable to the Intel Quartus Prime software EPCQ-L Serial Configuration Devices Datasheet 31 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 programming time. Because the FPGA reads the LSB of the .rpd data first during the configuration process, the LSB of .rpd bytes must be shifted out first during the read bytes operation and shifted in first during the write bytes operation. Writing and reading the .rpd file to and from the EPCQ-L device is different from the other data and address bytes. During the ISP of an EPCQ-L device, the cable pulls the nCONFIG signal low to reset the FPGA and overrides the 10-k pull-down resistor on the nCE pin of the FPGA. The download cable then uses the interface pins depending on the selected AS mode to program the EPCQ-L device. When programming is complete, the download cable releases the interface pins of the EPCQ-L device and the nCE pin of the FPGA and pulses the nCONFIG signal to start the configuration process. The FPGA can program the EPCQ-L device in-system using the JTAG interface with the serial flash loader (SFL). This solution allows you to indirectly program the EPCQ-L device using the same JTAG interface that is used to configure the FPGA. Related Information * Using the Serial FlashLoader with the Quartus II Software * Altera ASMI Parallel IP Core User Guide * Intel FPGA USB Download Cable II User Guide * Intel FPGA USB Download Cable User Guide * Intel FPGA Ethernet Download Cable II User Guide * Intel FPGA Ethernet Download Cable User Guide * Configuration, Design Security, and Remote System Upgrades in Intel Arria 10 Devices Document Revision History for EPCQ-L Serial Configuration Devices Datasheet Changes Document Version 2018.05.18 * * Updated content of Bit 3 of the Flag Status Register from VPP to Reserved. Updated the overshoot and undershoot note description in Absolute Maximum Ratings table. 2018.03.09 Added data retention feature information. EPCQ-L Serial Configuration Devices Datasheet 32 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Date December 2017 Version 2017.12.14 Changes * * * * * * May 2017 2017.05.22 * * * * * December 2016 2016.12.16 * * * October 2016 2016.10.31 * * * * May 2016 2016.05.30 Added support for Intel Cyclone 10 GX devices. Changed instances of the following: -- Arria 10 devices to Intel Arria 10 devices -- Stratix 10 devices to Intel Stratix 10 devices -- Quartus Prime software to Intel Quartus Prime software Added operation codes for the following operations: -- Read Status Register Operation Timing Diagram -- Write Status Register Operation Timing Diagram -- Read Flag Status Register Operation Timing Diagram -- Read Non-Volatile Configuration Register Operation Timing Diagram -- Write Non-Volatile Configuration Register Operation Timing Diagram -- 4BYTEADDREN Timing Diagram -- 4BYTEADDREX Timing Diagram -- Write Enable Operation Timing Diagram -- Write Disable Operation Timing Diagram -- Read Bytes Operation Timing Diagram -- Fast Read Operation Timing Diagram -- Extended Quad Input Fast Read Operation Timing Diagram -- Read Device Identification Operation Timing Diagram -- Write Bytes Operation Timing Diagram -- Extended Quad Input Fast Write Bytes Operation Sequence -- Erase Bulk Operation Timing Diagram -- Erase Sector Operation Timing Diagram Updated the operation code from binary to hex for each operation in the Operation Codes for EPCQ-L Devices table. Updated the Read Flag Status Register Operation Timing Diagram. Updated the note to the fast read and extended quad input fast read operations in the Operation Codes for EPCQ-L Devices table. Added Read flag status register, Dual I/O fast read, and Extended dual input fast write bytes operations. Updated instances of write status operation to write status register operation. Added Flag Status Register Bit Content table. Updated Read Status Register Operations. Updated Read Status Register. Updated address bytes for erase bulk and erase die to 4. Added erase subsector in Operation Codes for EPCQ-L Devices table. Updated tESS Max to 0.8. Added Stratix 10 support. Changed instances of Quartus II to Quartus Prime. Changed instances of USB-Blaster to FPGA USB Download Cable. Changed instances of EthernetBlaster to FPGA Ethernet Download Cable. Updated Signals for EPCQ-L Devices table by replacing NC with DNU. continued... EPCQ-L Serial Configuration Devices Datasheet 33 EPCQ-L Serial Configuration Devices Datasheet CF52013 | 2018.05.18 Date Version Changes March 2016 2016.03.31 Removed 'Preliminary' terms in Address Range for EPCQL256, EPCQ-L512 and EPCQ-L1024. December 2015 2015.12.14 Added link to EPCQ-L packaging information website. January 2015 2015.01.23 * * * * * * * * June 2014 2014.06.17 EPCQ-L Serial Configuration Devices Datasheet 34 Updated the package name to FBGA24. Changed erase bulk operation statement for EPCQ-L256 devices. Added stacked die device in 'Features'. Added Number of die column in 'Supported Devices'. Updated Read Bytes and Fast Read operation description to reflect stacked die properties. Added read non-volatile configuration register. Updated AS x1 dummy clock cycles for non-volatile configuration registers. Updated write non-volatile configuration register 16-bit register value. Initial release.