IS25WD020/040
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/12/2012
21
DEVICE OPERATION (CONTINUED)
ERASE OPERATION
The memory array of the IS25WD020/040 is organized
into uniform 4 Kbyte sectors or 64 Kbyte uniform
blocks (a block consists of sixteen adjacent sectors).
Before a byte can be reprogramm ed, the sector or
block that contains the byte must be era sed (erasi ng
sets bits to “1”). In order to erase the devices, there are
three erase instructions available: Sector Era se
(SECTOR_ER), Block Erase (BLOCK_ E R) and Chip
Erase (CHIP_ER). A sector erase ope ration allows any
individual sector to be erased without affecting the data
in other sectors. A block erase operation erases a ny
individual block. A chip erase operation erases the
whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to
any programming operation.
SECTOR_ER COMMAND (SECTOR ERASE)
OPERATION
A SECTOR_ER instruction erases a 4 Kbyte sector.
Before the execution of a SECTOR_ER i nstruction, the
Write Enable Latch (WEL) must be set via a Write
Enable (WREN) instruction. The WEL bit is reset
automatically after the completion of sector an erase
operation.
A SECTOR_ER instruction is entered, after CE# is
pulled low to select the device and stays low during the
entire instruction se quence The SECTOR_ER
instruction code, and three address bytes are input via
SI. Erase operation will start immediately after CE# is
pulled high. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
14 for Sector Erase Sequence.
During an erase operation, all instruction will be
ignored except the Read Status Registe r (RDSR)
instruction. The progress or com pletion of the erase
operation can be determined by reading the WIP bit in
the Status Register using a RDSR instruction. If the
WIP bit is “1”, the erase operation is still in progress. If
the WIP bit is “0”, the erase operation has been
completed.
BLOCK_ER COMMA ND (BLOCK ERASE)
OPERATION
A Block Erase (BLOCK_ER) instruction erases a 64
Kbyte block of the IS25WD020/040. Before the
execution of a BLOCK_ER instruction, the Write
Enable Latch (WEL) must be set via a Write Enable
(WREN) instruction. The WEL is reset automatically
after the completion of a block erase operation.
The BLOCK_ER instruction code and three address
bytes are input via SI. Erase operation will start
immediately after the CE# is pulled high, otherwise the
BLOCK_ER instruction will not be executed. The
internal control logic automatically handles the erase
voltage and timing. Refer to Figure 15 for Block Erase
Sequence.
CHIP_ER COMMAND (CH I P ERASE) OPERATION
A Chip Erase (CHIP_ER) instruction erases the entire
memory array of a IS25WD020/040. Before the
execution of CHIP_ER instruction, the Write Enable
Latch (WEL) must be set via a Write Enable (WREN)
instruction. The WEL is reset automati cally after
completion of a chip erase operation.
The CHIP_ER instruction code is input via the SI.
Erase operation will start immediately after CE# is
pulled high, otherwise the CHIP_ER instruction will not
be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure
16 for Chip Erase Sequence.