IS61DDB22M18A250M3L - INTEGRATED SILICON SOLUTION

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

1

FEATURES

• Single Power Supply Operation

- Low voltage range: 1.65 V – 1.95 V

• Memory Organization

- IS25WD020: 256K x 8 (2 Mbit)

- IS25WD040: 512K x 8 (4 Mbit)

• Cost Effective Sector/Block Architec ture

- 2Mb : Uniform 4KByte sectors / Four uniform

64KByte blocks

- 4Mb : Uniform 4KByte sectors / Eight uniform

64KByte blocks

• Serial Peripheral Interface (SPI) Compatible

- Supports single- or dual-output

- Supports SPI Modes 0 and 3

- Maximum 30 MHz clock rate for normal read

- Maximum 80 MHz clock rate for f ast read

• Page Program (up to 256 Bytes) Operation

- Typical 2 ms per page progra m

• Sector, Block or Chip Erase Operation

- Typical 7 ms sector, block or chip e ra se

• Low Power Consumption

- Typical 2 mA active read current

- Typical 6 mA program/erase current

• Hardware Write Protection

- Protect and unprotect the device from write

operation by Write Protect (WP#) Pin

• Software Write Protection

- The Block Protect (BP2, BP1, BP0) bits allow

partial or entire memory to be configured as read-

only

• High Product Endurance

- Guaranteed 200,000 pro gram/erase cycles per

single sector

- Minimum 20 years data retention

• Industrial Standard Pin-out and Package

- 8-pin 150mil SOIC

- 8-pin 150mil VVSOP

- 8-pin 208mil SOIC for IS25WD040

- 8-pin 300mil PDIP for IS25WD040

- 8-contact WSON

- Lead-free (Pb-free) package

GENERAL DESCRIPTION

The IS25WD020/040 are 2 Mbit / 4Mbit Serial Peripheral Interface (SPI) Flash memories, providing single- or

dual-output. The devices are designed to support a 30 MHz fclock rate in normal read mode, and 80 MHz in fast

read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage

ranging from 1.65 Volt to 1.95 Volt, to perform read, erase and program operations. The devices can be

programmed in stand ard EPROM programmers.

The IS25WD020/040 are accessed through a 4 -wire SPI Interface consisting of Serial Data Input/Output (S lO),

Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized

command codes and operations. The dual-output fast read operation provides and effective serial data rate of

160MHz.

The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in

one program operation. These device s are divided into uniform 4 KByte sectors or unifo rm 64 KByte blocks.

The IS25WD020/040 are manufactured on pFLASH™’s adv anced non-volatile technology. The devices are

offered in 8-pin SOIC 150mil, 8-pin VVSOP 150mil and 8-contact WSON. The 8-pin 208mil SOIC and 8-pin

300mil PDIP just for IS25WD040. The devices operate at wide temperatures between -40°C to +105° C.

2 Mbit / 4 Mbit Single Operating Voltage Serial Flash

Memory With 80 MHz Dual-Output SPI Bus Interface

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

2

CONNECTION DIAGRAMS

PIN DESCRIPTIONS

SYMBOL TYPE DESCRIPTION

CE# INPUT

Chip Enable: CE# low activates the devices internal circuitries for

device operation. CE# high deselect s the devices and switches into

standby mode to reduce the power consumption. When a device is not

selected, data will not be accepted via the serial input pin (Sl), and the

serial output pin (SO) will remain in a high impedance state.

SCK INPUT Serial Data Clock

SIO INPUT/OUTPUT Serial Data Input/Output

SO OUTPUT Serial Data Output

GND Ground

Vcc Device Power Supply

WP# INPUT Write Protect: A hardware program/erase protection for all or part of a

memory array. When the WP# pin is low, memory array write -p rotection depends

on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is

high, the devices are not write-protected.

HOLD# INPUT Hold: Pause serial commu nication by the master device without resetting

the serial sequen ce.

CE# CE#

SO

WP#

GND

Vcc

HOLD#

SCK

SIO

SCK

HOLD#

Vcc

SO

WP#

GND

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

8-Pin SOIC/VVSOP 8-Contact WSON

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

3

BLOCK DIAGRAM

SIO

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

4

SPI MODES DESCRIPTION

Multiple IS25WD020/040 devices can be connected on

the SPI serial bus and controlled by a S PI Master, i.e.

microcontroller, as shown in Figure 1. The devices

support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock

polarity when the SPI master is in Stand-by mode: the

serial clock remains at “0” (SCK = 0) for Mode 0 and

the clock remains at “1 ” (SCK = 1) for Mode 3. Please

refer to Figure 2. For both modes, the input data is

latched on the rising edge of Serial Clock (SCK), and

the output data is available from the falling edge of

SCK.

Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

SPI Master

(i.e. Microcontroller)

CS3 CS2 CS1

SPI Memory

Device

SPI Memory

Device

SPI Memory

Device

SPI Interface with

(0,0) or (1,1)

SDIO

SDI

SCK SCK SCK SCK SO SO SO

SI

O

SIO SIO

CE# CE# CE#

WP# WP# WP#

HOLD# HOLD# HOLD#

N

ote

: 1. Th

e

Wri

te

Pr

otect

(

WP

#)

a

n

d

H

o

l

d

(

H

O

LD

#)

s

i

g

n

a

l

s

h

ou

l

d

be

d

riv

e

n hi

g

h

o

r l

o

w

as

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

5

Figure 2. SPI Modes Supported

MSb

SCK

SO

SIO

In

p

ut mode

Mode 0

(

0

,

0

)

Mode 3

(

1

,

1

)

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

6

SYSTEM CONFIGURATION

The IS25WD020/040 devices are designed to interface directly with the synchronous Serial P eripheral Interface

(SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers.

The devices have two superset features that can be enabled through specific software instructions and the

Configuration Register:

Table 1 illustrates the memory map of the devices. The Configuration Register controls how the memory is

mapped.

BLOCK/SECTOR ADDRESSES

Table 1. Block/Sector Addresses of IS25WD020/040

Memory Density Block No. Block

Size

(Kbytes) Sector No. Sector

Size

(Kbytes) Address Range

4 Mbit

2 Mbit

Block 0 64

Sector 0 4 000000h – 000FFFh

Sector 1 4 001000h – 001FFFh

: : :

Sector 15 4 00F000h – 00FFFFh

Block 1 64

Sector 16 4 010000h – 010FFFh

Sector 17 4 011000h – 011FFFh

: : :

Sector 31 4 01F000h – 01FFFFh

: : : : :

Block 3 64 : 4 030000h – 0 3FFFFh

Block 4 64 : 4 040000h – 0 4FFFFh

: : : : :

Block 7 64 : 4 070000h – 0 7FFFFh

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

7

REGISTERS (CONTINUED)

STATUS REGISTER

Refer to Tables 5 and 6 for Status Register Format and

Status Register Bit Definitions.

The BP0, BP1, BP2, and SRWD are volatile memory

cells that can be written by a Write Statu s Re gister

(WRSR) instruction. The default value of the BP2, BP1,

BP0 were set to “0” and SRWD bits was set to “0” at

factory. Once a “0” or “1”is written, it will not be

changed by device power- up or power-down, and can

only be altered by the next WRSR instruction. The

Status Register can be rea d by the Read Status

Register (RDSR). Refer to Table 10 for Instruction Set.

The function of Status Register bits are descri bed as

follows:

WIP bit: The Write In Progress (WIP) bit is read-only,

and can be used to detect the progress or completio n

of a program or erase operation. When the WIP bit is

“0”, the device is ready for a write status register,

program or erase operation. When the WIP bit is “1”,

the device is busy.

WEL bit: The Write Enable Latch (WEL) bit indicate s

the status of the internal write enable latch. When the

WEL is “0”, the write enable latch is disabled, and all

write operations, including write status register, page

program, sector erase, block and chip erase operations

are inhibited. When the WEL bit is “1”, write operatio ns

are allowed. The WEL bit is set by a Write Enable

(WREN) instruction. Each write register, program and

erase instruction must be preceded by a WREN

instruction. The WEL bit can be reset by a Write

Disable (WRDI) instruction. It will automatically be the

reset after the completion of a write instructio n.

BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,

BP0) bits are used to define the portion of the memory

area to be protected. Refer to Tables 7, 8 and 9 for the

Block Write Protection bit settings. When a defined

combination of BP2, BP1 and BP0 bits are set, the

corresponding memory area is protected. Any program

or erase operation to that area will be inhibited. Note:

a Chip Erase (CHIP_ER) instruction is executed

successfully only if all the Block Protection Bits are set

as “0”s.

SRWD bit: The Status Register Write Disabl e (SRWD)

bit operates in conjunction with the Write Protection

(WP#) signal to provide a Hardware Protection Mo de.

When the SRWD is set to “0”, the Status Register is

not write-protected. When the SRWD is set to “1” and

the WP# is pulled low (VIL), the volatile bits of Status

Register (SRWD, BP2, BP1, BP0) become read-only,

and a WRSR instruction will be ignored. If the SRWD is

set to “1” and WP# is pulled high (VIH), t he Status

Register can be ch anged by a WRSR instruction.

Table 5. Status Register Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SRWD1 Reserved BP2 BP1 BP0 WEL WIP

Default (flash bit) 0 0 0 0 0 0 0

IS25WD020/040

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Rev. A

09/12/2012

8

REGISTERS (CONTINUED)

Table 6. Status Register Bit Definition

Bit Name Definition Read-

/Write Non-Volatile

bit

Bit 0 WIP Write In Progress Bit:

“0” indicates the device is ready

“1” indicates a write cycle is in progress and the device is busy R No

Bit 1 WEL Write Enable Latch:

“0” indicates the device is not write enabled

“1” indicates the device is write en abled (default) R/W No

Bit 2 BP0 Block Protection Bit: (See Table 7 and Table 8 for details)

“0” indicates the specific blocks are not write-protecte d (default)

“1” indicates the specific blocks are write-protected R/W Yes

Bit 3 BP1

Bit 4 BP2

Bits 5 – 6 N/A Reserved: Always “0” s N/A

Bit 7 SRWD Status Register Write Disable: (See Table 9 for details)

“0” indicates the Status Register i s not write-p rotected (default)

“1” indicates the Status Register i s write -protecte d R/W Yes

Table 8. Block Write Protect Bits for IS25WD02 0

Status Register Bits Protected Memory Area

BP2 BP1 BP0 2 Mbit

Not used 0 0 None

Not used 0 1 Upper eight (block : 3): 030000h – 03F FFFh

Not used 1 0 Upper quarter (two blocks :2 and 3): 020000h – 03FFFFh

Not used 1 1 Upper half (four blocks :0 to 3): 000000h – 03FFFFh

Table 8-1. Block Write Protect Bits for IS25WD040

Status Register Bits Protected Memory Area

BP2 BP1 BP0 4 Mbit

0 0 0 None

0 0 1 Upper eight (block : 7): 070000h – 07F FFFh

0 1 0 Upper quarter (two blocks :6 and 7): 060000h – 07FFFFh

0 1 1 Upper half (four blocks :4 to 7): 040000h – 07FFFFh

1 0 0

All Blocks (Block 0 to 7):

000000h – 07FFFFh

1 0 1

1 1 0

1 1 1

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

9

REGISTERS (CONTINUED)

PROTECTION MODE

The IS25WD020/040 have two types of write-

protection mechanisms: hardware and software.

These are used to prevent irrelevant operation in a

possibly noisy environment and protect the data

integrity.

HARDWARE WRITE-PROTECTION

The devices provide two hardware write -protection

features:

a. When inputting a program, erase or write status

register instruction, the number of clock pulse is

checked to determine whether it is a multiple of eight

before the executing. Any incomplete in struction

command sequence will be ignored.

0. The Write Protection (WP#) pin provides a

hardware write prote ction method for BP2, BP1,

BP0 and SRWD in the Status Register. Refer to

the STATUS REGISTER description.

c. Write inhibit is 1.5 V, all write sequence will be

ignored when Vcc drop to 1.5 V and lower

SOFTWARE WRITE PROTECTION

The IS25WD020/040 also provides two software write

protection features:

a. Before the execution of any program, erase or write

status register instruction, the Write Enable Latch

(WEL) bit must be enabled by executing a Write

Enable (WREN) instruction. If the WEL bit is not

enabled first, the program, erase o r write register

instruction will be ignored.

b. The Block Protection (BP2, BP1, BP0) bits allow part

or the whole memory area to be write-protected.

Table 9. Hardware Write Protection on Status

Register

SRWD WP# Status Register

0 Low Writable

1 Low Protected

0 High Writable

1 High Writable

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

10

DEVICE OPERATION

The IS25WD020/040 utilize an 8-bit instruction

register. Refer to Table 10 Instruction Set for details of

the Instructions and Instruction Codes. All instructions,

addresses, and data are shifted in with the most

significant bit (MSB) first on Serial Data Input (SI). The

input data on SI is latched on the rising edge of Serial

Clock (SCK) after Chip En able (CE#) is driven low

(VIL). Every instruction sequence starts with a one-byt e

instruction code and i s followe d by address bytes, data

bytes, or both address bytes and data bytes,

depending on the type of instruction. CE# must be

driven high (VIH) after the last bit of the instruction

sequence has been shifted in.

The timing for each instruction is illustrated in the

following operational descriptions.

Table 10. Instruction Set

Instruction Name Hex

Code Operation Command

Cycle Maximum

Frequency

RDID Abh Read Manufacturer and Product ID 4 Bytes 80 MHz

JEDEC ID READ 9Fh Read Manufacturer and Product ID by JEDEC ID

Command 1 Byte 80 MHz

RDMDID 90h Read Manufacturer and Device ID 4 Bytes 80 MHz

WREN 06h Write Enable 1 Byte 80 MHz

WRDI 04h Write Disable 1 Byte 80 MHz

RDSR 05h Read Status Register 1 Byte 80 MHz

WRSR 01h Write Status Register 2 Bytes 80 MHz

READ 03h Read Data Bytes from Memory at Normal Read Mode 4 Bytes 30 MHz

FAST_READ 0Bh Read Data Bytes from Me mory at Fast Read Mode 5 Bytes 80 MHz

FRDO 3Bh Fast Read Dual Output 5 Bytes 80 MHz

PAGE_ PROG 02h Page Program Data Bytes Into Memory 4 Bytes +

256B 80 MHz

SECTOR_ER D7h/

20h Sector Erase 4 Bytes 80 MHz

BLOCK_ER D8h Block Erase 4 Bytes 80 MHz

CHIP_ER C7h/

60h Chip Erase 1 Byte 80 MHz

HOLD OPERATION

HOLD# is used in conjunction with CE# to select

the IS25WD020/040. When the devices are

selected and a serial sequence is underway,

HOLD# can be used to pause the serial

communication with the m aster device without

resetting the serial sequence. To pa use, HOLD# is

brought low while the SCK signal is low. To resume

serial communication, HOLD# is brought high whil e

the SCK signal is low (SCK may still toggle during

HOLD). Inputs to Sl will be ignored while SO is in

the high impedance state.

IS25WD020/040

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DEVICE OPERATION (CONTINUED)

RDID COMMAND (READ PRODU CT

IDENTIFICATION) OPERATION

The Read Product Identification (RDID) instruction is

for reading out the old style of 8-bit Electronic

Signature, whose values are shown a s table of ID

Definitions. This is not same as RDID or JEDEC ID

instruction. It’s not recomm ended to use for new

design. For new design, please use RDID or JEDEC ID

instruction.

The RDES instruction code is followed by three dummy

bytes, each bit being latched-in on SI during the rising

edge of SCK. Then the Device ID is shifted out on SO

with the MSB first, each bit been shifted out during the

falling edge of SCK. The RDES instructi on is ended by

CE# goes high. The Device ID outputs repeatedly if

continuously send the additional clock cycles on SCK

while CE# is at low.

Table 11. Product Identification

Product Identification Data

Manufacturer ID First Byte 9Dh

Second Byte 7Fh

Device ID: Device ID 1 Device ID 2

IS25WD020 11h 32h

IS25WD040 12h 33h

Figure 3. Read Product Identification Sequence

01 8 31 38 39 46 47 54

HIGH IMPEDAN CE Device ID1 Device ID1 Device ID1

SCK

CE#

SI

SO

INSTRUCTION

97

1010 1011b

3 Dummy Bytes

IS25WD020/040

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Rev. A

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DEVICE OPERATION (CONTINUED)

JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)

OPERATION

The JEDEC ID READ instruction all ows the user to

read the manufacturer and produ ct ID of devices. Refer

to Table 11 Product Identification for pFlash

Manufacturer ID and Device ID. After the JEDEC ID

READ command is input, the second Manufacturer ID

(7Fh) is shifted out on SO with the MSB first, followed

by the first Manufacturer ID (9Dh) and the Device ID

(32h, in the case of the IS25WD020), each bit shifted

out during the falling edge of SCK. If CE# stays low

after the last bit of the Device ID is shifted out, the

Manufacturer ID and Device ID will loop until CE# is

pulled high.

Figure 4. Read Product Identification by JEDEC ID READ Sequence

SCK

CE#

SI

INSTRUCTION

1001 1111b

0815 23 24 31

716

HIGH IMPEDANCE

SO

Device ID2Manufacture ID1Manufacture ID2

IS25WD020/040

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Rev. A

09/12/2012

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DEVICE OPERATION (CONTINUED)

RDMDID COMMAND (READ DEVICE MANUF ACTURER AND DEVICE ID)

OPERATION

The RDMDID instruction allows the user to read the

manufacturer and product ID of devices. Refer to Table

11 Product Identification for pFlash Man ufacturer ID

and Device ID. The RDMDID command is input,

followed by a 24-bit address pointing to an ID table.

The table contains the first Manufacturer ID (9Dh) and

the Device ID (32h, in the case of the IS25WD020),

and is shifted out on SO with the MSB first, each bit

shifted out during the falling edge of SCK. If CE# stays

low after the last bit of the Device ID is shifted out, the

Manufacturer ID and Device ID will loop until CE# is

pulled high.

Figure 5. Read Product Identification by RDMDID READ Sequence

IS25WD020/040

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Rev. A

09/12/2012

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Note :

0. ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)

ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

15

DEVICE OPERATION (CONTINUED)

WRITE ENABLE OPERATION

The Write Enable (WREN) instruction is used to set the

Write Enable Latch (WEL) bit. The WEL bit of the

IS25WD020/040 is reset to the write –protected state

after power-up. The WEL bit must be write enable d

before any write operation, including sector, block

erase, chip erase, page program and write status

register operations. The WEL bit will be reset to the

write-protect state automatically upon completion of a

write operation. The WREN instruction is required

before any above operation is executed.

Figure 6. Write Enable Sequence

WRDI COMMAND (WRITE DISABLE) OPERATION

The Write Disable (WRDI) instruction resets the WEL

bit and disables all write instructions. The WRDI instruction i s not required after the execution of a write

instruction, since the WEL bi t is automatically reset.

Figure 7. Write Disable Sequence

SIO

IS25WD020/040

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Rev. A

09/12/2012

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DEVICE OPERATION (CONTINUED)

RDSR COMMAND (READ STATUS REGISTER) O PERATION

The Read Status Register (RDSR) instruction provides

access to the Status Register. During the execution of

a program, erase or write status registe r operation, all

other instructions will be ignored except the RDSR

instruction, which can be used to che ck the progress or

completion of an operation by reading the WIP bit of

Status Register.

Figure 8. Read Status Register Sequence

WRSR COMMAND (WRITE STATUS REGISTER) OPERATION

The Write Status Register (WRSR) instru ction allows

the user to enable or disable the block protection and

status register write prote ction features by writing “0”s

or “1” s into the volatile BP2, BP1, BP0 and SRWD

bits.

Figure 9. Write Status Register Sequ ence

SIO

IS25WD020/040

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Rev. A

09/12/2012

17

DEVICE OPERATION (CONTINUED)

READ COMMAND ( REA D D ATA ) OPERATION

The Read Data (READ) instruction is used to read

memory data of a IS25WD020/040 under norm al mode

running up to 30 MHz.

The READ instruction code is tran smitted via the Sl

line, followed by three address bytes (A23 – A0) of the

first memory location to be read. A total of 24 address

bits are shifted in, but only AMS (most significant

address) – A0 are decoded. The remaining bits (A23 –

AMS) are ignored. The first byte addressed can be at

any memory location. Upon completion, any data on

the Sl will be ignored. Refer to Table 12 for the related

Address Key.

The first byte data (D7 – D0) addressed is then shifted

out on the SO line, MSb first. A single byte of data, or

up to the whole memory array, can be re ad out in one

READ instruction. The address is automatically

incremented after each byte of data is shifted out. The

read operation can be terminated at any time by driving

CE# high (VIH) after the data come s out. When the

highest address of the device s is reached, the address

counter will roll over to the 000000h add ress, allo wing

the entire memory to be read in one cont inuous READ

instruction.

Table 12. Address Key

Address IS25WD020 IS25WD040

AN (AMS – A0) A17 – A0 A18 – A0

Don’t Care Bits A23 – A18 A23 – A19

Figure 12. Read Data Sequence

SIO

IS25WD020/040

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DEVICE OPERATION (CONTINUED)

FAST_READ COMMAND (FAST READ DATA) OPERATION

The FAST_READ instruction is u sed to read memory

data at up to a 80 MHz clock.

The FAST_READ instruction co de is followed by three

address bytes (A23 – A0) and a dummy byte (8

clocks), transmitted via the SI line, with each bit

latched-in during the rising edge of SCK. Then the first

data byte addressed is shifted out on the SO line, with

each bit shifted out at a maximum frequency fCT, during

the falling edge of SCK.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FAST_READ instruction. The

FAST_READ instruction is terminated by driving CE#

high (VIH).

Figure 13. Fast Read Data Sequence

SIO

IS25WD020/040

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DEVICE OPERATION (CONTINUED)

FRDO COMMAND (F AST READ DUAL OUTPUT ) OPERATION

The FRDO instruction is used to read m emory data on

two output pins each at up to a 80 MHz clock.

The FRDO instruction code is followed by three

address bytes (A23 – A0) and a dummy byte (8

clocks), transmitted via the SI line, with each bit

latched-in during the rising edge of SCK. Then the first

data byte addressed is shifted out on the SO and SIO

lines, with each pair of bits shifted out at a maximum

frequency fCT, during the falling edge of SCK. The first

bit (MSb) is output on SO, while simultaneously the

second bit is output on SIO.

The first byte addressed can be at any memory

location. The address is automatically incremented

after each byte of data is shifted out. When the highest

address is reached, the address counter will roll over to

the 000000h address, allowing the entire memory to be

read with a single FRDO instruction. FRDO instruction

is terminated by driving CE# high (VIH).

Figure 14. Fast Read Dual-Output Se quence

01234567 8910 11 28 29 30 31

...

INSTRUCTION = 0011 1011b ...

23 22 21 3210

3 - BYTE ADDRESS

CE#

SCK

SIO

SO HIGH IMPEDANCE

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

CE#

SCK

SIO

SO HIGH IMPEDANCE DATA OUT 1 DATA OUT 2

IS25WD020/040

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DEVICE OPERATION (CONTINUED)

PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION

The Page Program (PAGE_PROG) instruction allows

up to 256 bytes data to be programmed into memory in

a single operation. The destination of the memory to be

programmed must be outside the protected memo ry

area set by the Block Protection (BP2, BP1, BP0) bits.

A PAGE_PROG instruction which attempts to program

into a page that is write-protected will be ignored.

Before the execution of PAGE_PROG instruction, the

Write Enable Latch (WEL) must be enabled through a

Write Enable (WREN) inst r uction.

The PAGE_PROG instruction code, three address

bytes and program data (1 to 256 bytes) are input via

the Sl line. Program operation will start immediately

after the CE# is brought high, otherwise the

PAGE_PROG instruction will not be executed. The

internal control logic automatically handles the

programming voltages and timing. During a program

operation, all instructions will be ignored except the

RDSR instruction. The progress or completion of the

program operation ca n be determined by reading the

WIP bit in Status Register via a RDSR instruction. If

the WIP bit is “1”, the program operation is still in

progress. If WIP bit is “0”, the program operation has

completed.

If more than 256 bytes data are sent to a device, the

address counter rolls over within the same page, the

previously latched data are discarded, and the last 256

bytes data are kept to be programmed into the page.

The starting byte can be anywhere within the page.

When the end of the page is reached, the address will

wrap around to the beginning of the sam e page. If the

data to be programmed are less than a full page, the

data of all other bytes on the same page will remain

unchanged.

Note: A program operation can alter “1 ”s into “0”s, but

an erase operation is required to change “0”s back to

“1”s. A byte cannot be reprogrammed wi thout first

erasing the whole sector or block.

Figure 15. Page Program Sequence

SIO

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

21

DEVICE OPERATION (CONTINUED)

ERASE OPERATION

The memory array of the IS25WD020/040 is organized

into uniform 4 Kbyte sectors or 64 Kbyte uniform

blocks (a block consists of sixteen adjacent sectors).

Before a byte can be reprogramm ed, the sector or

block that contains the byte must be era sed (erasi ng

sets bits to “1”). In order to erase the devices, there are

three erase instructions available: Sector Era se

(SECTOR_ER), Block Erase (BLOCK_ E R) and Chip

Erase (CHIP_ER). A sector erase ope ration allows any

individual sector to be erased without affecting the data

in other sectors. A block erase operation erases a ny

individual block. A chip erase operation erases the

whole memory array of a device. A sector erase, block

erase or chip erase operation can be executed prior to

any programming operation.

SECTOR_ER COMMAND (SECTOR ERASE)

OPERATION

A SECTOR_ER instruction erases a 4 Kbyte sector.

Before the execution of a SECTOR_ER i nstruction, the

Write Enable Latch (WEL) must be set via a Write

Enable (WREN) instruction. The WEL bit is reset

automatically after the completion of sector an erase

operation.

A SECTOR_ER instruction is entered, after CE# is

pulled low to select the device and stays low during the

entire instruction se quence The SECTOR_ER

instruction code, and three address bytes are input via

SI. Erase operation will start immediately after CE# is

pulled high. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

14 for Sector Erase Sequence.

During an erase operation, all instruction will be

ignored except the Read Status Registe r (RDSR)

instruction. The progress or com pletion of the erase

operation can be determined by reading the WIP bit in

the Status Register using a RDSR instruction. If the

WIP bit is “1”, the erase operation is still in progress. If

the WIP bit is “0”, the erase operation has been

completed.

BLOCK_ER COMMA ND (BLOCK ERASE)

OPERATION

A Block Erase (BLOCK_ER) instruction erases a 64

Kbyte block of the IS25WD020/040. Before the

execution of a BLOCK_ER instruction, the Write

Enable Latch (WEL) must be set via a Write Enable

(WREN) instruction. The WEL is reset automatically

after the completion of a block erase operation.

The BLOCK_ER instruction code and three address

bytes are input via SI. Erase operation will start

immediately after the CE# is pulled high, otherwise the

BLOCK_ER instruction will not be executed. The

internal control logic automatically handles the erase

voltage and timing. Refer to Figure 15 for Block Erase

Sequence.

CHIP_ER COMMAND (CH I P ERASE) OPERATION

A Chip Erase (CHIP_ER) instruction erases the entire

memory array of a IS25WD020/040. Before the

execution of CHIP_ER instruction, the Write Enable

Latch (WEL) must be set via a Write Enable (WREN)

instruction. The WEL is reset automati cally after

completion of a chip erase operation.

The CHIP_ER instruction code is input via the SI.

Erase operation will start immediately after CE# is

pulled high, otherwise the CHIP_ER instruction will not

be executed. The internal control logic automatically

handles the erase voltage and timing. Refer to Figure

16 for Chip Erase Sequence.

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

22

DEVICE OPERATION (CONTINUED)

Figure 16. Sector Erase Sequence

Figure 17. Block Erase Sequence

Figure 18. Chip Erase Sequence

SIO

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

23

ABSOLUTE MAXIMUM RATINGS (1)

Temperature Under Bias -65oC to +125oC

Storage Temperature -65oC to +125oC

Surface Mount Lead Soldering Temperature Halogen-free Package 260oC 10 Seconds

Lead-free Package 260oC 10 Seconds

Input Voltage with Respect to Groun d on All Pins (2) -0.5 V to VCC + 0.5 V

All Output Voltage with Respect to Ground -0.5 V to VCC + 0.5 V

VCC (2) -0.5 V to +4.0 V

Notes:

1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only. The functional operation of the device conditions that exceed those

indicated in the operational sections of this spe cification is not implied. Exposure to absolute maximum rating

condition for extended periods may affe ct device reliability.

2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may

overshoot VCC by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is

-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to

exceed 20 ns.

DC AND AC OPERATING RANGE

Part Number IS25WD020/040

Operating Temperature (Extended Grade) -40oC to 105oC

Operating Temperature (Industrial Grade) -40oC to 85oC

Operating Temperature (Automotive, A1 Grade) -40oC to 85oC

Operating Temperature (Automotive, A2 Grade) -40oC to 105oC

Operating Temperature (Automotive, A3 Grade) -40oC to 125oC

Vcc Power Supply 1.65 V – 1.95 V

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

24

DC CHARACTERISTICS

Applicable over recommended operating range from:

VCC = 1.65 V to 1.95 V (unless otherwise noted).

Symbol Parameter Condition Min Typ Max Units

ICC1 Vcc Active Read Current VCC = 1.95Vat 30 MHz, SO = Open 2 5 mA

ICC2 Vcc Program/Erase Current VCC = 1.95Vat 30 MHz, SO = Open 6 10 mA

ISB1 Vcc Stand by Current CMOS VCC = 1.95V, CE# = VCC 10

A

ISB2 Vcc Stand by Current TTL VCC = 1.95V, CE# = VIH to VCC 2 mA

ILI Input Leakage Current VIN = 0V to VCC 1

A

ILO Output Leaka ge Current VIN = 0V to VCC, TAC = 0oC to 85oC 1

A

VIL Input Low Voltage -0.5 0.3 V

VIH Input High Voltage 0.7VCC VCC +

0.3 V

VOL Output Low Voltage 1.65V < VCC < 1.95V IOL = 2.1 mA 0.2 V

VOH Output High Voltage IOH = -100 A VCC –

0.2 V

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

25

AC CHARACTERISTICS

Applicable over recom m ended operating range from VCC = 1.65 V to 1.95 V

CL = 1 TTL Gate and 10 pF (unles s otherwise noted).

Symbol Parameter Min Typ Max Units

fCT Clock Frequency for fast read mode 0 80 MHz

fC Clock Frequency for read mode 0 30 MHz

tRI Input Rise Time 8 ns

tFI Input Fall Time 8 ns

tCKH SCK High Time 4 ns

tCKL SCK Low Time 4 ns

tCEH CE# High Time 25 ns

tCS CE# Setup Time 10 ns

tCH CE# Hold Time 5 ns

tDS Data In Setup Time 2 ns

tDH Data in Hold Time 2 ns

tHS Hold Setup Time 15 ns

tHD Hold Time 15 ns

tV Output Valid 8 ns

tOH Output Hold Time Normal Mode 0 ns

tLZ Hold to Output Low Z 20 ns

tHZ Hold to Output High Z 20 ns

tDIS Output Disable Time 20 ns

tEC Sector/Block/Chip Erase Time 7 15 ms

tPP Page Program Time 2 3 ms

tVCS VCC Set-up Time 50 s

tw Write Status Register time 2 ms

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

26

AC CHARACTERISTICS (CONTINUED)

SERIAL INPUT/OUTPUT TIMING (1)

Note: 1. For SPI Mode 0 (0,0)

SIO

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

27

AC CHARACTERISTICS (CONTINUED)

HOLD TIMING

PIN CAPACITANCE (f = 1 MHz, T = 25°C )

Typ Max Units Conditions

CIN 4 6 pF VIN = 0 V

COUT 8 12 pF VOUT = 0 V

Note: These parameters are characterized but not 100% tested.

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

28

POWER-UP AND POWER-DOWN

At Power-up and Power-down, the device must not be

selected (CE# must follow the voltage applied on Vcc)

until Vcc reaches the correct value:

- Vcc(min) at Power-up, and then for a furthe r delay of

tVCE

0. Vss at Power-down

Usually a simple pull-up resistor on CE# can be used

to insure safe and proper Power-up and Power-down.

To avoid data corruption and inadvertent write

operations during power up , a Power On Reset (POR)

circuit is included. The logic inside the device is held

reset while Vcc is less than the POR threshold value

(Vwi) during power up, the device does not respond to

any instruction until a time delay of tPUW has elapse d

after the moment that Vcc rised above the Vwi

threshold. However, the correct operation of the device

is not guaranteed if, by this time, Vcc is still below

Vcc(min). No Write Status Register, Pro gram or Erase

instructions should be sent until the later of:

- tPUW after Vcc passed the VWI thre shold

- tVCE after Vcc passed the Vcc(min) level

At Power-up, the device is in the following state:

- The device is in the Standby mode

- The Write Enable Latch (WEL) bit is reset

At Power-down, when Vcc drops from the operating

voltage, to below the Vwi, all write operations are

disabled

and the device does not respo nd to any write

instruction.

Chip Selection Not Allowed

All Write Comm ands are Rejected

tVCE Read Access Allowed Device fully accessible

tPUW

Vcc

Vcc(max)

Vcc(min)

Reset State

V (write inhibit)

Time

Symbol Parameter Min. Max. Unit

t

VCE *1

Vcc( m in ) to CE# Low 10 us

t

PUW *1

Pow er - U p t ime delay t o W r it e in struct ion 1 10 m s

N ot e : *1. T hese param et er s are charac t er ized onl y.

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

29

PROGRAM/ERASE PERFORMANCE

Parameter Unit Typ Max Remarks

Sector Erase Time ms 7 15 From writing erase command to erase completion

Block Erase Time ms 7 15 From writing erase command to erase completion

Chip Erase Time ms 7 15 From writing erase command to erase completion

Page Programming Time ms 2 3 From writing program command to prog ram completion

Note: These parameters are characterized and are not 100% tested.

RELIABILITY CHARACTERISTICS

Parameter Min Typ Unit Test Method

Endurance 200,000 Cycles JEDEC Standard A117

Data Retention 20 Years JEDEC Standard A103

ESD – Human Body Model 2,000 Volts JEDEC Standard A114

ESD – Machine Model 200 Volts JEDEC Standard A115

Latch-Up 100 + ICC1 mA JEDEC Standard 78

Note: These parameters are characterized and are not 100% tested.

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

30

PACKAGE TYPE INFORMATION

`

JN

8-Pin JEDEC 150mil Broad Small Outline Integrated Circuit (SOIC) Package

(measure in millimeters)

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

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PACKAGE TYPE INFORMATION (CONTINUED)

JB

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

32

PACKAGE TYPE INFORMATION (CONTINUED)

JP

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

33

PACKAGE TYPE INFORMATION (CONTINUED)

JA

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

34

PACKAGE TYPE INFORMATION (CONTINUED)

JV

8-pin VVSOP 150mil

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

35

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

36

PRODUCT ORDERING INFORMATION

IS25WD*** - JN L E

Temperature Range

E = Extended Grade (-40°C to +105°C)

I = Industrial Grade (-40°C to +85°C)

A1 = Automotive, A1 Grade (-40°C to +85°C)

A2 = Automotive, A2 Grade (-40°C to +105°C)

A3 = Automotive, A3 Grade (-40°C to +125°C)

Environmental Attribute

L = Lead-free (Pb-free) package

Package Type

JN = 8-pin SOIC 150mil

JV = 8-pin VVSOP 150mil

JB = 8-pin SOIC 208mil

JA = 8-pin PDIP 300 mil

JP = 8-contact WSON

Device Number

IS25WD020/040

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A

09/12/2012

37

ORDERING INFORMATION:

Density Frequency

(MHz) Order Part Number Package

2M 80

IS25WD020-JNLE 8-pin SOIC 150mil

IS25WD020-JVLE 8-pin VVSOP 150-mil

IS25WD020-JBLE 8-pin SOIC 208-mil

IS25WD020-JALE 8-pin PDIP 300mil

IS25WD020-JPLE 8-pin WSON

IS25WD020-JNLI 8-pin SOIC 150mil

IS25WD020-JVLI 8-pin VVSOP 150-mil

IS25WD020-JBLI 8-pin SOIC 208-mil

IS25WD020-JALI 8-pin PDIP 300mil

IS25WD020-JPLI 8-pin WSON

IS25WD020-JNLA1 8-pin SOIC 150mil

IS25WD020-JVLA1 8-pin VVSOP 150-mil

IS25WD020-JBLA1 8-pin SOIC 208-mil

IS25WD020-JALA1 8-pin PDIP 300mil

IS25WD020-JPLA1 8-pin WSON

IS25WD020-JNLA2 8-pin SOIC 150mil

IS25WD020-JVLA2 8-pin VVSOP 150-mil

IS25WD020-JBLA2 8-pin SOIC 208-mil

IS25WD020-JALA2 8-pin PDIP 300mil

IS25WD020-JPLA2 8-pin WSON

4M 80

IS25WD040-JNLE 8-pin SOIC 150mil

IS25WD040-JVLE 8-pin VVSOP 150-mil

IS25WD040-JBLE 8-pin SOIC 208-mil

IS25WD040-JALE 8-pin PDIP 300mil

IS25WD040-JPLE 8-pin WSON

IS25WD040-JNLI 8-pin SOIC 150mil

IS25WD040-JVLI 8-pin VVSOP 150-mil

IS25WD040-JBLI 8-pin SOIC 208-mil

IS25WD040-JALI 8-pin PDIP 300mil

IS25WD040-JPLI 8-pin WSON

IS25WD040-JNLA1 8-pin SOIC 150mil

IS25WD040-JVLA1 8-pin VVSOP 150-mil

IS25WD040-JBLA1 8-pin SOIC 208-mil

IS25WD040-JALA1 8-pin PDIP 300mil

IS25WD040-JPLA1 8-pin WSON

IS25WD040-JNLA2 8-pin SOIC 150mil

IS25WD040-JVLA2 8-pin VVSOP 150-mil

IS25WD040-JBLA2 8-pin SOIC 208-mil

IS25WD040-JALA2 8-pin PDIP 300mil

IS25WD040-JPLA2 8-pin WSON