M41T0DW6TR - STMicroelectronics, Inc.

1/19

PRELIMINARY DATA

October 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M41T0

SERIAL REAL-TIME CL OCK

FEATURES SUMMARY

■2.0 TO 5.5V CLOCK OPERA TING V OLT AGE

■COUNTERS FO R SECONDS, MINUTES,

HOU RS, DA Y, D ATE , MONTH, YEARS, and

CENTURY

■YEAR 2000 COMPLIA NT

■I2C BUS COMP ATIBLE (400kHz)

■LOW OPERATING CURRENT OF 130µA

■OPERATING TEMPERATURE OF –40 TO

85°C

■AUTOMATIC LEAP YEAR COMPENSATION

■SPEC IAL SOF T WARE PROGRAMMABLE

OUTPUT

■OSCILLATOR STOP DETECTION

Figure 1. 8-pin SOIC Pack ages

SO8 (M)

TSSOP8 (DW)

169mil width

M41T0

2/19

TABLE OF CONT ENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Logic Diag r am (Fi g u re 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

SO IC Conne ctions (Figure 3.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Bloc k Diag ram (Fi g ure 4 .) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Rating s (Table 2. ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Operat ing and AC Measurem ent Conditions (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AC Testing Input /Outp ut Waveform (Figure 5.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

C apacitanc e (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC Characte risti cs (Table 5. ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Crystal Electrical Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2-Wire Bus Chara cte rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Bus Data Transfer Sequen ce (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Acknowl edgem ent Sequenc e (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Bus Timin g Requirements Sequence (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

AC Characteristic s (Tab le 7. ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

READ Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Slave Address Location (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

R EAD Mo de Seq uence (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Alternate RE AD Mode Sequenc e (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

W RITE Mode Sequen ce (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

O s c illator Sto p D e t e c tio n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

Ini ti a l Powe r -o n Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Registe r Map (Table 8.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3/19

M41T0

SUMMARY DESCRIP TION

The M41T0 TIMEKEEPER® RAM is a low power

Serial T IMEKEEPER with a b uilt-in 3 2 .768kHz os-

cillator (external crystal c ont rolled). Eight registers

are used for the clock/calendar function and are

configured in bina ry cod ed decim al (BCD) format.

Addresses and data are transferred serially via a

two-line bi-directional bus. The built-in address

WRITE or READ data byte.

The M41T0 is supplied in 8 lead Plastic Small Out-

line package.

Figure 2. Logic Diagram

Figure 3. SOIC Connecti ons

Note: 1. NF pin m ust be ti ed to VSS.

Table 1. Signal Names

Note: 1. NF pin m ust be ti ed to VSS.

AI07028

OSCI

VCC

M41T0

VSS

SCL

OSCO

SDA

OUT

SDAVSS SCL

OUTOSCO

OSCI VCC

NF(1)

AI07029

M41T0

OSCI Oscillator Input

OCSO Oscillator Output

OUT Output Driver (Open Drain)

SDA Serial Data Address Input / Output

SCL Serial Clock

NF(1) No Function

VCC Supply Voltage

VSS Ground

M41T0

4/19

Figu re 4. Blo ck Dia gram

AI07030

SECONDS

OSCILLATOR

32.768 kHz

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

OSCI

OSCO

OUT

VCC

VSS

SCL

SDA

1 Hz

5/19

M41T0

MAX I MUM R AT I N G

Stressing the device ab ove t he rating listed in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not impl ied. Exposure to Absol ute Maxim um Ra t-

ing conditions for extended peri ods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE Program and other rel-

evant quality documents.

Table 2. Absolute Maximum Ratings

Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 and 120

seconds).

CAUTION: Negative undershoots below –0.3V are not al lowed on any pin while in the Battery Back-up mode.

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 85 °C

TSTG(1) Storage Temperature (VCC Off, Oscillator Off) –55 to 125 °C

VIO Input or Output Voltages –0.3 to 7 V

VCC Supply Voltage –0.3 to 7 V

IOOutput Current 20 mA

PDPower Dissipation 0.25 W

M41T0

6/19

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the follo wing DC and AC Charact eristic tables are

derived from tests pe rformed unde r t he Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. Operating and AC Measurem en t Conditions

Note: O ut put Hi-Z is defined as the poin t where dat a i s no long er dri ven.

Figure 5. AC Testing Input/Output Waveform

Table 4. Capacitance

No te : 1. Effective c apacitance me asured wi th power supply at 5V; s am p l ed only, not 100% tested.

2. At 25°C, f = 1MHz.

3. Outputs deselected .

Parameter M41T0 Unit

Supply Voltage (VCC)2.0 to 5.5 V

Ambient Operating Temperature (TA)–40 to 85 °C

Load Capacitance (CL)100 pF

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance (SCL) 7 pF

COUT(3) Output Capacitance (SDA, OUT) 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

7/19

M41T0

Table 5. DC Characteristics

Note: 1. Vali d for Ambient Operating Tem perature: TA = –40 t o 85°C; VCC = 2.0 to 5.5V (except where noted).

2. At 25° C.

Table 6. Crystal Electrical Characteristics

Note: 1. These values are externally supplied. STMicroelectronics recommends the K DS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-

hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz cryst al for industrial temperature operations. KDS can be contacted at kou-

ho u@ kd sj.c o. j p or htt p: //w ww .kd sj . co .j p for furthe r info rma tio n on this crys ta l type.

2. Load ca pa citor s are i nteg rated wit hin the M 41T0. C irc uit boa rd la yo ut con sidera tio ns fo r the 32 . 768kH z cry sta l of minim um trace

leng ths and isolation from RF generating signal s should be taken into account.

3. RS = 40 kΩ when VCC ≤ 2.5V.

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leaka ge Curren t 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Frequency (SCL) = 400kHz 3.0V 35 55 µA

5.5V 130 200 µA

ICC2(2) Supply Current (Standby) All inputs = VCC – 0.2V

Frequency (SCL) = 0Hz 3.0V 0.9 1.2 µA

5.5V 31

VIL Input Low Voltage – 0.3 0.3 VCC V

VIH Input High Voltage 0.7 VCC VCC +

0.3 V

VOL

Output Low Voltage IOL = 3mA 0.4 V

Output Low Voltage (Open

Drain) IOL = 10mA 0.4 V

Symbol Parameter(1,2) Min Typ Max Unit

fOResonant Frequency 32.768 kHz

RSSeries Resistance 60(3) KΩ

CLLoad Capacitance 12.5 pF

M41T0

8/19

OPERATION

The M41T0 clock operates as a slave device on

the serial bus . Access is obtained by implementing

a start condition f ollowed by the correct slave ad-

dress (D0h). The 8 bytes contained in th e device

can then be accessed sequentially in t he foll owing

order:

1. Seconds Register

2. Minutes Register

3. Century/Hours Register

4. Day Register

5. Date Register

6. Month Register

7. Years Register

8. Control Register

2-Wire Bus Characteristics

This bus is intended for communication between

different ICs. It consist s of two lines: one bi-direc-

tional f or dat a si gnals (SDA) and one for clock sig-

nals (SCL). Both the SDA and the SCL lines must

be connected to a positive supply voltage via a

pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During dat a transfer, the data line m ust rema in

stable whenever the clock line is High. Changes

in the data line while the clock line is High will be

interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer . A change in th e state of the

data line, from High to Low, while the c lock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the clock is High,

defines the STOP condition .

Data valid. The state of the data line represents

valid data when after a start condition, the data line

is stable for the duration of the High period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a start condi tion

and terminated with a stop condition. The num ber

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver acknowl-

edges with a ninth bit.

By definition, a devi ce that gives out a message i s

called “transmitter”, the receiving device that g ets

the message is called “receiver”. The device that

controls the message is called “master”. The de-

vices that are controlled by the master are cal led

“slaves”.

Acknowledge. E ac h byte of eight bits is f ollowed

by one Acknowledge B it. This Acknowledge Bit is

a low level put on the bus by the receiv er, whereas

the master generates an extra ac knowled ge relat-

ed clock pulse.

A slave receiver which is a ddressed is obliged to

generate an acknowledge after the reception of

each byte. Also, a master receiver must generate

an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times mus t

be taken int o account. A master receiver must sig-

nal an end-of-data to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. I n this case, the

transmitter must l eave the data li ne Hi gh to enable

the mast er to generate the S TOP c ondition.

9/19

M41T0

Figure 6. Serial Bus Data Transfer Sequen ce

Figure 7. Acknowledgement Sequence

Figure 8. Bus Timing Requirements Sequence

Note : P = STOP and S = ST ART

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41T0

10/19

Table 7. AC Characteristics

Note: 1. Vali d for Ambient Operating Tem perature: TA = –40 t o 85°C; VCC = 2.0 to 5.5V (except where noted).

2. Transmitter must internally provide a hold time to bridge the un defined region (300ns max.) of the falling edge of SCL.

Symbol Parameter(1) Min Typ Max Unit

fSCL SCL Clock Frequency 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 µs

tRSDA and SCL Rise Time 300 µs

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 µs

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 µs

tSU:DAT Data Setup Time 100 ns

tHD:DAT(2) Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 µs

tBUF Time the bus must be free before a new transmission can start 1.3 µs

11/19

M41T0

READ Mode

In this mode, the master reads the M41T0 slave

after setting the slave address (see Figure 9). Fol-

lowing the WRI TE Mode Control Bit (R/W = 0) and

the Acknowledge Bit, the word address An is writ-

ten to the on-chip address pointer. Next the

START condit ion and slave address are repeated,

followed by the READ Mode Control Bit (R/W =1).

At this point, the master transmitter becomes the

master receiver. The data byte which was ad-

dressed will be transm itted and the master receiv-

er will send an Acknowledge Bit to the slave

transmitter. The address pointer is only increment-

ed on reception of an Acknowledge Bit. The

M41T0 slave transmitter will now place the data

byte at address An+1 on the bus. The master re-

ceiver reads and ackno wledge s the n ew byte and

the address pointer is increment ed to An+2.

This cycle of reading consecutive addresses will

continue until the master receiver se nds a STOP

condition to the slave transmitter.

An alternate READ Mode may also be implement -

ed, whereby the master reads the M41T0 slave

without first w ri ting to the (volatile) address point-

er. The first address that is read is the last one

stored in the pointer (s ee Figure 11, page 12).

WRITE Mode

In this mode the master transmitter transmits to

the M41T0 slave receiver. Bus protocol is shown

in Figure 12, p age 12. Following the S TART con-

dition and slave address, a logic '0' (R/W = 0) is

placed on the bus and indicates to the addressed

device that word address An will follow and is to be

written to the on-chip address pointer. The data

word to be written to the memory is strobed in next

and the internal address pointer is increme nted to

the next memory location within the RAM on the

reception of an acknowledge clock. The M41T0

slave receiver will send an acknowledge clock to

the master transmitter after it has received the

slave address and again after it has received the

word address and eac h data byt e (see Fi gure 9).

Figure 9. Slave Address Locat ion

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

M41T0

12/19

Figure 10. READ Mode Sequence

Figu re 11 . Al te rnat e R E A D Mo de S equence

Figu re 12 . WRI TE Mode Se qu e nce

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

13/19

M41T0

CLOCK OPERATION

The M41T0 is driven by a quartz controlled oscilla-

tor with a nominal frequency of 32.768kHz. The

accuracy of the Real-Time Clock depends on the

frequency of t he quartz crystal that i s us ed as the

ti me-base for the RTC. The ei ght-byte Clock Reg-

ister (see Table 8, page 14) is used to both set the

clock and to read the date and ti me from the c lock,

in a binary coded decimal format. Seconds, Min-

utes, and Hours are contained within the first three

registers. Bits D6 and D7 of Clock Register 2

(Hours Registe r) contain the CENTURY ENABLE

Bit (CEB) and the CENTURY Bit (CB). Setting

CEB to a '1' will cause CB to toggle, either from '0'

to '1' or fr om '1' to '0' at the turn of the century (de-

pending upon its i ni tial state). If CEB is set to a '0',

CB will not toggle. B its D0 t hrough D2 of Register

3 contain the Day (day of week). Registers 4, 5

and 6 cont ain the Date (day of month), Mont h and

Years. The final register is the Control Register. Bit

D7 of Register 0 contains the STOP Bit (ST). Set-

ting this b it to a '1' w ill c a us e the o s c illat o r to s top.

If the device is expected to spend a significant

amo u nt of t ime on the s helf, t h e osc illator ma y b e

stopped to reduce current drain. When reset to a

'0' the oscillator restarts within four seconds (t ypi-

cally one second).

The seven clock registers may be read one byte at

a time, or in a sequ ential block. The Control Reg-

ister (Address location 7) may be accessed inde-

pendently. Provision has been made to assure

that a cloc k updat e does not occur while any of the

seven clock addresses are being read. If a clock

address is being read, an update of t he clock reg-

isters will be delayed by 250ms to allow the READ

to be completed before the update occurs. This

will pr ev e n t a tra n s it ion of d ata dur ing t h e R EA D .

Note: This 250ms del ay affec ts only the clock reg-

ister update and does not alter the actual clock

time.

Output Driver Pin

The OUT pin is an output driver that reflects the

contents of D7 of the Control Register. In other

words, when D7 of location 7 is a '0' then the OUT

pin will be driven low.

Note: The OUT pin is open drain which requires

an external pull-up resistor.

Oscillator Stop Detecti on

If the Oscillator Fail (OF) Bit is internally set to a '1,'

this indicates that the oscillator has either stopped,

or was stopped for some period of time and can be

used to judge the validity of t he cl ock and date da-

ta. T his bit w ill be se t to ' 1' any ti me the o scilla tor

stops. The following conditions c an cause the OF

Bi t to be s e t :

– The first time pow er is app lied (defa ults to a '1'

on power-up).

– The voltage present on VCC is insufficient to

support osci llation.

– The ST Bit is set to '1.'

– External int e rference or removal of the crystal.

This bit will remain set to '1' until written to logic '0. '

Initial Power-on Defaults

Upon initial application of power to the device, the

OUT Bit and OF Bit will be s et to a '1,' while the ST

Bit will be set to '0.' Al l o ther Register bits will ini-

tially power-on in a ran dom state.

M41T0

14/19

Table 8. Register Map

Keys : ST = STOP Bit

OUT = Output level

X = Don’t care

0 = Must be set to '0.'

CE B = C entury Ena bl e B i t

CB = Century B i t

OF = Oscillator Fail Bit

Note: 1. Wh en CEB is set to '1', CB will toggle from '0 ' to '1' or from '1' to '0' a t the t urn of the ce ntury (dependent u pon the initial value s et).

When CEB is set to '0', CB will not toggle.

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Seconds Seconds 00-59

1 OF 10 Minutes Minutes Minutes 00-59

2CEB (1) CB 10 Hours Hours Century/Hours 0-1/00-23

3 XXXXX Day Day 01-07

4 X X 10 Date Date Date 01 -31

5 X X X 10 M. Month Month 01-12

6 10 Years Years Year 00-99

7OUT0XXXXXX Control

15/19

M41T0

PART NUMBERING

Table 9. Ordering Information Scheme

For a list of available options (e.g., Speed, P ackage) or for further information on any aspect of this device,

please contact the ST Sales Office near est to you.

Example: M41T 0 M 6 TR

Device Type

M41T

Supply Voltage and Write Protect Voltage

0 = VCC = 2.0 to 5.5V

Package

M = SO8 (150mils width)

DW = TSSOP8 (169mil width)

Tem pera ture Rang e

6 = –40 to 85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

M41T0

16/19

PACKAGE MECHANICAL INF ORMATION

Figure 13. SO8 – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Drawing

Not e: Drawing is not to scale.

Table 10. SO8 – 8-lead Plastic Small Outline, 150 mils body width, Package Mechan ical Data

Symb mm inches

Typ Min Max Typ Min Max

A – 1.35 1.75 – 0.053 0.069

A1 – 0.10 0.25 – 0.004 0.010

B – 0.33 0.51 – 0.013 0.020

C – 0.19 0.25 – 0.007 0.010

D – 4.80 5.00 – 0.189 0.197

ddd – – 0.10 – – 0.004

E – 3.80 4.00 – 0.150 0.157

e 1.27 – – 0.050 – –

H – 5.80 6.20 – 0.228 0.244

h – 0.25 0.50 – 0.010 0.020

L – 0.40 0.90 – 0.016 0.035

α–0°8°–0°8°

N8 8

SO-A

ddd

LA1 α

h x 45˚

17/19

M41T0

Figure 14. TSS OP8 – 8 - lead , Th in Shr ink Small Package Outline

Not e: Drawing is not to scale.

Table 11. TSSOP8 – 8-lead, Thin Shri nk Smal l Package Outline Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A – – 1.20 – – 0.047

A1 – 0.05 0.15 – 0.002 0.006

A2 1.00 0.80 1.05 0.039 0.032 0.041

b – 0.19 0.30 – 0.008 0.012

c – 0.09 0.20 – 0.004 0.008

D 3.00 2.90 3.10 0.118 0.114 0.122

e 0.65 – – 0.026 – –

E 6.40 6.20 6.60 0.252 0.244 0.260

E1 4.40 4.30 4.50 0.173 0.169 0.177

L 0.60 0.45 0.75 0.024 0.018 0.030

L1 1.00 – – 0.039 – –

α–0°8°–0°8°

N8 8

CP – – 0.10 – – 0.004

TSSOP8AM

EE1

A2A

M41T0

18/19

RE VISION HISTORY

Table 12. Document Revisio n History

Date Rev. # Revision Details

June 2002 1.0 First Issue

07/26/02 1.1 Update DC Characteristics (Table 5)

09/09/02 1.2 Adjust DC Characteristics (Table 5)

09/18/02 1.3 Add TSSOP 8-pin package (Figure 1, 14; Table 9, 11)

10/17/02 1.4 Updated package information per Agrate (Figure 13; Table 10)

19/19

M41T0

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