Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. 00C
09/03/02
IS65C1024AL ISSI®
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
DESCRIPTION
The ISSI IS65C1024AL is a low power,131,072-word by 8-
bit
CMOS static RAM. It is fabricated using high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
FUNCTIONAL BLOCK DIAGRAM
128K x 8 LOW POWER CMOS
STATIC RAM
FEATURES
• High-speed access time: 55, 70 ns
•Low active power: 50 mW (typical)
•Low standby power: 100 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
• Temperature Offerings:
Option A: 0°C to 700C
Option A1: –40°C to +850C
Option A2: –40°C to +1050C
Option A3: –40°C to +1250C
• Standard Pin Configuration:
—
32-pin SOP/ 32-pin TSOP (Type 1)
A0-A16
CE1
OE
WE
512 X 2048
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
PRELIMINARY INFORMATION
SEPTEMBER 2002
2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
TRUTH TABLE
Mode WEWE
WEWE
WE CE1CE1
CE1CE1
CE1 CE2 OEOE
OEOE
OE I/O Operation Vcc Current
Not Selected X H X X High-Z ISB1, ISB2
(Power-down) X X L X High-Z ISB1, ISB2
Output Disabled H L H H High-Z I CC
Read H L H L DOUT ICC
Write L L H X DIN ICC
PIN CONFIGURATION
32-Pin SOP
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
VDD Power
GND Ground
OPERATING RANGE
Options
Ambient Temperature
VCC
A 0°C to 70°C 5V ± 10%
A1 –40°C to +85°C 5V ± 10%
A2 –40°C to +105°C 5V ± 10%
A3 –40°C to +125°C 5V ± 10%
PIN CONFIGURATION
32-Pin TSOP (Type 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VDD
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
ISSI
65C1024
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
V
DD
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +125 °C
PTPower Dissipation 1.0 W
IOUT DC Output Current (LOW) 50 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2 . Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Options Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 2.1 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.5 V
VIL Input LOW Voltage(1) –0.5 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD A, A1 –1 1 µA
A2, A3 –10 10
ILO Output Leakage GND ≤ VOUT ≤ VDD A, A1 –1 1 µA
CE1 =
VIH
, or A2, A3 – 1 0 10
CE2 =
VIL
, or OE =
VIH
or
WE =
VIL
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
4Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-55 ns -70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 55 — 70 — ns
tAA
(3)
Address Access Time — 55 — 70 ns
tOHA Output Hold Time 10 — 10 — n s
tACE1
(3)
CE1 Access Time — 55 — 70 ns
tACE2
(3)
CE2 Access Time — 55 — 70 ns
tDOE OE Access Time — 35 — 40 ns
tLZOE
(2)
OE to Low-Z Output 5 — 5 — ns
tHZOE
(2)
OE to High-Z Output 0 20 0 25 n s
tLZCE1
(2)
CE1 to Low-Z Output 10 — 10 — n s
tLZCE2
(2)
CE2 to Low-Z Output 10 — 10 — n s
tHZCE
(2)
CE1 or CE2 to High-Z Output 0 20 0 25 n s
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. tAA and tACE meet 85ns when tested to CMOS levels of VOH = 3.1 and VOL = 0.7 using Loading Condition specified in figure 1a.
(Only for options A2 and A3)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55 ns -70 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC Average operating CE1 = VIL, CE2 = VIH A—10—10 mA
Current VIN = VIH or VIL,A1—10—10
I I/O= 0 mA A2 — 15 — 15
A3 — 15 — 15
ICC1 Vdd Dynamic Operating VDD = Max., CE1 = VIL A—45—45 mA
Supply Current IOUT = 0 mA, f = fMAX A1 — 45 — 45
VIN = VIH or VIL A2 — 55 — 55
CE2 = VIH A3 — 55 — 55
ISB1TTL Standby Current VDD = Max., A — 2 — 2 mA
(TTL Inputs) VIN = VIH or VIL, CE1 ≥ VIH,A1 —2 —2
or CE2
≤
VIL, f = 0 A2 — 5 — 5
A3 —5 —5
ISB2CMOS Standby VDD = Max., A — 40 — 40 µA
Current (CMOS Inputs) CE1 ≥ VDD – 0.2V, or A1 — 40 — 40
CE2
≤
0.2V, VIN ≥ VDD – 0.2V, A2 — 50 — 50
or VIN
≤
VSS + 0.2V, f = 0 A3 — 85 — 85
Note:
1 . At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.6V to 2.4V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1a and 1b
AC TEST LOADS
1838 Ω
100 pF
Including
jig and
scope
993 Ω
OUTPUT
5V
1838 Ω
5 pF
Including
jig and
scope
993 Ω
OUTPUT
5V
Figure 1a. Figure 1b.
6Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-55 ns -70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 55 — 70 — n s
tSCE1CE1 to Write End 45 — 60 — ns
tSCE2CE2 to Write End 45 — 60 — ns
tAW Address Setup Time to Write End 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — n s
tSA Address Setup Time 0 — 0 — ns
tPWE
(4)
WE Pulse Width 40 — 50 — ns
tSD Data Setup to Write End 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 20 — 25 n s
tLZWE
(2)
WE HIGH to Low-Z Output 5 — 5 — n s
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3 . The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4 . Tested with OE HIGH.
Notes:
1. WE is HIGH for a Read Cycle.
2 . The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3 . Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
READ CYCLE NO. 2(1,3)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
t
HZCE
ADDRESS
OE
CE1
CE2
DOUT
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
WRITE CYCLE NO. 2 (CE1CE1
CE1CE1
CE1, CE2 Controlled)(1,2)
Notes:
1 . The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2 . I/O will assume the High-Z state if OE = VIH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WEWE
WEWE
WE Controlled)(1,2)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCE1
tSCE2
tAW
tHA
tPWE(4)
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
CE1
CE2
WE
DOUT
DIN
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE1
t
SA
t
HA
t
SCE2
t
PWE
(4)
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
DIN
CE1
CE2
WE
DOUT
8Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Typ. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 2.0 5.5 V
IDR Data Retention Current Vcc = 2.0V, CE1 ≥ Vcc – 0.2V A, A1 — 5 40 µ A
or CE2
≤ 0.2V
A2, A3 — 10 50
VIN ≥ VCC – 0.2V, or VIN
≤
VSS + 0.2V
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
Note:
1. Typical Values are measured at V
CC
= 5V, T
A
= 25
o
C and not 100% tested.
DATA RETENTION WAVEFORM (CE1CE1
CE1CE1
CE1 Controlled)
DATA RETENTION WAVEFORM (CE2 Controlled)
V
CC
CE1 ≥ V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE1
GND
4.5V
2.2V
Data Retention Mode
V
CC
CE2 ≤ 0.2V
t
SDR
t
RDR
V
DR
0.4V
CE2
GND
4.5V
2.2V
Data Retention Mode
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
PACKAGE INFORMATION
32pin 525mil Small Outline Package (Q)
0.109(2.769)
0.011(0.279)
0.099(2.515)
0.004(0.102)
0.020(0.508)
0.050(1.27) BSC
0.810(20.574)
0.804(20.422)
0.564(14.326)
0.546(13.868)
0.438(11.125)
0.444(11.278)
0.0125(0.318)
0.0061(0.155)
0.0425(1.080)
0.0235(0.597)
0 deg
8 deg
UNIT: INCH(mm)
0.014
(
0.356
)
32pin 8x20mm Small Outline Package (T)
UNIT: INCH(mm)
#1
#16
#32
#17
0.020(0.50)BSC
0.037(0.95)
0.041(1.05)
0.006(0.15)
0.002(0.05)
0.011(0.27)
0.007(0.17)
0.008(0.21)
0.004(0.10)
0.025(0.64)
0.021(0.54)
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.319(8.103)
0.311(7.900)
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/03/02
IS65C1024AL ISSI
®
ORDERING INFORMATION
Temperature Range (A): 0°C to 70°C
Speed (ns) Order Part No. Package
55 IS65C1024AL-55QA Plastic SOP
55 IS65C1024AL-55TA TSOP, Type 1
70 IS65C1024AL-70QA Plastic SOP
Temperature Range (A1): –40°C to +85°C
Speed (ns) Order Part No. Package
55 IS65C1024AL-55QA1 Plastic SOP
55 IS65C1024AL-55TA1 TSOP, Type 1
Temperature Range (A2): –40°C to +105°C
Speed (ns) Order Part No. Package
55 IS65C1024AL-55QA2 Plastic SOP
55 IS65C1024AL-55TA2 TSOP, Type 1
70 IS65C1024AL-70QA2 Plastic SOP
Temperature Range (A3): –40°C to +125°C
Speed (ns) Order Part No. Package
55 IS65C1024AL-55QA3 Plastic SOP
70 IS65C1024AL-70QA3 Plastic SOP
70 IS65C1024AL-70TA3 TSOP, Type 1
